SC531 Triple Low-side FET Driver with Digitally Controlled Current Limit POWER MANAGEMENT Features Description Dual 2A Source, 4A Sink FET Drivers Second Channel Enable Independent Drive Supplies Auxiliary 2A Source, 4A Sink FET Driver Precision Reference Output Current Limit Reference Output (Analog) Integrated Current Sense Blanking (Digital Input) Digitally Controlled High Precision Current Limit Current Limit Flag Current Input ZVS Comparator SPI Communications — 25 MHz Thermally Enhanced 4x4 (mm) MLPQ-UT-28 Package Lead-free, Halogen free, and RoHS/WEEE compliant The SC531 combines three low side drivers with a high speed digitally programmable current limit and a zero voltage switching (ZVS) comparator. Two drivers are normally used to operate the FETs for the power stage. They can operate separately to drive individual power FETs or can be combined to drive a single device. A third, auxiliary, gate drive is controlled by an independent input and can be used to drive the FET for an active clamp or ZVT switching. All three drivers have an independent supply which allows each drive voltage to be optimized for high efficiency. In addition, the SC531 has an SPI interface, 8-bit DAC, and current limit comparator to provide a high-speed digitally programmable current limit. This circuitry can be used for cycle by cycle current limiting or current waveform shaping. A digital output current limit flag is available for monitoring by the host controller. Applications Digitally Controlled Power Supplies Flyback Converter Boost Converter Forward Converter DC-DC and AC-DC Converters With Active Clamp PFC Converters With ZVT Constant Current Converter The SC531 also has a current-input ZVS comparator that can be used to sense changes in high voltage nodes, such as the power FET drain and inductor node (LX) versus the power stage supply, (HVIN in the typical application circuit). Typical Application Circuit D1 VOP T1 HVIN COUT 15pF CIN 3.3V VON 1µF VCC D2 ZVS IN OE2B SC531 IN3 OUT1 DIN CSB 47nF PVDD2 OUT2 DAC PGND2 VREFH PVDD3 VREF OUT3 180pF* 1µF C3 9V Q1 Q2 *optional Q3 1µF 1µF 9V 9V PGND3 VREFL BLANKB CLF GND Rev 2.0 2.49W PGND1 CLK 8-bit DAC 1kW 1MW ZVSP PVDD1 A0 SPI Interface 1MW ZVSN 200W* CSENSE © Semtech Corporation SC531 OUT1 PVDD1 PVDD2 OUT2 PGND2 OE2B Ordering Information PGND1 Pin Configuration 28 28 26 25 24 23 22 A0 1 21 CSB ZVSP 2 20 CLK ZVSN 3 19 DIN VCC 4 18 GND ZVS 5 17 VREFH PGND3 6 16 CSENSE OUT3 7 15 VREFL 11 12 13 14 CLF DAC VREF IN3 10 BLANKB 9 IN 8 PVDD3 T Device Package SC531ULTRT(1)(2) MLPQ-UT-28 4×4 SC531EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant, and halogen free. TOP VIEW MLPQ-UT-28; 4x4, 28 LEAD θJA = 32.5°C/W Marking Information SC531 yyww XXXXX XXXXX yyww = Date Code XXXXX = Semtech Lot Number XXXXX = Semtech Lot Number SC531 Absolute Maximum Ratings Recommended Operating Conditions PVDD1, PVDD2, PVDD3 (V) . . . . . . . . . . . . . . . . . -0.3 to +15.0 Ambient Temperature Range (°C). . . . . . . . . -40 < TA < +115 VCC (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +3.6 PVDD1, PVDD2, PVDD3 (V). . . . . . . . . . . . . . . 6 < PVDD < 12 VREFH, CSENSE (V) . . . . . . . . . . . . . . . . . . . -0.3 to +(VCC + 0.3) VCC (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15 < Vcc < 3.46 ZVS, ZVSP, ZVSN(V). . . . . . . . . . . . . . . . . . . -0.3 to +(VCC + 0.3) Maximum input Current for ZVSP, ZVSN (mA) . . . . . . . . < 40 DIN, CS, CLK, A0 (V). . . . . . . . . . . . . . . . . . . -0.3 to +(VCC + 0.3) VREF, IN3, CLF, OE2B (V) . . . . . . . . . . . . . . . -0.3 to +(VCC + 0.3) BLANKB, IN, DAC, CSB (V) . . . . . . . . . . . . . . -0.3 to +(VCC + 0.3) OUT1, OUT2, OUT3 (V) . . . . . . . . . . . . . . . . . . . . . -1 to +PVDD NOTES: PGND1, PGND2, PGND3 must be tied to GND. Thermal Information ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . 2 k V Thermal Resistance, Junction to Ambient(2) (°C/W).. ..... 32.5 PGND1, PGND2, PGND3, VREFL to GND (V). . . -0.3 to +0.3 Maximum Junction Temperature (°C). . . . . . . . . . . . . . . +125 NOTES: Voltages are all referenced to GND (Pin 18). Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150 Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260 Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless otherwise noted, TA = +25°C for Typ, -40ºC to +115°C for Min and Max, TJ(MAX) = 125ºC, PVDD = 6V to 12V, Vcc = 3.15V to 3.46V, bypass capacitor on PVDD, VCC = 2.2µF, VREF = VREFH = 0.1µF Parameter Symbol Conditions Combined PVDD Quiescent Current IPVDDL Combined PVDD Quiescent Current Min Typ Max Units Not switching, CSB=1, IN = IN3 = OE2B = low 1.5 2.5 mA IPVDDH Not switching, CSB=1, IN = IN3 = VCC, OE2B = low 2.2 3.5 mA IVCC Not switching, CSB=1 0.8 1.4 mA PVENABLE PVDD rising: UVLO sensing on PVDD1 only 4.5 4.75 V PVHYS UVLO sensing on PVDD1 only VCC UVLO Threshold VCCUVLO(TH) VCC rising VCC UVLO Hysteresis VCCUVLO(HYS) VCC falling Digital Input High VIH IN, DIN, CSB, CLK, A0, IN3, OE2B Digital Input Low VIL IN, DIN, CSB, CLK, A0, IN3, OE2B Supply Section VCC Quiescent Current PVDD UVLO Enable Voltage PVDD UVLO Hysteresis 4.25 250 2.65 2.8 mV 2.95 100 V mV Digital Section Digital Input High (BLANKB) VIH_BLNK Digital Input Low (BLANKB) VIL_BLNK 2.1 V 0.8 2.1 V V 0.4 V SC531 Electrical Characteristics (continued) Parameter Symbol Conditions Min Digital Output High VOH CLF, ZVS, ILOAD=7mA 2.64 Digital Output Low VOL CLF, ZVS, ILOAD=-7mA RBLANKB internal pull-up to VCC Typ Max Units Digital Section (continued) BLANKB pull-up resistance SPI CLK Frequency fCLK SPI CLK High & Low Time tSPI CSB, DIN to Clock Falling Edge Setup and Hold Time tSH Chip Select Reset Time tCSB 2.1 V 3.3 0.66 V 4.5 kW 25 MHz 15 ns 5 10 ns ns DAC Section DAC Response Time tRESPONSE Settling to within 1LSB ms 0.5 DAC INL INL -1 1 LSB DAC DNL DNL -0.2 0.2 LSB Voltage Reference VREF 0.245 0.255 V/V 5 mV 896 kW VREF/VREFH, HiZ voltmeter Voltage Reference Buffer Offset VBOFFSET -5 Voltage Ref Divider Resistance RREF 384 VSENSE 0 1.2 V VCOFFSET -6 6 mV 25 40 ns 45 70 ns 640 Current Sense Comparator Section Current Sense Voltage Range Comparator Offset Voltage CSENSE to CLF Propagation Delay tCLF CSENSE to Driver Output Propagation Delay tDRIV 1nF load, 60mV overdrive, 10% to 90% of drive output Driver Section Driver OUT1, OUT2, OUT3 Resistance (Sourcing) RDSP1,2,3 1.5 3 W Driver OUT1, OUT2, OUT3 Resistance (Sinking) RDSN1,2,3 0.7 1.5 W Rise Time — OUT1, OUT2, OUT3 tRISE1,2,3 PVDD=8V, load capacitance=1nF 10 ns Fall Time — OUT1, OUT2, OUT3 tFALL1,2,3 PVDD=8V, load capacitance=1nF 5 ns Propagation Delay from IN to OUT1, OUT2 tPROP1,2 PVDD=8V, load capacitance=1nF 25 45 ns SC531 Electrical Characteristics (continued) Parameter Symbol Conditions tPROP3 No load Min Typ Max Units 25 45 ns 100 ns 800 kHz 3 μA 5 V 40 ns 0.5 μs Driver Section (continued) Propagation Delay from IN3 to OUT3 OUTX Minimum On-time Driver 1,2,3 Switching Frequency PVDDX = 8V, COUT = 1nF 25 f1,2,3 ZVS Section ZVSP, ZVSN Offset Current IZVS 10mA < Input current < 40mA ZVSP, ZVSN to GND Voltage VZVS 0mA < Input current < 40mA Response Time (ZVS falling) tZVS_falling 10mA<Input Current< 40mA, 5mA overdrive Response Time (ZVS rising) tZVS_rising 10mA<Input Current< 40mA, 10mA overdrive -3 0 25 SC531 Pin Descriptions Pin # Pin Name Signal Type Pin Function 1 A0 Digital input Address for SPI interface 2 ZVSP Analog input ZVS comparator positive input 3 ZVSN Analog input ZVS comparator negative input 4 VCC Power input Input supply voltage. Connect a 2.2uF bypass capacitor from VCC to GND. 5 ZVS Digital output ZVS comparator output 6 PGND3 GROUND Driver 3 power ground. 7 OUT3 Power output 8 PVDD3 Power input Driver 3 supply voltage. Connect a 2.2uF bypass capacitor from PVDD3 to PGND3. 9 IN3 Digital input Driver 3 signal input 10 IN Digital input Driver 1 and 2 signal input 11 BLANKB Digital input Current limit blanking input 12 CLF Digital output Current limit flag 13 DAC Analog output DAC output 14 VREF Analog input/output 15 VREFL Analog input Low reference for VREF resistor divider and DAC. Typically connected to GND. 16 CSENSE Analog input Current sense input 17 VREFH Analog input High reference for top of VREF resistor divider 18 GND GROUND 19 DIN Digital input SPI data input 20 CLK Digital input SPI clock input 21 CSB Digital input SPI chip select input 22 OE2B Digital input Driver 2 enable 23 PGND2 GROUND 24 OUT2 Power output 25 PVDD2 Power input Driver 2 supply voltage. Connect a 2.2uF bypass capacitor from PVDD2 to PGND2. 26 PVDD1 Power input Driver 1 supply voltage. Connect a 2.2uF bypass capacitor from PVDD1 to PGND2. 27 OUT1 Power output 28 PGND1 GROUND Driver 1 power ground T Thermal Pad GROUND Connected to GND, use multiple thermal vias for heatsinking purposes Driver 3 output Reference Voltage IC Ground Driver 2 power ground Driver 2 output Driver 1 output SC531 Block Diagram IN 10 S Q VREFH 17 VREF 14 3R Ref. Bufffer R 26 PVDD1 27 OUT1 28 PGND1 12 CLF 25 PVDD2 24 OUT2 23 PGND2 22 OE2B 2 ZVSP 3 ZVSN 8 PVDD3 7 OUT3 6 PGND3 R VCC 4 DIN 19 CSB 21 CLK 20 A0 1 VCC SPI Interface 8-bit DAC GND VCC 3.33kW GND 18 DAC 13 VREFL 15 CSENSE 16 BLANKB 11 ZVS 5 IN3 9 VCC GND SC531 Typical Characteristics OUT1, OUT2 Rise Time OUT1, OUT2 Fall Time VCC = 3.3V, PVDD1/2/3 = 7.8V, Load = BSC190N15NS3G VCC = 3.3V, PVDD1/2/3 = 7.8V, Load = BSC190N15NS3G IN (2V/div) IN (2V/div) OUT1 (5V/div) OUT2 (5V/div) OUT1 (5V/div) OUT2 (5V/div) OE2B (1V/div) OE2B (1V/div) Time (40ns/div) Time (40ns/div) OUT3 Rise Time OUT3 Fall Time VCC = 3.3V, PVDD1/2/3 = 7.8V, Load = BSC190N15NS3G VCC = 3.3V, PVDD1/2/3 = 7.8V, Load = BSC190N15NS3G IN (2V/div) IN (2V/div) OUT3 (5V/div) OUT3 (5V/div) Time (40ns/div) Time (40ns/div) OUT1 Current Limit With CLF Flag SPI to DAC Response Time VCC = 3.3V, PVDD1/2/3 = 7.8V VCC = 3.3V, PVDD1/2/3 = 7.8V, Emulated CSENSE input IN (2V/div) OUT1 (5V/div) DAC (100mV/div) CLF (2V/div) CLK (5V/div) CSENSE (500mV/div) LX (50V/div) Time (1µs/div) Time (4µs/div) SC531 Applications Information Gate Drivers 1 and 2 The high-current output stage in the SC531 is capable of providing 2A source, 4A sink peak current and voltage swings from PVDD to PGND for both OUT1 and OUT2. These outputs can drive individual power FETs which can be used in parallel or can be combined to drive one larger device. The second output (OUT2) can be disabled to save power by setting OE2B input to a logic high. If OE2B is set high during normal switching operation, the OUT2 output is not disabled until the next falling edge of IN. The driver outputs follow the state of the IN pin. When IN is high OUT1 and OUT2 (if OE2B is low) are high. The outputs will be pulled low when IN goes low or when the current limit is reached. Reference Divider, Buffer, DAC, and Current Limit Comparator The SC531 contains a reference divider, buffer, DAC, and current limit comparator that combine to provide a highspeed and high-accuracy programmable current limit. The reference voltage is generated by a resistive divide by four from VREFH to VREFL. This voltage is referenced at the VREF pin. Alternatively, an external reference can drive the VREF pin if a different value is desired. The equation for the VREF voltage is shown below. 95() 95()+ 95()/ The VREFL input must be within +/-300mV of the GND pin and is typically connected to analog ground. The VREF voltage is buffered and then used as the reference for the 8-bit DAC. The 8-bit DAC is controlled by the SPI (see next section for protocol information). The output of the DAC connects to the DAC pin and to the negative input of the current limit comparator. The positive input of the current limit comparator is connected to the CSENSE pin through blanking circuitry. When the BLANKB pin is held low the CSENSE pin is disconnected from the comparator and the positive input is shorted to ground. The BLANKB pin has an internal pull- up resistance of 3.3 kΩ to VCC. If the BLANKB pin is not held low, then the output of the current limit comparator will be determined by the CSENSE and DAC voltages. If the DAC voltage is greater than CSENSE then the output of the comparator will be low. If the CSENSE voltage is greater than the DAC voltage then the output of the comparator will go high causing the CLF flag to go high and OUT1 and OUT2 to be driven low. This event is latched and will not be released until CSENSE goes below DAC and the IN pin goes from low to high. SPI Interface A write sequence begins by bringing CSB low. Once CSB is low, the data on the DIN line is clocked into the 16-bit shift register on the falling edges of CLK. On the 16th falling clock edge, the last data bit is clocked in and the DAC is updated. CSB can be held low or high at this point and any data or clock pulses following the 16th falling clock edge are ignored. CSB must be brought high for the minimum specified time before the next write sequence is initiated with the falling edge of CSB. Figure 3 shows the Serial Timing Diagram and Figure 4 shows the Input Register Contents. ZVS Comparator The ZVS comparator is a current-input (Norton) comparator that provides information that the ZVS condition has been reached by comparing the LX node to HV IN. The falling edge of the power FET LX node going below HVIN (ZVS output going low) is the faster edge. The structure of the comparator allows fast detection with a large voltage range. Series resistors are placed from LX to ZVSP and HVIN to ZVSN. The resistor value should be chosen based on the voltage levels that are being compared and should be optimized to produce input currents in the 10-40μA range. The ZVSP and ZVSN pins can vary from 2-4V based on this normal input current range. The ZVSN and ZSVP input pins can tolerate currents up to 300μA, but the accuracy and speed specifications are only valid in the 10-40μA range. SC531 Applications Information (continued) Gate Driver 3 Gate Driver 3 is a third auxiliary gate drive that is controlled by the IN3 pin, an independent input. It has a separate power supply (PVDD3) and ground (PGND3) connection. The output OUT3 is 2A source, 4A sink capable. This output can be used as a general purpose driver which can be used to drive the FET for an active clamp or active snubber. Other uses include driving the FET for softswitching ZVT or to drive a secondary PWM output. Applications The SC531 is suited for applications which contain a microcontroller or DSP to control PWM switching. The auxiliary OUT3 output and the DAC controlled current limit can be used to implement a variety of switching topologies. By driving the IN3 input with a signal that is inverted from the IN1 input, the OUT3 driver can be used to drive an external P-channel FET for an active clamp converter. In addition, the DAC can be programmed to vary in real-time as a function of the main error voltage from the system microcontroller. This causes each OUT1/2 pulse to terminate when the peak current reaches the real-time DAC setting, resulting in current-mode operation. Combining the DAC control with the external P-channel FET circuitry results in an Active Clamp Current Mode Converter. Refer to Figure 1. The above converter can also be used to provide a programmable constant current output by setting the DAC to a constant value. The IN input has a longer duty cycle than is required to maintain the output, but each OUT1/2 pulse is terminated early by the current limit function. The average current to the load will equal the peak inductor current reduced by 50% of the inductor ripple current. PCB Layout Guidelines Any switch-mode converter requires a good PCB layout to achieve best performance. The following guidelines should be followed to produce an optimum PCB layout. All bypass capacitors should be located close to the pins which they connect to. Use short, direct copper traces to connect between the capacitor and the IC pins. Bypass capacitors should be placed on the same side of the PCB as the IC. Use a 2.2μF minimum capacitor for all bypassing. The pins which require bypass capacitors are shown below: VCC, GND PVDD1, PGND1 PVDD2, PGND2 PVDD3, PGND3 The connections between the PGND pins and the power FETs should be short and direct, using a ground plane if available. If vias are required use multiple vias to reduce impedance between the IC and the FETs. The gate traces should be short and direct. Use wide, short gate traces to reduce susceptibility to noise generated by nearby FET switching. The gate trace routings should avoid any of the FET drain nodes. The CSENSE signal should be referenced to GND (analog ground). A capacitor on the CSENSE input should be located near the CSENSE pin and connected to GND, and connected to the IC with short direct traces. Any VREFH, VREFL, or VREF bypass capacitors should be placed close to the pins, routed with direct traces, and connected to GND. The OUT3 output can be used to drive the FET for a ZVT switch such as is used in PFC boost converters. The ZVS comparator can be used to detect when the ZVT FET has completed its discharge of the main FET by connecting two additional resistors to the ZVS inputs, RZ1 and RZ2, and resistors RZ3 and RZ4 should be selected to keep the keep the ZVSP/N input current below 300uA at maximum VIN. Refer to Figure 2. 10 SC531 Applications Information (continued) T1 HVIN VOP L1 D1 COUT CIN 3.3V VON 1µF VCC D2 ZVS IN OE2B SC531 PVDD1 A0 OUT1 DIN Error Amp Function PVDD2 CLK 3.3V DAC PGND2 VREFH PVDD3 VREF 47nF Leading Edge Blanking OUT2 OUT3 BLANKB 180pF C3 1µF Q1 Q3 Q2 PMOS 9V 1µF 9V 1µF 1µF 1W PGND3 VREFL 2.49W 9V PGND1 CSB 8-bit DAC 1kW 1MW ZVSP IN3 µC 1MW ZVSN 200W 10kW CLF GND CSENSE Figure 1 — Current-Mode Forward Converter With Active Clamp L1 D1 VBOOST AC 10M VAC_IN 1µF VCC RZ1 250k IN OE2B SC531 OUT1 DIN 1µF 9V D2 L2 Q1 PGND1 CSB PVDD2 CLK 47nF RZ4 ZVSP PVDD1 A0 RZ2 250k RZ3 ZVSN IN3 COUT 9V ZVS VAC_IN CIN 20k 3.3V µC + OUT2 DAC PGND2 VREFH PVDD3 VREF OUT3 1µF 1µF 9V Q2 Q3 9V PGND3 VREFL BLANKB CLF GND CSENSE RSNS Figure 2 — ZVT Switching PFC Boost Converter 11 SC531 Applications Information (continued) 1/fCLK 2 1 SCLK // 13 tSPI tSH 14 15 16 tSPI tSH tCSB CSB // tSH DIN DB15 // DB0 // tSH Figure 3 — Serial Timing Diagram MSB 0 A0 0 1 D7 LSB D6 D5 D4 D3 D2 D1 D0 X X X X Data Bits Figure 4 — Input Register Contents 12 SC531 Outline Drawing – 4x4 MLPQ-UT28 DIMENSIONS A D DIM B PIN 1 INDICATOR (LASER MARK) A A1 A2 b D D1 E E1 e L N aaa bbb E A2 A aaa INCHES MIN .020 .000 .006 .154 .100 .154 .100 .012 NOM MAX .024 .001 (.006) .008 .010 .157 .161 .104 .108 .157 .161 .104 .108 .016 BSC .016 .020 28 .003 .004 MILLIMETERS MIN 0.50 0.00 NOM (0.152) 0.15 0.20 3.90 4.00 2.55 2.65 3.90 4.00 2.55 2.65 0.40 BSC 0.30 0.40 28 0.08 0.10 MAX 0.60 0.02 0.25 4.10 2.75 4.10 2.75 0.50 SEATING C C A1 PLANE LxN D1 E/2 E1 2 1 N e bxN D/2 bbb C A B NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 3. CENTER PAD IS CONNECTED TO PIN 18(GROUND). 13 SC531 Land Pattern – 4x4 MLPQ-UT28 K DIMENSIONS (C) G H DIM INCHES MILLIMETERS C (.156) (3.95) G .122 3.10 H .104 2.65 K .104 2.65 P .016 0.40 X .008 0.20 Y .033 0.85 Z .189 4.80 Z Y X P NOTES: 1. 2. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. 14 SC531 © Semtech Corporation All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 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