SX1257 DATASHEET WIRELESS & SENSING PRODUCTS SX1257 RF Front-End Transceiver Low Power Digital I and Q RF Multi-PHY Mode Transceiver VBAT VR_ANA1 VR_ANA2 VR_DIG Power Distribution System 0 to -30 dB with 2 dB steps RESET RF_IN RX pre-filter CT ΣΔ RX pre-filter CT ΣΔ 1b Q_OUT Div by 2 Fractional-N Frequency Synthesizer ATT Div by 2 Fractional-N Frequency Synthesizer TX Filter DAC TX Filter DAC I_OUT 1b MISO Control Registers and Interface Single to Diff 0 to -48 dB with 6 dB steps MOSI SCK NSS CLKIN CLKOUT 1b I_IN RF_OP Driver RF_ON 1b Q_IN XO 36 MHz XTA XTB GENERAL DESCRIPTION The SX1257 is a highly integrated RF front-end to digital I and Q modulator/demodulator Multi-PHY mode transceiver capable of supporting multiple constant and non-constant envelope modulation schemes. It is designed to operate over the 862 - 960 MHz European, North American and Japanese ISM (Industrial, Scientific and Medical) licenseexempt frequency bands. Its highly integrated architecture allows for a minimum of external components whilst maintaining maximum design flexibility. All major RF communication parameters are programmable and most of them can be dynamically set. The SX1257 offers support for both narrow-band and wide-band communication modes without the need to modify external components. The SX1257 is optimized for low power consumption while offering the provision for high RF output power and channelized operation. TrueRF™ technology enables a low-cost external component count whilst still satisfying ETSI, FCC and ARIB regulations. APPLICATIONS KEY PRODUCT FEATURES Fully flexible I and Q modulator and demodulator Half or full-duplex operation Bullet proof RX LNA Analog TX and RX pre-filtering Programmable tap TX FIR-DAC filter Linear TX amplifier for both constant and non-constant envelope modulation schemes ORDERING INFORMATION Part Number Temperature Range Qty. per Reel Package SX1257IWLTRT -40;+85 C 3000 MLPQW-32 Pb-free, Halogen Free RoHS / WEEE compliant product IEEE 802.15.4g SUN Multi-PHY Mode Smartgrid Cognitive / Software Defined Radio (SDR) SX1257 Rev 1 February 2012 Page 1 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Table of Contents 1. 2. 3. General Description ................................................................................................................................................ 6 1.1. Simplified Block Diagram ............................................................................................................................... 6 1.2. Pin and Marking Diagram................................................................................................................................ 7 1.3. Pin Description ................................................................................................................................................ 8 Electrical Characteristics......................................................................................................................................... 9 2.1. ESD Notice...................................................................................................................................................... 9 2.2. Absolute Maximum Ratings ............................................................................................................................ 9 2.3. Operating Range............................................................................................................................................. 9 2.4. Electrical Specifications ................................................................................................................................ 10 2.4.1. Power Consumption............................................................................................................................... 10 2.4.2. Frequency Synthesis.............................................................................................................................. 10 2.4.3. Transmitter Front-End ............................................................................................................................ 11 2.4.4. Receiver Front-End ................................................................................................................................ 11 2.4.5. SPI Bus Digital Specification.................................................................................................................. 12 Chip Description.................................................................................................................................................... 13 3.1. Power Supply Strategy.................................................................................................................................. 13 3.2. Low Battery Detector..................................................................................................................................... 13 3.3. Frequency Synthesizer ................................................................................................................................. 13 3.3.1. Reference Oscillator............................................................................................................................... 13 3.3.2. CLK_OUT Output................................................................................................................................... 14 3.3.3. PLL Architecture..................................................................................................................................... 14 3.4. 3.3.3.1. VCO................................................................................................................................................... 14 3.3.3.2. PLL Bandwidth .................................................................................................................................. 14 3.3.3.3. Carrier Frequency and Resolution .................................................................................................... 14 3.3.3.4. PLL Lock Time .................................................................................................................................. 15 3.3.3.5. Lock Detect Indicator......................................................................................................................... 15 Transmitter Analog Front-End Description.................................................................................................... 15 3.4.1. Architectural Description ........................................................................................................................ 15 3.4.2. TX I / Q Channel Filters.......................................................................................................................... 15 3.4.3. TX I / Q Up-Conversion Mixers .............................................................................................................. 16 3.4.4. RF Amplifier ........................................................................................................................................... 16 3.5. Transmitter Digital Baseband Description..................................................................................................... 17 3.5.1. Digital-to-Analog Converters .................................................................................................................. 17 3.5.2. I and Q Serial Interface .......................................................................................................................... 18 3.6. Receiver Analog Front-End Description........................................................................................................ 19 3.6.1. Architectural Description ........................................................................................................................ 19 3.6.2. LNA and Single to Differential Buffer ..................................................................................................... 19 3.6.3. I /Q Downconversion Quadrature Mixer................................................................................................. 19 3.6.4. Baseband Analog Filters and Amplifiers ................................................................................................ 19 3.7. Receiver Digital Baseband............................................................................................................................ 20 3.7.1. Architectural Block Diagram................................................................................................................... 20 3.7.2. Analog-to-Digital Converters .................................................................................................................. 20 SX1257 Rev 1 February 2012 Page 2 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 3.7.3. Temperature Sensor .............................................................................................................................. 20 3.7.4. I and Q Serial Interface .......................................................................................................................... 21 3.8. 4. 5. 6. 7. Loop-Back .................................................................................................................................................... 21 3.8.1. Digital Loop-Back ................................................................................................................................... 21 3.8.2. RF Loop Back ........................................................................................................................................ 22 Digital Interface ..................................................................................................................................................... 23 4.1. SPI Bus Interface .......................................................................................................................................... 23 4.2. Digital IO Pin Mapping .................................................................................................................................. 24 Configuration and Status Registers ...................................................................................................................... 25 5.1. General Description ...................................................................................................................................... 25 5.2. Mode Configuration Registers....................................................................................................................... 26 5.3. Frequency Synthesizer Configuration Registers........................................................................................... 26 5.4. Revision Configuration Register.................................................................................................................... 27 5.5. Transmitter Front-End Configuration Registers ............................................................................................ 28 5.6. Receiver Front-End Configuration Registers ................................................................................................ 29 5.7. DIO Mapping Configuration Register ............................................................................................................ 30 5.8. Additional Parameter Configuration Registers .............................................................................................. 30 Application Information ......................................................................................................................................... 32 6.1. Crystal Resonator Specification .................................................................................................................... 32 6.2. Reset of the Chip .......................................................................................................................................... 32 6.2.1. POR ....................................................................................................................................................... 32 6.2.2. Manual Reset ......................................................................................................................................... 33 6.3. TX Noise Shaper........................................................................................................................................... 33 6.4. Reference Design ......................................................................................................................................... 34 Packaging Information .......................................................................................................................................... 35 7.1. Package Outline Drawing.............................................................................................................................. 35 7.2. Recommended Land Pattern ........................................................................................................................ 35 7.3. Thermal Impedance ...................................................................................................................................... 36 7.4. Tape and Reel Specification ......................................................................................................................... 36 8. Chip Revisions ...................................................................................................................................................... 37 9. Revision History .................................................................................................................................................... 37 SX1257 Rev 1 February 2012 Page 3 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Index of figures Block Diagram .......................................................................................................................................................... 6 Pin Diagram ............................................................................................................................................................. 7 Marking Diagram ...................................................................................................................................................... 7 TCXO Connection .................................................................................................................................................. 13 SX1257 Transmitter Analog Front-End Block Diagram ......................................................................................... 15 FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 32 ........................................................... 17 FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 64 ........................................................... 18 Transmitter I and Q Channel Bit-Stream Timing Diagram ..................................................................................... 18 SX1257 Receiver Analog Front-End Block Diagram ............................................................................................. 19 SX1257 Digital Receiver Baseband Block Diagram .............................................................................................. 20 Temperature Sensor Response ............................................................................................................................. 21 Receiver I and Q Channel Bit-Stream Timing Diagram ......................................................................................... 21 Digital and RF Loop-Back Paths ............................................................................................................................ 22 SPI Timing Diagram (Single Access) ..................................................................................................................... 23 POR Timing Diagram ............................................................................................................................................. 32 Manual Reset Timing Diagram .............................................................................................................................. 33 Example Digital Modulator Implementation ........................................................................................................... 33 SX1257 Application Schematic .............................................................................................................................. 34 Package Outline Drawing ...................................................................................................................................... 35 Recommended Land Pattern ................................................................................................................................. 35 Tape and Reel Specification .................................................................................................................................. 36 SX1257 Rev 1 February 2012 Page 4 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Index of Tables SX1257 Pinout ........................................................................................................................................................ 8 Absolute Maximum Ratings .................................................................................................................................... 9 Operating Ranges ................................................................................................................................................... 9 Power Consumption Specification ........................................................................................................................ 10 Frequency Synthesizer Specification .................................................................................................................... 10 TX Front-End Specifications ................................................................................................................................. 11 RX Front-End Specification ................................................................................................................................... 11 SPI Digital Specification ........................................................................................................................................ 12 TX Analog Filter Single Sideband Bandwidth ........................................................................................................ 16 TX DAC Single Sideband Bandwidth ..................................................................................................................... 17 DIO Mapping ......................................................................................................................................................... 24 Configuration Register Summary .......................................................................................................................... 25 Mode Configuration Registers .............................................................................................................................. 26 Frequency Synthesizer Configuration Registers ................................................................................................... 26 Revision Configuration Register ........................................................................................................................... 27 Transmitter Front-End Configuration Registers .................................................................................................... 28 Receiver Front-End Configuration Registers ........................................................................................................ 29 DIO Mapping Configuration Register .................................................................................................................... 30 Additional Parameters Configuration Registers .................................................................................................... 30 Crystal Resonator Specification ............................................................................................................................. 32 Chip Revision Identification .................................................................................................................................... 37 Datasheet Revision History .................................................................................................................................... 37 SX1257 Rev 1 February 2012 Page 5 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 1. General Description The SX1257 is a single-chip Zero-IF RF-to-digital front-end transceiver integrated circuit ideally suited for today's high performance multi-PHY mode or SDR ISM band RF applications. The SX1257 has a maximum signal bandwidth of 500 kHz in both transmission and reception and is intended as a high performance, low-cost RF-to-digital converter and provides a generic RF front-end that allows several constant and non-constant envelope modulation schemes to be handled, such as the MR-FSK, MR-OFDM and MR-O-QPSK PHYs of the IEEE 802.15.4g standard for Smart Utility Networks (SUN) and Smartgrid applications in the 862 - 960 MHz license-exempt frequency bands. The SX1257's advanced features set greatly simplifies system design whilst the high level of integration reduces the external BOM to an optional RF power amplifier, and a handful of passive decoupling and matching components. A simple 4-wire 1-bit digital serial interface is provided for the baseband I and Q data streams to a baseband processor. The SX1257 can operate in both half and full-duplex mode and is compliant with ETSI, FCC and ARIB regulatory requirements. It is available in a MLPQ-W 5 x 5 mm 32 lead package. 1.1. Simplified Block Diagram VBAT VR_ANA1 VR_ANA2 VR_DIG Power Distribution System 0 to -30 dB with 2 dB steps RESET RF_IN RX pre-filter CT ΣΔ RX pre-filter CT ΣΔ 1b Q_OUT Div by 2 Fractional-N Frequency Synthesizer ATT Div by 2 Fractional-N Frequency Synthesizer TX Filter DAC TX Filter DAC I_OUT 1b MISO Control Registers and Interface Single to Diff 0 to -48 dB with 6 dB steps MOSI SCK NSS CLK_IN CLK_OUT 1b I_IN RF_OP Driver RF_ON 1b Q_IN XO 36 MHz XTA XTB Figure 1. Block Diagram SX1257 Rev 1 February 2012 Page 6 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 1.2. Pin and Marking Diagram 25 VR_ANA2 26 GND 27 RF_IN 28 GND 29 RF_ON 30 RF_OP 31 GND 32 VBAT3 The following diagrams illustrate the pin arrangement of the MLPQ-W package (top view) and the IC marking description. 6 XTA 19 MOSI 7 GND 18 MISO 8 XTB 17 SCK 16 VBAT2 20 NSS 15 I_OUT 21 DIO0 5 VR_DIG 14 Q_OUT 4 GND 13 I_IN 22 DIO1 12 Q_IN 23 DIO2 3 VR_ANA1 11 CLK_IN 2 VBAT1 10 CLK_OUT 24 DIO3 9 RESET 1 VR_PA Figure 2. Pin Diagram Figure 3. Marking Diagram Notes yyww refers to the data code xxxxxx refers to the lot number SX1257 Rev 1 February 2012 Page 7 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 1.3. Pin Description Table 1 SX1257 Pinout Number Name Type 0 Ground - Exposed ground pad 1 VR_PA - Regulated supply for TX amplifier 2 VBAT1 - VBAT Supply voltage 3 VR_ANA1 - Regulated supply for analog TX circuit 4 GND - Ground 5 VR_DIG - Regulated supply for digital circuit 6 XTA I/O 7 GND - 8 XTB I/O Crystal pad / input for external clock 9 Reset I/O Reset 10 CLK_OUT O 36 MHz digital clock output 11 CLK_IN I 36 MHz digital clock input 12 Q_IN I Digital baseband data input for I (inphase) channel DAC 13 I_IN I Digital baseband data input for Q (quadrature) channel DAC 14 Q_OUT O Digital baseband data output from I (inphase) channel ADC 15 I_OUT O Digital baseband data output from Q (quadrature) channel ADC 16 VBAT2 - VBAT supply voltage 17 SCK I SPI clock 18 MISO O Master In Slave Output SPI output 19 MOSI I Master Out Slave Input SPI input 20 NSS I SPI chip select 21 DIO0 O Digital I/O, software configured 22 DIO1 O Digital I/O, software configured 23 DIO2 O Digital I/O, software configured 24 DIO3 O Digital I/O, software configured 25 VR_ANA2 - Regulated supply for analog RX circuit 26 GND - Ground 27 RF_IN I RX LNA input 28 GND - Ground 29 RF_ON O Differential TX Output, negative node 30 RF_OP O Differential TX Output, positive node 31 GND - Ground 32 VBAT3 - VBAT supply for TX amplifier SX1257 Rev 1 February 2012 Description Crystal pad Ground Page 8 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 2. Electrical Characteristics 2.1. ESD Notice The SX1257 is a high performance radio frequency device Class 3A of the JEDEC standard JESD22-A114-C (Human Body Model) on all pins Class B of the JEDEC standard JESD22-A115-A (Machine Model) on all pins Class III of the JEDEC standard JESD22-C101-C (Charged Device Model) on all pins 2.2. Absolute Maximum Ratings Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2 Absolute Maximum Ratings Symbol Description Min Max Units VDDmr Maximum Supply Voltage -0.5 3.9 V Tmr Maximum Temperature -55 115 °C Tj Maximum Junction Temperature - 125 °C Pmr Maximum RF Input Level - +6 dBm 2.3. Operating Range Operating ranges define the limits for functional operation and parametric characteristics of the device as described in this section. Functionality outside these limits is not implied. Table 3 Operating Ranges Symbol Description Min Max Units VDDop Operational Supply Voltage 2.7 3.6 V Top Operational Temperature -40 +85 °C Clop Load Capacitance on Digital Ports - 25 pF ML RF Input Level - 0 dBm SX1257 Rev 1 February 2012 Page 9 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 2.4. Electrical Specifications The table below gives the electrical specifications of the transceiver under the following conditions: supply Voltage = 3.3 V, temperature = 25 °C, fXOSC = 36 MHz, fRF = 915 MHz, OFDM with 16-QAM, 3/4 rate coded with 26 active tones (IEEE 802.15.4g MR-OFDM Option 3). Output power = -5 dBm (100 ohm differential transmission), TXBWANA = 250 kHz, RXBWANA = 250 kHz, External baseband RX filter = 150 kHz, unless otherwise specified. 2.4.1. Power Consumption Table 4 Power Consumption Specification Symbol Description IDDSL Supply Current in Sleep Mode IDDST Supply Current in Standby Mode IDDRX Supply Current in Receive Mode IDDTX Supply Current in Transmit Mode Conditions Crystal oscillator enabled RFOutput Power = -5 dBm Min Typ Max Units - 0.5 1 uA - 1.15 1.5 mA - 20 25 mA - 58 85 mA 2.4.2. Frequency Synthesis Table 5 Frequency Synthesizer Specification Symbol Description Conditions Min Typ Max Units FR Synthesizer Frequency Range Programmable 862 - 1020 MHz FXOSC Crystal Oscillator Frequency See Section 5 32 36 36 MHz TS_OS Crystal Oscillator Wake-up Time From sleep mode - 300 500 us TS_FS RX Frequency Synthesizer Wake-up Time Crystal Oscillator Enabled - 100 150 us FSTEP Frequency Synthesizer Step Size FSTEP = FXOSC / 219 61 68.7 68.7 Hz TS_HOP_RX RX Frequency Synthesizer Hop Time (to within 10 kHz of target frequency) 200 kHz step 400 kHz step 1.2 MHz step 25 MHz step - tbd tbd tbd tbd - us us us us TS_HOP_TX RX Frequency Synthesizer Hop Time (to within 10 kHz of target frequency) 200 kHz step 400 kHz step 1.2 MHz step 25 MHz step - tbd tbd tbd tbd - us us us us SX1257 Rev 1 February 2012 Page 10 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 2.4.3. Transmitter Front-End Table 6 TX Front-End Specifications Symbol Description Conditions Min Typ Max Units FCLK_IN External Clock Frequency for TX Synthesizer or DAC input clock SX1257 slave mode 32 - 36 MHz TXPmax TX Maximum Output Power Saturated Power +5 +8 - dBm TXP1dB TX 1 dB Compression Point Peak Value +3 +6 - dBm TXOIP3 TX Output IP3 -5 dBm average output power +13 +16 - dBm PHN Transmitter Phase Noise 100 kHz offset from carrier - -98 - dBc/Hz PHNF Transmitter Output Noise Floor 10 MHz offset from carrier -131 -128 - dBc/Hz PHNID Transmitter Integrated DSB Phase Noise Integrated bandwidth from 500 Hz to 125 kHz - 0.6 1.5 °RMS TXGM Transmitter IQ Gain Mismatch - 0.5 1 dB TXPM Transmitter IQ Phase Mismatch - 1 3 ° TXBWANA Transmitter Analog Prefilter BW (SSB) Programmable 210 - 850 kHz TXBWANAPrc Transmitter Analog Prefilter BW precision -30 - +30 % TXBWDIFG Transmitter FIR-DAC Taps Programmable 24 - 64 - TXLO TX LO Leakage (Before DC offset Calibration) ADC rms input: -10 dBFS - -8 - dBc TXEVM Transmitter Error Vector Magnitude TS_TR Transmitter Wake-up Time tbd Frequency synthesizer enabled dB - 120 - us Min Typ Max Units 32 - 36 MHz - - 0.01 % Maximum LNA Gain - 7 10 dB Adjustable in 2 dB steps - 70 - dB +10 -28 -25 - dBm dBm 2.4.4. Receiver Front-End Table 7 RX Front-End Specification Symbol Description Conditions FCLK_IN External Clock Frequency for RX ADC SX1257 slave mode CLK_INJ External Clock Jitter Specification RXNF Receiver Noise Figure RXGR RX Gain Range IIP3 3rd Order Input Intercept Point Unwanted tones are 2 MHz and 3.8 MHz above the LO RXGM Receiver IQ Gain Mismatch - 0.5 1 dB RXPM Receiver IQ Phase Mismatch - 1 3 ° SX1257 Rev 1 February 2012 ©2012 Semtech Corp. External clock. White noise Lowest LNA gain Highest LNA gain Page 11 www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Table 7 RX Front-End Specification Symbol Description Conditions Min Typ Max Units RXBWANA Receiver Analog Prefilter BW (SSB) Programmable 250 - 750 kHz TS_RE Receiver Wake-up Time Frequency synthesizer enabled - tbd - ms Min Typ Max Units 2.4.5. SPI Bus Digital Specification Table 8 SPI Digital Specification Symbol Description Conditions VIH Digital Input High Level 0.8 - - VDD VIL Digital Input Low Level - - 0.2 VDD VOH Digital Output High Level Imax = 1 mA 0.9 - - VDD VOL Digital Output Low Level Imax = -1 mA - - 0.1 VDD FSCK SCK Frequency - - 10 MHz tch SCK High Time 50 - - ns tcl SCK Low Time 50 - - ns trise SCK Rise Time - 5 - ns tfall SCK Fall Time - 5 - ns tsetup MOSI Set-up Time From MOSI change to SCK rising edge 30 - - ns thold MOSI Hold Time From SCK rising edge to MOSI change 60 - - ns tnsetup NSS Set-up Time From NSS falling edge to SCK rising edge 30 - - ns tnhold NSS Hold Time From SCK falling edge to NSS rising edge 100 - - ns tnhigh NSS High Time Between SPI Access 20 - - ns tdata Data Hold and Set-up Time 250 - - ns SX1257 Rev 1 February 2012 ©2012 Semtech Corp. Page 12 www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 3. Chip Description This section describes the architecture of the SX1257 Multi-PHY mode transceiver. 3.1. Power Supply Strategy The SX1257 employs an advanced power distribution scheme (PDS), which provides stable operating characteristics over the full temperature and voltage range of operation. The SX1257 can be powered from any low-noise voltage source via pins VBAT1, VBAT2 and VBAT3. Decoupling capacitors should be connected, as suggested in the reference design, on VR_PA, VR_DIG, VR_ANA1 and VR_ANA2 pins to ensure a correct operation of the built-in voltage regulators. 3.2. Low Battery Detector A low battery detector is also included allowing the generation of an interrupt signal in response to passing a programmable threshold adjustable through the register RegLowBat. The interrupt signal can be mapped to the DIO0 pin, through the programmation of RegDioMapping. 3.3. Frequency Synthesizer The SX1257 incorporates two separate state of the art fractional-N PLLs for the TX and RX circuit blocks 3.3.1. Reference Oscillator The crystal oscillator is the main timing reference of the SX1257. It provides the reference source for the transmit and receive frequency synthesizers and as a clock for digital processing. The XO startup time, TS_OSC, depends on the actual XTAL being connected on pins XTA and XTB. When using the builtin sequencer, the SX1257 optimizes the startup time and automatically triggers the PLL when the XO signal is stable. To manually control the startup time, the user should monitor the signal CLK_OUT which will only be made available on the output buffer when a stable XO oscillation is achieved. An external crystal controlled source, such as a clipped-sinewave TCXO, clock can be used to replace the crystal oscillator, This external source should be provided on XTB (pin 8) and XTA (pin 6) should be left open, as illustrated in Figure 4, below. XTA GND XTB VCC OP VCC GND CD Figure 4. TCXO Connection SX1257 Rev 1 February 2012 Page 13 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS The peak-peak amplitude of the input signal must never exceed 1.8 V. Please consult your TCXO supplier for an appropriate value of decoupling capacitor, CD. Due to the low jitter requirements required by the receiver digital block it is recommended that only a crystal controlled external frequency source is used. 3.3.2. CLK_OUT Output For master mode operation the SX1257 provides a system clock output made available at pin CLK_OUT. 3.3.3. PLL Architecture The SX1257 incorporates two fourth-order type fractional-N sigma-delta PLLs. The PLLs include integrated VCO and programmable bandwidth loop filter, removing the need for any external components. The PLLs are autocalibrating and are capable of fast switching and settling times. 3.3.3.1. VCO Both TX and RX VCOs operate at twice the RF frequency, with the oscillators centered at 1.9 GHz. This reduces any LO leakage in receive mode, to improve the quadrature precision of the receiver, and to reduce the pulling effects on the VCO during transmission. The VCO calibration is fully automated, calibration times are fully transparent to the end-user as the processing time is included in the TS_TR and TS_RE specifications. 3.3.3.2. PLL Bandwidth The bandwidth of the PLL loop filters are independently configurable via the configuration registers TxPllBw and RxPllBw for the modulation schemes supported, as well as fast channel switching and lock times to support FHSS and frequency agile applications, such as AFA. 3.3.3.3. Carrier Frequency and Resolution Both the TX and RX embed a 19-bit sigma-delta modulator and the frequency resolution, constant over the entire frequency range, is calculated using the following formula: F XOSC F STEP = --------------19 2 The RX and RX carrier frequencies are programmed through registers RegFrfRx and RegFrfTx, split across register addresses 0x01 to 0x03 and 0x04 to 0x06, respectively, and are calculated by: F RF = F STEP × Frfxx ( 23, 0 ) where: Frfxx is the integer value of the RegFrfRx or RegFrfTx as defined above. Note: As stated above, the Frfxx settings are split across 3 bytes for both the transmitter and receiver frequency synthesizers. A change in the center frequency will only be taken into account when the least significant byte FrfxxLsb in RegFrfxxLsb is written and when exiting SLEEP mode SX1257 Rev 1 February 2012 Page 14 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 3.3.3.4. PLL Lock Time RX and TX PLL lock times are a function of a number of technical factors, such as synthesized frequency, frequency step, etc. The SX1257 includes an auto-sequencer that manages the start-up sequence of the PLL. 3.3.3.5. Lock Detect Indicator A lock indication signal for both RX and TX PLLs can be accessed via DIO pins, and is toggled high when the PLL reaches its locking range. Please refer to Table 11 to map this interrupt to the desired DIO pins. 3.4. Transmitter Analog Front-End Description The analog front-end of the SX1257 transmitter stage comprises the TX frequency synthesizer, I and Q channel filters, the I / Q mixer and RF amplifier blocks. 3.4.1. Architectural Description The block diagram of the transmitter front-end block is illustrated below. TX Fractional-N Frequency Synthesizer RF Loop-Back (To RX) Div by 2 Differential I-Channel Filter I-Channel DAC RF_OP Driver RF_ON Differential I/Q Mixer Q-Channel DAC Differential Q-Channel Filter Figure 5. SX1257 Transmitter Analog Front-End Block Diagram 3.4.2. TX I / Q Channel Filters Differential analog I and Q signals input to the TX Front-End from the TX FIR DAC are filtered by I and Q channel filters. These filters smooth the reconstructed analog waveforms and remove quantization noise generated by the I and Q channel TX FIR DACs. The filters are unity gain third-order low pass Butterworth types with programmable bandwidth configured via TxAnaBw. The 3 dB BW of the analog TX filter BW can be calculated from: 17.15 BW 3dB = -----------------------------------------------------------------( 41 – RegTxBwAna ( 4, 0 ) ) SX1257 Rev 1 February 2012 Page 15 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS The analog filter bandwidth should be set to greater than the signal bandwidth so as to reduce any group delay variations. The range of programmable TX analog filter bandwidths is tabulated below in Table 9. Table 9 TX Analog Filter Single Sideband Bandwidth TxAnaBw (Dec) TxAnaBw (Bin) SSB Filter BW (kHz) TxAnaBw (Dec) TxAnaBw (Bin) SSB Filter BW (kHz) 0 00000 209 16 10000 343 1 00001 214 17 10001 357 2 00010 220 18 10010 373 3 00011 226 19 10011 390 4 00100 232 20 10100 408 5 00101 238 21 10101 429 6 00110 245 22 10110 451 7 00111 252 23 10111 476 8 01000 260 24 11000 504 9 01001 268 25 11001 536 10 01010 277 26 11010 572 11 01011 286 27 11011 613 12 01100 296 28 11100 660 13 01101 306 29 11101 715 14 01110 318 30 11110 780 15 01111 330 31 11111 858 3.4.3. TX I / Q Up-Conversion Mixers The TX I / Q mixer block mixes the baseband analog I and Q signals with that from the PLL frequency synthesizer and up converts to the RF carrier frequency. The mixer block includes a highly linear I/ Q mixer stage with programmable gain configurable via configuration register RegTxGain. The modulated RF signal is input to the TX RF amplifier stage. 3.4.4. RF Amplifier The TX amplifier receives the input signal from the TX mixer and provides two differential outputs. The first output provides the RF_OP and RF_ON signals in TX mode. The second output is used to provide an internal differential signal to the receiver during RX gain calibration. The amplifier provides good linear performance required to meet the peak to average power level variation of OFDM. The peak output power is +5 dBm, which allows for an average output power of greater than -5 dBm with 10 dB back-off. The Output signal is intended to be amplified through a suitable external RF power amplifier to the maximum permissible SX1257 Rev 1 February 2012 Page 16 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS level allowed by relevant regulatory standards. The optimum load impedance presented RF amplifier is 100 ohms differential. 3.5. Transmitter Digital Baseband Description The transmitter digital baseband section contains separate I and Q channel digital-to-analog convertors. 3.5.1. Digital-to-Analog Converters The TX DAC is the first block of the SX1257 transmitter. It accepts the 1-bit I and Q noise shaped 32 Msample/second or 36 MSample/second bit-stream from the baseand processor and converts into two analog differential signals. Each TX DAC provides 8-bits of resolution in a 500 kHz bandwidth which corresponds to maximum RF transmitted double sideband bandwidth of 1 MHz. A programmable Finite Impulse Response (FIR) filter allows the removal of the digital modulator noise from the external baseband processor. The number of taps implemented by the FIR-DAC and subsequent single-side DAC bandwidth is controlled by the parameter TxDacBw. Table 10 TX DAC Single Sideband Bandwidth TxDacBw (Dec) TxDacBw (Bin) No. DAC-FIR Taps 0 000 24 1 001 32 2 010 40 3 011 48 4 100 56 5 101 64 SSB Filter BW (kHz) 450 290 Examples of the FIR DAC normalized magnitude response are illustrated below. Figure 6. FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 32 SX1257 Rev 1 February 2012 Page 17 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Figure 7. FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 64 The DAC 3dB bandwidth is proportional to the sampling frequency fs and inversely proportional to the number of taps N. In the case where fS = 32MHz with N = 32 the 3 dB bandwidth is typically 450 kHz. Reducing the bandwidth may be useful to reduce the quantisation noise contribution when the signal bandwidth request is lower, as is illustrated in the case where N = 64, resulting in a 3 dB bandwidth of approximately 290 kHz. 3.5.2. I and Q Serial Interface I and Q data is input to the DACs on the rising edge of the reference sampling clock and is sampled on a falling edge. The TX DAC can be used either with an external clock CLK_IN or with the internal clock, available on CLK_OUT for data synchronization (recommended mode). The I and Q channel bit stream timing diagram is illustrated below. tDATA tDATA CLK_IN OR CLK_OUT I/Q INPUT Figure 8. Transmitter I and Q Channel Bit-Stream Timing Diagram SX1257 Rev 1 February 2012 Page 18 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 3.6. Receiver Analog Front-End Description The SX1257 Receiver Front-End is based upon a Zero-IF architecture, ideally suited to handle multiple complex modulation schemes. The RX chain incorporates a programmable gain LNA and single to differential buffer, I / Q mixer, separate I and Q channel analog low-pass filters and programmable baseband amplifiers. The amplified differential analog I and Q outputs are input to two 5th order continuous-time Sigma-Delta Analog to Digital Converters (ADC) for further signal processing in the digital domain. 3.6.1. Architectural Description The block diagram of the receiver front-end block is illustrated below. LNA I-Channel Pre-Filter Single to Differential Balun I-Channel Baseband Amplifier I-Channel CT ΣΔ ADC RF_IN Differential I/Q Mixer Q-Channel CT ΣΔ ADC Q-Channel Pre-Filter RF LoopBack (From TX) Q-Channel Baseband Amplifier Div by 2 TX Fractional-N Frequency Synthesizer Figure 9. SX1257 Receiver Analog Front-End Block Diagram 3.6.2. LNA and Single to Differential Buffer The LNA uses a common-gate topology, which allows for a flat characteristic over the whole frequency range. It is designed to have an input impedance of 50 Ohms or 200 Ohms (as selected with bit LnaZin in RegRxAnaGain). A single to differential buffer is implemented to improve the second order linearity of the receiver. The LNA gain, including the single-to-differential buffer, is programmable over a 48 dB dynamic range, and gain control can be enabled via an external AGC function. 3.6.3. I /Q Downconversion Quadrature Mixer The mixer is inserted between output of the RF buffer stage and the input of the I and Q channel analog low-pass filter stages.This block is designed to downconvert the spectrum of the input RF signal to base-band and offers both high IIP2 and IIP3 responses. 3.6.4. Baseband Analog Filters and Amplifiers The differential I and Q baseband mixer signals are pre-filtered by a programmable 1st order low-pass pre-filter and input to programmable linear baseband amplifiers. The single sideband 3 dB bandwidth of the pre-filters can be programmed between 250 kHz and 750 kHz. This additional pre-filtering improves the selectivity of the receiver for complex modulation schemes, such as OFDM. SX1257 Rev 1 February 2012 Page 19 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS The amplifier stage gain offers 32 dB of programmable gain, in 2 dB steps, from -24 dB to +6 dB via configuration register RegRxAnaGain while the analog filter bandwidth is programmed via the two least significant bits of configuration register RegRxBw. 3.7. Receiver Digital Baseband The receiver digital baseband section contains separate I and Q channel continuous time Sigma-Delta analog-to-digital converters to digitize and filter the analog bit stream. 3.7.1. Architectural Block Diagram The block diagram of the receiver digital baseband is illustrated below. I-Channel Baseband Amplifier I(t) 1-bit serial stream I-Channel CT ΣΔ ADC Q-Channel CT ΣΔ ADC Q(t) 1-bit serial stream SX1257 LOGIC Q-Channel Baseband Amplifier DSP CLK_IN or CLK_OUT DSP INTERFACE Figure 10. SX1257 Digital Receiver Baseband Block Diagram 3.7.2. Analog-to-Digital Converters The receiver digital baseband consists of separate I and Q channel 5th order continuous-time sigma-delta modulator analog -to-digital converters which sample and digitize the analog baseband I and Q signals output at the analog baseband amplifiers. The ADC output allows for 13-bits of resolution after decimation and filtering by the external baseband processor within a 500 kHz maxium bandwidth, corresponding to a maximum RF received double sideband bandwidth of 1 MHz. The ADC output is one bit per channel quadrarure bit stream at 32 or 36 MSamples/s. 3.7.3. Temperature Sensor The receiver ADC can be used to perform a temperature measurement by digitizing the sensor response. The response of the sensor is -1C / Lsb. Since a CMOS temperature sensor is not accurate by nature, the sensor should be calibrated at ambient temperature for a precise reading. It takes less than 100 us for the SX1257 to evaluate the temperature (from setting RxAdcTemp = “1”). The AdcTemp value can be read at Q_OUT. Since there is no on-chip decimation or averaging it is recommmended that data on Q_OUT is externally processed, for example using a simple FFT. The temperature measurement should be performed with the SX1257 in StandbyEnable Mode (RegMode = 0x01) SX1257 Rev 1 February 2012 Page 20 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS RxAdcTemp -1°C/Lsb RxAdcTemp(t) RxAdcTemp(t-1) Returns 150d (typ.) Needs calibration -40°C t t+1 Ambient +85°C Figure 11. Temperature Sensor Response 3.7.4. I and Q Serial Interface I and Q data is input to the ADCs on the rising edge of the reference sampling clock and is sampled on a falling edge. The RX ADC can be used either with an external clock CLK_IN or with the internal clock, available on CLK_OUT (recommended mode) for data synchronization. The I and Q channel bit stream timing diagram is illustrated below. tDATA tDATA CLK_IN OR CLK_OUT I/Q OUTPUT Figure 12. Receiver I and Q Channel Bit-Stream Timing Diagram 3.8. Loop-Back The SX1257 provides mechanisms to both monitor and externally calibrate both the RF transmission path and the I and Q bit streams generated by the external baseband processor. 3.8.1. Digital Loop-Back The digital loop-back enables the connection of the input and output I and Q baseband bit streams prior to processing by the SX1257. This loop back path enables the validation of the transmitter and receiver baseband processing paths. SX1257 Rev 1 February 2012 Page 21 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 3.8.2. RF Loop Back The RF loop-back path connects the balanced RF output signal of the transmitter driver stage to the output of the differential mixer of the receiver. This path provides a mechanism for the external baseband processor to implement a calibration for the following: - Receiver I, Q gain mismatch - Receiver I and Q phase imbalance - Transmitter I, Q gain mismatch - Transmitter I and Q phase imbalance - Transmitter DC offset I-Channel Pre-Filter Single to Differential Balun LNA I-Channel Baseband Amplifier RF_IN Differential I/Q Mixer Q-Channel Pre-Filter RF Loop-Back I-Channel CT ΣΔ ADC I_OUT Q-Channel CT ΣΔ ADC Q_OUT Q-Channel Baseband Amplifier Digital Loop-Back Differential I-Channel Filter RF_OP Differential I/Q Mixer Driver RF_ON I-Channel DAC I_IN Q-Channel DAC Q_IN Differential Q-Channel Filter Figure 13. Digital and RF Loop-Back Paths SX1257 Rev 1 February 2012 Page 22 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 4. Digital Interface The SX1257 has several operating modes, configuration parameters and internal status indicators. All these operating modes, configuration parameters and status information are stored in internal registers that may be accessed by the external micro-controller via the serial SPI interface. 4.1. SPI Bus Interface The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented. Two access modes to the registers are provided: SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The NSS pin goes low at the begin of the frame and goes high after the data byte. BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the last byte transfer. An example of a typical SPI single access to a register is illustrated below. NSS SCK MOSI wnr A [6] A [5] A [4] A [3] A [2] A [1] A [0] MISO Dw [7] Dw [6] Dw [5] Dw [4] Dw [3] Dw [2] Dw [1] Dw [0] Dr [7] Dr [6] Dr [5] Dr [4] Dr [3] Dr [2] Dr [1] Dr [0] Figure 14. SPI Timing Diagram (Single Access) MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the rising edge of SCK. MISO is generated by the slave on the falling edge of SCK. A transfer always starts by the NSS pin going low. MISO is high impedance when NSS is high. The first byte is the address byte. It is made of: wnr bit, which is 1 for write access and 0 for read access 7 bits of address, MSB first The second byte is a data byte, either sent on MOSI by the master in case of a write access, or received by the master on MISO in case of read access. The data byte is transmitted MSB first. Succeeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without rising NSS and re-sending the address. The address is then automatically incremented at each new byte received (BURST mode). SX1257 Rev 1 February 2012 Page 23 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is actually a special case of BURST mode with only 1 data byte transferred. During the write accesses, the byte transferred from the slave to the master on the MISO line is the value of the written register before the write operation. 4.2. Digital IO Pin Mapping Four general purpose IO pins are available on the SX1257 and their configuration is controlled through the RegDioMapping configuration register. Table 11 DIO Mapping Mode Diox Mapping DIO3 DIO2 DIO1 DIO0 Sleep 00 - - - - 01 - - - - 10 - - - - 11 - - - 00 - xosc_ready - - 01 - - - - 10 - - - - 11 - - - - 00 pll_lock_rx - - pll_lock_rx 01 - - - pll_lock_rx 10 - - - pll_lock_rx 11 - - - Low Bat 00 pll_lock_tx - pll_lock_tx - 01 - - - - 10 - - - - 11 - - - - Standby RX TX SX1257 Rev 1 February 2012 Page 24 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 5. Configuration and Status Registers 5.1. General Description Table 12 Configuration Register Summary Address Register Name 0x00 RegMode 0x00 Operating modes of the SX1257 0x01 RegFrfRxMsb 0xCB RX carrier frequency MSB 0x02 RegFrfRxMid 0x55 RX carrier frequency intermediate bits 0x03 RegFrfRxLsb 0x55 RX carrier frequency LSB 0x04 RegFrfTxMsb 0x00 RX carrier frequency MSB 0x05 RegFrfTxxMid 0xCB RX carrier frequency intermediate bits 0x06 RegFrfTxLsb 0x55 RX carrier frequency LSB 0x07 RegVersion 0x01 Semtech ID relating to the silicon revision 0x08 RegTxGain 0x2E TX DAC and mixer gain setting 0x0A RegTxBw 0x30 TX FE PLL and analog filter bandwidths 0x0B RegTxDacBw 0x02 TX DAC bandwidth 0x0C RegRxAnaGain 0x3F RX FE LNA and baseband amplifier gain 0x0D RegRxBw 0xFD RX FE ADC and analog filter bandwidths 0x0E RegRxPLLBw 0x06 RX FE PLL bandwidth 0x0F RegDioMapping 0x00 Mapping of DIO pins 0x10 RegClkSelect 0x02 Sampling clock congfiguration 0x11 RegMode Status 0x00 SX1257 mode status 0x1A RegLowBatThres 0x02 Low battery threshold Notes Reset Value Default Value Description - Reset values are automatically refreshed at Power on Reset - DEFAULT values are the Semtech recommended register values, optimizing the device operation - Registers for which the DEFAULT value differs from the RESET values are denoted by a * in the tables of this section SX1257 Rev 1 February 2012 Page 25 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 5.2. Mode Configuration Registers Table 13 Mode Configuration Registers Name (Address) RegMode (0x00) Bits 7-4 Variable Name - Mode Default Value r 0000 Description unused 3 PADriverEnable rw 0 Enables the TX PA driver 0 = Disabled 1 = Enabled 2 TxEnable rw 0 Enables the TX front-end and PLL (except the TX PA driver) 0 = Disabled 1 = Enabled 1 RxEnable rw 0 Enables the RX front-end and PLL 0 = Disabled 1 = Enabled 0 StandbyEnable rw 1 Enables the PDS and the oscillator in Standby Mode 0 = Disabled 1 = Enabled 5.3. Frequency Synthesizer Configuration Registers Table 14 Frequency Synthesizer Configuration Registers Name (Address) Bits RegFrfRxMsb (0x01) 7-0 RefFrfRxMid (0x02) RefFrfRxLsb (0x03) Variable Name Mode Default Value Description FrfRx(23:16) rw 0xCB MSB of the RX carrier frequency 7-0 FrfRx(15:8) rw 0x55 Middle byte of the RX carrier frequency 7-0 FrfRx(7:0) rw 0x55 LSB of the RX carrier frequency F RF = F STEP × Frfxx ( 23, 0 ) With a 36 MHz XO default value 0xCB5555 FrfRx = 915 MHz and frequency resolution = 68.66455 Hz The RX RF frequency is updated only under the following conditions:Hz (36 MHz XO) - RefFrfRxLsb is written - When exiting SLEEP mode RegFrfTxMsb (0x04) SX1257 Rev 1 February 2012 7-0 FrfTx(23:16) rw 0xCB Page 26 ©2012 Semtech Corp. MSB of the TX carrier frequency www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Table 14 Frequency Synthesizer Configuration Registers Name (Address) Bits Variable Name Mode Default Value Description RefFrfTxMid (0x05) 7-0 FrfTx(15:8) rw 0x55 Middle byte of the TX carrier frequency RefFrfTxLsb (0x06) 7-0 FrfTx(7:0) rw 0x55 LSB of the TX carrier frequency F RF = F STEP × Frfxx ( 23, 0 ) With a 36 MHz XO default value 0xCB5555 FrfTx = 915 MHz and frequency resolution = 68.66455 Hz The TX RF frequency is updated only under the following conditions:Hz (36 MHz XO) - RefFrfTxLsb is written - When exiting SLEEP mode 5.4. Revision Configuration Register Table 15 Revision Configuration Register Name (Address) RegRevision (0x07) SX1257 Rev 1 February 2012 Bits 7-0 Variable Name Version Mode Default Value r 0x21 Page 27 ©2012 Semtech Corp. Description IC version code (Current revision V2A) www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 5.5. Transmitter Front-End Configuration Registers Table 16 Transmitter Front-End Configuration Registers Name (Address) RegTxGain (0x08) Bits 7 Variable Name - Mode Default Value r 0 Description Unused 6-4 TxDacGain rw 010 DAC gain, programmable in 3 dB steps: 000 = maximum gain - 9 dB 001 = maximum gain - 6 dB 010 = maximum gain - 3 dB 011 = maximum gain (0 dB full scale) 3-0 TXMixerGain rw 1110 Mixer gain, programmable in 2 dB steps: Gain ∼ – 38 + 2 × Int ( TxMixerGain ( 3, 0 ) ) dB RegTxBw (0x0A) 7 - r 0 unused TX PLL bandwidth, programmable: 00 = 75 kHz 01 = 150 kHz 10 = 225 kHz 11 = 300 kHz 6-5 TxPllBw rw 11 4-0 TxAnaBw rw 0000 TX analog filter bandwidth, programmable: 17.5 Bandwidth = ------------------------------------------------------------------- MHz 2 × ( 41 – Int ( TxBw ( 4, 0 ) ) ) RegTxDacBw (0x0B) 7-3 - 2-0 TxDacBw r 00000 rw 010 unused Number of taps of TX FIR-DAC, programmable: N = 24 + 8 × Int ( TxDacBw ( 2, 0 ) ) where NMAX = 64 SX1257 Rev 1 February 2012 Page 28 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 5.6. Receiver Front-End Configuration Registers Table 17 Receiver Front-End Configuration Registers Name (Address) RegRxAnaGain (0x0C) Bits Variable Name Mode Default Value Description 7-5 RxLnaGain rw 001 RX LNA gain setting: 000 = not used 001 = G1 = highest gain power - 0 dB 010 = G2 = highest gain power - 6 dB 011 = G3 = highest gain power - 12 dB 100 = G4 = highest gain power - 24 dB 101 = G5 = highest gain power - 36 dB 110 = G6 = highest gain power - 48 dB 111 = not used 4-1 RxBasebandGain rw 1111 RX Baseband amplifier gain, programmable: Gain = Gain + 2 × Int ( RxBasebandGain ( 4, 1 ) )dB 1 RegRxBw (0x0D) RegRxPLLBw (0x0E) LnaZin rw 1 7-5 RxAdcBw rw 111 RX ADC BW, programmable: 010 = 100 kHz < RxAdcBw < 200 kHz 101 = 200 kHz < RxAdcBw < 400 kHz 111 = 400kHz < RxAdcBw 4-2 RxAdcTrim rw 111 RX ADC trim 32 MHz reference crystal: RxAdcTrim = 110 36 MHz reference crystal: RxAdcTrim = 101 1-0 RxBasebandBw rw 01 Bandwidth of RX analog roofing filter, programmable: 00 = 750 kHz 01 = 500 kHz 10 = 375 kHz 11 = 250 kHz 7-3 - r 0000 2-1 RxPllBw rw 11 RX PLL bandwidth, programmable: 00 = 75 kHz 01 = 150 kHz 10 = 225 kHz 11 = 300 kHz RxAdcTemp rw 0 RX ADC temperature measurement mode 0 = Disabled 1 = Enabled 0 SX1257 Rev 1 February 2012 Page 29 ©2012 Semtech Corp. LNA input impedance 0 = 50 Ω 1 = 200 Ω unused www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 5.7. DIO Mapping Configuration Register Table 18 DIO Mapping Configuration Register Name (Address) Bits RegDioMapping (0x0F) Variable Name Mode Default Value 7-6 Dio0Mapping rw 00 5-4 Dio1Mapping rw 00 3-2 Dio2Mapping rw 00 1-0 Dio3Mapping rw 00 Description Mapping of pins DIO0 to DIO3. See Table 11for further information. 5.8. Additional Parameter Configuration Registers Table 19 Additional Parameters Configuration Registers Name (Address) Bits RegClkSelect (0x10) 7-4 RegModeStatus (0x11) SX1257 Rev 1 February 2012 Variable Name - Mode Default Value r 0000 Description unused 3 DigitalLoopBack rw 0 Digital loop back enable 0 = Disabled 1 = Enabled 2 RfLoopBack rw 0 RF Loop back enable for RX analog gain calibration 0 = Disabled 1 = Enabled 1 Clk_out rw 1 CLK_OUT enable 0 = Disabled 1 = Enabled 0 TxDacClkSelect rw 0 Clock select for TX DAC 0 = Internal clock (XTAL) 1 = External clock (CLK_IN) r 00000 rw 0 LowBat detect flag 0 = VBAT > LowBat threshold 1 = VBAT < LowBat threshold (low battery) 7-3 - unused 2 LowBatEnable 1 PllLockRx r 0 Asserted when RX PLL locked 0 PlllLockTx r 0 Asserted when TX PLL locked Page 30 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS Table 19 Additional Parameters Configuration Registers Name (Address) Bits RegLowBatThres (0x1A) 7-3 - 2-0 LowBatThres SX1257 Rev 1 February 2012 Variable Name Mode Default Value r 00000 rw 010 Page 31 ©2012 Semtech Corp. Description unused LowBat Threshold 000 = 2.516 V 001 = 2.619 V 010 = 2.724 V 011 = 2.829 V 100 = 2.935 V 101 = 3.037 V 110 = 3.143 V 111 = 3.245 V www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 6. Application Information 6.1. Crystal Resonator Specification The specification for the crystal resonator of the reference oscillator circuit block is tabulated below in Table 20. Table 20 Crystal Resonator Specification Symbol Description Min Typ Max Units FXOSC XTAL Frequency 32 - 36 MHz RS XTAL Series Resistance - 30 140 Ω C0 XTAL Shunt Capacitance - 2.8 7 pF CLOAD External Foot Capacitance 8 16 22 pF Notes Conditions On each pin XTA and XTB - The initial frequency tolerance, temperature stability and ageing performance should be chosen in accordance with the target operating temperature range and the receiver bandwidth selected - The loading capacitance should be applied externally, and adapted to the actual Cload specification of the XTAL 6.2. Reset of the Chip A power-on reset of the SX1257 is automatically triggered at power up. Additionally, a manual reset can be issued by controlling the RESET pin (pin 9). 6.2.1. POR If the application requires the disconnection of VDD from the SX1257, despite the extremely low Sleep Mode current, the user should wait for 10 ms from of the end of the POR cycle before commencing communications over the SPI bus. Pin 9 (RESET) should be left floating during the POR sequence. VDD Pin 9 (Output) Undefined Wait for 10 ms SX1257 is ready from this point on Figure 15. POR Timing Diagram Please note that CLK_OUT activity can be used to detect that the chip is ready. SX1257 Rev 1 February 2012 Page 32 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 6.2.2. Manual Reset A manual reset of the SX1257 is possible even for applications in which VDD cannot be physically disconnected. Pin 9 should be pulled high for a hundred microseconds, and then released. The user should then wait for 5 ms before using the chip. VDD Pin 9 (Input) High-Z “1” High-Z > 100 us Wait for 5 ms SX1257 is ready from this point on Figure 16. Manual Reset Timing Diagram Please note that whilst pin 9 is driven high, an over current consumption of 10 mA may be observed on VDD 6.3. TX Noise Shaper In order to generate a single TX bit-stream, th 8-bit I and Q signal should be processed by an external third order sigmadelta modulator (implemented within the baseband processor). The noise shaper should be stable for input signals lower than -3dBFS and compatible with SX1257 noise requirements. It is advised that the integrator outputs are saturated to avoid any wraparound of the 2’s-complement digital word. A representative block diagram of a single-bit feed-forward modulator is illustrated below. + OUTPUT + Sign INPUT + Z-1/(1-Z)-1 Z-1/(1-Z)-1 Z-1/(1-Z)-1 IDEAL Integrator (with Delay) IDEAL Integrator (with Delay) IDEAL Integrator (with Delay) + - Figure 17. Example Digital Modulator Implementation SX1257 Rev 1 February 2012 Page 33 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 6.4. Reference Design Please contact your Semtech representative for evaluation tools, reference designs and design assistance. Note that all schematics shown in this section are full schematics, listing ALL required components, including those required for power supply decoupling. Figure 18. SX1257 Application Schematic SX1257 Rev 1 February 2012 Page 34 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 7. Packaging Information 7.1. Package Outline Drawing A D B DIM PIN 1 INDICATOR (LASER MARK) A A1 A2 b D D1 E E1 e L N aaa bbb E A2 A SEATING PLANE aaa C DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX .028 .030 .031 - .002 .000 - (.008) .008 .010 .012 .193 .197 .201 .118 .122 .126 .193 .197 .201 .118 .122 .126 .020 BSC .012 .016 .020 32 .003 .004 0.70 0.75 0.80 - 0.05 0.00 - (0.20) 0.18 0.25 0.30 4.90 5.00 5.10 3.00 3.10 3.20 4.90 5.00 5.10 3.00 3.10 3.20 0.50 BSC 0.30 0.40 0.50 32 0.08 0.10 C A1 D1 LxN E/2 E1 2 1 N bxN e bbb C A B D/2 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. Figure 19. Package Outline Drawing 7.2. Recommended Land Pattern H (C) DIMENSIONS Z K G Y X DIM C G H K P X Y Z INCHES (.193) .161 .130 .130 .020 .012 .031 .224 MILLIMETERS (4.90) 4.10 3.30 3.30 0.50 0.30 0.80 5.70 P NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD SHALL BE CONNECTED TO A SYSTEM GROUND PLANE. FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR FUNCTIONAL PERFORMANCE OF THE DEVICE. 4. SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS. Figure 20. Recommended Land Pattern SX1257 Rev 1 February 2012 Page 35 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 7.3. Thermal Impedance The thermal impedance of this package is: Theta ja = 23.8° C/W typ., calculated from a package in still air, on a 4-layer FR4 PCB, as per the Jedec standard. 7.4. Tape and Reel Specification Carrier Tape (mm) Reel (mm) Tape Width (W) Pocket Pitch (P) AO / B O KO Reel Size 12 +/- 0.30 8 +/- 0.20 5.25 +/- 0.20 1.10 +/- 0.10 330.2 Note Reel Width Min. Trailer Length (mm) 12.4 400 Min. Leader Length (mm) QTY per Reel 400 3000 Single sprocket holes Figure 21. Tape and Reel Specification SX1257 Rev 1 February 2012 Page 36 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS 8. Chip Revisions SX1257 revision history is tabulated below in Figure 21. Table 21 Chip Revision Identification Chip Version Register Value @Address 0x07 V2A 0x21 Lot Codes (See Figure 3) - Comment - 9. Revision History Table 22 Datasheet Revision History Revision Date 1 February 2012 SX1257 Rev 1 February 2012 Comment First FINAL datasheet revision Page 37 ©2012 Semtech Corp. www.semtech.com SX1257 DATASHEET WIRELESS & SENSING PRODUCTS © Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Contact information Semtech Corporation Wireless and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 E-mail: E-mail Support Internet: http://www.semtech.com SX1257 Rev 1 February 2012 Page 38 ©2012 Semtech Corp. www.semtech.com