SPANSION S70FL256P_00

S70FL256P
256-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
S70FL256P Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S70FL256P_00
Revision 04
Issue Date June 24, 2011
D a t a
S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
S70FL256P
S70FL256P_00_04 June 24, 2011
S70FL256P
256-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
Distinctive Characteristics
Architectural Advantages
 Single power supply operation
– Full voltage range: 2.7 to 3.6V read and write operations
 Memory architecture
– Uniform 64 kB sectors
– Top or bottom parameter block (Two 64-kB sectors broken down
into sixteen 4-kB sub-sectors each) for each Flash die
– Uniform 256 kB sectors (no 4-kB sub-sectors)
– 256-byte page size
 Program
–
–
–
–
Page Program (up to 256 bytes) in 1.5 ms (typical)
Program operations are on a page by page basis
Accelerated programming mode via 9V W#/ACC pin
Quad Page Programming
 Erase
– Bulk erase function for each Flash die
– Sector erase (SE) command (D8h) for 64 kB and 256 kB sectors
– Sub-sector erase (P4E) command (20h) for 4 kB sectors
(for uniform 64-kB sector device only)
– Sub-sector erase (P8E) command (40h) for 8 kB sectors
(for uniform 64-kB sector device only)
 Cycling endurance
 One time programmable (OTP) area on each Flash die for
permanent, secure identification; can be programmed and
locked at the factory or by the customer
 CFI (Common Flash Interface) compliant: allows host system
to identify and accommodate multiple flash devices
 Process technology
– Manufactured on 0.09 µm MirrorBit® process technology
 Package option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 24-ball BGA (6 x 8 mm) package, 5 x 5 pin configuration
Performance Characteristics
 Speed
– Normal READ (Serial): 40 MHz clock rate
– FAST_READ (Serial): 104 MHz clock rate (maximum)
– DUAL I/O FAST_READ: 80 MHz clock rate or
20 MB/s effective data rate
– QUAD I/O FAST_READ: 80 MHz clock rate or
40 MB/s effective data rate
 Power saving standby mode
– Standby Mode 160 µA (typical)
– Deep Power-Down Mode 6 µA (typical)
– 100,000 cycles per sector typical
 Data retention
Memory Protection Features
– 20 years typical
 Memory protection
 Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward
compatibility
– W#/ACC pin works in conjunction with Status Register Bits to
protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status
General Description
This document contains information for the S70FL256P device, which is a dual die stack of two S25FL129P die. For detailed
specifications, please refer to the discrete die data sheet:
Document
Publication Identification Number (PID)
S25FL129P Data Sheet
S25FL129P_00
Publication Number S70FL256P_00
Revision 04
Issue Date June 24, 2011
D a t a
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Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
4
1.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
Simultaneous Die Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Sequential Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
Sector/Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
9.
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10.
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
10.1 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11.
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11.1 SL3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width) . . . . . . . . . . . 16
11.2 ZSA024 — 24-ball Ball Grid Array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
S70FL256P
11
11
11
11
11
11
11
11
S70FL256P_00_04 June 24, 2011
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Figures
Figure 2.1
Figure 2.2
Figure 9.1
Figure 10.1
June 24, 2011 S70FL256P_00_04
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
S70FL256P
5
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Tables
Table 5.1
Table 7.1
Table 8.1
Table 9.1
6
S70FL256P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
S70FL256P
S70FL256P_00_04 June 24, 2011
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1. Block Diagram
SI/IO0
W#/ACC/IO2
S I/IO 0
W #/A C C /IO 2
S O /IO 1
HOLD#/IO3
H O LD #/IO 3
SCK
SCK
CS#1
CS#
FL129P
Flash
Memory
SO/IO1
VSS
VSS
VCC
VCC
S I/IO 0
W #/A C C /IO 2
S O /IO 1
H O LD #/IO 3
SCK
CS#2
FL129P
Flash
Memory
VSS
CS#
VCC
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S70FL256P
7
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2.
S h e e t
Connection Diagrams
Figure 2.1 16-pin Plastic Small Outline Package (SO)
HOLD#/IO3
1
16
SCK
VCC
2
15
SI/IO0
DNC
3
14
DNC
DNC
4
13
DNC
DNC
5
12
DNC
CS2#
6
11
DNC
CS1#
7
10
GND
SO/IO1
8
9
W#/ACC/IO2
Note:
DNC = Do Not Connect (Reserved for future use)
Figure 2.2 6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration
1
2
3
4
5
DNC
DNC
DNC
DNC
DNC
SCK
GND
VCC
DNC
DNC
CS1#
CS2# W#/ACC/IO2 DNC
DNC
SO/IO1
SI/IO0 HOLD#/IO3 DNC
DNC
DNC
A
B
C
D
E
8
S70FL256P
DNC
DNC
DNC
S70FL256P_00_04 June 24, 2011
D a t a
3.
S h e e t
Input/Output Descriptions
Signal
I/O
Description
SO/IO1
I/O
Serial Data Output: Transfers data serially out of the device on the falling edge of SCK.
Functions as an I/O pin in Dual and Quad I/O, and Quad Page Program modes.
SI/IO0
I/O
Serial Data Input: Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK. Functions as an I/O pin in Dual
and Quad I/O mode.
SCK
Input
Serial Clock: Provides serial interface timing. Latches commands, addresses, and data on SI on
rising edge of SCK. Triggers output on SO after the falling edge of SCK.
Input
Chip Selects: Places one of the Flash die in active power mode when driven low. Deselects
Flash die and places SO at high impedance when high. After power-up, device requires a falling
edge on CS1# and CS2# before any command is written. Device is in standby mode when a
program, erase, or Write Status Register operation is not in progress.
HOLD#/IO3
I/O
Hold: Pauses any serial communication with the device without deselecting it. When driven low,
SO is at high impedance, and all input at SI and SCK are ignored. Requires that CS1# or CS2#
also be driven low. Functions as an I/O pin in Quad I/O mode.
W#/ACC/IO2
I/O
Write Protect: Protects the memory area specified by Status Register bits BP2:BP0. When
driven low, prevents any program or erase command from altering the data in the protected
memory area. Functions as an I/O pin in Quad I/O mode.
VCC
Input
Supply Voltage
GND
Input
Ground
CS1#
CS2#
4. Logic Symbol
VCC
SI/IO0
SO/IO1
SCK
CS1#
CS2#
W#/ACC/IO2
HOLD#/IO3
GND
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5.
S h e e t
Ordering Information
The ordering part number is formed by a valid combination of the following:
S70FL
256
P
0X
M
F
I
00
1
Packing Type (Note 1)
0
= Tray
1
= Tube
3
= 13” Tape and Reel
Model Number (Additional Ordering Options)
21 = BGA package, Uniform 256 kB sectors
20 = BGA package, Uniform 64 kB sectors
01 = SO package, Uniform 256 kB sectors
00 = SO package, Uniform 64 kB sectors
Temperature Range
I
=
Industrial (–40°C to + 85°C)
Package Materials
F
= Lead (Pb)-free
H
= Low-Halogen, Lead (Pb)-free
Package Type
M
= 16-pin SO package
B
= 24-ball BGA 6 x 8 mm package, 1.00 mm pitch
Speed
0X =
104 MHz
Device Technology
P
= 0.09 µm MirrorBit® Process Technology
Density
256 =
256 Mbit
Device Family
S70FL
Spansion Stacked Memory 3.0 Volt-Only, Serial Peripheral Interface (SPI) Flash Memory
5.1
Valid Combinations
Table 5.1 lists the valid combinations configurations planned to be supported in volume for this device.
Table 5.1 S70FL256P Valid Combinations Table
S70FL256P Valid Combinations
Base Ordering
Part Number
Speed Option
Package and
Temperature
MFI
S70FL256P
0X
BHI
Model
Number
00
01
20
21
Packing Type
0, 1, 3
0, 3
Package Marking
70FL256P0XMFI00
70FL256P0XMFI01
70FL256P0XBHI20
70FL256P0XBHI21
Note:
1. Package Marking omits the leading “S70” and speed, package and model number.
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6. Device Operations
6.1
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
6.2
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
6.3
Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the
user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then
read out of the second die via CS2#.
6.4
Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via
a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be
issued for each die.
6.5
Status Register
Each Flash die of the dual die stack is managed by its own Status Register. Reads and updates to the Status
Registers must be managed separately. It is recommended that Status Register control bit settings of each
die are kept identical to maintain consistency when switching between die.
6.6
Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the
Configuration Register control bits must be managed separately. It is recommended that Configuration
Register control bit settings of each die are kept identical to maintain consistency when switching between
die.
6.7
Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and
BPNV bits of each die must be managed separately. By default, each die is configured to be protected
starting at the top (highest address) of each array, but no address range is protected. It is recommended that
the Block Protection settings of each die are kept identical to maintain consistency when switching between
die.
7. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the
FL256P dual die stack will have identical identification data as the FL129P die, with the exception of the CFI
data at byte 27h, as shown in Table 7.1.
Table 7.1 Product Group CFI Device Geometry Definition
Byte
Data
Description
27h
19h
Device Size = 2^N byte
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8.
S h e e t
DC Characteristics
This section summarizes the DC Characteristics of the device. Designers should check that the operating
conditions in their circuit match the measurement conditions specified in the Test Specifications in Table 9.1
on page 13, when relying on the quoted parameters.
Table 8.1 DC Characteristics (CMOS Compatible)
Limits
Symbol
Parameter
Test Conditions
Unit
Min.
VCC
Supply Voltage
VHH
ACC Program Acceleration
Voltage
VIL
Typ. (1)
Max.
2.7
3.6
V
8.5
9.5
V
Input Low Voltage
-0.3
0.3 x VCC
V
VIH
Input High Voltage
0.7 x VCC
VCC +0.5
V
VOL
Output Low Voltage
IOL = 1.6 mA, VCC = VCC min.
VOH
Output High Voltage
IOH = -0.1 mA
VCC = 2.7V to 3.6V
0.4
VCC-0.6
V
V
ILI
Input Leakage Current
VCC = VCC Max,
VIN = VCC or GND
2
µA
ILO
Output Leakage Current
VCC = VCC Max,
VIN = VCC or GND
2
µA
At 80 MHz
(Dual or Quad)
44
ICC1
Active Power Supply Current READ
(SO = Open)
At 104 MHz (Serial)
32
At 40 MHz (Serial)
15
ICC2
Active Power Supply Current
(Page Program)
CS# = VCC
26
mA
ICC3
Active Power Supply Current
(WRR)
CS# = VCC
15
mA
ICC4
Active Power Supply Current
(SE)
CS# = VCC
26
mA
ICC5
Active Power Supply Current
(BE) (2)
CS# = VCC
26
mA
ISB1
Standby Current
CS# = VCC;
SO + VIN = GND or VCC
160
500
µA
IPD
Deep Power-down Current
CS# = VCC;
SO + VIN = GND or VCC
6
20
µA
mA
Notes:
1. Typical values are at TAI = 25°C and VCC = 3V.
2. Bulk Erase is on a die per die basis, not for the whole device.
12
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9. Test Conditions
Figure 9.1 AC Measurements I/O Waveform
0.8 VCC
0.7 VCC
0.5 VCC
0.3 VCC
Input Levels
0.2 VCC
Input and Output
Timing Reference levels
Table 9.1 Test Specifications
Symbol
Parameter
CL
Load Capacitance
Min
Max
30
Input Rise and Fall Times (1)
Unit
pF
5
ns
Input Pulse Voltage
0.2 VCC to 0.8 VCC
V
Input Timing Reference Voltage
0.3 VCC to 0.7 VCC
V
Output Timing Reference Voltage
0.5 VCC
V
Note:
1. Input rise and fall times are 0-100%.
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10. AC Characteristics
Figure 10.1 AC Characteristics
Symbol
(Notes)
fR
fC
Parameter
(Notes)
Min.
(Notes)
Typ
(Notes)
Max
(Notes)
Unit
SCK Clock Frequency for READ command
DC
40
MHz
SCK Clock Frequency for RDID command
DC
50
MHz
SCK Clock Frequency for all others:
FAST_READ, PP, QPP, P4E, P8E, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRR, READ_ID
DC
104 (serial)
80 (dual/quad)
MHz
tWH, tCH (5)
Clock High Time
4.5
ns
tWL, tCL (5)
Clock Low Time
4.5
ns
tCRT, tCLCH
Clock Rise Time (slew rate)
0.1
V/ns
tCFT, tCHCL
Clock Fall Time (slew rate)
0.1
V/ns
CS# High Time (Read Instructions)
CS# High Time (Program/Erase)
10
tCS (9)
ns
50
tCSS
CS# Active Setup Time (relative to SCK)
3
ns
tCSH
CS# Active Hold Time (relative to SCK)
3
ns
tSU:DAT
Data in Setup Time
3
ns
tHD:DAT
Data in Hold Time
2
ns
Clock Low to Output Valid
0
tHO
Output Hold Time
0
tDIS
Output Disable Time
tV
9 (Serial)
10.5 (Dual/Quad)
7.8 (Serial)
9 (Dual/Quad)
ns
8
ns
ns
tHLCH
HOLD# Active Setup Time (relative to SCK)
3
ns
tCHHH
HOLD# Active Hold Time (relative to SCK)
3
ns
tHHCH
HOLD# Non Active Setup Time (relative to SCK)
3
ns
tCHHL
HOLD# Non Active Hold Time (relative to SCK)
3
ns
tHZ
HOLD# enable to Output Invalid
8
ns
tLZ
HOLD# disable to Output Valid
8
ns
tWPS
W#/ACC Setup Time (4)
20
tWPH
W#/ACC Hold Time (4)
100
tW
WRR Cycle Time
tPP
Page Programming (1)(2)
tEP
Page Programming (ACC = 9V) (1)(2)(3)
Sector Erase Time (64 kB) (1)(2)
tSE
Sector Erase Time (256 kB) (1)(2)
ns
ns
50
ms
1.5
3
ms
1.2
2.4
ms
0.5
2
sec
2
8
sec
tBE
Bulk Erase Time (1)(2)(8)
128
256
sec
tPE
Parameter Sector Erase Time (4 kB or 8 kB) (1)(2)
200
800
ms
tRES
Deep Power-down to Standby Mode
30
µs
tDP
Time to enter Deep Power-down Mode
10
tVHH
ACC Voltage Rise and Fall time
tWC
ACC at VHH and VIL or VIH to first command
µs
2.2
µs
5
µs
Notes:
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0V; 10,000 cycles; checkerboard data pattern.
2. Under worst-case conditions of 85°C; VCC = 2.7V; 100,000 cycles.
3. Acceleration mode (9V ACC) only in Program mode, not Erase.
4. Only applicable as a constraint for WRR instruction when SRWD is set to a ‘1’.
5. tWH + tWL must be less than or equal to 1/fC.
6.  Full Vcc range (2.7 – 3.6V) and CL = 30 pF.
7.  Regulated Vcc range (3.0 – 3.6V) and CL = 30 pF.
8. Bulk Erase is on a die per die basis, not for the whole device.
9. When switching between die, a minimum time of tCS must be kept between the rising edge of one chip select and the falling edge of the
other for operations and data to be valid.
14
S70FL256P
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D a t a
10.1
S h e e t
Capacitance
Symbol
CIN
COUT
Parameter
Input Capacitance
(applies to CS1#, CS2#, SCK, SI/IO0, SO/IO1, W#/ACC/IO2, HOLD#/IO3)
Output Capacitance
(applies to SI/IO0, SO/IO1, W#/ACC/IO2, HOLD#/IO3)
Test
Conditions
Min
Max
Unit
VOUT = 0V
6
pF
VIN = 0V
8
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
3. For more information on pin capacitance, please consult the IBIS models.
June 24, 2011 S70FL256P_00_04
S70FL256P
15
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11. Physical Dimensions
11.1
SL3 016 — 16-pin Wide Plastic Small Outline Package (300-mil Body Width)
NOTES:
PACKAGE
JEDEC
SYMBOL
SL3016 (inches)
MS-013(D)AA
MIN
MAX
1.
ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS.
SL3016 (mm)
2.
DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994.
MS-013(D)AA
3.
DIMENSION D DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 mm
PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 mm PER SIDE. D AND E1
DIMENSIONS ARE DETERMINED AT DATUM H.
MIN
MAX
A
0.093
0.104
2.35
2.65
A1
0.004
0.012
0.10
0.30
A2
0.081
0.104
2.05
2.55
b
0.012
0.020
0.31
0.51
b1
0.011
0.019
0.27
0.48
c
0.008
0.013
0.20
0.33
c1
0.008
0.012
0.20
0.30
D
0.406 BSC
10.30 BSC
E
0.406 BSC
10.30 BSC
E1
0.295 BSC
7.50 BSC
e
L
.050 BSC
0.016
0.050
1.27 BSC
0.40
.055 REF
1.40 REF
L2
.010 BSC
0.25 BSC
16
0.10
0.30
0.25
0.75
θ
0°
8°
0°
8°
θ1
5°
15°
5°
0°
DATUMS A AND B TO BE DETERMINED AT DATUM H.
6.
"N" IS THE MAXIMUM NUMBER OF TERMINAL POSITIONS FOR
THE SPECIFIED PACKAGE LENGTH.
7.
THE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 TO 0.25 mm FROM THE LEAD TIP.
8.
DIMENSION "b" DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.10 mm TOTAL
IN EXCESS OF THE "b" DIMENSION AT MAXIMUM MATERIAL
CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OF THE LEAD FOOT.
9.
THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT,
THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX
AREA INDICATED.
10.
LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED
FROM THE SEATING PLANE.
15°
0°
THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE
BOTTOM. DIMENSIONS D AND E1 ARE DETERMINED AT THE
OUTMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF
MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD
FLASH. BUT INCLUDING ANY MISMATCH BETWEEN THE TOP
AND BOTTOM OF THE PLASTIC BODY.
5.
16
h
θ2
4.
1.27
L1
N
.
3644 \ 16-038.03 Rev C \ 02.03.10 (JK)
16
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D a t a
11.2
S h e e t
ZSA024 — 24-ball Ball Grid Array (6 x 8 mm) package
PACKAGE
ZSA024
JEDEC
N/A
DxE
SYMBOL
NOTES:
8.00 mm x 6.00 mm
PACKAGE
MIN
NOM
MAX
A
---
---
1.20
A1
0.20
---
---
A2
0.70
---
0.90
NOTE
PROFILE
BALL HEIGHT
BODY THICKNESS
D
8.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
D1
4.00 BSC.
MATRIX FOOTPRINT
E1
4.00 BSC.
MATRIX FOOTPRINT
MD
5
MATRIX SIZE D DIRECTION
ME
5
MATRIX SIZE E DIRECTION
n
Øb
24
0.35
0.40
DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
3.
BALL POSITION DESIGNATION PER JEP95, SECTION
4.3, SPP-010.
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
6
7
BALL DIAMETER
1.00 BSC.
BALL PITCH
eD
1.00 BSC
BALL PITCH
SD / SE
0.00
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE
CROWNS OF THE SOLDER BALLS.
BALL COUNT
0.45
eE
A1
1.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A
AND B AND DEFINE THE POSITION OF THE CENTER SOLDER
BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW SD OR SE = 0.000.
SOLDER BALL PLACEMENT
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
DEPOPULATED SOLDER BALLS
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3645 16-038.86 Rev A \ 02.26.10
June 24, 2011 S70FL256P_00_04
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12. Revision History
Section
Description
Revision 01 (March 3, 2010)
Initial release
Revision 02 (March 17, 2010)
Valid Combinations
Corrected Package Marking specification from discrete to MCP format
Read Identification (RDID)
Added section to explain CFI change from FL129P
Revision 03 (June 17, 2010)
General
Changed product description from “256-Mbit CMOS 3.0 Volt Flash Memory with 93-MHz SPI Serial
(Serial Peripheral Interface) Multi I/O Bus” to “256-Mbit CMOS 3.0 Volt Flash Memory with 104-MHz
SPI Serial (Serial Peripheral Interface) Multi I/O Bus”
Changed data sheet status from Advanced Information to Preliminary
Changed Normal READ clock rate from 36 to 40 MHz
Distinctive Characteristics
Changed FAST_READ maximum clock rate from 93 to 104 MHz
Changed DUAL I/O FAST_READ clock rate from 72 to 80 MHz and effective data rate from18 to
20 MB/s
Ordering Information
Changed description for Speed characters 0X from 93 to 104 MHz
Changed ILI (Input Leakage Current) value from ± 4 to ± 2 µA (max)
Changed ILO (Output Leakage Current) value from ± 4 to ± 2 µA (max)
Changed ICC1 (Active Power Supply Current - READ) test condition frequencies from 72/93/36 MHz
to 80/104/40 MHz
Changed ICC1 (Active Power Supply Current - READ) value @ 80 MHz (dual/quad) from 41.8 to
44 mA (max)
DC Characteristics
Changed ICC1 (Active Power Supply Current - READ) value @ 104 MHz (serial) from 27.5 to
32 mA (max)
Changed ICC1 (Active Power Supply Current - READ) value @ 40 MHz (serial) from13.2 to
15 mA (max)
Changed ICC2 (Active Power Supply Current - Page Program) value from 28.6 to 26 mA (max)
Changed ICC3 (Active Power Supply Current - WRR) value from 16.5 to 15 mA (max)
Changed ICC4 (Active Power Supply Current - SE) value from 28.6 to 26 mA (max)
Changed ICC5 (Active Power Supply Current - BE) value from 28.6 to 26 mA (max)
Added Note 2, clarifying that Bulk Erase is on a die per die basis, not for the whole device
Test Conditions
Added note clarifying that input rise and fall times are 0-100%
Changed fR (SCK Frequency for READ/RDID) values from 36/45 to 40/50 MHz (max)
Changed fC (SCK Frequency for others) values from 93/72 to 104/80 MHz (max)
Changed tV (Clock Low to Output Valid) values from 9.6/11.4/7.8/9.6 to 9/10.5/7.8/9 ns (max)
AC Characteristics
Added tBE (Bulk Erase Time)
Added Note 8 clarifying that Bulk Erase is on a die per die basis, not for the whole device
Added Note 9 clarifying that a minimum time of tCS must be kept between the rising edge of one chip
select and the falling edge of the other when switching between die for proper device functionality.
Merged CIN capacitance values into a single line item
Capacitance
Merged Single I/O, Dual I/O, and Quad I/O max capacitance values into a single line item
Added CIN / COUT (Input / Output Capacitance) values of 6/8 pF (max)
Added Notes clarifying test conditions
Revision 04 (June 24, 2011)
Global
18
Promoted data sheet designation from Preliminary to Full Production
S70FL256P
S70FL256P_00_04 June 24, 2011
D a t a
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2010-2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™,
EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries.
Other names used are for informational purposes only and may be trademarks of their respective owners.
June 24, 2011 S70FL256P_00_04
S70FL256P
19