LD49150XX08 LD49150XX10, LD49150XX12 1.5 A very low drop for low output voltage regulator Features ■ Input voltage range: – VI = 1.4 V to 5.5 V – VBIAS = 3 V to 6 V ■ Stable with ceramic capacitor ■ ±1.5 % initial tolerance ■ Maximum dropout voltage (VI - VO) of 200 mV over temperature ■ Adjustable output voltage down to 0.8 V ■ Ultra fast transient response (up to 10 MHz bandwidth) Description ■ Excellent line and load regulation specifications ■ Logic controlled shutdown option ■ Thermal shutdown and current limit protection ■ Junction temperature range: - 25 °C to 125 °C The LD49150xx is a high-bandwidth, low-dropout, 1.5 A voltage regulator, ideal for powering core voltages of low-power microprocessors. The LD49150xx implements a dual supply configuration allowing for very low output impedance and very fast transient response. The LD49150xx requires a bias input supply and a main input supply, allowing for ultra-low input voltages on the main supply rail. The input supply operates from 1.4 V to 5.5 V and the bias supply requires between 3 V and 6 V for proper operation. The LD49150xx offers fixed output voltages from 0.8 V to 1.8 V and adjustable output voltages down to 0.8 V. The LD49150xx requires a minimum output capacitance for stability, and work optimally with small ceramic capacitors. Applications ■ Graphics processors ■ PC add-in cards ■ Microprocessor core voltage supply ■ Low voltage digital ICs ■ High efficiency linear power supplies ■ SMPS post regulators Table 1. PPAK DFN6 (3x3 mm) Device summary Order codes PPAK (tape and reel) DFN6 (tape and reel) (1) Output voltages 0.8 V (2) LD49150PT08R LD49150PT10R LD49150PU10R 1.0 V LD49150PT12R LD49150PU12R 1.2 V 1. Available on request. 2. Adjustable version. June 2010 Doc ID 13446 Rev 3 1/22 www.st.com 22 Contents LD49150XX08, LD49150XX10, LD49150XX12 Contents 1 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Alternative application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 Input supply voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2 Bias supply voltage (VBIAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 Minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6 Power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.7 Power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 Heatsinking PPAK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.9 Adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10 Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 1 Typical application circuits Figure 1. Adjustable version Figure 2. Fixed version with Enable Doc ID 13446 Rev 3 Typical application circuits 3/22 Alternative application circuits LD49150XX08, LD49150XX10, LD49150XX12 2 Alternative application circuits Figure 3. Single supply voltage solution Figure 4. LD49150xx plus DC-DC pre-regulator to reduce power dissipation 4/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 Pin configuration 3 Pin configuration Figure 5. Pin connections (top view for PPAK, bottom view for DFN) PPAK DFN6 (3 x 3 mm) Table 2. Pin n° for PPAK 1 Pin description Pin n° for DFN Symbol Note EN For fixed versions: Enable (Input) - Logic High = Enable, Logic Low = Shutdown. ADJ For adjustable versions: Adjustable regulator feedback input. Connect to resistor voltage divider. Input voltage which supplies current to the output power device. 2 2 3 VIN 3 1 GND Ground (TAB is connected to ground). 4 4 VOUT Regulator output. 5 6 VBIAS Input bias voltage for powering all circuitry on the regulator with the exception of the output power device. 5 N.C. Not connect. Doc ID 13446 Rev 3 5/22 Diagram LD49150XX08, LD49150XX10, LD49150XX12 4 Diagram Figure 6. Block diagram 6/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 5 Maximum ratings Table 3. Absolute maximum ratings (1) Symbol Parameter Maximum ratings Value Unit VIN Supply voltage -0.3 to 7 V VOUT Output voltage -0.3 to VIN + 0.3 -0.3 to VBIAS + 0.3 V VBIAS BIAS supply voltage -0.3 to 7 V VEN Enable input voltage -0.3 to 7 V PD Power dissipation TSTG Internally limited Storage temperature range -50 to 150 °C 1. All the values are referred to ground. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4. Operating ratings Symbol Parameter Value Unit VIN Supply voltage 1.4 to 5.5 V VOUT Output voltage 0.8 to 4.5 V VBIAS BIAS supply voltage 3 to 6 V VEN Enable input voltage 0 to VBIAS V Junction temperature range -25 to 125 °C TJ Doc ID 13446 Rev 3 7/22 Electrical characteristics 6 LD49150XX08, LD49150XX10, LD49150XX12 Electrical characteristics TJ = - 25 °C to 125 °C, VBIAS = VO + 2.1 V (1); VI = VO+1 V; VEN = VBIAS (2), IO = 10 mA; CI = 1 µF; CO = 10 µF; CBIAS = 1 µF; unless otherwise specified. Typical values are referred to TJ = 25 °C. Table 5. Electrical characteristics Symbol VO Parameter Output voltage accuracy Test conditions Min. TJ = 25 °C, fixed voltage options -1.5 1.5 -3 3 -0.1 0.1 %/V 1 % 200 mV 1.5 2.1 V IL = 0 mA 4 6 IL = 1.5 A 4 6 Over temperature range VLINE Line regulation VI = VO + 1 V to 5.5 V VLOAD Load regulation IL = 0 mA to 3 A, VBIAS ≥ 3 V VDROP Dropout voltage (VI - VO) IL = 1.5 A VDROP Dropout voltage (VBIAS- VO) IL = 1.5 A (1) IGND IGND_SHD IVBIAS IL Ground pin current Ground pin current in shutdown Current through VBIAS Current limit Typ. Max. Unit % mA VEN ≤ 0.4 V (2) 5 IL = 0 mA 3 5 IL = 1.5 A 3 5 µA mA VO = 0 V 2.5 Regulator Enable 1.4 A Enable input (2) VEN Enable input threshold (fixed voltage only) IEN Enable pin input current V Regulator Shutdown 0.4 0.1 1 µA Reference VREF Reference voltage SVR Supply voltage rejection TJ = 25 °C 0.788 0.8 0.812 Over temperature range 0.776 0.8 0.824 V VI = 2.5 V ± 0.5 V, VO = 1 V, F = 120 Hz, VBIAS = 3.3 V 1. For VO ≤ 1 V, VBIAS dropout specification does not apply due to a minimum 3 V VBIAS input. 2. Fixed output voltage version only. 8/22 Doc ID 13446 Rev 3 68 dB LD49150XX08, LD49150XX10, LD49150XX12 Typical characteristics 7 Typical characteristics Figure 7. Reference voltage vs. temperature Figure 8. Figure 9. Load regulation vs. temperature Figure 10. Line regulation vs. temperature Figure 11. Output voltage vs. input voltage Output voltage vs. temperature Figure 12. Dropout voltage (VIN-VOUT) vs. temperature Doc ID 13446 Rev 3 9/22 Typical characteristics LD49150XX08, LD49150XX10, LD49150XX12 Figure 13. Dropout voltage (VIN-VOUT) vs. temperature Figure 14. VBIAS pin current vs. temperature Figure 15. Noise vs. frequency Figure 16. Quiescent current vs. temperature Figure 17. Supply voltage rejection vs. output Figure 18. Stability region vs. COUT & High current ESR 10/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 Typical characteristics Figure 19. Stability region vs. COUT & low ESR Figure 20. VBIAS & VIN start up transient response (VIN and VBIAS start up at the same time) VIN=VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF Figure 21. VIN start up transient response (VBIAS start up before VIN) Figure 22. VIN start up transient response (VBIAS start up before VIN) VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF VIN=2.5V, VBIAS=VINH=3.1V, VOUT=1V, COUT=1µF Doc ID 13446 Rev 3 11/22 Typical characteristics LD49150XX08, LD49150XX10, LD49150XX12 Figure 23. VIN start up transient response (VBIAS start up before VIN and VINH=VIN) VIN=VINH=2.5V, VBIAS=3.1V, VOUT=1V, COUT=1µF 12/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 8 Application hints Application hints The LD49150xx is an ultra-high performance, low dropout linear regulator, designed for high current application that requires fast transient response. The LD49150xx operates from two input voltages, to reduce dropout voltage. The LD49150xx is designed so that a minimum of external component are necessary. 8.1 Input supply voltage (VIN) VIN provides the power input current to the LD49150xx. The minimum input voltage can be as low as 1.4 V, allowing conversion from very low voltage supplies to achieve low output voltage levels with very low power dissipation. 8.2 Bias supply voltage (VBIAS) The LD49150xx control circuitry is supplied the VBIAS pin which requires a very low bias current (3 mA typ.) even at the maximum output current level (1.5 A). A bypass capacitor on the bias pin is recommended to improve the performance of the LD49150xx during line and load transient. The small ceramic capacitor from VBIAS to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. In typical applications a 1 µF ceramic chip capacitor may be used. The VBIAS input voltage must be 2.1 V above the output voltage, with a minimum VBIAS input voltage of 3 V. 8.3 External capacitors To assure regulator stability, input and output capacitors are required as shown in the 1: Typical application circuits. 8.4 Output capacitor The LD49150xx requires a minimum output capacitance to maintain stability. A ceramic chip capacitor of at least 1 µF is required. However, specific capacitor selection could be needed to ensure the transient response. A 1 µF ceramic chip capacitor satisfies most applications but 10 µF is recommended to ensure better transient performances. In applications where the VIN level is close to the maximum operating voltage (VIN > 4 V), it is strongly recommended to use an output capacitors of, at least, 10 µF in order to avoid over-voltage stress on the Input/output power pins during short circuit conditions due to parasitic inductive effect. The output capacitor must be located as close as possible to the output pin of the LD49150xx. The ESR (equivalent series resistance) of the output capacitor must be within the "stable" region as shown in the typical characteristics figures. Both ceramic and tantalum capacitors are suitable. 8.5 Minimum load current The LD49150xx does not require a minimum load to maintain output voltage regulation. Doc ID 13446 Rev 3 13/22 Application hints 8.6 LD49150XX08, LD49150XX10, LD49150XX12 Power sequencing recommendations In order to ensure the correct biasing and settling of the regulator internal circuitry during the startup phase, as well as to avoid overvoltage spikes at the output, it is recommended to provide for the correct power sequencing. As a general rule the VIN and VINH signals timings at startup should be chosen properly, so that they are applied to the device after the VBIAS voltage is already settled at its minimum operative value (see paragraph 8.2: Bias supply voltage (VBIAS)). This can be achieved, for instance, by avoiding too slow VBIAS rising edges (Tr >10 ms). Provided that the above condition is satisfied, when fast VIN transient input (Tr < 100 µs) is present, a smooth startup, with limited overvoltage on the output, can be obtained by applying VIN voltage at the same time as the VBIAS voltage (refer to Figure 20, Figure 21 and Figure 22 on page 11). In the fixed voltage versions it is possible to reduce overvoltage spikes during very fast startup (Tr << 100 µs) by pulling the VINH pin up to VIN voltage (see Figure 23 on page 12). 8.7 Power dissipation/heatsinking A heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. Under all possible conditions, the junction temperature must be within the range specified under operating conditions. The total power dissipation of the device is given by: PD = VIN x IIN + VBIAS x IBIAS - VOUT x IOUT Where: ● VIN, input supply voltage ● VBIAS, bias supply voltage ● VOUT, output voltage ● IOUT, load current From this data, we can calculate the thermal resistance (θSA) required for the heat sink using the following formula: θSA = (TJ - TA/PD) - (θJC + θCS) The maximum allowed temperature rise (TRmax) depends on the maximum ambient temperature (TAmax) of the application, and the maximum allowable junction temperature (TJmax): TRmax = TJmax - TAmax The maximum allowable value for junction to ambient thermal resistance, θJA, can be calculated using the formula: θJAmax = TRmax / PD This part is available for the PPAK package. The thermal resistance depends on the amount of copper area or heat sink, and on air flow. If the maximum allowable value of θJA calculated above is ≥ 100 °C/W for the PPAK package, no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. If the value for allowable θJA falls below these limits, a heat sink is required as described below. 14/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 8.8 Application hints Heatsinking PPAK package The PPAK package uses the copper plane on the PCB as a heatsink. The tab of these packages is soldered to the copper plane for heat sinking. It is also possible to use the PCB ground plane a heatsink. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, it can be an unbroken GND area on the opposite side where the IC is situated with a dissipating area thermally connected through vias holes, filled by solder. Figure 26 shows a curve for θJA of the PPAK package for different copper area sizes, using a typical PCB with 1/16 in thick G10/FR4. Figure 24. θJA vs. copper area for PPAK package 8.9 Adjustable regulator design The LD49150xx adjustable version allows fixing output voltage anywhere between 0.8 V and 4.5 V using two resistors as shown in the typical application circuit. For example, to fix the R1 resistor value between VOUT and the ADJ pin, the resistor value between ADJ and GND (R2) is calculated by: R2 = R1 [0.8/(VOUT - 0.8)] Where VOUT is the desired output voltage. It is suggested to use R1 values lower than 10 kΩ to obtain better load transient performances. Even, higher values up to 100 kΩ are suitable. 8.10 Enable The fixed output voltage versions of LD49150xx feature an active high Enable input (EN) that allows on-off control of the regulator. The EN input threshold is guaranteed between 0.4 V and 1.4 V, for simple logic interfacing. The regulator is set in shut down mode when VEN < 0.4 V and it is in operating mode (VOUT activated) when VEN > 1.4 V. If not in use, the EN pin must be tied directly to the VIN to keep the regulator continuously activated. The En pin must not be left at high impedance. Doc ID 13446 Rev 3 15/22 Package mechanical data 9 LD49150XX08, LD49150XX10, LD49150XX12 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 16/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 Package mechanical data PPAK mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.4 0.6 0.015 0.023 B2 5.2 5.4 0.204 0.212 0.023 C 0.45 0.6 0.017 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 6.6 0.252 D1 E 5.1 6.4 E1 0.201 4.7 e 0.260 0.185 1.27 0.050 G 4.9 5.25 0.193 0.206 G1 2.38 2.7 0.093 0.106 H 9.35 10.1 0.368 L2 0.8 L4 0.6 L5 1 L6 1 1 2.8 0.031 0.023 0.039 0.397 0.039 0.039 0.110 0078180-E Doc ID 13446 Rev 3 17/22 Package mechanical data LD49150XX08, LD49150XX10, LD49150XX12 DFN6 (3x3 mm) mechanical data mm. inch. Dim. Min. Typ. Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0 0.02 0.05 0 0.001 0.002 A3 0.20 0.008 b 0.23 0.30 0.38 0.009 0.012 0.015 D 2.90 3.00 3.10 0.114 0.118 0.122 D2 2.23 2.38 2.48 0.088 0.094 0.098 E 2.90 3.00 3.10 0.114 0.118 0.122 E2 1.50 1.65 1.75 0.059 0.065 0.069 e L 0.95 0.30 0.40 0.037 0.50 0.012 0.016 0.020 7946637A 18/22 Doc ID 13446 Rev 3 LD49150XX08, LD49150XX10, LD49150XX12 Package mechanical data Tape & reel DPAK-PPAK mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 13.0 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 Max. 0.504 0.512 22.4 0.519 0.882 Ao 6.80 6.90 7.00 0.268 0.272 0.2.76 Bo 10.40 10.50 10.60 0.409 0.413 0.417 Ko 2.55 2.65 2.75 0.100 0.104 0.105 Po 3.9 4.0 4.1 0.153 0.157 0.161 P 7.9 8.0 8.1 0.311 0.315 0.319 Doc ID 13446 Rev 3 19/22 Package mechanical data LD49150XX08, LD49150XX10, LD49150XX12 Tape & reel QFNxx/DFNxx (3x3) mechanical data mm. inch. Dim. Min. Typ. A Min. Typ. 180 13.2 12.8 D 20.2 0.795 N 60 2.362 0.504 0.519 14.4 0.567 Ao 3.3 0.130 Bo 3.3 0.130 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 13446 Rev 3 Max. 7.087 C T 20/22 Max. LD49150XX08, LD49150XX10, LD49150XX12 10 Revision history Table 6. Document revision history Revision history Date Revision Changes 18-Apr-2007 1 Initial release. 12-Jan-2009 2 Added new package DFN6 (3x3 mm) and mechanical data. 29-Jun-2010 3 Modified Section 8.6: Power sequencing recommendations on page 14. Doc ID 13446 Rev 3 21/22 LD49150XX08, LD49150XX10, LD49150XX12 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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