STMICROELECTRONICS SPC56EL60L5

SPC56EL60x, SPC56EL54x
SPC564L60x, SPC564L54x
32-bit Power Architecture® microcontroller for automotive
SIL3/ASILD chassis and safety applications
Datasheet − production data
Features
■
■
■
High-performance e200z4d dual core
– 32-bit Power Architecture® technology CPU
– Core frequency as high as 120 MHz
– Dual issue five-stage pipeline core
– Variable Length Encoding (VLE)
– Memory Management Unit (MMU)
– 4 KB instruction cache with error detection
code
– Signal processing engine (SPE)
LQFP144 (20 x 20 x 1.4 mm)
LQFP100 (14 x 14x 1.4 mm)
■
Decoupled Parallel mode for high-performance
use of replicated cores
■
Nexus Class 3+ interface
Memory available
– Up to 1 MB flash memory with ECC
– Up to 128 KB on-chip SRAM with ECC
– Built-in RWW capabilities for EEPROM
emulation
■
Interrupts
– Replicated 16-priority controller
– Replicated 16-channel eDMA controller
■
GPIOs individually programmable as input,
output or special function
SIL3/ASILD innovative safety concept:
LockStep mode and Fail-safe protection
– Sphere of replication (SoR) for key
components (such as CPU core, eDMA,
crossbar switch)
– Fault collection and control unit (FCCU)
– Redundancy control and checker unit
(RCCU) on outputs of the SoR connected
to FCCU
– Boot-time Built-In Self-Test for Memory
(MBIST) and Logic (LBIST) triggered by
hardware
– Boot-time Built-In Self-Test for ADC and
flash memory triggered by software
– Replicated safety enhanced watchdog
– Replicated junction temperature sensor
– Non-maskable interrupt (NMI)
– 16-region memory protection unit (MPU)
– Clock monitoring units (CMU)
– Power management unit (PMU)
– Cyclic redundancy check (CRC) unit
■
Three 6-channel general-purpose eTimer units
■
2 FlexPWM units
– Four 16-bit channels per module
■
Communications interfaces
– 2 LINFlexD channels
– 3 DSPI channels with automatic chip select
generation
– 2 FlexCAN interfaces (2.0B Active) with 32
message objects
– FlexRay module (V2.1 Rev. A) with 2
channels, 64 message buffers and data
rates up to 10 Mbit/s
■
Two 12-bit analog-to-digital converters (ADCs)
– 16 input channels
– Programmable cross triggering unit (CTU)
to synchronize ADCs conversion with timer
and PWM
■
Sine wave generator (D/A with low pass filter)
■
On-chip CAN/UART bootstrap loader
■
Single 3.0 V to 3.6 V voltage supply
■
Ambient temperature range –40 °C to 125 °C
■
Junction temperature range –40 °C to 150 °C
August 2012
This is information on a product in full production.
Doc ID 15457 Rev 8
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www.st.com
1
Contents
SPC56XL60/54
Contents
1
2/160
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1
Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3
Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5
Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.1
High-performance e200z4d core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.5.2
Crossbar switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.3
Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.5.4
Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . 13
1.5.5
On-chip flash memory with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.6
On-chip SRAM with ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5.7
Platform flash memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.8
Platform Static RAM Controller (SRAMC) . . . . . . . . . . . . . . . . . . . . . . . 15
1.5.9
Memory subsystem access time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.10
Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.11
Peripheral bridge (PBRIDGE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.12
Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.5.13
System clocks and clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.14
Frequency-Modulated Phase-Locked Loop (FMPLL) . . . . . . . . . . . . . . 18
1.5.15
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.16
Internal Reference Clock (RC) oscillator . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.17
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5.18
Periodic Interrupt Timer Module (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.19
System Timer Module (STM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.20
Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.21
Fault Collection and Control Unit (FCCU) . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.22
System Integration Unit Lite (SIUL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.23
Non-Maskable Interrupt (NMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.24
Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.25
System Status and Configuration Module (SSCM) . . . . . . . . . . . . . . . . 21
1.5.26
FlexCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.27
FlexRay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Contents
1.5.28
Serial communication interface module (LINFlexD) . . . . . . . . . . . . . . . . 24
1.5.29
Deserial Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . 24
1.5.30
FlexPWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5.31
eTimer module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.32
Sine Wave Generator (SWG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.5.33
Analog-to-Digital Converter module (ADC) . . . . . . . . . . . . . . . . . . . . . . 27
1.5.34
Cross Triggering Unit (CTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.35
Cyclic Redundancy Checker (CRC) Unit . . . . . . . . . . . . . . . . . . . . . . . . 29
1.5.36
Redundancy Control and Checker Unit (RCCU) . . . . . . . . . . . . . . . . . . 29
1.5.37
Junction temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.38
Nexus Port Controller (NPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.39
IEEE 1149.1 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.40
Voltage regulator / Power Management Unit (PMU) . . . . . . . . . . . . . . . 31
1.5.41
Built-In Self-Test (BIST) capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 33
2.1
Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.2
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.4.1
General notes for specifications at maximum junction temperature . . 101
3.5
Electromagnetic Interference (EMI) characteristics . . . . . . . . . . . . . . . . 102
3.6
Electrostatic discharge (ESD) characteristics . . . . . . . . . . . . . . . . . . . . 103
3.7
Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.8
Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 104
3.9
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.10
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
3.11
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . 111
3.12
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 111
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Contents
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3.13
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.14
16 MHz RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . 114
3.15
ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.15.1
3.16
Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.17
SWG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.18
AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.18.1
3.19
3.20
4
Input Impedance and ADC Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Pad AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.19.1
Reset sequence duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.19.2
Reset sequence description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.19.3
Reset sequence trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.19.4
Reset sequence — start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.19.5
External watchdog window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
AC timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.20.1
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.20.2
WKUP/NMI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.20.3
IEEE 1149.1 JTAG interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.20.4
Nexus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.20.5
External interrupt timing (IRQ pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
3.20.6
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
4.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
SPC56XL60/54 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Platform memory access time summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LQFP100 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
LQFP144 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LFBGA257 pin function summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Recommended operating conditions (3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Thermal characteristics for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Thermal characteristics for LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Thermal characteristics for LFBGA257 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EMI configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EMI emission testing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Latch-up results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Recommended operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Voltage regulator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Current consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
FMPLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RC oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
ADC conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Flash memory program and erase electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 120
Flash memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Flash memory module life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
MPC5643L SWG Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Pad AC specifications (3.3 V , IPP_HVE = 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
RESET sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Reset sequence trigger — reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Voltage Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
RESET electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
WKUP/NMI glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DSPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
LQFP100 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
LFBGA257 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
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List of figures
SPC56XL60/54
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
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Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
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SPC56XL60/54 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SPC56XL60/54 LQFP144 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPC56XL60/54 LFBGA257 pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
BCP68 board schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Crystal oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Main oscillator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
ADC characteristics and error definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Input Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Transient Behavior during Sampling Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Spectral representation of input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Pad output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Destructive Reset Sequence, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Destructive Reset Sequence, BIST disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
External Reset Sequence Long, BIST enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Functional Reset Sequence Long. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Functional Reset Sequence Short . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Reset sequence start for Destructive Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Reset sequence start via RESET assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Reset sequence - External watchdog trigger window position . . . . . . . . . . . . . . . . . . . . . 129
Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Nexus output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Nexus EVTI Input Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Nexus Double Data Rate (DDR) Mode output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Nexus TDI, TMS, TDO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
External interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
DSPI classic SPI timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
DSPI classic SPI timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DSPI classic SPI timing — slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DSPI classic SPI timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
DSPI modified transfer format timing — master, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . 140
DSPI modified transfer format timing — master, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . 141
DSPI modified transfer format timing – slave, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . 141
DSPI modified transfer format timing — slave, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . 142
DSPI PCS strobe (PCSS) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
LQFP100 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
LQFP144 package mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
LFBGA257 package mechanical drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Commercial product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Doc ID 15457 Rev 8
SPC56XL60/54
1
Introduction
1.1
Document overview
Introduction
This document describes the features of the family and options available within the family
members, and highlights important electrical and physical characteristics of the devices.
This document provides electrical specifications, pin assignments, and package diagrams
for the SPC56XL60/54 series of microcontroller units (MCUs). For functional
characteristics, see the SPC56XL60/54 Microcontroller Reference Manual. For use of the
SPC56XL60/54 in a fail-safe system according to safety standard IEC 61508, see the
Safety Application Guide for SPCEL60.
1.2
Description
The Leopard series microcontrollers are system-on-chip devices that are built on Power
Architecture technology and contain enhancements that improve the architecture’s fit in
embedded applications, include additional instruction support for digital signal processing
(DSP) and integrate technologies such as an enhanced time processor unit, enhanced
queued analog-to-digital converter, Controller Area Network, and an enhanced modular
input-output system.
The SPC56XL60/54 family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding range of automotive-focused
products designed to address electrical hydraulic power steering (EHPS), electric power
steering (EPS) and airbag applications. The advanced and cost-efficient host processor
core of the SPC56XL60/54 automotive controller family complies with the Power
Architecture embedded category. It operates at speeds as high as 120 MHz and offers highperformance processing optimized for low power consumption. It capitalizes on the available
development infrastructure of current Power Architecture devices and is supported with
software drivers, operating systems and configuration code to assist with users’
implementations.
1.3
Device comparison
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Introduction
Table 1.
SPC56XL60/54
SPC56XL60/54 device summary
Feature
SPC56EL60
SPC56EL54
2 × e200z4
(in lock-step or decoupled
operation)
2 × e200z4
(in lock-step or decoupled
operation)
Harvard
Harvard
0–120 MHz (+2% FM)
0–120 MHz (+2% FM)
>240 MIPS
>240 MIPS
Yes
Yes
16 entry
16 entry
Instruction set PPC
Yes
Yes
Instruction set VLE
Yes
Yes
Instruction cache
4 KB, EDC
4 KB, EDC
MPU-16 regions
Yes, replicated module
Yes, replicated module
Yes
Yes
Type
Architecture
Execution speed
DMIPS intrinsic performance
CPU
SIMD (DSP + FPU)
MMU
Semaphore unit (SEMA4)
Core bus
AHB, 32-bit address, 64-bit data AHB, 32-bit address, 64-bit data
Buses
Internal periphery bus
Crossbar
Master × slave ports
Flash
32-bit address, 32-bit data
32-bit address, 32-bit data
Lock Step Mode: 4 × 3
Lock Step Mode: 4 × 3
Decoupled Parallel Mode: 6 × 3 Decoupled Parallel Mode: 6 × 3
1 MB, ECC, RWW
768 K, ECC, RWW
128 KB, ECC
96 KB, ECC
Memory
Static RAM (SRAM)
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SPC56XL60/54
Table 1.
Introduction
SPC56XL60/54 device summary (continued)
Feature
SPC56EL60
SPC56EL54
16 interrupt levels, replicated
module
16 interrupt levels, replicated
module
Periodic Interrupt Timer (PIT)
1 × 4 channels
1 × 4 channels
System Timer Module (STM)
1 × 4 channels, replicated
module
1 × 4 channels, replicated
module
Yes, replicated module
Yes, replicated module
16 channels, replicated module
16 channels, replicated module
FlexRay
1 × 64 message buffers, dual
channel
1 × 64 message buffers, dual
channel
FlexCAN
2 × 32 message buffers
2 × 32 message buffers
2
2
Clock out
Yes
Yes
Fault Collection and Control Unit
(FCCU)
Yes
Yes
Cross Triggering Unit (CTU)
Yes
Yes
3 × 6 channels(1)
3 × 6 channels(1)
Interrupt Controller (INTC)
Software Watchdog Timer
(SWT)
eDMA
Modules
LINFlexD (UART and LIN with
DMA support)
eTimer
FlexPWM
2 Module 4 × (2 + 1) channels(2) 2 Module 4 × (2 + 1) channels(2)
Analog-to-Digital Converter
(ADC)
2 × 12-bit ADC, 16 channels per 2 × 12-bit ADC, 16 channels per
ADC
ADC
(3 internal, 4 shared and 9
(3 internal, 4 shared and 9
external)
external)
Sine Wave Generator (SWG)
32 point
32 point
3 × DSPI
as many as 8 chip selects
3 × DSPI
as many as 8 chip selects
Cyclic Redundancy Checker
(CRC) unit
Yes
Yes
Junction temperature sensor
(TSENS)
Yes, replicated module
Yes, replicated module
≥ 16
≥ 16
3.3 V with integrated
bypassable ballast transistor
External ballast transistor not
needed for bare die
3.3 V with integrated
bypassable ballast transistor
External ballast transistor not
needed for bare die
3.0 V – 3.6 V and 4.5 V – 5.5 V
3.0 V – 3.6 V and 4.5 V – 5.5 V
2
2
16 MHz
16 MHz
4 – 40 MHz
4 – 40 MHz
Deserial Serial Peripheral
Interface (DSPI)
Modules
(cont.)
Digital I/Os
Device power supply
Supply
Analog reference voltage
Frequency-modulated phaselocked loop (FMPLL)
Clocking
Internal RC oscillator
External crystal oscillator
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Introduction
Table 1.
SPC56XL60/54
SPC56XL60/54 device summary (continued)
Feature
Debug
SPC56EL60
SPC56EL54
Nexus
Level 3+
Level 3+
LQFP
100 pins
144 pins
100 pins
144 pins
LBGA(3)
LBGA257
LBGA257
–40 to 150 °C
–40 to 150 °C
–40 to 125 °C
–40 to 125 °C
Packages
Temperature range (junction)
Temperature Ambient temperature range
using external ballast transistor
(LQFP)
1. The third eTimer (eTimer_2) is available with external I/O access only in the BGA package, on the LQFP package
eTimer_2 is available internally only without any external I/O access.
2. The second FlexPWM module is available only in the BGA package.
3. LBGA257 available only as development package.
1.4
Block diagram
Figure 1 shows a top-level block diagram of the SPC56XL60/54 device.
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Introduction
PMU
JTAG
Nexus
e200z4
SWT
ECSM
STM
INTC
SPE
VLE
VLE
ECSM
STM
INTC
MMU
FlexRay
I-CACHE
eDMA
SWT
SPE
MMU
SEMA4
e200z4
SEMA4
I-CACHE
RC
eDMA
Crossbar Switch
Crossbar Switch
Memory Protection Unit
Memory Protection Unit
ECC logic for SRAM
ECC logic for SRAM
PBRIDGE
RC
TSENS
PBRIDGE
RC
Flash memory
ECC bits + logic
TSENS
SRAM
ECC bits
ADC
BAM
CMU
CRC
CTU
DSPI
ECC
ECSM
eDMA
FCCU
FlexCAN
FMPLL
INTC
IRCOSC
JTAG
– Analog-to-Digital Converter
– Boot Assist Module
– Clock Monitoring Unit
– Cyclic Redundancy Check unit
– Cross Triggering Unit
– Serial Peripherals Interface
– Error Correction Code
– Error Correction Status Module
– Enhanced Direct Memory Access controller
– Fault Collection and Control Unit
– Controller Area Network controller
– Frequency Modulated Phase Locked Loop
– Interrupt Controller
– Internal RC Oscillator
– Joint Test Action Group interface
Figure 1.
LINFlexD
MC
PBRIDGE
PIT
PMU
RC
RTC
SEMA4
SIUL
SSCM
STM
SWG
SWT
TSENS
XOSC
PIT
FCCU
SWG
CRC
DSPI
DSPI
DSPI
LINFlexD
LINFlexD
FlexCAN
FlexCAN
eTimer
eTimer
eTimer
FlexPWM
FlexPWM
CMU
IRCOSC
ADC
CTU
FMPLL
WakeUp
CMU
Secondary FMPLL
SIUL
CMU
SSCM
XOSC
ADC
BAM
MC
RC
– LIN controller with DMA support
– Mode Entry, Clock, Reset, & Power
– Peripheral bridge
– Periodic Interrupt Timer
– Power Management Unit
– Redundancy Checker
– Real Time Clock
– Semaphore Unit
– System Integration Unit Lite
– System Status and Configuration Module
– System Timer Module
– Sine Wave Generator
– Software Watchdog Timer
– Temperature Sensor
– Crystal Oscillator
SPC56XL60/54 block diagram
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Introduction
SPC56XL60/54
1.5
Feature details
1.5.1
High-performance e200z4d core
The e200z4d Power Architecture® core provides the following features:
●
●
●
2 independent execution units, both supporting fixed-point and floating-point operations
Dual issue 32-bit Power Architecture technology compliant
–
5-stage pipeline (IF, DEC, EX1, EX2, WB)
–
In-order execution and instruction retirement
Full support for Power Architecture instruction set and Variable Length Encoding (VLE)
–
Mix of classic 32-bit and 16-bit instruction allowed
–
Optimization of code size possible
●
Thirty-two 64-bit general purpose registers (GPRs)
●
Harvard bus (32-bit address, 64-bit data)
●
–
I-Bus interface capable of one outstanding transaction plus one piped with no waiton-data return
–
D-Bus interface capable of two transactions outstanding to fill AHB pipe
I-cache and I-cache controller
–
●
No data cache
●
16-entry MMU
●
8-entry branch table buffer
●
Branch look-ahead instruction buffer to accelerate branching
●
Dedicated branch address calculator
●
3 cycles worst case for missed branch
●
Load/store unit
–
Fully pipelined
–
Single-cycle load latency
–
Big- and little-endian modes supported
–
Misaligned access support
–
Single stall cycle on load to use
●
Single-cycle throughput (2-cycle latency) integer 32 × 32 multiplication
●
4 – 14 cycles integer 32 × 32 division (average division on various benchmark of nine
cycles)
●
Single precision floating-point unit
●
–
1 cycle throughput (2-cycle latency) floating-point 32 × 32 multiplication
–
Target 9 cycles (worst case acceptable is 12 cycles) throughput floating-point 32 ×
32 division
–
Special square root and min/max function implemented
Signal processing support: APU-SPE 1.1
–
12/160
4 KB, 256-bit cache line (programmable for 2- or 4-way)
Support for vectorized mode: as many as two floating-point instructions per clock
●
Vectored interrupt support
●
Reservation instruction to support read-modify-write constructs
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SPC56XL60/54
●
1.5.2
Introduction
Extensive system development and tracing support via Nexus debug port
Crossbar switch (XBAR)
The XBAR multi-port crossbar switch supports simultaneous connections between four
master ports and three slave ports. The crossbar supports a 32-bit address bus width and a
64-bit data bus width.
The crossbar allows four concurrent transactions to occur from any master port to any slave
port, although one of those transfers must be an instruction fetch from internal flash
memory. If a slave port is simultaneously requested by more than one master port,
arbitration logic selects the higher priority master and grants it ownership of the slave port.
All other masters requesting that slave port are stalled until the higher priority master
completes its transactions.
The crossbar provides the following features:
●
4 masters and 3 slaves supported per each replicated crossbar
–
Masters allocation for each crossbar: e200z4d core with two independent bus
interface units (BIU) for I and D access (2 masters), one eDMA, one FlexRay
–
Slaves allocation for each crossbar: a redundant flash-memory controller with 2
slave ports to guarantee maximum flexibility to handle Instruction and Data array,
one redundant SRAM controller with 1 slave port each and 1 redundant peripheral
bus bridge
●
32-bit address bus and 64-bit data bus
●
Programmable arbitration priority
–
●
Requesting masters can be treated with equal priority and are granted access to a
slave port in round-robin method, based upon the ID of the last master to be
granted access or a priority order can be assigned by software at application run
time
Temporary dynamic priority elevation of masters
The XBAR is replicated for each processing channel.
1.5.3
Memory Protection Unit (MPU)
The Memory Protection Unit splits the physical memory into 16 different regions. Each
master (eDMA, FlexRay, CPU) can be assigned different access rights to each region.
●
16-region MPU with concurrent checks against each master access
●
32-byte granularity for protected address region
The memory protection unit is replicated for each processing channel.
1.5.4
Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module
capable of performing complex data movements via 16 programmable channels, with
minimal intervention from the host processor. The hardware microarchitecture includes a
DMA engine which performs source and destination address calculations, and the actual
data movement operations, along with an SRAM-based memory containing the transfer
control descriptors (TCD) for the channels. This implementation is used to minimize the
overall block size.
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Introduction
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The eDMA module provides the following features:
●
16 channels supporting 8-, 16-, and 32-bit value single or block transfers
●
Support variable sized queues and circular buffered queue
●
Source and destination address registers independently configured to post-increment
or stay constant
●
Support major and minor loop offset
●
Support minor and major loop done signals
●
DMA task initiated either by hardware requestor or by software
●
Each DMA task can optionally generate an interrupt at completion and retirement of the
task
●
Signal to indicate closure of last minor loop
●
Transfer control descriptors mapped inside the SRAM
The eDMA controller is replicated for each processing channel.
1.5.5
On-chip flash memory with ECC
This device includes programmable, non-volatile flash memory. The non-volatile memory
(NVM) can be used for instruction storage or data storage, or both. The flash memory
module interfaces with the system bus through a dedicated flash memory array controller. It
supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to
flash memory. The module contains four 128-bit prefetch buffers. Prefetch buffer hits allow
no-wait responses. Buffer misses incur a 3 wait state response at 120 MHz.
The flash memory module provides the following features
1.5.6
●
Up to 1 MB of flash memory in unique multi-partitioned hard macro
●
Sectorization:
–
1 MB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 2 × 256 KB
–
768 KB: 16 KB + 2 × 48 KB + 16 KB + 2 × 64 KB + 2 × 128 KB + 1 × 256 KB
●
EEPROM emulation (in software) within same module but on different partition
●
16 KB test sector and 16 KB shadow block for test, censorship device and user option
bits
●
Wait states:
–
3 wait states for frequencies =< 120 MHz
–
2 wait states for frequencies =< 80 MHz
–
1 wait state for frequencies =< 60 MHz
●
Flash memory line 128-bit wide with 8-bit ECC on 64-bit word (total 144 bits)
●
Accessed via a 64-bit wide bus for write and a 128-bit wide array for read operations
●
1-bit error correction, 2-bit error detection
On-chip SRAM with ECC
The SPC56XL60/54 SRAM provides a general-purpose single port memory.
ECC handling is done on a 32-bit boundary for data and it is extended to the address to
have the highest possible diagnostic coverage including the array internal address decoder.
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Introduction
The SRAM module provides the following features:
●
System SRAM: 128 KB
●
ECC on 32-bit word (syndrome of 7 bits)
–
1.5.7
ECC covers SRAM bus address
●
1-bit error correction, 2-bit error detection
●
Wait states:
–
1 wait state for frequencies =< 120 MHz
–
0 wait states for frequencies =< 80 MHz
Platform flash memory controller
The following list summarizes the key features of the flash memory controller:
●
Single AHB port interface supports a 64-bit data bus. All AHB aligned and unaligned
reads within the 32-bit container are supported. Only aligned word writes are
supported.
●
Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each
bank.
●
Code flash (bank0) interface provides configurable read buffering and page prefetch
support.
–
Four page-read buffers (each 128 bits wide) and a prefetch controller support
speculative reading and optimized flash access.
●
Single-cycle read responses (0 AHB data-phase wait states) for hits in the buffers. The
buffers implement a least-recently-used replacement algorithm to maximize
performance.
●
Programmable response for read-while-write sequences including support for stallwhile-write, optional stall notification interrupt, optional flash operation abort , and
optional abort notification interrupt.
●
Separate and independent configurable access timing (on a per bank basis) to support
use across a wide range of platforms and frequencies.
●
Support of address-based read access timing for emulation of other memory types.
●
Support for reporting of single- and multi-bit error events.
●
Typical operating configuration loaded into programming model by system reset.
The platform flash controller is replicated for each processor.
1.5.8
Platform Static RAM Controller (SRAMC)
The SRAMC module is the platform SRAM array controller, with integrated error detection
and correction.
The main features of the SRAMC provide connectivity for the following interfaces:
●
XBAR Slave Port (64-bit data path)
●
ECSM (ECC Error Reporting, error injection and configuration)
●
SRAM array
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The following functions are implemented:
●
ECC encoding (32-bit boundary for data and complete address bus)
●
ECC decoding (32-bit boundary and entire address)
●
Address translation from the AHB protocol on the XBAR to the SRAM array
The platform SRAM controller is replicated for each processor.
1.5.9
Memory subsystem access time
Every memory access the CPU performs requires at least one system clock cycle for the
data phase of the access. Slower memories or peripherals may require additional data
phase wait states. Additional data phase wait states may also occur if the slave being
accessed is not parked on the requesting master in the crossbar.
Table 2 shows the number of additional data phase wait states required for a range of
memory accesses.
Table 2.
Platform memory access time summary
AHB transfer
Data phase
wait states
Description
e200z4d instruction fetch
0
Flash memory prefetch buffer hit (page hit)
e200z4d instruction fetch
3
Flash memory prefetch buffer miss
(based on 4-cycle random flash array access time)
e200z4d data read
0–1
SRAM read
e200z4d data write
0
SRAM 32-bit write
e200z4d data write
0
SRAM 64-bit write (executed as 2 x 32-bit writes)
e200z4d data write
0–2
SRAM 8-,16-bit write
(Read-modify-Write for ECC)
e200z4d flash memory read
0
Flash memory prefetch buffer hit (page hit)
e200z4d flash memory read
3
Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle
of program flash memory controller arbitration)
1.5.10
Error Correction Status Module (ECSM)
The ECSM on this device manages the ECC configuration and reporting for the platform
memories (flash memory and SRAM). It does not implement the actual ECC calculation. A
detected error (double error for flash memory or SRAM) is also reported to the FCCU. The
following errors and indications are reported into the ECSM dedicated registers:
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●
ECC error status and configuration for flash memory and SRAM
●
ECC error reporting for flash memory
●
ECC error reporting for SRAM
●
ECC error injection for SRAM
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1.5.11
Introduction
Peripheral bridge (PBRIDGE)
The PBRIDGE implements the following features:
1.5.12
●
Duplicated periphery
●
Master access privilege level per peripheral (per master: read access enable; write
access enable)
●
Checker applied on PBRIDGE output toward periphery
●
Byte endianess swap capability
Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for
statically scheduled hard real-time systems.
For high-priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the interrupt service routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
The INTC supports the priority ceiling protocol for coherent accesses. By providing a
modifiable priority mask, the priority can be raised temporarily so that all tasks which share
the resource can not preempt each other.
The INTC provides the following features:
●
Duplicated periphery
●
Unique 9-bit vector per interrupt source
●
16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source
●
Priority elevation for shared resource
The INTC is replicated for each processor.
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Introduction
1.5.13
SPC56XL60/54
System clocks and clock generation
The following list summarizes the system clock and clock generation on this device:
●
Lock status continuously monitored by lock detect circuitry
●
Loss-of-clock (LOC) detection for reference and feedback clocks
●
On-chip loop filter (for improved electromagnetic interference performance and fewer
external components required)
●
Programmable output clock divider of system clock (÷1, ÷2, ÷4, ÷8)
●
FlexPWM module and as many as three eTimer modules running on an auxiliary clock
independent from system clock (with max frequency 120 MHz)
●
On-chip crystal oscillator with automatic level control
●
Dedicated internal 16 MHz internal RC oscillator for rapid start-up
–
●
1.5.14
Supports automated frequency trimming by hardware during device startup and by
user application
Auxiliary clock domain for motor control periphery (FlexPWM, eTimer, CTU, ADC, and
SWG)
Frequency-Modulated Phase-Locked Loop (FMPLL)
Each device has two FMPLLs.
Each FMPLL allows the user to generate high speed system clocks starting from a minimum
reference of 4 MHz input clock. Further, the FMPLL supports programmable frequency
modulation of the system clock. The FMPLL multiplication factor, output clock divider ratio
are all software configurable. The FMPLLs have the following major features:
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●
Input frequency: 4–40 MHz continuous range (limited by the crystal oscillator)
●
Voltage controlled oscillator (VCO) range: 256–512 MHz
●
Frequency modulation via software control to reduce and control emission peaks
–
Modulation depth ±2% if centered or 0% to –4% if downshifted via software control
register
–
Modulation frequency: triangular modulation with 25 kHz nominal rate
●
Option to switch modulation on and off via software interface
●
Output divider (ODF) for reduced frequency operation without re-lock
●
3 modes of operation
–
Bypass mode
–
Normal FMPLL mode with crystal reference (default)
–
Normal FMPLL mode with external reference
●
Lock monitor circuitry with lock status
●
Loss-of-lock detection for reference and feedback clocks
●
Self-clocked mode (SCM) operation
●
On-chip loop filter
Doc ID 15457 Rev 8
SPC56XL60/54
●
1.5.15
Introduction
Auxiliary FMPLL
–
Used for FlexRay due to precise symbol rate requirement by the protocol
–
Used for motor control periphery and connected IP (A/D digital interface CTU) to
allow independent frequencies of operation for PWM and timers and jitter-free
control
–
Option to enable/disable modulation to avoid protocol violation on jitter and/or
potential unadjusted error in electric motor control loop
–
Allows to run motor control periphery at different (precisely lower, equal or higher
as required) frequency than the system to ensure higher resolution
Main oscillator
The main oscillator provides these features:
1.5.16
●
Input frequency range 4–40 MHz
●
Crystal input mode
●
External reference clock (3.3 V) input mode
●
FMPLL reference
Internal Reference Clock (RC) oscillator
The architecture uses constant current charging of a capacitor. The voltage at the capacitor
is compared to the stable bandgap reference voltage. The RC oscillator is the device safe
clock.
The RC oscillator provides these features:
1.5.17
●
Nominal frequency 16 MHz
●
±5% variation over voltage and temperature after process trim
●
Clock output of the RC oscillator serves as system clock source in case loss of lock or
loss of clock is detected by the FMPLL
●
RC oscillator is used as the default system clock during startup and can be used as
back-up input source of FMPLL(s) in case XOSC fails
Clock, reset, power, mode and test control modules (MC_CGM,
MC_RGM, MC_PCU, and MC_ME)
These modules provide the following:
●
Clock gating and clock distribution control
●
Halt, stop mode control
●
Flexible configurable system and auxiliary clock dividers
●
Various execution modes
–
HALT and STOP mode as reduced activity low power mode
–
Reset, Idle, Test, Safe
–
Various RUN modes with software selectable powered modules
–
No stand-by mode implemented (no internal switchable power domains)
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Introduction
1.5.18
SPC56XL60/54
Periodic Interrupt Timer Module (PIT)
The PIT module implements the following features:
1.5.19
●
4 general purpose interrupt timers
●
32-bit counter resolution
●
Can be used for software tick or DMA trigger operation
System Timer Module (STM)
The STM implements the following features:
●
Up-counter with 4 output compare registers
●
OS task protection and hardware tick implementation per AUTOSAR(a) requirement
The STM is replicated for each processor.
1.5.20
Software Watchdog Timer (SWT)
This module implements the following features:
●
Fault tolerant output
●
Safe internal RC oscillator as reference clock
●
Windowed watchdog
●
Program flow control monitor with 16-bit pseudorandom key generation
●
Allows a high level of safety (SIL3 monitor)
The SWT module is replicated for each processor.
1.5.21
Fault Collection and Control Unit (FCCU)
The FCCU module has the following features:
1.5.22
●
Redundant collection of hardware checker results
●
Redundant collection of error information and latch of faults from critical modules on
the device
●
Collection of self-test results
●
Configurable and graded fault control
–
Internal reactions (no internal reaction, IRQ, Functional Reset, Destructive Reset,
or Safe mode entered)
–
External reaction (failure is reported to the external/surrounding system via
configurable output pins)
System Integration Unit Lite (SIUL)
The SIUL controls MCU reset configuration, pad configuration, external interrupt, general
purpose I/O (GPIO), internal peripheral multiplexing, and system reset operation. The reset
configuration block contains the external pin boot configuration logic. The pad configuration
block controls the static electrical characteristics of I/O pins. The GPIO block provides
uniform and discrete input/output control of the I/O pins of the MCU.
a. Automotive Open System Architecture
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SPC56XL60/54
Introduction
The SIU provides the following features:
●
Centralized pad control on a per-pin basis
–
●
1.5.23
Pin function selection
–
Configurable weak pull-up/down
–
Configurable slew rate control (slow/medium/fast)
–
Hysteresis on GPIO pins
–
Configurable automatic safe mode pad control
Input filtering for external interrupts
Non-Maskable Interrupt (NMI)
The non-maskable interrupt with de-glitching filter supports high-priority core exceptions.
1.5.24
Boot Assist Module (BAM)
The BAM is a block of read-only memory with hard-coded content. The BAM program is
executed only if serial booting mode is selected via boot configuration pins.
The BAM provides the following features:
1.5.25
●
Enables booting via serial mode (FlexCAN or LINFlex-UART)
●
Supports programmable 64-bit password protection for serial boot mode
●
Supports serial bootloading of either Power Architecture code (default) or VLE code
●
Automatic switch to serial boot mode if internal flash memory is blank or invalid
System Status and Configuration Module (SSCM)
The SSCM on this device features the following:
1.5.26
●
System configuration and status
●
Debug port status and debug port enable
●
Multiple boot code starting locations out of reset through implementation of search for
valid Reset Configuration Half Word
●
Sets up the MMU to allow user boot code to execute as either Power Architecture code
(default) or as VLE code out of flash memory
●
Triggering of device self-tests during reset phase of device boot
FlexCAN
The FlexCAN module is a communication controller implementing the CAN protocol
according to Bosch Specification version 2.0B. The CAN protocol was designed to be used
primarily as a vehicle serial data bus, meeting the specific requirements of this field: realtime processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness
and required bandwidth.
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Introduction
SPC56XL60/54
The FlexCAN module provides the following features:
●
–
Standard data and remote frames
–
Extended data and remote frames
–
0 to 8 bytes data length
–
Programmable bit rate as fast as 1Mbit/s
●
32 message buffers of 0 to 8 bytes data length
●
Each message buffer configurable as receive or transmit buffer, all supporting standard
and extended messages
●
Programmable loop-back mode supporting self-test operation
●
3 programmable mask registers
●
Programmable transmit-first scheme: lowest ID or lowest buffer number
●
Time stamp based on 16-bit free-running timer
●
Global network time, synchronized by a specific message
●
Maskable interrupts
●
Independent of the transmission medium (an external transceiver is assumed)
●
High immunity to EMI
●
Short latency time due to an arbitration scheme for high-priority messages
●
Transmit features
●
●
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Full implementation of the CAN protocol specification, version 2.0B
–
Supports configuration of multiple mailboxes to form message queues of scalable
depth
–
Arbitration scheme according to message ID or message buffer number
–
Internal arbitration to guarantee no inner or outer priority inversion
–
Transmit abort procedure and notification
Receive features
–
Individual programmable filters for each mailbox
–
8 mailboxes configurable as a 6-entry receive FIFO
–
8 programmable acceptance filters for receive FIFO
Programmable clock source
–
System clock
–
Direct oscillator clock to avoid FMPLL jitter
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1.5.27
Introduction
FlexRay
The FlexRay module provides the following features:
●
Full implementation of FlexRay Protocol Specification 2.1 Rev. A
●
64 configurable message buffers can be handled
●
Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate
●
Message buffers configurable as transmit or receive
●
Message buffer size configurable
●
Message filtering for all message buffers based on Frame ID, cycle count, and
message ID
●
Programmable acceptance filters for receive FIFO
●
Message buffer header, status, and payload data stored in system memory (SRAM)
●
Internal FlexRay memories have error detection and correction
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Introduction
1.5.28
SPC56XL60/54
Serial communication interface module (LINFlexD)
The LINFlexD module (LINFlex with DMA support) on this device features the following:
●
Supports LIN Master mode, LIN Slave mode and UART mode
●
LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications
●
Manages LIN frame transmission and reception without CPU intervention
●
LIN features
●
●
●
1.5.29
–
Autonomous LIN frame handling
–
Message buffer to store as many as 8 data bytes
–
Supports messages as long as 64 bytes
–
Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing,
checksum and Time-out errors)
–
Classic or extended checksum calculation
–
Configurable break duration of up to 50-bit times
–
Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)
–
Diagnostic features (Loop back, LIN bus stuck dominant detection)
–
Interrupt driven operation with 16 interrupt sources
LIN slave mode features
–
Autonomous LIN header handling
–
Autonomous LIN response handling
UART mode
–
Full-duplex operation
–
Standard non return-to-zero (NRZ) mark/space format
–
Data buffers with 4-byte receive, 4-byte transmit
–
Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)
–
Configurable parity scheme: none, odd, even, always 0
–
Speed as fast as 2 Mbit/s
–
Error detection and flagging (Parity, Noise and Framing errors)
–
Interrupt driven operation with four interrupt sources
–
Separate transmitter and receiver CPU interrupt sources
–
16-bit programmable baud-rate modulus counter and 16-bit fractional
–
Two receiver wake-up methods
Support for DMA enabled transfers
Deserial Serial Peripheral Interface (DSPI)
The DSPI modules provide a synchronous serial interface for communication between the
SPC56XL60/54 and external devices.
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Introduction
A DSPI module provides these features:
1.5.30
●
Full duplex, synchronous transfers
●
Master or slave operation
●
Programmable master bit rates
●
Programmable clock polarity and phase
●
End-of-transmission interrupt flag
●
Programmable transfer baud rate
●
Programmable data frames from 4 to 16 bits
●
As many as 8 chip select lines available, depending on package and pin multiplexing
●
4 clock and transfer attributes registers
●
Chip select strobe available as alternate function on one of the chip select pins for deglitching
●
FIFOs for buffering as many as 5 transfers on the transmit and receive side
●
Queueing operation possible through use of the eDMA
●
General purpose I/O functionality on pins when not used for SPI
FlexPWM
The pulse width modulator module (FlexPWM) contains four PWM channels, each of which
is configured to control a single half-bridge power stage. Two modules are included on
LFBGA257 devices; on the LQFP144 package, only one module is present. Additionally,
four fault input channels are provided per FlexPWM module.
This PWM is capable of controlling most motor types, including:
●
AC induction motors (ACIM)
●
Permanent Magnet AC motors (PMAC)
●
Brushless (BLDC) and brush DC motors (BDC)
●
Switched (SRM) and variable reluctance motors (VRM)
●
Stepper motors
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Introduction
SPC56XL60/54
A FlexPWM module implements the following features:
●
16 bits of resolution for center, edge aligned, and asymmetrical PWMs
●
Maximum operating frequency as high as 120 MHz
–
●
Fine granularity control for enhanced resolution of the PWM period
●
PWM outputs can operate as complementary pairs or independent channels
●
Ability to accept signed numbers for PWM generation
●
Independent control of both edges of each PWM output
●
Synchronization to external hardware or other PWM supported
●
Double buffered PWM registers
–
Integral reload rates from 1 to 16
–
Half cycle reload capability
●
Multiple ADC trigger events can be generated per PWM cycle via hardware
●
Fault inputs can be assigned to control multiple PWM outputs
●
Programmable filters for fault inputs
●
Independently programmable PWM output polarity
●
Independent top and bottom deadtime insertion
●
Each complementary pair can operate with its own PWM frequency and deadtime
values
●
Individual software control for each PWM output
●
All outputs can be forced to a value simultaneously
●
PWMX pin can optionally output a third signal from each channel
●
Channels not used for PWM generation can be used for buffered output compare
functions
●
Channels not used for PWM generation can be used for input capture functions
●
Enhanced dual edge capture functionality
●
Option to supply the source for each complementary PWM signal pair from any of the
following:
●
26/160
Clock source not modulated and independent from system clock (generated via
secondary FMPLL)
–
External digital pin
–
Internal timer channel
–
External ADC input, taking into account values set in ADC high- and low-limit
registers
DMA support
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SPC56XL60/54
1.5.31
Introduction
eTimer module
The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is
available internally only without any external I/O access). Six 16-bit general purpose
up/down timer/counters per module are implemented with the following features:
●
Maximum clock frequency of 120 MHz
●
Individual channel capability
●
1.5.32
–
Input capture trigger
–
Output compare
–
Double buffer (to capture rising edge and falling edge)
–
Separate prescaler for each counter
–
Selectable clock source
–
0–100% pulse measurement
–
Rotation direction flag (Quad decoder mode)
Maximum count rate
–
Equals peripheral clock divided by 2 for external event counting
–
Equals peripheral clock for internal clock counting
●
Cascadeable counters
●
Programmable count modulo
●
Quadrature decode capabilities
●
Counters can share available input pins
●
Count once or repeatedly
●
Preloadable counters
●
Pins available as GPIO when timer functionality not in use
●
DMA support
Sine Wave Generator (SWG)
A digital-to-analog converter is available to generate a sine wave based on 32 stored values
for external devices (ex: resolver).
1.5.33
Analog-to-Digital Converter module (ADC)
The ADC module features include:
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Introduction
SPC56XL60/54
Analog part:
●
2 on-chip ADCs
–
12-bit resolution SAR architecture
–
Same digital interface as in the SPC560P family
–
A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16
channels)
–
One channel dedicated to each T-sensor to enable temperature reading during
application
–
Separated reference for each ADC
–
Shared analog supply voltage for both ADCs
–
One sample and hold unit per ADC
–
Adjustable sampling and conversion time
Digital part:
●
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range) before results are stored in the appropriate ADC result location
●
2 modes of operation: CPU Mode or CTU Mode
●
CPU mode features
●
●
1.5.34
–
Register based interface with the CPU: one result register per channel
–
ADC state machine managing three request flows: regular command, hardware
injected command, software injected command
–
Selectable priority between software and hardware injected commands
–
4 analog watchdogs comparing ADC results against predefined levels (low, high,
range)
–
DMA compatible interface
CTU mode features
–
Triggered mode only
–
4 independent result queues (1 × 16 entries, 2 × 8 entries, 1 × 4 entries)
–
Result alignment circuitry (left justified; right justified)
–
32-bit read mode allows to have channel ID on one of the 16-bit parts
–
DMA compatible interfaces
Built-in self-test features triggered by software
Cross Triggering Unit (CTU)
The ADC cross triggering unit allows automatic generation of ADC conversion requests on
user selected conditions without CPU load during the PWM period and with minimized CPU
load for dynamic configuration.
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Introduction
The CTU implements the following features:
1.5.35
●
Cross triggering between ADC, FlexPWM, eTimer, and external pins
●
Double buffered trigger generation unit with as many as 8 independent triggers
generated from external triggers
●
Maximum operating frequency less than or equal to 120 MHz
●
Trigger generation unit configurable in sequential mode or in triggered mode
●
Trigger delay unit to compensate the delay of external low pass filter
●
Double buffered global trigger unit allowing eTimer synchronization and/or ADC
command generation
●
Double buffered ADC command list pointers to minimize ADC-trigger unit update
●
Double buffered ADC conversion command list with as many as 24 ADC commands
●
Each trigger capable of generating consecutive commands
●
ADC conversion command allows control of ADC channel from each ADC, single or
synchronous sampling, independent result queue selection
●
DMA support with safety features
Cyclic Redundancy Checker (CRC) Unit
The CRC module is a configurable multiple data flow unit to compute CRC signatures on
data written to its input register.
The CRC unit has the following features:
1.5.36
●
3 sets of registers to allow 3 concurrent contexts with possibly different CRC
computations, each with a selectable polynomial and seed
●
Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores
result in internal register.
The following standard CRC polynomials are implemented:
–
x8 + x4 + x3 + x2 + 1 [8-bit CRC]
–
x16 + x12 + x5 + 1 [16-bit CRC-CCITT]
–
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
[32-bit CRC-ethernet(32)]
●
Key engine to be coupled with communication periphery where CRC application is
added to allow implementation of safe communication protocol
●
Offloads core from cycle-consuming CRC and helps checking configuration signature
for safe start-up or periodic procedures
●
CRC unit connected as peripheral bus on internal peripheral bus
●
DMA support
Redundancy Control and Checker Unit (RCCU)
The RCCU checks all outputs of the sphere of replication (addresses, data, control signals).
It has the following features:
●
Duplicated module to guarantee highest possible diagnostic coverage (check of
checker)
●
Multiple times replicated IPs are used as checkers on the SoR outputs
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Introduction
1.5.37
SPC56XL60/54
Junction temperature sensor
The junction temperature sensor provides a value via an ADC channel that can be used by
software to calculate the device junction temperature.
The key parameters of the junction temperature sensor include:
1.5.38
●
Nominal temperature range from –40 to 150 °C
●
Software temperature alarm via analog ADC comparator possible
Nexus Port Controller (NPC)
The NPC module provides real-time development support capabilities for this device in
compliance with the IEEE-ISTO 5001-2003. This development support is supplied for MCUs
without requiring external address and data pins for internal visibility.
The NPC block interfaces to the host processor and internal buses to provide development
support as per the IEEE-ISTO 5001-2003 Class 3+, including selected features from Class
4 standard.
The development support provided includes program trace, data trace, watchpoint trace,
ownership trace, run-time access to the MCUs internal memory map and access to the
Power Architecture internal registers during halt. The Nexus interface also supports a JTAG
only mode using only the JTAG pins. The following features are implemented:
●
Full and reduced port modes
●
MCKO (message clock out) pin
●
4 or 12 MDO (message data out) pins(b)
●
2 MSEO (message start/end out) pins
●
EVTO (event out) pin
–
Auxiliary input port
●
EVTI (event in) pin
●
5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)
–
●
Supports JTAG mode
Host processor (e200) development support features
–
Data trace via data write messaging (DWM) and data read messaging (DRM).
This allows the development tool to trace reads or writes, or both, to selected
internal memory resources.
–
Ownership trace via ownership trace messaging (OTM). OTM facilitates ownership
trace by providing visibility of which process ID or operating system task is
activated. An ownership trace message is transmitted when a new process/task is
activated, allowing development tools to trace ownership flow.
–
Program trace via branch trace messaging (BTM). Branch trace messaging
displays program flow discontinuities (direct branches, indirect branches,
exceptions, etc.), allowing the development tool to interpolate what transpires
between the discontinuities. Thus, static code may be traced.
b. 4 MDO pins on LQFP144 package, 12 MDO pins on LFBGA257 package.
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1.5.39
Introduction
–
Watchpoint messaging (WPM) via the auxiliary port
–
Watchpoint trigger enable of program and/or data trace messaging
–
Data tracing of instruction fetches via private opcodes
IEEE 1149.1 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. All data input to and output
from the JTAGC block is communicated in serial format. The JTAGC block is compliant with
the IEEE standard.
The JTAG controller provides the following features:
●
1.5.40
IEEE Test Access Port (TAP) interface with 5 pins:
–
TDI
–
TMS
–
TCK
–
TDO
–
JCOMP
●
Selectable modes of operation include JTAGC/debug or normal system operation
●
5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
–
BYPASS
–
IDCODE
–
EXTEST
–
SAMPLE
–
SAMPLE/PRELOAD
●
3 test data registers: a bypass register, a boundary scan register, and a device
identification register. The size of the boundary scan register is parameterized to
support a variety of boundary scan chain lengths.
●
TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry
Voltage regulator / Power Management Unit (PMU)
The on-chip voltage regulator module provides the following features:
●
Single external rail required
●
Single high supply required: nominal 3.3 V both for packaged and Known Good Die
option
–
Packaged option requires external ballast transistor due to reduced dissipation
capacity at high temperature but can use embedded transistor if power dissipation
is maintained within package dissipation capacity (lower frequency of operation)
–
Known Good Die option uses embedded ballast transistor as dissipation capacity
is increased to reduce system cost
●
All I/Os are at same voltage as external supply (3.3 V nominal)
●
Duplicated Low-Voltage Detectors (LVD) to guarantee proper operation at all stages
(reset, configuration, normal operation) and, to maximize safety coverage, one LVD can
be tested while the other operates (on-line self-testing feature)
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Introduction
1.5.41
SPC56XL60/54
Built-In Self-Test (BIST) capability
This device includes the following protection against latent faults:
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●
Boot-time Memory Built-In Self-Test (MBIST)
●
Boot-time scan-based Logic Built-In Self-Test (LBIST)
●
Run-time ADC Built-In Self-Test (BIST)
●
Run-time Built-In Self Test of LVDs
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
2
Package pinouts and signal descriptions
2.1
Package pinouts
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
A[15]
A[14]
C[6]
FCCU_F[1]
B[6]
A[13]
A[9]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
A[11]
A[10]
B[3]
B[2]
C[10]
B[1]
B[0]
Figure 2 shows the LQFP100 pinout.
75
75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LQFP100 package
74
74
73
73
72
72
71
71
70
70
69
69
68
68
67
67
66
66
65
65
64
64
63
63
62
62
61
61
60
60
59
59
58
58
57
57
56
56
55
55
54
54
53
53
52
52
51
51
A[4]
VPP_TEST
D[14]
C[14]
C[13]
D[12]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
A[2]
C[12]
C[11]
D[11]
D[10]
A[1]
A[0]
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
B[7]
B[8]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
B[14]
C[0]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
48
49
49
50
50
NMI
A[6]
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
VDD_HV_IO
VSS_HV_IO
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
Figure 2.
LQFP100 pinout
Figure 3 shows the SPC56XL60/54 in the LQFP144 package.
Doc ID 15457 Rev 8
33/160
SPC56XL60/54
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LQFP144 package
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
D[7]
FCCU_F[0]
VDD_LV_COR
VSS_LV_COR
C[1]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
VDD_HV_ADR0
VSS_HV_ADR0
B[9]
B[10]
B[11]
B[12]
VDD_HV_ADR1
VSS_HV_ADR1
VDD_HV_ADV
VSS_HV_ADV
B[13]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
E[0]
BCTRL
VDD_LV_COR
VSS_LV_COR
VDD_HV_PMU
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NMI
A[6]
D[1]
F[4]
F[5]
VDD_HV_IO
VSS_HV_IO
F[6]
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
VDD_HV_REG_0
VSS_LV_COR
VDD_LV_COR
F[7]
F[8]
VDD_HV_IO
VSS_HV_IO
F[9]
F[10]
F[11]
D[9]
VDD_HV_OSC
VSS_HV_OSC
XTAL
EXTAL
RESET
D[8]
D[5]
D[6]
VSS_LV_PLL0_PLL1
VDD_LV_PLL0_PLL1
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
A[15]
A[14]
C[6]
FCCU_F[1]
D[2]
F[3]
B[6]
VSS_LV_COR
A[13]
VDD_LV_COR
A[9]
F[0]
VSS_LV_COR
VDD_LV_COR
VDD_HV_REG_2
D[4]
D[3]
VSS_HV_IO
VDD_HV_IO
D[0]
C[15]
JCOMP
A[12]
E[15]
A[11]
E[14]
A[10]
E[13]
B[3]
F[14]
B[2]
F[15]
F[13]
C[10]
B[1]
B[0]
Package pinouts and signal descriptions
Figure 3.
SPC56XL60/54 LQFP144 pinout (top view)
Figure 4 shows the SPC56XL60/54 in the LFBGA257 package.
34/160
Doc ID 15457 Rev 8
A[4]
VPP_TEST
F[12]
D[14]
G[3]
C[14]
G[2]
C[13]
G[4]
D[12]
G[6]
VDD_HV_FLA
VSS_HV_FLA
VDD_HV_REG_1
VSS_LV_COR
VDD_LV_COR
A[3]
VDD_HV_IO
VSS_HV_IO
B[4]
TCK
TMS
B[5]
G[5]
A[2]
G[7]
C[12]
G[8]
C[11]
G[9]
D[11]
G[10]
D[10]
G[11]
A[1]
A[0]
SPC56XL60/54
1
A
_IO
VSS_HV VSS_HV
_IO
C
4
VDD_HV
F[5]
5
H[2]
H[0]
6
G[14]
A[14]
B[6]
NC(1)
F[4]
VSS_HV FCCU_
F[1]
_IO
A[15]
C[6]
F[6]
D[1]
NMI
F
H[1]
G[12]
A[7]
A[8]
F[3]
A[9]
D[2]
A[13]
VSS_LV_ VDD_LV_
VDD_HV
VSS_HV
C[5]
G[15]
F[9]
F[8]
L
F[10]
F[11]
M
VDD_HV VDD_HV
_OSC
N
XTAL
VSS_HV
RESET
T
EXTAL
VSS_HV VDD_HV
_IO
U
FCCU
_F[0]
B[2]
15
C[10]
VSS_HV
F[0]
I[0]
H[12]
E[15]
E[14]
B[3]
F[13]
B[0]
B[1]
VSS_HV
JCOMP
H[11]
I[1]
F[14]
_REG_2
COR
COR
_IO
NC
A[11]
E[13]
F[15]
_IO
A[4]
F[12]
D[14]
G[3]
COR
COR
COR
COR
VPP
NC
C[14]
G[2]
I[3]
NC
C[13]
I[2]
G[4]
D[12]
H[13]
H[9]
G[6]
COR
VSS_LV
VSS_LV VDD_LV
VSS_LV
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
VDD_LV
C[7]
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
D[9]
NC
VDD_LV VSS_LV
VSS_LV
VSS_LV
VSS_LV
VSS_LV VDD_LV
D[8]
NC
VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV VDD_LV
D[5]
VSS_LV_
_REG_0
_IO
_TEST
VSS_LV
VDD_HV VDD_HV
VDD_HV VSS_HV
_IO
VSS_LV
A[5]
_IO
VDD_HV
VDD_LV VSS_LV
C[4]
COR
17
_IO
VDD_HV VSS_HV
_IO
16
VSS_HV VSS_HV
_IO
COR
COR
VDD_HV VDD_HV
_REG_1
H[6]
_FLA
VDD_HV VSS_HV
H[15]
_REG_1
_FLA
NC
H[8]
H[7]
A[3]
NC
TCK
H[4]
B[4]
C[11]
B[5]
TMS
H[5]
NC
C[12]
A[2]
G[5]
G[10]
G[8]
G[7]
VSS_HV
D[11]
G[9]
PLL
D[6]
VDD_LV_ VDD_LV_ VSS_LV_
_OSC
R
A[10]
14
COR
_IO
VSS_HV
H[14]
13
COR
_IO
P
D[0]
VDD_HV VDD_HV
COR
COR
_REG_0
K
H[10]
12
VDD_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VSS_LV_ VDD_LV_
A[6]
_IO
F[7]
A[12]
11
VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_ VDD_LV_
_IO
J
D[4]
_REG_2
COR
G[13]
C[15]
10
_IO
MDO0
H
9
VDD_HV
_IO
E
H[3]
D[3]
8
_IO
COR
G
7
_IO
_IO
D
3
VSS_HV VSS_HV VDD_HV
_IO
B
2
Package pinouts and signal descriptions
VSS_HV
PLL
COR
COR
D[7]
B[7]
E[6]
_IO
NC
B[8]
NC
_IO
VDD_HV
B[10]
_ADR0
C[1]
E[5]
E[7]
_IO
VSS_HV
_IO
_IO
NC
1
2
3
E[4]
4
C[2]
5
E[2]
6
B[9]
7
VDD_HV
B[14]
_IO
B[13]
B[15]
VDD_LV_ VSS_LV_ VDD_HV
COR
COR
_IO
C[0]
BCTRL
A[1]
_ADR1
B[11]
_ADR0
VSS_HV VSS_HV
VSS_HV VDD_HV
VSS_HV
_IO
E[9]
E[10]
E[12]
E[0]
A[0]
NC
VDD_HV
D[10]
VDD_HV VSS_HV
G[11]
VSS_HV VSS_HV
_ADR1
B[12]
8
_IO
VDD_HV VSS_HV
_ADV
_ADV
9
10
E[11]
NC
_PMU
11
12
13
14
15
_IO
_IO
_IO
16
17
1. NC = Not connected (the pin is physically not connected to anything on the device)
Figure 4.
SPC56XL60/54 LFBGA257 pinout (top view)
Table 3 (LQFP100 pin function summary), Table 4, and Table 5 provide the pin function
summaries for the 100-pin, 144-pin, and 257-pin packages, respectively, listing all the
signals multiplexed to each pin.
Doc ID 15457 Rev 8
35/160
Package pinouts and signal descriptions
Table 3.
Port/function
1
NMI
3
4
5
6
7
8
9
36/160
LQFP100 pin function summary
Pin #
2
SPC56XL60/54
A[6]
Peripheral
Output function
Input function
—
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
D[1]
A[7]
C[4]
A[8]
C[5]
A[5]
C[7]
10
VDD_HV_REG_0
—
11
VSS_LV_COR
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
12
VDD_LV_COR
—
13
VDD_HV_IO
—
14
VSS_HV_IO
—
15
D[9]
Peripheral
Output function
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
16
VDD_HV_OSC
—
17
VSS_HV_OSC
—
18
XTAL
—
19
EXTAL
—
20
RESET
—
21
22
23
D[8]
D[5]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
D[6]
24
VSS_LV_PLL0_PLL1
—
25
VDD_LV_PLL0_PLL1
—
26
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
Analog output
—
FCCU
F[0]
F[0]
D[7]
27
FCCU_F[0]
28
VDD_LV_COR
—
29
VSS_LV_COR
—
30
Input function
B[7]
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 3.
Pin #
31
32
SPC56XL60/54
LQFP100 pin function summary (continued)
Port/function
B[8]
Peripheral
Output function
Input function
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
E[2]
33
VDD_HV_ADR0
—
34
VSS_HV_ADR0
—
SIUL
35
B[9]
—
GPIO[25]
—
AN[11]
—
GPIO[26]
—
AN[12]
—
GPIO[27]
—
AN[13]
—
GPIO[28]
—
AN[14]
ADC_0
ADC_1
SIUL
36
B[10]
ADC_0
ADC_1
SIUL
37
B[11]
ADC_0
ADC_1
SIUL
38
B[12]
ADC_0
ADC_1
39
VDD_HV_ADR1
—
40
VSS_HV_ADR1
—
41
VDD_HV_ADV
—
42
VSS_HV_ADV
—
43
44
45
46
47
38/160
B[13]
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
B[14]
C[0]
E[0]
BCTRL
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
48
VDD_LV_COR
—
49
VSS_LV_COR
—
50
VDD_HV_PMU
—
51
52
53
54
55
56
57
58
Peripheral
Output function
Input function
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
A[0]
A[1]
D[10]
D[11]
C[11]
C[12]
A[2]
B[5]
59
TMS
—
60
TCK
—
61
B[4]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
Doc ID 15457 Rev 8
39/160
Package pinouts and signal descriptions
Table 3.
LQFP100 pin function summary (continued)
Pin #
Port/function
62
VSS_HV_IO
—
63
VDD_HV_IO
—
64
Peripheral
Output function
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
A[3]
VDD_LV_COR
—
66
VSS_LV_COR
—
67
VDD_HV_REG_1
—
68
VSS_HV_FLA
—
69
VDD_HV_FLA
—
71
72
D[12]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
C[13]
C[14]
73
D[14]
74
VPP_TEST(1)
75
Input function
SIUL
65
70
40/160
SPC56XL60/54
—
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
A[4]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
Pin #
76
77
78
79
80
81
82
LQFP100 pin function summary (continued)
Port/function
B[0]
Peripheral
Output function
Input function
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
DEBUG[2]
SIUL
—
EIRQ[17]
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
DEBUG[3]
LINFlexD_0
—
RXD
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
B[1]
C[10]
B[2]
B[3]
A[10]
A[11]
Doc ID 15457 Rev 8
41/160
Package pinouts and signal descriptions
Table 3.
Pin #
83
84
85
86
LQFP100 pin function summary (continued)
Port/function
A[12]
JCOMP
Peripheral
Output function
Input function
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
—
—
JCOMP
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
C[15]
D[0]
87
VDD_HV_IO
—
88
VSS_HV_IO
—
89
90
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
D[3]
D[4]
91
VDD_HV_REG_2
—
92
VDD_LV_COR
—
93
VSS_LV_COR
—
94
42/160
SPC56XL60/54
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
A[9]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 3.
Pin #
95
96
97
98
99
100
LQFP100 pin function summary (continued)
Port/function
A[13]
Peripheral
Output function
Input function
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
FCCU
F[1]
F[1]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
B[6]
FCCU_F[1]
C[6]
A[14]
A[15]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 4.
LQFP144 pin function summary
Pin #
Port/function
1
NMI
2
A[6]
Peripheral
Output function
Input function
—
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
Doc ID 15457 Rev 8
43/160
Package pinouts and signal descriptions
Table 4.
Pin #
3
4
5
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
D[1]
F[4]
F[5]
6
VDD_HV_IO
—
7
VSS_HV_IO
—
8
F[6]
9
10
11
12
13
14
44/160
SPC56XL60/54
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
MDO0
A[7]
C[4]
A[8]
C[5]
A[5]
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
Pin #
15
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
C[7]
16
VDD_HV_REG_0
—
17
VSS_LV_COR
—
18
VDD_LV_COR
—
19
F[7]
20
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
F[8]
21
VDD_HV_IO
—
22
VSS_HV_IO
—
23
F[9]
24
25
26
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
—
EVTI
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
F[10]
F[11]
D[9]
27
VDD_HV_OSC
—
28
VSS_HV_OSC
—
29
XTAL
—
30
EXTAL
—
31
RESET
—
32
33
D[8]
D[5]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
Doc ID 15457 Rev 8
45/160
Package pinouts and signal descriptions
Table 4.
Pin #
34
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
D[6]
35
VSS_LV_PLL0_PLL1
—
36
VDD_LV_PLL0_PLL1
—
37
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
FCCU
F[0]
F[0]
D[7]
38
FCCU_F[0]
39
VDD_LV_COR
—
40
VSS_LV_COR
—
41
C[1]
42
43
44
45
46
47
48
49
46/160
SPC56XL60/54
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
E[4]
B[7]
E[5]
C[2]
E[6]
B[8]
E[7]
E[2]
50
VDD_HV_ADR0
—
51
VSS_HV_ADR0
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
Pin #
52
53
54
55
LQFP144 pin function summary (continued)
Port/function
B[9]
B[10]
B[11]
B[12]
Peripheral
Output function
Input function
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
56
VDD_HV_ADR1
—
57
VSS_HV_ADR1
—
58
VDD_HV_ADV
—
59
VSS_HV_ADV
—
60
61
62
63
64
65
66
67
B[13]
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
E[9]
B[15]
E[10]
B[14]
E[11]
C[0]
E[12]
Doc ID 15457 Rev 8
47/160
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
68
E[0]
Peripheral
Output function
Input function
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
69
BCTRL
—
70
VDD_LV_COR
—
71
VSS_LV_COR
—
72
VDD_HV_PMU
—
73
74
75
76
77
78
79
80
48/160
SPC56XL60/54
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
A[0]
A[1]
G[11]
D[10]
G[10]
D[11]
G[9]
C[11]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
Pin #
81
82
83
84
85
86
LQFP144 pin function summary (continued)
Port/function
G[8]
C[12]
Peripheral
Output function
Input function
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
G[7]
A[2]
G[5]
B[5]
87
TMS
—
88
TCK
—
89
B[4]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
90
VSS_HV_IO
—
91
VDD_HV_IO
—
92
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
A[3]
93
VDD_LV_COR
—
94
VSS_LV_COR
—
Doc ID 15457 Rev 8
49/160
Package pinouts and signal descriptions
Table 4.
LQFP144 pin function summary (continued)
Pin #
Port/function
95
VDD_HV_REG_1
—
96
VSS_HV_FLA
—
97
VDD_HV_FLA
—
98
G[6]
99
100
101
102
103
104
105
50/160
SPC56XL60/54
D[12]
G[4]
Peripheral
Output function
Input function
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
C[13]
G[2]
C[14]
G[3]
D[14]
106
F[12]
107
VPP_TEST(1)
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
Pin #
108
109
110
111
112
113
114
115
116
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
A[4]
B[0]
B[1]
C[10]
F[13]
F[15]
B[2]
F[14]
B[3]
Doc ID 15457 Rev 8
51/160
Package pinouts and signal descriptions
Table 4.
Pin #
117
118
119
120
121
122
123
124
52/160
SPC56XL60/54
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
—
—
JCOMP
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
E[13]
A[10]
E[14]
A[11]
E[15]
A[12]
JCOMP
C[15]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 4.
Pin #
125
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
D[0]
126
VDD_HV_IO
—
127
VSS_HV_IO
—
128
129
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
D[3]
D[4]
130
VDD_HV_REG_2
—
131
VDD_LV_COR
—
132
VSS_LV_COR
—
133
134
135
136
137
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
F[0]
A[9]
—
VDD_LV_COR
A[13]
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
—
VSS_LV_COR
Doc ID 15457 Rev 8
53/160
Package pinouts and signal descriptions
Table 4.
Pin #
138
139
140
141
142
143
144
SPC56XL60/54
LQFP144 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
FCCU
F[1]
F[1]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
B[6]
F[3]
D[2]
FCCU_F[1]
C[6]
A[14]
A[15]
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
Table 5.
54/160
LFBGA257 pin function summary
Pin #
Port/function
Peripheral
Output function
A1
VSS_HV_IO_RING
—
A2
VSS_HV_IO_RING
—
A3
VDD_HV_IO_RING
—
A4
H[2]
Input function
SIUL
GPIO[114]
GPIO[114]
NPC
MDO[5]
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
A5
H[0]
A6
A7
A8
A9
A10
A11
A12
A13
A14
Peripheral
Output function
Input function
SIUL
GPIO[112]
GPIO[112]
NPC
MDO[7]
—
SIUL
GPIO[110]
GPIO[110]
NPC
MDO[9]
—
SIUL
GPIO[51]
GPIO[51]
FlexRay
CB_TX
—
eTimer_1
ETC[4]
ETC[4]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[47]
GPIO[47]
FlexRay
CA_TR_EN
—
eTimer_1
ETC[0]
ETC[0]
FlexPWM_0
A[1]
A[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
G[14]
D[3]
C[15]
—
VDD_HV_IO_RING
A[12]
H[10]
H[14]
A[10]
SIUL
GPIO[12]
GPIO[12]
DSPI_2
SOUT
—
FlexPWM_0
A[2]
A[2]
FlexPWM_0
B[2]
B[2]
SIUL
—
EIRQ[11]
SIUL
GPIO[122]
GPIO[122]
FlexPWM_1
X[2]
X[2]
eTimer_2
ETC[2]
ETC[2]
SIUL
GPIO[126]
GPIO[126]
FlexPWM_1
A[3]
A[3]
eTimer_2
ETC[4]
ETC[4]
SIUL
GPIO[10]
GPIO[10]
DSPI_2
CS0
CS0
FlexPWM_0
B[0]
B[0]
FlexPWM_0
X[2]
X[2]
SIUL
—
EIRQ[9]
SIUL
GPIO[18]
GPIO[18]
LINFlexD_0
TXD
—
SSCM
DEBUG[2]
—
SIUL
—
EIRQ[17]
B[2]
Doc ID 15457 Rev 8
55/160
Package pinouts and signal descriptions
Table 5.
Pin #
A15
LFBGA257 pin function summary (continued)
Port/function
Peripheral
Output function
Input function
SIUL
GPIO[42]
GPIO[42]
DSPI_2
CS2
—
FlexPWM_0
A[3]
A[3]
FlexPWM_0
—
FAULT[1]
C[10]
A16
VSS_HV_IO_RING
—
A17
VSS_HV_IO_RING
—
B1
VSS_HV_IO_RING
—
B2
VSS_HV_IO_RING
—
B3
B4
B5
B6
B7
B8
56/160
SPC56XL60/54
SIUL
GPIO[22]
GPIO[22]
MC_CGM
clk_out
—
DSPI_2
CS2
—
SIUL
—
EIRQ[18]
SIUL
GPIO[14]
GPIO[14]
FlexCAN_1
TXD
—
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[13]
SIUL
GPIO[83]
GPIO[83]
DSPI_0
CS6
—
SIUL
GPIO[9]
GPIO[9]
DSPI_2
CS1
—
FlexPWM_0
B[3]
B[3]
FlexPWM_0
—
FAULT[0]
SIUL
GPIO[52]
GPIO[52]
FlexRay
CB_TR_EN
—
eTimer_1
ETC[5]
ETC[5]
FlexPWM_0
B[3]
B[3]
SIUL
GPIO[48]
GPIO[48]
FlexRay
CA_TX
—
eTimer_1
ETC[1]
ETC[1]
FlexPWM_0
B[1]
B[1]
B[6]
A[14]
F[3]
A[9]
D[4]
D[0]
B9
VSS_HV_IO_RING
B10
H[12]
—
SIUL
GPIO[124]
GPIO[124]
FlexPWM_1
B[2]
B[2]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
Pin #
B11
B12
B13
B14
B15
LFBGA257 pin function summary (continued)
Port/function
E[15]
E[14]
B[3]
F[13]
B[0]
Peripheral
Output function
Input function
SIUL
GPIO[79]
GPIO[79]
DSPI_0
CS1
—
SIUL
—
EIRQ[27]
SIUL
GPIO[78]
GPIO[78]
eTimer_1
ETC[5]
ETC[5]
SIUL
—
EIRQ[26]
SIUL
GPIO[19]
GPIO[19]
SSCM
DEBUG[3]
—
LINFlexD_0
—
RXD
SIUL
GPIO[93]
GPIO[93]
eTimer_1
ETC[4]
ETC[4]
SIUL
—
EIRQ[31]
SIUL
GPIO[16]
GPIO[16]
FlexCAN_0
TXD
—
eTimer_1
ETC[2]
ETC[2]
SSCM
DEBUG[0]
—
SIUL
—
EIRQ[15]
B16
VDD_HV_IO_RING
—
B17
VSS_HV_IO_RING
—
C1
VDD_HV_IO_RING
—
C2
Not connected
—
C3
VSS_HV_IO_RING
—
C4
FCCU_F[1]
C5
C6
FCCU
F[1]
F[1]
SIUL
GPIO[50]
GPIO[50]
eTimer_1
ETC[3]
ETC[3]
FlexPWM_0
X[3]
X[3]
FlexRay
—
CB_RX
SIUL
GPIO[13]
GPIO[13]
FlexPWM_0
B[2]
B[2]
DSPI_2
—
SIN
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[12]
D[2]
A[13]
C7
VDD_HV_REG_2
—
C8
VDD_HV_REG_2
—
Doc ID 15457 Rev 8
57/160
Package pinouts and signal descriptions
Table 5.
Pin #
C9
Port/function
C11
H[11]
C14
C15
C16
C17
D1
D2
Peripheral
Output function
Input function
SIUL
GPIO[128]
GPIO[128]
eTimer_2
ETC[0]
ETC[0]
DSPI_0
CS4
—
FlexPWM_1
—
FAULT[0]
—
—
JCOMP
SIUL
GPIO[123]
GPIO[123]
FlexPWM_1
A[2]
A[2]
SIUL
GPIO[129]
GPIO[129]
eTimer_2
ETC[1]
ETC[1]
DSPI_0
CS5
—
FlexPWM_1
—
FAULT[1]
SIUL
GPIO[94]
GPIO[94]
LINFlexD_1
TXD
—
SIUL
GPIO[17]
GPIO[17]
eTimer_1
ETC[3]
ETC[3]
SSCM
DEBUG[1]
—
FlexCAN_0
—
RXD
FlexCAN_1
—
RXD
SIUL
—
EIRQ[16]
I[0]
JCOMP
C13
58/160
LFBGA257 pin function summary (continued)
C10
C12
SPC56XL60/54
I[1]
F[14]
B[1]
—
VSS_HV_IO_RING
SIUL
GPIO[4]
GPIO[4]
eTimer_1
ETC[0]
ETC[0]
DSPI_2
CS1
—
eTimer_0
ETC[4]
ETC[4]
MC_RGM
—
FAB
SIUL
—
EIRQ[4]
SIUL
GPIO[92]
GPIO[92]
eTimer_1
ETC[3]
ETC[3]
SIUL
—
EIRQ[30]
SIUL
GPIO[85]
GPIO[85]
NPC
MDO[2]
—
SIUL
GPIO[84]
GPIO[84]
NPC
MDO[3]
—
A[4]
F[12]
F[5]
F[4]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
Pin #
D3
D4
LFBGA257 pin function summary (continued)
Port/function
A[15]
C[6]
Peripheral
Output function
Input function
SIUL
GPIO[15]
GPIO[15]
eTimer_1
ETC[5]
ETC[5]
FlexCAN_1
—
RXD
FlexCAN_0
—
RXD
SIUL
—
EIRQ[14]
SIUL
GPIO[38]
GPIO[38]
DSPI_0
SOUT
—
FlexPWM_0
B[1]
B[1]
SSCM
DEBUG[6]
—
SIUL
—
EIRQ[24]
D5
VSS_LV_CORE_RING
—
D6
VDD_LV_CORE_RING
—
D7
SIUL
GPIO[80]
GPIO[80]
FlexPWM_0
A[1]
A[1]
eTimer_0
—
ETC[2]
SIUL
—
EIRQ[28]
F[0]
D8
VDD_HV_IO_RING
—
D9
VSS_HV_IO_RING
—
D10
Not connected
—
D11
D12
D13
A[11]
SIUL
GPIO[11]
GPIO[11]
DSPI_2
SCK
SCK
FlexPWM_0
A[0]
A[0]
FlexPWM_0
A[2]
A[2]
SIUL
—
EIRQ[10]
SIUL
GPIO[77]
GPIO[77]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
—
EIRQ[25]
SIUL
GPIO[95]
GPIO[95]
LINFlexD_1
—
RXD
E[13]
F[15]
D14
VDD_HV_IO_RING
—
D15
VPP_TEST(1)
—
D16
D[14]
SIUL
GPIO[62]
GPIO[62]
FlexPWM_0
B[1]
B[1]
eTimer_0
—
ETC[3]
Doc ID 15457 Rev 8
59/160
Package pinouts and signal descriptions
Table 5.
Pin #
D17
Port/function
G[3]
MDO0
E2
F[6]
Peripheral
Output function
Input function
SIUL
GPIO[99]
GPIO[99]
FlexPWM_0
A[2]
A[2]
eTimer_0
—
ETC[4]
—
SIUL
GPIO[86]
GPIO[86]
NPC
MDO[1]
—
SIUL
GPIO[49]
GPIO[49]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
FlexRay
—
CA_RX
D[1]
E4
NMI
—
E14
Not connected
—
E15
E16
E17
F1
F2
F3
F4
60/160
LFBGA257 pin function summary (continued)
E1
E3
SPC56XL60/54
C[14]
G[2]
I[3]
SIUL
GPIO[46]
GPIO[46]
eTimer_1
ETC[2]
ETC[2]
CTU_0
EXT_TGR
—
SIUL
GPIO[98]
GPIO[98]
FlexPWM_0
X[2]
X[2]
DSPI_1
CS1
—
SIUL
GPIO[131]
GPIO[131]
eTimer_2
ETC[3]
ETC[3]
DSPI_0
CS7
—
CTU_0
EXT_TGR
—
FlexPWM_1
—
FAULT[3]
SIUL
GPIO[113]
GPIO[113]
NPC
MDO[6]
—
SIUL
GPIO[108]
GPIO[108]
NPC
MDO[11]
—
SIUL
GPIO[7]
GPIO[7]
DSPI_1
SOUT
—
SIUL
—
EIRQ[7]
SIUL
GPIO[8]
GPIO[8]
DSPI_1
—
SIN
SIUL
—
EIRQ[8]
H[1]
G[12]
A[7]
A[8]
F6
VDD_LV_CORE_RING
—
F7
VDD_LV_CORE_RING
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
F8
VDD_LV_CORE_RING
—
F9
VDD_LV_CORE_RING
—
F10
VDD_LV_CORE_RING
—
F11
VDD_LV_CORE_RING
—
F12
VDD_LV_CORE_RING
—
F14
Not connected
—
F15
F16
F17
G1
G2
G3
G4
Peripheral
Output function
Input function
SIUL
GPIO[45]
GPIO[45]
eTimer_1
ETC[1]
ETC[1]
CTU_0
—
EXT_IN
FlexPWM_0
—
EXT_SYNC
SIUL
GPIO[130]
GPIO[130]
eTimer_2
ETC[2]
ETC[2]
DSPI_0
CS6
—
FlexPWM_1
—
FAULT[2]
SIUL
GPIO[100]
GPIO[100]
FlexPWM_0
B[2]
B[2]
eTimer_0
—
ETC[5]
SIUL
GPIO[115]
GPIO[115]
NPC
MDO[4]
—
C[13]
I[2]
G[4]
H[3]
—
VDD_HV_IO_RING
C[5]
A[6]
SIUL
GPIO[37]
GPIO[37]
DSPI_0
SCK
SCK
SSCM
DEBUG[5]
—
FlexPWM_0
—
FAULT[3]
SIUL
—
EIRQ[23]
SIUL
GPIO[6]
GPIO[6]
DSPI_1
SCK
SCK
SIUL
—
EIRQ[6]
G6
VDD_LV_CORE_RING
—
G7
VSS_LV_CORE_RING
—
G8
VSS_LV_CORE_RING
—
G9
VSS_LV_CORE_RING
—
G10
VSS_LV_CORE_RING
—
G11
VSS_LV_CORE_RING
—
G12
VDD_LV_CORE_RING
—
Doc ID 15457 Rev 8
61/160
Package pinouts and signal descriptions
Table 5.
Pin #
G14
G15
G16
G17
H1
H2
H3
H4
62/160
SPC56XL60/54
LFBGA257 pin function summary (continued)
Port/function
D[12]
H[13]
H[9]
Peripheral
Output function
Input function
SIUL
GPIO[60]
GPIO[60]
FlexPWM_0
X[1]
X[1]
LINFlexD_1
—
RXD
SIUL
GPIO[125]
GPIO[125]
FlexPWM_1
X[3]
X[3]
eTimer_2
ETC[3]
ETC[3]
SIUL
GPIO[121]
GPIO[121]
FlexPWM_1
B[1]
B[1]
DSPI_0
CS7
—
SIUL
GPIO[102]
GPIO[102]
FlexPWM_0
A[3]
A[3]
SIUL
GPIO[109]
GPIO[109]
NPC
MDO[10]
—
G[6]
G[13]
VSS_HV_IO_RING
C[4]
A[5]
—
SIUL
GPIO[36]
GPIO[36]
DSPI_0
CS0
CS0
FlexPWM_0
X[1]
X[1]
SSCM
DEBUG[4]
—
SIUL
—
EIRQ[22]
SIUL
GPIO[5]
GPIO[5]
DSPI_1
CS0
CS0
eTimer_1
ETC[5]
ETC[5]
DSPI_0
CS7
—
SIUL
—
EIRQ[5]
H6
VDD_LV
—
H7
VSS_LV
—
H8
VSS_LV
—
H9
VSS_LV
—
H10
VSS_LV
—
H11
VSS_LV
—
H12
VDD_LV
—
H14
VSS_LV
—
H15
VDD_HV_REG_1
—
H16
VDD_HV_FLA
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
Pin #
H17
J1
J2
LFBGA257 pin function summary (continued)
Port/function
H[6]
Peripheral
Output function
Input function
SIUL
GPIO[118]
GPIO[118]
FlexPWM_1
B[0]
B[0]
DSPI_0
CS5
—
SIUL
GPIO[87]
GPIO[87]
NPC
MCKO
—
SIUL
GPIO[111]
GPIO[111]
NPC
MDO[8]
—
F[7]
G[15]
J3
VDD_HV_REG_0
—
J4
VDD_HV_REG_0
—
J6
VDD_LV
—
J7
VSS_LV
—
J8
VSS_LV
—
J9
VSS_LV
—
J10
VSS_LV
—
J11
VSS_LV
—
J12
VDD_LV
—
J14
VDD_LV
—
J15
VDD_HV_REG_1
—
J16
VSS_HV_FLA
—
J17
K1
K2
K3
K4
H[15]
SIUL
GPIO[127]
GPIO[127]
FlexPWM_1
B[3]
B[3]
eTimer_2
ETC[5]
ETC[5]
SIUL
GPIO[89]
GPIO[89]
NPC
MSEO[0]
—
SIUL
GPIO[88]
GPIO[88]
NPC
MSEO[1]
—
NPC
RDY
—
SIUL
GPIO[132]
GPIO[132]
SIUL
GPIO[39]
GPIO[39]
FlexPWM_0
A[1]
A[1]
SSCM
DEBUG[7]
—
DSPI_0
—
SIN
F[9]
F[8]
RDY
C[7]
K6
VDD_LV
—
K7
VSS_LV
—
K8
VSS_LV
—
Doc ID 15457 Rev 8
63/160
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
K9
VSS_LV
—
K10
VSS_LV
—
K11
VSS_LV
—
K12
VDD_LV
—
K14
Not connected
—
K15
K16
K17
L1
L2
L3
64/160
SPC56XL60/54
H[8]
H[7]
Peripheral
Output function
Input function
SIUL
GPIO[120]
GPIO[120]
FlexPWM_1
A[1]
A[1]
DSPI_0
CS6
—
SIUL
GPIO[119]
GPIO[119]
FlexPWM_1
X[1]
X[1]
eTimer_2
ETC[1]
ETC[1]
SIUL
GPIO[3]
GPIO[3]
eTimer_0
ETC[3]
ETC[3]
DSPI_2
CS0
CS0
FlexPWM_0
B[3]
B[3]
MC_RGM
—
ABS[2]
SIUL
—
EIRQ[3]
SIUL
GPIO[90]
GPIO[90]
NPC
EVTO
—
SIUL
GPIO[91]
GPIO[91]
NPC
—
EVTI
SIUL
GPIO[57]
GPIO[57]
FlexPWM_0
X[0]
X[0]
LINFlexD_1
TXD
—
A[3]
F[10]
F[11]
D[9]
L4
Not connected
—
L6
VDD_LV
—
L7
VSS_LV
—
L8
VSS_LV
—
L9
VSS_LV
—
L10
VSS_LV
—
L11
VSS_LV
—
L12
VDD_LV
—
L14
Not connected
—
L15
TCK
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
Pin #
L16
L17
LFBGA257 pin function summary (continued)
Port/function
H[4]
Peripheral
Output function
Input function
SIUL
GPIO[116]
GPIO[116]
FlexPWM_1
X[0]
X[0]
eTimer_2
ETC[0]
ETC[0]
SIUL
GPIO[20]
GPIO[20]
JTAGC
TDO
—
B[4]
M1
VDD_HV_OSC
—
M2
VDD_HV_IO_RING
—
M3
D[8]
SIUL
GPIO[56]
GPIO[56]
DSPI_1
CS2
—
eTimer_1
ETC[4]
ETC[4]
DSPI_0
CS5
—
FlexPWM_0
—
FAULT[3]
M4
Not connected
—
M6
VDD_LV
—
M7
VDD_LV
—
M8
VDD_LV
—
M9
VDD_LV
—
M10
VDD_LV
—
M11
VDD_LV
—
M12
VDD_LV
—
M14
M15
M16
M17
C[11]
SIUL
GPIO[43]
GPIO[43]
eTimer_0
ETC[4]
ETC[4]
DSPI_2
CS2
—
SIUL
GPIO[21]
GPIO[21]
JTAGC
—
TDI
B[5]
TMS
H[5]
—
SIUL
GPIO[117]
GPIO[117]
FlexPWM_1
A[0]
A[0]
DSPI_0
CS4
—
N1
XTAL
—
N2
VSS_HV_IO_RING
—
N3
N4
D[5]
SIUL
GPIO[53]
GPIO[53]
DSPI_0
CS3
—
FlexPWM_0
—
FAULT[2]
VSS_LV_PLL0_PLL1
—
Doc ID 15457 Rev 8
65/160
Package pinouts and signal descriptions
Table 5.
Port/function
N14
Not connected
N16
N17
C[12]
Peripheral
Output function
SIUL
GPIO[44]
GPIO[44]
eTimer_0
ETC[5]
ETC[5]
DSPI_2
CS3
—
SIUL
GPIO[2]
GPIO[2]
eTimer_0
ETC[2]
ETC[2]
FlexPWM_0
A[3]
A[3]
DSPI_2
—
SIN
MC_RGM
—
ABS[0]
SIUL
—
EIRQ[2]
SIUL
GPIO[101]
GPIO[101]
FlexPWM_0
X[3]
X[3]
DSPI_2
CS3
—
A[2]
G[5]
VSS_HV_OSC
—
P2
RESET
—
SIUL
GPIO[54]
GPIO[54]
DSPI_0
CS2
—
FlexPWM_0
X[3]
X[3]
FlexPWM_0
—
FAULT[1]
D[6]
P4
VDD_LV_PLL0_PLL1
—
P5
VDD_LV_CORE_RING
—
P6
VSS_LV_CORE_RING
—
P7
B[8]
SIUL
—
GPIO[24]
eTimer_0
—
ETC[5]
ADC_0
—
AN[1]
P8
Not connected
—
P9
VSS_HV_IO_RING
—
P10
VDD_HV_IO_RING
—
P11
Input function
—
P1
P3
66/160
LFBGA257 pin function summary (continued)
Pin #
N15
SPC56XL60/54
SIUL
—
GPIO[30]
eTimer_0
—
ETC[4]
SIUL
—
EIRQ[19]
ADC_1
—
AN[1]
B[14]
P12
VDD_LV_CORE_RING
—
P13
VSS_LV_CORE_RING
—
P14
VDD_HV_IO_RING
—
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
Pin #
P15
P16
P17
LFBGA257 pin function summary (continued)
Port/function
G[8]
R2
FCCU_F[0]
R3
VSS_HV_IO_RING
R6
R7
R8
R9
R10
R11
Input function
SIUL
GPIO[106]
GPIO[106]
FlexRay
DBG2
—
DSPI_2
CS3
—
FlexPWM_0
—
FAULT[2]
SIUL
GPIO[104]
GPIO[104]
FlexRay
DBG0
—
DSPI_0
CS1
—
FlexPWM_0
—
FAULT[0]
SIUL
—
EIRQ[21]
SIUL
GPIO[103]
GPIO[103]
FlexPWM_0
B[3]
B[3]
G[7]
EXTAL
R5
Output function
G[10]
R1
R4
Peripheral
—
FCCU
F[0]
F[0]
—
SIUL
GPIO[55]
GPIO[55]
DSPI_1
CS3
—
DSPI_0
CS4
—
SWG
analog output
—
SIUL
—
GPIO[23]
LINFlexD_0
—
RXD
ADC_0
—
AN[0]
SIUL
—
GPIO[70]
ADC_0
—
AN[4]
D[7]
B[7]
E[6]
—
VDD_HV_ADR0
B[10]
SIUL
—
GPIO[26]
ADC_0
ADC_1
—
AN[12]
VDD_HV_ADR1
B[13]
B[15]
—
SIUL
—
GPIO[29]
LINFlexD_1
—
RXD
ADC_1
—
AN[0]
SIUL
—
GPIO[31]
SIUL
—
EIRQ[20]
ADC_1
—
AN[2]
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 5.
Port/function
R12
C[0]
R14
R15
R16
R17
Peripheral
Output function
Input function
SIUL
—
GPIO[32]
ADC_1
—
AN[3]
BCTRL
—
SIUL
GPIO[1]
GPIO[1]
eTimer_0
ETC[1]
ETC[1]
DSPI_2
SOUT
—
SIUL
—
EIRQ[1]
A[1]
VSS_HV_IO_RING
D[11]
G[9]
—
SIUL
GPIO[59]
GPIO[59]
FlexPWM_0
B[0]
B[0]
eTimer_0
—
ETC[1]
SIUL
GPIO[105]
GPIO[105]
FlexRay
DBG1
—
DSPI_1
CS1
—
FlexPWM_0
—
FAULT[1]
SIUL
—
EIRQ[29]
T1
VSS_HV_IO_RING
—
T2
VDD_HV_IO_RING
—
T3
Not connected
—
T4
C[1]
T5
T6
T7
T8
SIUL
—
GPIO[33]
ADC_0
—
AN[2]
SIUL
—
GPIO[69]
ADC_0
—
AN[8]
SIUL
—
GPIO[71]
ADC_0
—
AN[6]
E[5]
E[7]
VSS_HV_ADR0
B[11]
T9
VSS_HV_ADR1
T10
E[9]
T11
68/160
LFBGA257 pin function summary (continued)
Pin #
R13
SPC56XL60/54
—
SIUL
—
GPIO[27]
ADC_0
ADC_1
—
AN[13]
—
SIUL
—
GPIO[73]
ADC_1
—
AN[7]
SIUL
—
GPIO[74]
ADC_1
—
AN[8]
E[10]
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
Table 5.
LFBGA257 pin function summary (continued)
Pin #
Port/function
T12
E[12]
T13
T14
T15
Peripheral
Output function
Input function
SIUL
—
GPIO[76]
ADC_1
—
AN[6]
SIUL
—
GPIO[64]
ADC_1
—
AN[5]
SIUL
GPIO[0]
GPIO[0]
eTimer_0
ETC[0]
ETC[0]
DSPI_2
SCK
SCK
SIUL
—
EIRQ[0]
SIUL
GPIO[58]
GPIO[58]
FlexPWM_0
A[0]
A[0]
eTimer_0
—
ETC[0]
E[0]
A[0]
D[10]
T16
VDD_HV_IO_RING
—
T17
VSS_HV_IO_RING
—
U1
VSS_HV_IO_RING
—
U2
VSS_HV_IO_RING
—
U3
Not connected
—
U4
E[4]
U5
U6
U7
U8
SIUL
—
GPIO[68]
ADC_0
—
AN[7]
SIUL
—
GPIO[34]
ADC_0
—
AN[3]
SIUL
—
GPIO[66]
ADC_0
—
AN[5]
SIUL
—
GPIO[25]
ADC_0
ADC_1
—
AN[11]
SIUL
—
GPIO[28]
ADC_0
ADC_1
—
AN[14]
C[2]
E[2]
B[9]
B[12]
U9
VDD_HV_ADV
—
U10
VSS_HV_ADV
—
U11
E[11]
SIUL
—
GPIO[75]
ADC_1
—
AN[4]
U12
Not connected
—
U13
Not connected
—
U14
VDD_HV_PMU
—
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 5.
SPC56XL60/54
LFBGA257 pin function summary (continued)
Pin #
Port/function
U15
Peripheral
Output function
Input function
SIUL
GPIO[107]
GPIO[107]
FlexRay
DBG3
—
FlexPWM_0
—
FAULT[3]
G[11]
U16
VSS_HV_IO_RING
—
U17
VSS_HV_IO_RING
—
1. VPP_TEST should always be tied to ground (VSS) for normal operations.
2.2
Supply pins
Table 6.
Supply pins
Supply
Pin #
100
pkg
144
pkg
257
pkg
Voltage regulator external NPN ballast base control pin
47
69
R13
VDD_LV_COR
Core logic supply
48
70
VDD_LV(1)
VSS_LV_COR
Core regulator ground
49
71
VSS_LV(2)
VDD_HV_PMU
Voltage regulator supply
50
72
U14
VDD_HV_ADR0 ADC_0 high reference voltage
33
50
R7
VSS_HV_ADR0 ADC_0 low reference voltage
34
51
T7
VDD_HV_ADR1 ADC_1 high reference voltage
39
56
R9
VSS_HV_ADR1 ADC_1 low reference voltage
40
57
T9
Symbol
Description
VREG control and power supply pins
BCTRL
ADC_0/ADC_1 reference voltage and ADC supply
VDD_HV_ADV
ADC voltage supply for ADC_0 and ADC_1
41
58
U9
VSS_HV_ADV
ADC ground for ADC_0 and ADC_1
42
59
U10
Power supply pins (3.3 V)
VDD_HV_IO
3.3 V Input/Output supply voltage
—
6
VDD_HV(3)
VSS_HV_IO
3.3 V Input/Output ground
—
7
VSS_HV(4)
10
16
J3
VDD_HV_REG_0 VDD_HV_REG_0
VDD_HV_IO
3.3 V Input/Output supply voltage
13
21
VDD_HV(3)
VSS_HV_IO
3.3 V Input/Output ground
14
22
VSS_HV(4)
VDD_HV_OSC
Crystal oscillator amplifier supply voltage
16
27
M1
VSS_HV_OSC
Crystal oscillator amplifier ground
17
28
P1
VSS_HV_IO
3.3 V Input/Output ground
62
90
VSS_HV(4)
VDD_HV_IO
3.3 V Input/Output supply voltage
63
91
VDD_HV(3)
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Doc ID 15457 Rev 8
SPC56XL60/54
Table 6.
Package pinouts and signal descriptions
Supply pins (continued)
Supply
Symbol
Description
VDD_HV_REG_1 VDD_HV_REG_1
Pin #
100
pkg
144
pkg
257
pkg
67
95
H15
VSS_HV_FLA
VSS_HV_FLA
68
96
J16
VDD_HV_FLA
VDD_HV_FLA
69
97
H16
VDD_HV_IO
VDD_HV_IO
87
126 VDD_HV(3)
VSS_HV_IO
VSS_HV_IO
88
127 VSS_HV(4)
91
130
C7
VDD_HV_REG_2 VDD_HV_REG_2
Power supply pins (1.2 V)
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
11
17
VSS_HV(2)
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
12
18
VDD_LV(1)
VSS 1V2
VSS_LV_PLL0_PLL1 /
1.2 V Decoupling pins for on-chip FMPLL modules. Decoupling
capacitor must be connected between this pin and VDD_LV_PLL.
24
35
N4
VDD 1V2
VDD_LV_PLL0_PLL1
Decoupling pins for on-chip FMPLL modules. Decoupling capacitor must
be connected between this pin and VSS_LV_PLL.
25
36
P4
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
28
39
VDD_LV(1)
VSS_LV_COR
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
29
40
VSS_LV(2)
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VSS_LV_REGCOR.
—
70
VDD_LV(1)
VSS_LV_COR
VSS_LV_REGCOR0
Decoupling pins for core logic and Regulator feedback. Decoupling
capacitor must be connected between this pins and VDD_LV_REGCOR.
—
71
VSS_LV(2)
VDD_LV_COR
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VSS_LV_COR pin.
65
93
VDD_LV(1)
VSS_LV_COR
VSS_LV_COR
/ 1.2 V Decoupling pins for core logic. Decoupling capacitor must be
connected between these pins and the nearest VDD_LV_COR pin.
66
94
VSS_LV(2)
VDD_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
92
131 VDD_LV(1)
VDD 1V2
Doc ID 15457 Rev 8
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Package pinouts and signal descriptions
Table 6.
SPC56XL60/54
Supply pins (continued)
Supply
Pin #
Symbol
Description
100
pkg
144
pkg
257
pkg
VSS 1V2
VSS_LV_COR
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
93
132
VSS_LV(2)
VDD 1V2
VDD_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
—
135 VDD_LV(1)
VSS 1V2
VSS_LV_COR /
Decoupling pins for core logic. Decoupling capacitor must be connected
between these pins and the nearest VDD_LV_COR pin.
—
137
VSS_LV(2)
1. VDD_LV balls are tied together on the LFBGA257 substrate.
2. VSS_LV balls are tied together on the LFBGA257 substrate.
3. VDD_HV balls are tied together on the LFBGA257 substrate.
4. VSS_HV balls are tied together on the LFBGA257 substrate.
2.3
System pins
Table 7.
System pins
Pin #
Symbol
Description
Direction
100
pkg
144
pkg
257
pkg
Output only
—
9
E1
Non Maskable Interrupt
Input only
1
1
E4
Input for oscillator amplifier circuit and internal clock generator
Input only
18
29
N1
(4)
19
30
R1
Dedicated pins
MDO0(1)
NMI
(2)
XTAL
EXTAL(3)
Nexus Message Data Output — line
Input/Output
Oscillator amplifier output
TMS(2)
JTAG state machine control
Input only
59
87
M16
TCK(2)
JTAG clock
Input only
60
88
L15
JTAG compliance select
Input only
84
123
C10
Bidirectional
20
31
P2
74
107
D15
(5)
JCOMP
Reset pin
RESET
Bidirectional reset with Schmitt-Trigger characteristics and
noise filter. This pin has medium drive strength. Output drive is
open drain and must be terminated by an external resistor of
value 1KOhm.(6)
Test pin
VPP TEST
Pin for testing purpose only. To be tied to ground in normal
operating mode.
1. This pad is configured for Fast (F) pad speed.
72/160
Doc ID 15457 Rev 8
SPC56XL60/54
Package pinouts and signal descriptions
2. This pad contains a weak pull-up.
3. EXTAL is an "Output" in "crystal" mode, and is an "Input" in "ext clock" mode.
4. In XOSC Bypass Mode, the analog portion of crystal oscillator (amplifier) is disabled. An external clock can be applied at
EXTAL as an input. In XOSC Normal Mode, EXTAL is an output
5. This pad contains a weak pull-down.
6. RESET output shall be considered valid only after the 3.3V supply reaches its stable value.
Note:
None of system pins (except RESET) provides an open drain output.
2.4
Pin muxing
Table 8 defines the pin list and muxing for this device.
Each entry of Table 8 shows all the possible configurations for each pin, via the alternate
functions. The default function assigned to each pin after reset is indicated by ALT0.
Note:
Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or
voltage may cause unpredictable device behavior or damage.
Pins labeled “Reserved” are to be tied to ground. Not doing so may cause unpredictable
device behavior.
Doc ID 15457 Rev 8
73/160
Port
name
Pin muxing
PCR
Peripheral
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
51
73
T14
—
M
S
52
74
R14
Pull down
M
S
57
84
N16
Port A
A[0]
Doc ID 15457 Rev 8
A[1]
A[2]
SIUL
GPIO[0]
ALT0
GPIO[0]
—
eTimer_0
ETC[0]
ALT1
ETC[0]
PSMI[35];
PADSEL=0
DSPI_2
SCK
ALT2
SCK
PSMI[1];
PADSEL=0
SIUL
—
—
EIRQ[0]
—
SIUL
GPIO[1]
ALT0
GPIO[1]
—
eTimer_0
ETC[1]
ALT1
ETC[1]
PSMI[36];
PADSEL=0
DSPI_2
SOUT
ALT2
—
—
SIUL
—
—
EIRQ[1]
—
SIUL
GPIO[2]
ALT0
GPIO[2]
—
eTimer_0
ETC[2]
ALT1
ETC[2]
PSMI[37];
PADSEL=0
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=0
PCR[0]
PCR[1]
PCR[2]
—
—
SIN
MC_RGM
—
—
ABS[0]
—
SIUL
—
—
EIRQ[2]
—
SPC56XL60/54
DSPI_2
PSMI[2];
PADSEL=0
Package pinouts and signal descriptions
74/160
Table 8.
Port
name
A[3]
A[5]
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[3]
ALT0
GPIO[3]
—
eTimer_0
ETC[3]
ALT1
ETC[3]
PSMI[38];
PADSEL=0
DSPI_2
CS0
ALT2
CS0
PSMI[3];
PADSEL=0
Peripheral
PCR[3]
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=0
MC_RGM
—
—
ABS[2]
—
SIUL
—
—
EIRQ[3]
—
SIUL
GPIO[4]
ALT0
GPIO[4]
—
eTimer_1
ETC[0]
ALT1
ETC[0]
PSMI[9];
PADSEL=0
DSPI_2
CS1
ALT2
—
—
eTimer_0
ETC[4]
ALT3
ETC[4]
PSMI[7];
PADSEL=0
MC_RGM
—
—
FAB
—
SIUL
—
—
EIRQ[4]
—
SIUL
GPIO[5]
ALT0
GPIO[5]
—
DSPI_1
CS0
ALT1
CS0
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=0
DSPI_0
CS7
ALT3
—
—
SIUL
—
—
EIRQ[5]
—
PCR[4]
PCR[5]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
Pull down
M
S
64
92
K17
Pull down
M
S
75
108
C16
—
M
S
8
14
H4
75/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
A[4]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
A[6]
A[7]
Doc ID 15457 Rev 8
A[8]
A[9]
A[10]
Pin muxing (continued)
PCR
PCR[6]
PCR[7]
PCR[8]
PCR[9]
PCR[10]
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[6]
ALT0
GPIO[6]
—
DSPI_1
SCK
ALT1
SCK
—
SIUL
—
—
EIRQ[6]
—
SIUL
GPIO[7]
ALT0
GPIO[7]
—
DSPI_1
SOUT
ALT1
—
—
SIUL
—
—
EIRQ[7]
—
SIUL
GPIO[8]
ALT0
GPIO[8]
—
DSPI_1
—
—
SIN
—
SIUL
—
—
EIRQ[8]
—
SIUL
GPIO[9]
ALT0
GPIO[9]
—
DSPI_2
CS1
ALT1
—
—
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=0
SIUL
GPIO[10]
ALT0
GPIO[10]
—
DSPI_2
CS0
ALT1
CS0
PSMI[3];
PADSEL=1
FlexPWM_0
B[0]
ALT2
B[0]
PSMI[24];
PADSEL=0
FlexPWM_0
X[2]
ALT3
X[2]
PSMI[29];
PADSEL=0
SIUL
—
—
EIRQ[9]
—
Peripheral
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
2
2
G4
—
M
S
4
10
F3
—
M
S
6
12
F4
—
M
S
94
134
B6
—
M
S
81
118
A13
SPC56XL60/54
Alternate
output
function
Package pinouts and signal descriptions
76/160
Table 8.
Port
name
A[11]
A[13]
PCR
PCR[11]
PCR[12]
PCR[13]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[11]
ALT0
GPIO[11]
—
DSPI_2
SCK
ALT1
SCK
PSMI[1];
PADSEL=1
FlexPWM_0
A[0]
ALT2
A[0]
PSMI[20];
PADSEL=0
FlexPWM_0
A[2]
ALT3
A[2]
PSMI[22];
PADSEL=0
SIUL
—
—
EIRQ[10]
—
SIUL
GPIO[12]
ALT0
GPIO[12]
—
DSPI_2
SOUT
ALT1
—
—
FlexPWM_0
A[2]
ALT2
A[2]
PSMI[22];
PADSEL=1
FlexPWM_0
B[2]
ALT3
B[2]
PSMI[26];
PADSEL=0
SIUL
—
—
EIRQ[11]
—
SIUL
GPIO[13]
ALT0
GPIO[13]
—
FlexPWM_0
B[2]
ALT2
B[2]
PSMI[26];
PADSEL=1
DSPI_2
—
—
SIN
PSMI[2];
PADSEL=1
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=1
SIUL
—
—
EIRQ[12]
—
Peripheral
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
82
120
D11
—
M
S
83
122
A10
—
M
S
95
136
C6
77/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
A[12]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
A[14]
Doc ID 15457 Rev 8
A[15]
Pin muxing (continued)
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[14]
ALT0
GPIO[14]
—
FlexCAN_1
TXD
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=0
SIUL
—
—
EIRQ[13]
—
SIUL
GPIO[15]
ALT0
GPIO[15]
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=0
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=0
SIUL
—
—
EIRQ[14]
—
Peripheral
PCR[14]
PCR[15]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
99
143
B4
—
M
S
100
144
D3
—
M
S
76
109
B15
Package pinouts and signal descriptions
78/160
Table 8.
Port B
B[0]
PCR[16]
SIUL
GPIO[16]
ALT0
GPIO[16]
—
FlexCAN_0
TXD
ALT1
—
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=0
SSCM
DEBUG[0]
ALT3
—
—
SIUL
—
—
EIRQ[15]
—
SPC56XL60/54
Port
name
B[1]
B[3]
B[4](2)
B[5]
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[17]
ALT0
GPIO[17]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=0
SSCM
DEBUG[1]
ALT3
—
—
FlexCAN_0
—
—
RXD
PSMI[33];
PADSEL=1
FlexCAN_1
—
—
RXD
PSMI[34];
PADSEL=1
SIUL
—
—
EIRQ[16]
—
SIUL
GPIO[18]
ALT0
GPIO[18]
—
LINFlexD_0
TXD
ALT1
—
—
SSCM
DEBUG[2]
ALT3
—
—
SIUL
—
—
EIRQ[17]
—
SIUL
GPIO[19]
ALT0
GPIO[19]
—
SSCM
DEBUG[3]
ALT3
—
—
Peripheral
PCR[17]
PCR[18]
PCR[19]
LINFlexD_0
—
—
RXD
PSMI[31];
PADSEL=0
SIUL
GPIO[20]
ALT0
GPIO[20]
—
JTAGC
TDO
ALT1
—
—
SIUL
GPIO[21]
ALT0
GPIO[21]
—
JTAGC
—
—
TDI
—
PCR[20]
PCR[21]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
77
110
C14
—
M
S
79
114
A14
—
M
S
80
116
B13
—
F
S
61
89
L17
Pull up
M
S
58
86
M15
79/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
B[2]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
B[6]
B[7]
Doc ID 15457 Rev 8
B[8]
B[9]
B[10]
B[11]
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[22]
ALT0
GPIO[22]
—
MC_CGM
clk_out
ALT1
—
—
DSPI_2
CS2
ALT2
—
—
SIUL
—
EIRQ[18]
—
SIUL
—
ALT0
GPI[23]
—
LINFlexD_0
—
—
RXD
PSMI[31];
PADSEL=1
ADC_0
—
—
AN[0](3)
—
SIUL
—
ALT0
GPI[24]
—
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=2
ADC_0
—
—
AN[1](3)
—
SIUL
—
ALT0
GPI[25]
—
ADC_0
ADC_1
—
—
AN[11](3)
—
SIUL
—
ALT0
GPI[26]
—
ADC_0
ADC_1
—
—
AN[12](3)
—
SIUL
—
ALT0
GPI[27]
—
ADC_0
ADC_1
—
—
AN[13](3)
—
SIUL
—
ALT0
GPI[28]
—
ADC_0
ADC_1
—
—
AN[14](3)
—
Peripheral
PCR[22]
PCR[23]
PCR[24]
PCR[25]
PCR[26]
PCR[27]
PCR[28]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
F
S
96
138
B3
—
—
—
30
43
R5
—
—
—
31
47
P7
—
—
—
35
52
U7
—
—
—
36
53
R8
—
—
—
37
54
T8
—
—
—
38
55
U8
SPC56XL60/54
B[12]
Pin muxing (continued)
Package pinouts and signal descriptions
80/160
Table 8.
Port
name
B[13]
B[14]
Pin muxing (continued)
PCR
PCR[29]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
—
ALT0
GPI[29]
—
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=0
ADC_1
—
—
AN[0](3)
—
SIUL
—
ALT0
GPI[30]
—
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=2
Peripheral
PCR[30]
B[15]
PCR[31]
—
—
EIRQ[19]
AN[1]
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
—
—
43
60
R10
—
—
—
44
64
P11
—
—
—
—
62
R11
—
—
—
45
66
R12
—
—
—
—
41
T4
—
—
—
—
45
U5
—
(3)
—
ADC_1
—
—
SIUL
—
ALT0
GPI[31]
—
SIUL
—
—
EIRQ[20]
—
ADC_1
—
—
AN[2](3)
—
Port C
SIUL
C[0]
C[1]
C[2]
—
ALT0
GPI[32]
—
—
PCR[32]
ADC_1
—
—
AN[3](3)
SIUL
—
ALT0
GPI[33]
—
—
PCR[33]
ADC_0
—
—
AN[2](3)
SIUL
—
ALT0
GPI[34]
—
—
AN[3](3)
—
PCR[34]
ADC_0
—
81/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
SIUL
Weak pull
config during
reset
SPC56XL60/54
Table 8.
Port
name
C[4]
Doc ID 15457 Rev 8
C[5]
C[6]
PCR
PCR[36]
PCR[37]
PCR[38]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[36]
ALT0
GPIO[36]
—
DSPI_0
CS0
ALT1
CS0
—
FlexPWM_0
X[1]
ALT2
X[1]
PSMI[28];
PADSEL=0
SSCM
DEBUG[4]
ALT3
—
—
SIUL
—
—
EIRQ[22]
—
SIUL
GPIO[37]
ALT0
GPIO[37]
—
DSPI_0
SCK
ALT1
SCK
—
SSCM
DEBUG[5]
ALT3
—
—
Peripheral
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=0
SIUL
—
—
EIRQ[23]
—
SIUL
GPIO[38]
ALT0
GPIO[38]
—
DSPI_0
SOUT
ALT1
—
—
FlexPWM_0
B[1]
ALT2
B[1]
PSMI[25];
PADSEL=0
SSCM
DEBUG[6]
ALT3
—
—
SIUL
—
—
EIRQ[24]
—
SIUL
GPIO[39]
ALT0
GPIO[39]
—
FlexPWM_0
A[1]
ALT2
A[1]
PSMI[21];
PADSEL=0
SSCM
DEBUG[7]
ALT3
—
—
DSPI_0
—
—
SIN
—
PCR[39]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
5
11
H3
—
M
S
7
13
G3
—
M
S
98
142
D4
—
M
S
9
15
K4
SPC56XL60/54
C[7]
Pin muxing (continued)
Package pinouts and signal descriptions
82/160
Table 8.
Port
name
C[10]
C[12]
C[13]
C[14]
PCR
PCR[42]
PCR[43]
PCR[44]
83/160
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[42]
ALT0
GPIO[42]
—
DSPI_2
CS2
ALT1
—
—
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=0
SIUL
GPIO[43]
ALT0
GPIO[43]
—
eTimer_0
ETC[4]
ALT1
ETC[4]
PSMI[7];
PADSEL=1
DSPI_2
CS2
ALT2
—
—
SIUL
GPIO[44]
ALT0
GPIO[44]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=0
DSPI_2
CS3
ALT2
—
—
SIUL
GPIO[45]
ALT0
GPIO[45]
—
eTimer_1
ETC[1]
ALT1
ETC[1]
PSMI[10];
PADSEL=0
CTU_0
—
—
EXT_IN
PSMI[0];
PADSEL=0
FlexPWM_0
—
—
EXT_SYNC
PSMI[15];
PADSEL=0
SIUL
GPIO[46]
ALT0
GPIO[46]
—
eTimer_1
ETC[2]
ALT1
ETC[2]
PSMI[11];
PADSEL=1
CTU_0
EXT_TGR
ALT2
—
—
Peripheral
PCR[45]
PCR[46]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
78
111
A15
—
M
S
55
80
M14
—
M
S
56
82
N15
—
M
S
71
101
F15
—
M
S
72
103
E15
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
C[11]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
C[15]
Pin muxing (continued)
PCR
PCR[47]
Doc ID 15457 Rev 8
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[47]
ALT0
GPIO[47]
—
FlexRay
CA_TR_EN
ALT1
—
—
eTimer_1
ETC[0]
ALT2
ETC[0]
PSMI[9];
PADSEL=1
FlexPWM_0
A[1]
ALT3
A[1]
PSMI[21];
PADSEL=1
CTU_0
—
—
EXT_IN
PSMI[0];
PADSEL=1
FlexPWM_0
—
—
EXT_SYNC
PSMI[15];
PADSEL=1
Peripheral
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
SYM
S
85
124
A8
—
SYM
S
86
125
B8
—
M
S
3
3
E3
Package pinouts and signal descriptions
84/160
Table 8.
Port D
D[0]
D[1]
PCR[48]
GPIO[48]
ALT0
GPIO[48]
—
FlexRay
CA_TX
ALT1
—
—
eTimer_1
ETC[1]
ALT2
ETC[1]
PSMI[10];
PADSEL=1
FlexPWM_0
B[1]
ALT3
B[1]
PSMI[25];
PADSEL=1
SIUL
GPIO[49]
ALT0
GPIO[49]
—
eTimer_1
ETC[2]
ALT2
ETC[2]
PSMI[11];
PADSEL=2
CTU_0
EXT_TGR
ALT3
—
—
FlexRay
—
—
CA_RX
—
PCR[49]
SPC56XL60/54
SIUL
Port
name
D[2]
D[4]
D[5]
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[50]
ALT0
GPIO[50]
—
eTimer_1
ETC[3]
ALT2
ETC[3]
PSMI[12];
PADSEL=1
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=0
FlexRay
—
—
CB_RX
—
SIUL
GPIO[51]
ALT0
GPIO[51]
—
FlexRay
CB_TX
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=1
FlexPWM_0
A[3]
ALT3
A[3]
PSMI[23];
PADSEL=2
SIUL
GPIO[52]
ALT0
GPIO[52]
—
FlexRay
CB_TR_EN
ALT1
—
—
eTimer_1
ETC[5]
ALT2
ETC[5]
PSMI[14];
PADSEL=2
FlexPWM_0
B[3]
ALT3
B[3]
PSMI[27];
PADSEL=2
SIUL
GPIO[53]
ALT0
GPIO[53]
—
DSPI_0
CS3
ALT1
—
—
FAULT[2]
PSMI[18];
PADSEL=0
Peripheral
PCR[50]
PCR[51]
PCR[52]
PCR[53]
FlexPWM_0
—
—
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
140
C5
—
SYM
S
89
128
A7
—
SYM
S
90
129
B7
—
M
S
22
33
N3
85/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
D[3]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
D[6]
Doc ID 15457 Rev 8
D[7]
D[8]
D[9]
Pin muxing (continued)
PCR
PCR[54]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[54]
ALT0
GPIO[54]
—
DSPI_0
CS2
ALT1
—
—
FlexPWM_0
X[3]
ALT3
X[3]
PSMI[30];
PADSEL=1
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=1
SIUL
GPIO[55]
ALT0
GPIO[55]
—
DSPI_1
CS3
ALT1
—
—
DSPI_0
CS4
ALT3
—
—
SWG
analog output
—
—
—
SIUL
GPIO[56]
ALT0
GPIO[56]
—
DSPI_1
CS2
ALT1
—
—
eTimer_1
ETC[4]
ALT2
ETC[4]
PSMI[13];
PADSEL=2
DSPI_0
CS5
ALT3
—
—
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=1
SIUL
GPIO[57]
ALT0
GPIO[57]
—
FlexPWM_0
X[0]
ALT1
X[0]
—
LINFlexD_1
TXD
ALT2
—
—
Peripheral
PCR[55]
PCR[56]
PCR[57]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
23
34
P3
—
M
S
26
37
R4
—
M
S
21
32
M3
—
M
S
15
26
L3
Package pinouts and signal descriptions
86/160
Table 8.
SPC56XL60/54
Port
name
D[10]
D[11]
D[14]
PCR
PCR[58]
PCR[59]
PCR[60]
PCR[62]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[58]
ALT0
GPIO[58]
—
FlexPWM_0
A[0]
ALT1
A[0]
PSMI[20];
PADSEL=1
eTimer_0
—
—
ETC[0]
PSMI[35];
PADSEL=1
SIUL
GPIO[59]
ALT0
GPIO[59]
—
FlexPWM_0
B[0]
ALT1
B[0]
PSMI[24];
PADSEL=1
eTimer_0
—
—
ETC[1]
PSMI[36];
PADSEL=1
SIUL
GPIO[60]
ALT0
GPIO[60]
FlexPWM_0
X[1]
ALT1
X[1]
PSMI[28];
PADSEL=1
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=1
SIUL
GPIO[62]
ALT0
GPIO[62]
—
FlexPWM_0
B[1]
ALT1
B[1]
PSMI[25];
PADSEL=2
eTimer_0
—
—
ETC[3]
PSMI[38];
PADSEL=1
Peripheral
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
53
76
T15
—
M
S
54
78
R16
—
M
S
70
99
G14
—
M
S
73
105
D16
—
—
—
46
68
T13
—
—
—
32
49
U6
Port E
SIUL
E[0]
87/160
E[2]
—
ALT0
GPI[64]
—
—
PCR[64]
ADC_1
—
—
AN[5](3)
SIUL
—
ALT0
GPI[66]
—
—
AN[5](3)
—
PCR[66]
ADC_0
—
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
D[12]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Pin muxing (continued)
Port
name
PCR
E[4]
PCR[68]
Peripheral
SIUL
E[5]
E[6]
Doc ID 15457 Rev 8
E[7]
E[9]
E[10]
E[11]
E[12]
E[13]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
—
ALT0
GPI[68]
—
(3)
—
ADC_0
—
—
SIUL
—
ALT0
GPI[69]
—
ADC_0
—
—
AN[8](3)
—
SIUL
—
ALT0
GPI[70]
—
—
PCR[69]
PCR[70]
AN[7]
ADC_0
—
—
AN[4](3)
SIUL
—
ALT0
GPI[71]
—
ADC_0
—
—
AN[6](3)
—
SIUL
—
ALT0
GPI[73]
—
—
PCR[71]
PCR[73]
ADC_1
—
—
AN[7](3)
SIUL
—
ALT0
GPI[74]
—
ADC_1
—
—
AN[8](3)
—
SIUL
—
ALT0
GPI[75]
—
—
PCR[74]
PCR[75]
—
—
SIUL
—
ALT0
GPI[76]
—
ADC_1
—
—
AN[6](3)
—
SIUL
GPIO[77]
ALT0
GPIO[77]
—
eTimer_0
ETC[5]
ALT1
ETC[5]
PSMI[8];
PADSEL=1
DSPI_2
CS3
ALT2
—
—
SIUL
—
—
EIRQ[25]
—
PCR[76]
PCR[77]
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
—
—
—
42
U4
—
—
—
—
44
T5
—
—
—
—
46
R6
—
—
—
—
48
T6
—
—
—
—
61
T10
—
—
—
—
63
T11
—
—
—
—
65
U11
—
—
—
—
67
T12
—
M
S
—
117
D12
SPC56XL60/54
ADC_1
AN[4](3)
Weak pull
config during
reset
Package pinouts and signal descriptions
88/160
Table 8.
Port
name
E[14]
E[15]
Pin muxing (continued)
PCR
PCR[78]
PCR[79]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[78]
ALT0
GPIO[78]
—
eTimer_1
ETC[5]
ALT1
ETC[5]
PSMI[14];
PADSEL=3
SIUL
—
—
EIRQ[26]
—
SIUL
GPIO[79]
ALT0
GPIO[79]
—
DSPI_0
CS1
ALT1
—
—
SIUL
—
—
EIRQ[27]
—
Peripheral
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
119
B12
—
M
S
—
121
B11
—
M
S
—
133
D7
—
M
S
—
139
B5
—
F
S
—
4
D2
—
F
S
—
5
D1
—
F
S
—
8
E2
Port F
F[0]
F[3]
F[4]
F[5]
F[6]
SIUL
GPIO[80]
ALT0
GPIO[80]
—
FlexPWM_0
A[1]
ALT1
A[1]
PSMI[21];
PADSEL=2
PCR[80]
eTimer_0
—
—
ETC[2]
PSMI[37];
PADSEL=1
SIUL
—
—
EIRQ[28]
—
SIUL
GPIO[83]
ALT0
GPIO[83]
—
DSPI_0
CS6
ALT1
—
—
SIUL
GPIO[84]
ALT0
GPIO[84]
—
NPC
MDO[3]
ALT2
—
—
SIUL
GPIO[85]
ALT0
GPIO[85]
—
NPC
MDO[2]
ALT2
—
—
SIUL
GPIO[86]
ALT0
GPIO[86]
—
NPC
MDO[1]
ALT2
—
—
PCR[83]
PCR[84]
PCR[85]
PCR[86]
89/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
SRC
=1
SPC56XL60/54
Table 8.
Pin muxing (continued)
Port
name
PCR
F[7]
PCR[87]
F[8]
F[9]
Doc ID 15457 Rev 8
F[10]
F[11]
F[12]
F[13]
F[14]
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[87]
ALT0
GPIO[87]
—
NPC
MCKO
ALT2
—
—
SIUL
GPIO[88]
ALT0
GPIO[88]
—
NPC
MSEO[1]
ALT2
—
—
SIUL
GPIO[89]
ALT0
GPIO[89]
—
NPC
MSEO[0]
ALT2
—
—
SIUL
GPIO[90]
ALT0
GPIO[90]
—
NPC
EVTO
ALT2
—
—
SIUL
GPIO[91]
ALT0
GPIO[91]
—
NPC
—
ALT2
EVTI
—
SIUL
GPIO[92]
ALT0
GPIO[92]
—
eTimer_1
ETC[3]
ALT1
ETC[3]
PSMI[12];
PADSEL=2
SIUL
—
—
EIRQ[30]
—
SIUL
GPIO[93]
ALT0
GPIO[93]
—
eTimer_1
ETC[4]
ALT1
ETC[4]
PSMI[13];
PADSEL=3
SIUL
—
—
EIRQ[31]
—
SIUL
GPIO[94]
ALT0
GPIO[94]
—
LINFlexD_1
TXD
ALT1
—
—
SIUL
GPIO[95]
ALT0
GPIO[95]
—
LINFlexD_1
—
—
RXD
PSMI[32];
PADSEL=2
Peripheral
PCR[88]
PCR[89]
PCR[90]
PCR[91]
PCR[92]
PCR[93]
PCR[94]
PCR[95]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
F
S
—
19
J1
—
F
S
—
20
K2
—
F
S
—
23
K1
—
F
S
—
24
L1
—
M
S
—
25
L2
—
M
S
—
106
C17
—
M
S
—
112
B14
—
M
S
—
115
C13
—
M
S
—
113
D13
SPC56XL60/54
F[15]
Alternate
output
function
Package pinouts and signal descriptions
90/160
Table 8.
Port
name
Pin muxing (continued)
PCR
Peripheral
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
SPC56XL60/54
Table 8.
FCCU
FCCU_
F[0]
—
FCCU
F[0]
ALT0
F[0]
—
—
S
S
27
38
R2
FCCU_
F[1]
—
FCCU
F[1]
ALT0
F[1]
—
—
S
S
97
141
C4
—
M
S
—
102
E16
—
M
S
—
104
D17
—
M
S
—
100
F17
—
M
S
—
85
N17
Port G
G[3]
G[4]
G[5]
PCR[98]
PCR[99]
PCR[100]
PCR[101]
GPIO[98]
ALT0
GPIO[98]
—
FlexPWM_0
X[2]
ALT1
X[2]
PSMI[29];
PADSEL=1
DSPI_1
CS1
ALT2
—
—
SIUL
GPIO[99]
ALT0
GPIO[99]
—
FlexPWM_0
A[2]
ALT1
A[2]
PSMI[22];
PADSEL=2
eTimer_0
—
—
ETC[4]
PSMI[7];
PADSEL=3
SIUL
GPIO[100]
ALT0
GPIO[100]
—
FlexPWM_0
B[2]
ALT1
B[2]
PSMI[26];
PADSEL=2
eTimer_0
—
—
ETC[5]
PSMI[8];
PADSEL=3
SIUL
GPIO[101]
ALT0
GPIO[101]
—
FlexPWM_0
X[3]
ALT1
X[3]
PSMI[30];
PADSEL=2
DSPI_2
CS3
ALT2
—
—
91/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
G[2]
SIUL
Pin muxing (continued)
Port
name
PCR
G[6]
PCR[102]
G[7]
Doc ID 15457 Rev 8
G[8]
G[9]
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[102]
ALT0
GPIO[102]
—
FlexPWM_0
A[3]
ALT1
A[3]
PSMI[23];
PADSEL=3
SIUL
GPIO[103]
ALT0
GPIO[103]
FlexPWM_0
B[3]
ALT1
B[3]
PSMI[27];
PADSEL=3
SIUL
GPIO[104]
ALT0
GPIO[104]
—
FlexRay
DBG0
ALT1
—
—
DSPI_0
CS1
ALT2
—
—
Peripheral
PCR[103]
PCR[104]
PCR[105]
PCR[106]
FlexPWM_0
—
—
FAULT[0]
PSMI[16];
PADSEL=2
SIUL
—
—
EIRQ[21]
—
SIUL
GPIO[105]
ALT0
GPIO[105]
—
FlexRay
DBG1
ALT1
—
—
DSPI_1
CS1
ALT2
—
—
FlexPWM_0
—
—
FAULT[1]
PSMI[17];
PADSEL=2
SIUL
—
—
EIRQ[29]
—
SIUL
GPIO[106]
ALT0
GPIO[106]
—
FlexRay
DBG2
ALT1
—
—
DSPI_2
CS3
ALT2
—
—
FlexPWM_0
—
—
FAULT[2]
PSMI[18];
PADSEL=1
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
98
G17
—
M
S
—
83
P17
—
M
S
—
81
P16
—
M
S
—
79
R17
—
M
S
—
77
P15
SPC56XL60/54
G[10]
Alternate
output
function
Package pinouts and signal descriptions
92/160
Table 8.
Port
name
G[11]
G[12]
G[14]
G[15]
PCR
PCR[107]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[107]
ALT0
GPIO[107]
—
FlexRay
DBG3
ALT1
—
—
Peripheral
FlexPWM_0
—
—
FAULT[3]
PSMI[19];
PADSEL=2
SIUL
GPIO[108]
ALT0
GPIO[108]
—
NPC
MDO[11]
ALT2
—
—
SIUL
GPIO[109]
ALT0
GPIO[109]
—
NPC
MDO[10]
ALT2
—
—
SIUL
GPIO[110]
ALT0
GPIO[110]
—
NPC
MDO[9]
ALT2
—
—
SIUL
GPIO[111]
ALT0
GPIO[111]
—
NPC
MDO[8]
ALT2
—
—
PCR[108]
PCR[109]
PCR[110]
PCR[111]
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
75
U15
—
F
S
—
—
F2
—
F
S
—
—
H1
—
F
S
—
—
A6
—
F
S
—
—
J2
—
F
S
—
—
A5
—
F
S
—
—
F1
—
F
S
—
—
A4
—
F
S
—
—
G1
Port H
H[0]
H[1]
H[2]
H[3]
SIUL
GPIO[112]
ALT0
GPIO[112]
—
NPC
MDO[7]
ALT2
—
—
SIUL
GPIO[113]
ALT0
GPIO[113]
—
NPC
MDO[6]
ALT2
—
—
SIUL
GPIO[114]
ALT0
GPIO[114]
—
NPC
MDO[5]
ALT2
—
—
SIUL
GPIO[115]
ALT0
GPIO[115]
—
NPC
MDO[4]
ALT2
—
—
PCR[112]
PCR[113]
PCR[114]
PCR[115]
93/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
G[13]
Pin muxing (continued)
SPC56XL60/54
Table 8.
Port
name
H[4]
H[5]
Doc ID 15457 Rev 8
H[6]
H[7]
H[8]
H[9]
PCR
PCR[116]
PCR[117]
PCR[118]
PCR[119]
PCR[120]
PCR[121]
PCR[122]
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[116]
ALT0
GPIO[116]
—
FlexPWM_1
X[0]
ALT1
X[0]
—
Peripheral
eTimer_2
ETC[0]
ALT2
ETC[0]
PSMI[39];
PADSEL=0
SIUL
GPIO[117]
ALT0
GPIO[117]
—
FlexPWM_1
A[0]
ALT1
A[0]
—
DSPI_0
CS4
ALT3
—
—
SIUL
GPIO[118]
ALT0
GPIO[118]
—
FlexPWM_1
B[0]
ALT1
B[0]
—
DSPI_0
CS5
ALT3
—
—
SIUL
GPIO[119]
ALT0
GPIO[119]
—
FlexPWM_1
X[1]
ALT1
X[1]
—
eTimer_2
ETC[1]
ALT2
ETC[1]
PSMI[40];
PADSEL=0
SIUL
GPIO[120]
ALT0
GPIO[120]
—
FlexPWM_1
A[1]
ALT1
A[1]
—
DSPI_0
CS6
ALT3
—
—
SIUL
GPIO[121]
ALT0
GPIO[121]
—
FlexPWM_1
B[1]
ALT1
B[1]
—
DSPI_0
CS7
ALT3
—
—
SIUL
GPIO[122]
ALT0
GPIO[122]
—
FlexPWM_1
X[2]
ALT1
X[2]
—
eTimer_2
ETC[2]
ALT2
ETC[2]
—
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
—
L16
—
M
S
—
—
M17
—
M
S
—
—
H17
—
M
S
—
—
K16
—
M
S
—
—
K15
—
M
S
—
—
G16
—
M
S
—
—
A11
SPC56XL60/54
H[10]
Pin muxing (continued)
Package pinouts and signal descriptions
94/160
Table 8.
Pin muxing (continued)
Port
name
PCR
H[11]
PCR[123]
H[12]
H[13]
H[15]
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[123]
ALT0
GPIO[123]
—
FlexPWM_1
A[2]
ALT1
A[2]
—
SIUL
GPIO[124]
ALT0
GPIO[124]
—
FlexPWM_1
B[2]
ALT1
B[2]
—
SIUL
GPIO[125]
ALT0
GPIO[125]
—
FlexPWM_1
X[3]
ALT1
X[3]
—
Peripheral
PCR[124]
PCR[125]
PCR[126]
PCR[127]
eTimer_2
ETC[3]
ALT2
ETC[3]
PSMI[42];
PADSEL=0
SIUL
GPIO[126]
ALT0
GPIO[126]
—
FlexPWM_1
A[3]
ALT1
A[3]
—
eTimer_2
ETC[4]
ALT2
ETC[4]
—
SIUL
GPIO[127]
ALT0
GPIO[127]
—
FlexPWM_1
B[3]
ALT1
B[3]
—
eTimer_2
ETC[5]
ALT2
ETC[5]
—
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
—
C11
—
M
S
—
—
B10
—
M
S
—
—
G15
—
M
S
—
—
A12
—
M
S
—
—
J17
—
M
S
—
—
C9
Port I
I[0]
SIUL
GPIO[128]
ALT0
GPIO[128]
—
eTimer_2
ETC[0]
ALT1
ETC[0]
PSMI[39];
PADSEL=1
DSPI_0
CS4
ALT2
—
—
FlexPWM_1
—
—
FAULT[0]
—
PCR[128]
95/160
Package pinouts and signal descriptions
Doc ID 15457 Rev 8
H[14]
Alternate
output
function
SPC56XL60/54
Table 8.
Port
name
I[1]
Doc ID 15457 Rev 8
I[2]
I[3]
RDY
Pin muxing (continued)
PCR
Alternate
output
function
Output
mux sel
Input
functions
Input mux
select
SIUL
GPIO[129]
ALT0
GPIO[129]
—
eTimer_2
ETC[1]
ALT1
ETC[1]
PSMI[40];
PADSEL=1
DSPI_0
CS5
ALT2
—
—
FlexPWM_1
—
—
FAULT[1]
—
SIUL
GPIO[130]
ALT0
GPIO[130]
—
eTimer_2
ETC[2]
ALT1
ETC[2]
PSMI[41];
PADSEL=1
Peripheral
PCR[129]
PCR[130]
PCR[131]
PCR[132]
DSPI_0
CS6
ALT2
—
—
FlexPWM_1
—
—
FAULT[2]
—
SIUL
GPIO[131]
ALT0
GPIO[131]
—
eTimer_2
ETC[3]
ALT1
ETC[3]
PSMI[42];
PADSEL=1
DSPI_0
CS7
ALT2
—
—
CTU_0
EXT_TGR
ALT3
—
—
FlexPWM_1
—
—
FAULT[3]
—
SIUL
GPIO[132]
ALT0
GPIO[132]
—
NPC
RDY
ALT2
—
Weak pull
config during
reset
Pad
speed(1)
Pin #
SRC
=1
SRC
=0
100
pkg
144
pkg
257
pkg
—
M
S
—
—
C12
—
M
S
—
—
F16
—
M
S
—
—
E17
—
F
S
—
—
Package pinouts and signal descriptions
96/160
Table 8.
K3
—
1. Programmable via the SRC (Slew Rate Control) bit in the respective Pad Configuration Register; S = Slow, M = Medium, F = Fast, SYM = Symmetric (for FlexRay)
2. The default function of this pin out of reset is ALT1 (TDO).
Note:
Open Drain can be configured by the PCRn for all pins used as output (except FCCU_F[0] and FCCU_F[1] ).
SPC56XL60/54
3. Analog
SPC56XL60/54
Electrical characteristics
3
Electrical characteristics
3.1
Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for this device.
This device is designed to operate at 120 MHz. The electrical specifications are preliminary
and are from previous designs, design simulations, or initial evaluation. These specifications
may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications
have been completed.
The “Symbol” column of the electrical parameter and timings tables contains an additional
column containing “SR”, “CC”, “P”, “C”, “T”, or “D”.
●
“SR” identifies system requirements—conditions that must be provided to ensure
normal device operation. An example is the input voltage of a voltage regulator.
●
“CC” identifies controller characteristics—indicating the characteristics and timing of
the signals that the chip provides.
●
“P”, “C”, “T”, or “D” apply only to controller characteristics—specifications that define
normal device operation. They specify how each characteristic is guaranteed.
–
P: parameter is guaranteed by production testing of each individual device.
–
C: parameter is guaranteed by design characterization. Measurements are taken
from a statistically relevant sample size across process variations.
–
T: parameter is guaranteed by design characterization on a small sample size
from typical devices under typical conditions unless otherwise noted. All values
are shown in the typical (“typ”) column are within this category.
–
D: parameters are derived mainly from simulations.
3.2
Absolute maximum ratings
Table 9.
Absolute maximum ratings(1)
Symbol
Parameter
Conditions
Min
Max(2)
Unit
V
VDD_HV_REG
SR
3.3 V voltage regulator supply voltage
—
–0.3
4.0(3), (4)
VDD_HV_IOx
SR
3.3 V input/output supply voltage
—
–0.3
4.0(3), (4)
V
VSS_HV_IOx
SR
Input/output ground voltage
—
–0.1
0.1
V
V
VDD_HV_FLA
SR
3.3 V flash supply voltage
—
–0.3
4.0(3), (4)
VSS_HV_FLA
SR
Flash memory ground
—
–0.1
0.1
V
VDD_HV_OSC
SR
3.3 V crystal oscillator amplifier supply
voltage
—
–0.3
4.0(3), (4)
V
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier reference
voltage
—
–0.1
0.1
V
3.3 V / 5.0 V ADC_0 high reference voltage
3.3 V / 5.0 V ADC_1 high reference voltage
—
–0.3
6.0
V
VDD_HV_ADR0(5)
SR
VDD_HV_ADR1
Doc ID 15457 Rev 8
97/160
Electrical characteristics
Table 9.
SPC56XL60/54
Absolute maximum ratings(1) (continued)
Conditions
Min
Max(2)
Unit
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
—
–0.1
0.1
V
4.0(3), (4)
V
0.1
V
3.0 × 10
(3.0 V/sec)
0.5 V/µs
V/µs
–0.3
6.0(6)
VDD + 0.3(6),
V
–0.3
Symbol
Parameter
VSS_HV_ADR0
SR
VSS_HV_ADR1
VDD_HV_ADV
SR
3.3 V ADC supply voltage
—
–0.3
VSS_HV_ADV
SR
3.3 V ADC supply ground
—
–0.1
-6
TVDD
VIN
SR
Supply ramp rate
—
SR
—
Voltage on any pin with respect to ground
(VSS_HV_IOx)
Relative to VDD
(7)
IINJPAD
SR
Injected input current on any pin during
overload condition
—
–10
10
mA
IINJSUM
SR
Absolute sum of all injected input currents
during overload condition
—
–50
50
mA
TSTG
SR
Storage temperature
—
–55
150
°C
1. Functional operating conditions are given in the DC electrical characteristics. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress
have not yet been determined.
3. 5.3 V for 10 hours cumulative over lifetime of device, 3.3 V +10% for time remaining.
4. Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.
5. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated be operated at different voltages, and need to be supplied by the
same voltage source.
6. Internal structures hold the input voltage less than the maximum voltage on all pads powered by VDDE supplies, if the
maximum injection current specification is met (2 mA for all pins) and VDDE is within the operating voltage specifications.
7. Only when VDD < 5.2 V.
3.3
Recommended operating conditions
Table 10.
Recommended operating conditions (3.3 V)
Symbol
Parameter
Conditions
Min(1)
Max
Unit
VDD_HV_REG
SR 3.3 V voltage regulator supply voltage
—
3.0
3.6
V
VDD_HV_IOx
SR 3.3 V input/output supply voltage
—
3.0
3.6
V
VSS_HV_IOx
SR Input/output ground voltage
—
0
0
V
VDD_HV_FLA
SR 3.3 V flash supply voltage
—
3.0
3.6
V
VSS_HV_FLA
SR Flash memory ground
—
0
0
V
VDD_HV_OSC
SR 3.3 V crystal oscillator amplifier supply voltage
—
3.0
3.6
V
VSS_HV_OSC
SR
3.3 V crystal oscillator amplifier reference
voltage
—
0
0
V
—
4.5 to 5.5 or
3.0 to 3.6
V
3.3 V / 5.0 V ADC_0 high reference voltage
VDD_HV_ADR0(2)
SR
VDD_HV_ADR1
3.3 V / 5.0 V ADC_1 high reference voltage
98/160
Doc ID 15457 Rev 8
SPC56XL60/54
Table 10.
Electrical characteristics
Recommended operating conditions (3.3 V) (continued)
Symbol
Parameter
Conditions
Min(1)
Max
Unit
—
3.0
3.6
V
—
0
0
V
VDD_HV_ADV
SR 3.3 V ADC supply voltage
VSS_HV_AD0
VSS_HV_AD1
SR
VSS_HV_ADV
SR 3.3 V ADC supply ground
—
0
0
V
VDD_LV_REGCOR
SR Internal supply voltage
—
—
—
V
VSS_LV_REGCOR
SR Internal reference voltage
—
0
0
V
VDD_LV_CORx(2) SR Internal supply voltage
—
—
—
V
VSS_LV_CORx(3) SR Internal reference voltage
—
0
0
V
SR Internal supply voltage
—
—
—
V
SR Internal reference voltage
—
0
0
V
(3)
(4)
VDD_LV_PLL
(2)
VSS_LV_PLL(3)
ADC_0 ground and low reference voltage
ADC_1 ground and low reference voltage
TA
SR Ambient temperature under bias
fCPU ≤ 120 MHz
–40
125
°C
TJ
SR Junction temperature under bias
—
–40
150
°C
1. Full functionality cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and
I/Os DC electrical specification may not be guaranteed.
2. VDD_HV_ADR0 and VDD_HV_ADR1 cannot be operated at different voltages, and need to be supplied by the same voltage
source.
3. Can be connected to emitter of external NPN. Low voltage supplies are not under user control. They are produced by an
on-chip voltage regulator.
4. For the device to function properly, the low voltage grounds (VSS_LV_xxx) must be shorted to high voltage grounds
(VSS_HV_xxx) and the low voltage supply pins (VDD_LV_xxx) must be connected to the external ballast emitter, if one is used.
3.4
Thermal characteristics
Table 11.
Thermal characteristics for LQFP100 package(1)
Symbol
Parameter
Conditions
Value
RθJA
D
Thermal resistance, junction-to-ambient natural Single layer board – 1s
convection(2)
Four layer board – 2s2p
46
RθJMA
D
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
36
34
28
Unit
°C/W
°C/W
RθJB
D Thermal resistance junction-to-board(3)
—
19
°C/W
RθJC
D Thermal resistance junction-to-case(4)
—
8
°C/W
—
2
°C/W
ΨJT
D Junction-to-package-top natural
convection(5)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
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5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Table 12.
Symbol
Parameter
Conditions
Value
Unit
Single layer board – 1s
44
Four layer board – 2s2p
36
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
35
30
D
Thermal resistance junction-to-board(3)
—
24
°C/W
D
Thermal resistance junction-to-case(4)
—
8
°C/W
—
2
°C/W
RθJA
D
RθJMA
D
RθJB
RθJC
ΨJT
Thermal characteristics for LQFP144 package(1)
D
Thermal resistance, junction-to-ambient
natural convection(2)
Junction-to-package-top natural
°C/W
convection(5)
°C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Table 13.
Symbol
RθJA
D
RθJMA
D
RθJB
D
RθJC
ΨJT
D
D
Thermal characteristics for LFBGA257 package(1)
Parameter
Conditions
Thermal resistance junction-to-ambient natural Single layer board – 1s
convection(2)
Four layer board – 2s2p
Value
Unit
46
°C/W
26
Thermal resistance, junction-to-ambient forced Single layer board – 1s
convection at 200 ft/min
Four layer board – 2s2p
22
Thermal resistance junction-to-board(3)
—
13
°C/W
—
8
°C/W
—
2
°C/W
Thermal resistance junction-to-case
Junction-to-package-top natural
(4)
convection(5)
37
°C/W
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Junction-to-Ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
3. Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
4. Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
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3.4.1
Electrical characteristics
General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from Equation 1:
Equation 1 TJ = TA + (RθJA × PD)
where:
TA
= ambient temperature for the package (oC)
RθJA
= junction to ambient thermal resistance (oC/W)
PD
= power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by a
factor of two. Which value is closer to the application depends on the power dissipated by
other components on the board. The value obtained on a single layer board is appropriate
for the tightly packed printed circuit board. The value obtained on the board with the internal
planes is usually appropriate if the board has low power dissipation and the components are
well separated.
When a heat sink is used, the thermal resistance is expressed in Equation 2 as the sum of a
junction to case thermal resistance and a case to ambient thermal resistance:
Equation 2
RθJA = RθJC + RθCA
where:
RθJA
= junction to ambient thermal resistance (°C/W)
RθJC
= junction to case thermal resistance (°C/W)
RθCA
= case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the thermal
environment to change the case to ambient thermal resistance, RθCA. For instance, the user
can change the size of the heat sink, the air flow around the device, the interface material,
the mounting arrangement on printed circuit board, or change the thermal dissipation on the
printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks are
not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using Equation 3:
Equation 3 TJ = TT + (ΨJT × PD)
where:
TT
= thermocouple temperature on top of the package (°C)
ΨJT
= thermal characterization parameter (°C/W)
PD
= power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a 40
gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the package.
A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of
wire extending from the junction. The thermocouple wire is placed flat against the package
case to avoid measurement errors caused by cooling effects of the thermocouple wire.
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Electrical characteristics
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References
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134 USA
(408) 943-6900
MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering
Documents at 800-854-7179 or 303-397-7956.
JEDEC specifications are available on the WEB at http://www.jedec.org.
3.5
1.
C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an
Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998,
pp. 47–54.
2.
G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled
Applications,” Electronic Packaging and Production, pp. 53–58, March 1998.
3.
B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal
Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San
Diego, 1999, pp. 212–220.
Electromagnetic Interference (EMI) characteristics
The characteristics in Table 15 were measured using:
●
Device configuration, tet conditions, and EM testing per standard IEC61967-2
●
Supply voltage of 3.3 V DC
●
Ambient temperature of 25 °C
The configuration information referenced in Table 15 is explained in Table 14.
Table 14.
EMI configuration summary
Configuration name
Description
Configuration A
–
–
–
–
–
High emission = all pads have max slew rate, LVDS pads running at 40 MHz
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
No PLL frequency modulation
IEC level I (≤ 36 dBμV)
Configuration B
–
–
–
–
–
Reference emission = pads use min, mid and max slew rates, LVDS pads disabled
Oscillator frequency = 40 MHz
System bus frequency = 80 MHz
2% PLL frequency modulation
IEC level K(≤ 30 dBμV)
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Table 15.
EMI emission testing specifications
Symbol
VEME
Electrical characteristics
Parameter
Conditions
Min
Typ
Max
Configuration A; frequency range
150 kHz–50 MHz
—
16
—
Configuration A; frequency range 50–
150 MHz
—
16
—
Configuration A; frequency range 150–
500 MHz
—
32
—
Configuration A; frequency range 500–
1000 MHz
—
25
—
Configuration B; frequency range 50–
150 MHz
—
15
—
Configuration B; frequency range 50–
150 MHz
—
21
—
Configuration B; frequency range 150–
500 MHz
—
30
—
Configuration B; frequency range 500–
1000 MHz
—
24
—
CC Radiated emissions
Unit
dBμV
EMC testing was performed and documented according to these standards: [IEC61508-27.4.5.1.b, IEC61508-2-7.2.3.2.e, IEC61508-2-Table-A.17 (partially), IEC61508-2-TableB.5(partially),SRS2110]
EME testing was performed and documented according to these standards: [IEC 61967-2 &
-4]
EMS testing was performed and documented according to these standards: [IEC 62132-2 &
-4]
Contact FSL for detailed information pertaining to the EMC, EME, and EMS testing and
results.
3.6
Electrostatic discharge (ESD) characteristics
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n + 1) supply pin). This test
conforms to the AEC-Q100-002/-003/-011 standard. For more details, refer to the
application note Electrostatic Discharge Sensitivity Measurement (AN1181).
Table 16.
No.
ESD ratings(1), (2)
Symbol
Parameter
Conditions
Class
Max value(3)
Unit
1
VESD(HBM)
SR
Electrostatic discharge
(Human Body Model)
TA = 25 °C
conforming to AEC-Q100-002
H1C
2000
V
2
VESD(MM)
SR
Electrostatic discharge
(Machine Model)
TA = 25 °C
conforming to AEC-Q100-003
M2
200
V
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Electrical characteristics
Table 16.
No.
3
SPC56XL60/54
ESD ratings(1), (2) (continued)
Symbol
VESD(CDM)
Parameter
SR
Conditions
Class
Electrostatic discharge TA = 25 °C
(Charged Device Model) conforming to AEC-Q100-011
Max value(3)
Unit
500
C3A
V
750 (corners)
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification
requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at
room temperature followed by hot temperature, unless specified otherwise in the device specification.
3. Data based on characterization results, not tested in production.
3.7
Static latch-up (LU)
Two complementary static tests are required on six parts to assess the latch-up
performance:
●
A supply overvoltage is applied to each power supply pin.
●
A current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with the EIA/JESD 78 IC latch-up standard.
Table 17.
No.
1
3.8
Latch-up results
Symbol
LU
Parameter
SR
Static latch-up class
Conditions
Class
TA = 125 °C conforming to JESD 78
II level A
Voltage regulator electrical characteristics
The voltage regulator is composed of the following blocks:
●
High power regulator HPREG1 (internal ballast to support core current)
●
High power regulator HPREG2 (external NPN to support core current)
●
Low voltage detector (LVD_MAIN_1) for 3.3 V supply to IO (VDDIO)
●
Low voltage detector (LVD_MAIN_2) for 3.3 V supply (VDDREG)
●
Low voltage detector (LVD_MAIN_3) for 3.3 V flash supply (VDDFLASH)
●
Low voltage detector (LVD_DIG_MAIN) for 1.2 V digital core supply (HPVDD)
●
Low voltage detector (LVD_DIG_BKUP) for the self-test of LVD_DIG_MAIN
●
High voltage detector (HVD_DIG_MAIN) for 1.2 V digital CORE supply (HPVDD)
●
High voltage detector (HVD_DIG_BKUP) for the self-test of HVD_DIG_MAIN.
●
Power on Reset (POR)
HPREG1 uses an internal ballast to support the core current. HPREG2 is used only when
external NPN transistor is present on board to supply core current. The MPC5643L always
powers up using HPREG1 if an external NPN transistor is present. Then the MPC5643L
makes a transition from HPREG1 to HPREG2. This transition is dynamic. Once HPREG2 is
fully operational, the controller part of HPREG1 is switched off.
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Electrical characteristics
The following bipolar transistors are supported:
●
BCP68 from ON Semiconductor
●
BCX68 from Infineon
Table 18.
Recommended operating characteristics
Symbol
hFE( β )
PD
Parameter
DC current gain (Beta)
Maximum power dissipation @
TA=25°C(1)
Value
Unit
85 - 375
—
1.5
W
1.0
A
ICMaxDC
Maximum peak collector current
VCESAT
Collector-to-emitter saturation
voltage(Max)
600(2)
mV
VBE
Base-to-emitter voltage (Max)
1.0
V
1. derating factor 12mW/degC
2. Adjust resistor at bipolar transistor collector for 3.3V to avoid VCE<VCESAT
The recommended external ballast transistor is the bipolar transistor BCP68 with the gain
range of 85 up to 375 (for IC=500mA, VCE=1V) provided by several suppliers. This includes
the gain variations BCP68-10, BCP68-16 and BCP68-25.The most important parameters for
the interoperability with the integrated voltage regulator are the DC current gain (hFE) and
the temperature coefficient of the gain (XTB). While the specified gain range of most BCP68
vendors is the same, there are slight variations in the temperature coefficient parameter.
MPC5643LVoltage regulator operation was simulated against the typical variation on
temperature coefficient and against the specified gain range to have a robust design.
Table 19.
Symbol
Voltage regulator electrical specifications
Parameter
Cext
External decoupling/
stability capacitor
SR
Combined ESR of
external capacitor
Number of pins for
SR external decoupling/
stability capacitor
CV1V2
tSU
SR
Total capacitance on
1.2 V pins
Start-up time after main
supply stabilization
Conditions
Min
Typ
Max
Unit
Min, max values shall be
granted with respect to
tolerance, voltage,
temperature, and aging
variations.
12
—
40
µF
—
0.01
—
0.10
Ω
—
5
—
—
—
Ceramic capacitors,
taking into account
tolerance, aging, voltage
and temperature
variation
300
—
900
nF
Cload = 10 µF × 4
—
—
2.5
ms
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Electrical characteristics
Table 19.
Voltage regulator electrical specifications (continued)
Symbol
—
—
—
—
SPC56XL60/54
D
D
D
Parameter
Conditions
Min
Typ
Max
Unit
Main High Voltage
Power - Low Voltage
Detection, upper
threshold
—
—
—
2.9
V
Main supply low voltage
detector, lower threshold
—
2.6
—
—
V
Before a destructive
reset initialization phase
completion
1.355
—
1.495
Digital supply high
voltage detector upper
threshold
Digital supply high
voltage detector lower
threshold
V
After a destructive reset
initialization phase
completion
1.39
—
1.47
Before a destructive
reset initialization phase
completion
1.315
—
1.455
V
After a destructive reset
initialization phase
completion
1.35
—
1.38
—
D
Digital supply low
voltage detector lower
threshold
Before a destructive
reset initialization phase
completion
1.080
—
1.140
V
—
D
Digital supply low
voltage detector upper
threshold
After a destructive reset
initialization phase
completion
1.16
—
1.22
V
—
D
POR rising/ falling
supply threshold voltage
—
1.6
—
2.6
V
—
3
—
0.5 ×106
V/s
—
SR Supply ramp rate
—
D
LVD_MAIN: Time
constant of RC filter at
LVD input
3.3V noise rejection at
the input of
LVD comparator
1.1
—
—
µs
—
D
HVD_DIG: Time
constant of RC filter at
LVD input
1.2V noise rejection at
the input of
LVD comparator
0.1
—
—
µs
—
D
LVD_DIG: Time
constant of RC filter at
LVD input
1.2V noise rejection at
the input of
LVD comparator
0.1
—
—
µs
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Electrical characteristics
VDD
BCP68
BCRTL
V1V2 ring on board
Rb
Rs
Lb
ESR
Cv1v2
Cint
Cext
V1V2 pin
SPC56XL60/54
Figure 5.
BCP68 board schematic example
Note:
The combined ESR of the capacitors used on 1.2 V pins (V1V2 in the picture) shall be in the
range of 1 mΩ to 100 mΩ. The minimum value of the ESR is constrained by the resonance
caused by the external components, bonding inductance, and internal decoupling. The
minimum ESR is required to avoid the resonance and make the regulator stable.
3.9
DC electrical characteristics
Table 20 gives the DC electrical characteristics at 3.3 V (3.0 V < VDD_HV_IOx < 3.6 V).
Table 20.
Symbol
DC electrical characteristics(1)
Parameter
Conditions
Min
Typ
Max
Unit
VIL
D Minimum low level input voltage
—
–0.1(2)
—
—
V
VIL
P Maximum level input voltage
—
—
—
0.35 VDD_HV_IOx
V
VIH
P Minimum high level input voltage
—
0.65 VDD_HV_IOx
—
—
V
VIH
D Maximum high level input voltage
—
—
—
VHYS
T Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
—
V
VOL_S
P Slow, low level output voltage
IOL = 1.5 mA
—
—
0.5
V
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VDD_HV_IOx +
0.1(2)
V
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Electrical characteristics
SPC56XL60/54
DC electrical characteristics(1) (continued)
Table 20.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOH = –
1.5 mA
VDD_HV_IOx –
0.8
—
—
V
IOL = 2 mA
—
—
0.5
V
VDD_HV_IOx –
0.8
—
—
V
VOH_S
P Slow, high level output voltage
VOL_M
P Medium, low level output voltage
VOH_M
P Medium, high level output voltage IOH = –2 mA
VOL_F
P Fast, high level output voltage
IOL = 1.5 mA
—
—
0.5
V
VOH_F
P Fast, high level output voltage
IOH = –
1.5 mA
VDD_HV_IOx –
0.8
—
—
V
VOL_SYM
P
Symmetric, high level output
voltage
IOL = 1.5 mA
—
—
0.5
V
VOH_SYM
P
Symmetric, high level output
voltage
IOH = –
1.5 mA
VDD_HV_IOx –
0.8
—
—
V
—
–1
—
1
mA
VIN = VIL
–130
—
—
VIN = VIH
—
—
–10
VIN = VIL
10
—
—
VIN = VIH
—
—
130
-1
—
1
-0.5
—
0.5
-1
—
1
–0.1(2)
—
0.35 VDD_HV_IOx
IINJ
T DC injection current per pin
IPU
P Equivalent pull-up current
IPD
P Equivalent pull-down current
µA
µA
Input leakage current
(all bidirectional ports)
IIL
P
Input leakage current
(all ADC input-only ports)
TJ = –40 to
+150 °C
Input leakage current
(shared ADC input-only ports)
VILR
VIHR
VHYSR
VOLR
IPD
P RESET, low level input voltage
—
+0.1(2)
V
P RESET, high level input voltage
—
0.65 VDD_HV_IOx
—
D RESET, Schmitt trigger hysteresis
—
0.1 VDD_HV_IOx
—
—
V
D RESET, low level output voltage
IOL = 2 mA
—
—
0.5
V
RESET, equivalent pull-down
current
VIN = VIL
10
—
—
VIN = VIH
—
—
130
D
VDD_HV_IOx
μA
V
µA
1. These specifications are design targets and subject to change per device characterization.
2. “SR” parameter values must not exceed the absolute maximum ratings shown in Table 9.
3.10
Supply current characteristics
Current consumption data is given in Table 21. These specifications are design targets and
are subject to change per device characterization.
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Table 21.
Electrical characteristics
Current consumption characteristics
Symbol
IDD_LV_FULL
+ IDD_LV_PLL
Parameter
T Operating current
IDD_LV_TYP
T Operating current
+ IDD_LV_PLL(2)
IDD_LV_TYP
P Operating current
+ IDD_LV_PLL(2)
IDD_LV_BIST
+ IDD_LV_PLL
T Operating current
Conditions(1)
Min
Typ
Max
Unit
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
50 mA+
2.18 mA*fCPU[MHz]
1.2 V supplies
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
80 mA+
2.50 mA*fCPU[MHz]
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
26 mA+
2.10 mA*fCPU[MHz]
1.2 V supplies
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
41 mA+
2.30 mA*fCPU[MHz]
1.2 V supplies
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
279 mA
1.2 V supplies
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
318 mA
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
250
1.2 V supplies during
LBIST (full LBIST
configuration)
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
290
mA
mA
mA
mA
IDD_LV_TYP +
IDD_LV_PLL
T Operating current
1.2V supplies
Tj=105C
VDD_LV_COR = 1.2V
—
—
275
mA
IDD_LV_TYP +
IDD_LV_PLL
T Operating current
1.2V supplies
Tj=125C
VDD_LV_COR = 1.2V
—
—
299
mA
T Operating current
1.2V supplies
Tj=105C
VDD_LV_COR = 1.2V
DPM Mode
—
—
189
mA
T Operating current
1.2V supplies
Tj=125C
VDD_LV_COR = 1.2V
DPM Mode
—
—
214
mA
IDD_LV_TYP +
IDD_LV_PLL
IDD_LV_TYP +
IDD_LV_PLL
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Electrical characteristics
Table 21.
Current consumption characteristics (continued)
Symbol
IDD_LV_TYP +
IDD_LV_PLL
IDD_LV_STOP
IDD_LV_HALT
IDD_HV_ADC(3),
(4)
Parameter
IDD_HV_OSC
IDD_HV_FLASH
Conditions(1)
Min
Typ
Max
Unit
T Operating current
1.2V supplies
Tj=150C
VDD_LV_COR = 1.2V
DPM Mode
—
—
253
mA
T
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
50
T
Operating current in TJ = 55 °C
VDD STOP mode
VDD_LV_COR = 1.32 V
—
—
57
P
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
72
T
TJ = ambient
VDD_LV_COR = 1.32 V
—
—
58
T
Operating current in TJ = 55 °C
VDD HALT mode
VDD_LV_COR = 1.32 V
—
—
64
P
TJ = 150 °C
VDD_LV_COR = 1.32 V
—
—
80
T Operating current
TJ = 150 °C
120 MHz
ADC operating at
60 MHz
VDD_HV_ADC = 3.6 V
—
—
10
TJ = 150 °C
120 MHz
ADC operating at
60 MHz
VDD_HV_REF = 3.6 V
—
—
3
TJ = 150 °C
120 MHz
ADC operating at
60 MHz
VDD_HV_REF = 5.5 V
—
—
5
T Operating current
TJ = 150 °C
3.3 V supplies
120 MHz
—
—
900
μA
T Operating current
TJ = 150 °C
3.3 V supplies
120 MHz
—
—
4
mA
IDD_HV_AREF(4) T Operating current
(5)
SPC56XL60/54
mA
mA
mA
mA
1. Devices configured for DPM mode, single core only with Core 0 executing typical code at 120 MHz from SRAM and Core 1
in reset. If core execution mode not specified, the device is configured for LSM mode with both cores executing typical code
at 120 MHz from SRAM.
2. Enabled Modules in 'Typical mode': FlexPWM0, ETimer0/1/2, CTU, SWG, DMA, FlexCAN0/1, LINFlex, ADC1, DSPI0/1,
PIT, CRC, PLL0/1, I/O supply current excluded
3. Internal structures hold the input voltage less than VDDA + 1.0 V on all pads powered by VDDA supplies, if the maximum
injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications.
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Electrical characteristics
4. This value is the total current for both ADCs.
5. VFLASH is only available in the calibration package.
3.11
Temperature sensor electrical characteristics
Table 22.
Temperature sensor electrical characteristics
Symbol
Parameter
—
P
Accuracy
TS
D
Minimum sampling period
3.12
Conditions
TJ = –40 °C to 150 °C
—
Min
Max
Unit
–10
10
°C
4
—
µs
Main oscillator electrical characteristics
The device provides an oscillator/resonator driver. Figure 6 describes a simple model of the
internal oscillator driver and provides an example of a connection for an oscillator or a
resonator.
EXTAL
Crystal
CL
EXTAL
RP
XTAL
CL
DEVICE
VDD
I
EXTAL
Resonator
R
XTAL
DEVICE
XTAL
DEVICE
Figure 6.
Note:
Crystal oscillator and resonator connection scheme
XTAL/EXTAL must not be directly used to drive external circuits.
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Electrical characteristics
SPC56XL60/54
MTRANS
1
0
VXTAL
1/fXOSCHS
VXOSCHS
90%
VXOSCHSOP
10%
TXOSCHSSU
Figure 7.
Table 23.
Main oscillator electrical characteristics
Main oscillator electrical characteristics
×
Symbol
fXOSCHS
Parameter
Max
4.0
—
40.0
MHz
VDD = 3.3 V ±10%
4.5
—
13.25
mA/V
fOSC = 4, 8, 10, 12, 16 MHz
1.3
—
—
fOSC = 40 MHz
1.1
—
—
Oscillation operating
point
—
—
0.82
—
V
D Oscillator consumption
—
—
—
3.5
mA
—
—
6
—
—
2
0.65 × VD
—
VDD + 0.4
V
—
0.35 × VDD
V
S
Oscillator frequency
R
Oscillator
transconductance
VXOSCHS
D Oscillation amplitude
D
—
fOSC = 4, 8, 10, 12
MHz(2)
TXOSCHSSU
T Oscillator start-up time
VIH
S Input high level CMOS
R Schmitt Trigger
Oscillator bypass mode
VIL
S Input low level CMOS
R Schmitt Trigger
Oscillator bypass mode
fOSC = 16, 40 MHz(2)
V
ms
D
1. VDD = 3.3 V ±10%, TJ = –40 to +150 °C, unless otherwise specified.
2. The recommended configuration for maximizing the oscillator margin are:
XOSC_MARGIN = 0 for 4 MHz quartz
XOSC_MARGIN = 1 for 8/16/40 MHz quartz
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Unit
Typ
P
IXOSCHS
Value
Conditions(1)
Min
gmXOSCHS
VXOSCHSOP
valid internal clock
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–0.4
SPC56XL60/54
Electrical characteristics
3.13
FMPLL electrical characteristics
Table 24.
FMPLL electrical characteristics
Symbol
Parameter
fREF_CRYSTAL
FMPLL reference
D
fREF_EXT
frequency range(1)
fPLL_IN
Crystal reference
Min
Typ
Max
Unit
4
—
40
MHz
Phase detector input
D frequency range (after predivider)
—
4
—
16
MHz
Clock frequency range in
normal mode
—
4
—
120(2)
MHz
20
—
150
MHz
fFMPLLOUT D
fFREE
Conditions
P Free running frequency
Measured using clock division
(typically ÷16)
fsys
D
On-chip FMPLL
frequency(2)
—
16
—
120
MHz
tCYC
D System clock period
—
—
—
1 / fsys
ns
fLORL
fLORH
Lower limit
1.6
—
3.7
D
Upper limit
24
—
56
fSCM
D
—
20
—
150
MHz
tLOCK
P Lock time
Stable oscillator (fPLLIN = 4 MHz),
stable VDD
—
—
200
µs
Loss of reference
frequency window(3)
MHz
Self-clocked mode
frequency(4),(5)
tlpll
D FMPLL lock time (6), (7)
—
—
—
200
μs
tdc
D Duty cycle of reference
—
40
—
60
%
Long-term jitter (avg. over 2 ms
interval), fFMPLLOUT maximum
–6
—
6
ns
PHI @ 120 MHz,
Input clock @ 4 MHz
—
—
175
ps
Single period jitter (peak to PHI @ 100 MHz,
peak)
Input clock @ 4 MHz
—
—
185
ps
PHI @ 80 MHz,
Input clock @ 4 MHz
—
—
200
ps
PHI @ 16 MHz,
Input clock @ 4 MHz
—
—
±6
ns
CJITTER
ΔtPKJIT
ΔtLTJIT
T
T
CLKOUT period
jitter(8),(9),(10),(11)
T Long term jitter
fLCK
D Frequency LOCK range
—
–6
—
6
% fFMPLLOUT
fUL
D Frequency un-LOCK range
—
–18
—
18
% fFMPLLOUT
fCS
fDS
Center spread
±0.25
—
±2.0
D Modulation depth
%
Down spread
–0.5
—
-8.0
fFMPLLOUT
—
—
100
kHz
fMOD
D Modulation
frequency(12)
—
1. Considering operation with FMPLL not bypassed.
2. With FM; the value does not include a possible +2% modulation
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Electrical characteristics
SPC56XL60/54
3. “Loss of Reference Frequency” window is the reference frequency range outside of which the FMPLL is in self clocked
mode.
4. Self clocked mode frequency is the frequency that the FMPLL operates at when the reference frequency falls outside the
fLOR window.
5. fVCO is the frequency at the output of the VCO; its range is 256–512 MHz.
fSCM is the self-clocked mode frequency (free running frequency); its range is 20–150 MHz.
fSYS = fVCO÷ODF
6. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this
FMPLL, load capacitors should not exceed these limits.
7. This specification applies to the period required for the FMPLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).
8. This value is determined by the crystal manufacturer and board design.
9. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fSYS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FMPLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency increase the CJITTER
percentage for a given interval.
10. Proper PC board layout procedures must be followed to achieve specifications.
11. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of CJITTER and either
fCS or fDS (depending on whether center spread or down spread modulation is enabled).
12. Modulation depth is attenuated from depth setting when operating at modulation frequencies above 50 kHz.
3.14
16 MHz RC oscillator electrical characteristics
Table 25.
RC oscillator electrical characteristics
Symbol
fRC
3.15
Parameter
Conditions
Min
Typical
Max
Unit
—
15.04
16
16.96
MHz
P RC oscillator frequency
ADC electrical characteristics
The device provides a 12-bit Successive Approximation Register (SAR) Analog-to-Digital
Converter.
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Electrical characteristics
Offset Error OSE Gain Error GE
4095
4094
4093
4092
4091
4090
( 2)
1 LSB ideal =(VrefH-VrefL)/ 4096 =
3.3V/ 4096 = 0.806 mV
Total Unadjusted Error
TUE = +/- 6 LSB = +/- 4.84mV
code out
7
( 1)
6
5
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer
curve
(5)
4
(4)
3
(3)
2
1
1 LSB (ideal)
0
1
2
3
Offset Error OSE
Figure 8.
3.15.1
4
5
6
7
4089 4090 4091 4092 4093 4094 4095
Vin(A) (LSBideal)
ADC characteristics and error definitions
Input Impedance and ADC Accuracy
To preserve the accuracy of the A/D converter, it is necessary that analog input pins have
low AC impedance. Placing a capacitor with good high frequency characteristics at the input
pin of the device can be effective: the capacitor should be as large as possible, ideally
infinite. This capacitor contributes to attenuating the noise present on the input pin; further, it
sources charge during the sampling phase, when the analog signal source is a highimpedance source.
A real filter can typically be obtained by using a series resistance with a capacitor on the
input pin (simple RC filter). The RC filtering may be limited according to the value of source
impedance of the transducer or circuit supplying the analog signal to be measured. The filter
at the input pins must be designed taking into account the dynamic characteristics of the
input signal (bandwidth) and the equivalent input impedance of the ADC itself.
In fact a current sink contributor is represented by the charge sharing effects with the
sampling capacitance: CS being substantially a switched capacitance, with a frequency
equal to the conversion rate of the ADC, it can be seen as a resistive path to ground. For
instance, assuming a conversion rate of 1 MHz, with CS equal to 7.5 pF, a resistance of
133 kΩ is obtained (REQ = 1 / (fC × CS), where fc represents the conversion rate at the
considered channel). To minimize the error induced by the voltage partitioning between this
resistance (sampled voltage on CS) and the sum of RS + RF, the external circuit must be
designed to respect the Equation 4:
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Electrical characteristics
SPC56XL60/54
Equation 4
R +R
VA
S
F
• --------------------- < 1--- LSB
R EQ
2
Equation 4 generates a constraint for external network design, in particular on resistive
path. Internal switch resistances (RSW and RAD) can be neglected with respect to external
resistances.
EXTERNAL CIRCUIT
INTERNAL CIRCUIT SCHEME
VDD
Source
RS
Filter
RF
Current Limiter
RL
CF
VA
CP1
Channel
Selection
Sampling
RSW1
RAD
CP2
CS
RS Source Impedance
RF Filter Resistance
CF Filter Capacitance
Current Limiter Resistance
RL
RSW1 Channel Selection Switch Impedance
RAD Sampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
Figure 9.
Input Equivalent Circuit
A second aspect involving the capacitance network shall be considered. Assuming the three
capacitances CF, CP1 and CP2 are initially charged at the source voltage VA (refer to the
equivalent circuit reported in Figure 9): A charge sharing phenomenon is installed when the
sampling phase is started (A/D switch close).
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Electrical characteristics
Voltage Transient on CS
VCS
VA
VA2
ΔV < 0.5 LSB
1
2
τ1 < (RSW + RAD) CS << TS
τ2 = RL (CS + CP1 + CP2)
VA1
TS
t
Figure 10. Transient Behavior during Sampling Phase
In particular two different transient periods can be distinguished:
●
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the
sampling capacitance CS occurs (CS is supposed initially completely discharged):
considering a worst case (since the time constant in reality would be faster) in which
CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and
CS are in series, and the time constant is
Equation 5
τ 1 = ( R SW + R AD )
CP • CS
• ---------------------CP + CS
Equation 5 can again be simplified considering only CS as an additional worst
condition. In reality, the transient is faster, but the A/D converter circuitry has been
designed to be robust also in the very worst case: the sampling time TS is always much
longer than the internal time constant:
Equation 6
τ 1 < ( R SW + R AD ) • C S « T S
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the
voltage VA1 on the capacitance according to Equation 7:
Equation 7
V A1 • ( C S + C P1 + C P2 ) = V A • ( C P1 + C P2 )
●
A second charge transfer involves also CF (that is typically bigger than the on-chip
capacitance) through the resistance RL: again considering the worst case in which CP2
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Electrical characteristics
SPC56XL60/54
and CS were in parallel to CP1 (since the time constant in reality would be faster), the
time constant is:
Equation 8
τ 2 < R L • ( C S + C P1 + C P2 )
In this case, the time constant depends on the external circuit: in particular imposing
that the transient is completed well before the end of sampling time TS, a constraints on
RL sizing is obtained:
Equation 9
10 • τ 2 = 10 • R L • ( C S + C P1 + C P2 ) < TS
Of course, RL shall be sized also according to the current limitation constraints, in
combination with RS (source impedance) and RF (filter resistance). Being CF
definitively bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the
charge transfer transient) will be much higher than VA1. Equation 10 must be respected
(charge balance assuming now CS already charged at VA1):
Equation 10
VA2 • ( C S + C P1 + C P2 + C F ) = V A • C F + V A1 • ( C P1 + C P2 + C S )
The two transients above are not influenced by the voltage source that, due to the presence
of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on
CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with
respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing.
Analog Source Bandwidth (VA)
TC ≤ 2 RFCF (Conversion Rate vs. Filter Pole)
Noise
fF = f0 (Anti-aliasing Filtering Condition)
2 f0 ≤ fC (Nyquist)
f0
f
Anti-Aliasing Filter (fF = RC Filter pole)
fF
Figure 11.
f
Sampled Signal Spectrum (fC = conversion Rate)
f0
fC
f
Spectral representation of input signal
Calling f0 the bandwidth of the source signal (and as a consequence the cut-off frequency of
the anti-aliasing filter, fF), according to the Nyquist theorem the conversion rate fC must be at
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Electrical characteristics
least 2f0; it means that the constant time of the filter is greater than or at least equal to twice
the conversion period (TC). Again the conversion period TC is longer than the sampling time
TS, which is just a portion of it, even when fixed channel continuous conversion mode is
selected (fastest conversion rate at a specific channel): in conclusion it is evident that the
time constant of the filter RFCF is definitively much higher than the sampling time TS, so the
charge level on CS cannot be modified by the analog signal source during the time in which
the sampling switch is closed.
The considerations above lead to impose new constraints on the external circuit, to reduce
the accuracy error due to the voltage drop on CS; from the two charge balance equations
above, it is simple to derive Equation 11 between the ideal and real sampled voltage on CS:
Equation 11
C P1 + C P2 + C F
VA
------------ = -------------------------------------------------------V A2
C P1 + C P2 + C F + C S
From this formula, in the worst case (when VA is maximum, that is for instance 5 V),
assuming to accept a maximum error of half a count, a constraint is evident on CF value:
Equation 12
C F > 8192 • C S
Table 26.
ADC conversion characteristics
Conditions(1)
Min
ADC Clock frequency (depends on ADC
S configuration)
R (The duty cycle depends on AD_CK(2)
frequency)
—
3
—
S
Sampling frequency
R
—
—
—
60 MHz
383
60 MHz
Symbol
fCK
fs
tsample
Parameter
D Sample time(4)
time(5)
Typ Max
60
983.6
Unit
MHz
(3)
KHz
—
—
ns
600
—
—
ns
tconv
D Conversion
CS(6)
D ADC input sampling capacitance
—
—
—
7.32
pF
CP1(6)
D ADC input pin capacitance 1
—
—
—
5((7))
pF
CP2(6)
D ADC input pin capacitance 2
—
—
—
0.8
pF
VREF range = 4.5 to 5.5 V
—
—
0.3
kΩ
VREF range = 3.0 to 3.6 V
—
—
875
W
RSW1(6)
D Internal resistance of analog source
RAD(6)
D Internal resistance of analog source
—
—
—
825
W
P Integral non linearity
—
–3
—
3
LSB
—
–1
—
2
LSB
INL
linearity(8)
DNL
P Differential non
OFS
T Offset error
—
–6
—
6
LSB
GNE
T Gain error
—
–6
—
6
LSB
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Electrical characteristics
Table 26.
SPC56XL60/54
ADC conversion characteristics (continued)
Symbol
Conditions(1)
Parameter
Min
Typ Max
Unit
(single ADC channel)
IS1WINJ
Max leakage
150C
—
—
250
nA
–3
—
3
mA
150C
—
—
300
nA
|Vref_ad0 - Vref_ad1| <
150mV
–3.6
—
3.6
mA
Max positive/negative injection
(double ADC channel)
Max leakage
IS1WWINJ
Max positive/negative injection
SNR
T Signal-to-noise ratio
Vref = 3.3V
67
—
—
dB
SNR
T Signal-to-noise ratio
Vref = 5.0V
69
—
—
dB
THD
T Total harmonic distortion
—
-65
—
—
dB
SINAD
T Signal-to-noise and distortion
—
65
—
—
dB
ENOB
T Effective number of bits
—
10.5
—
—
bits
Without current injection
–6
—
6
LSB
With current injection
–8
—
8
LSB
Without current injection
–8
—
8
LSB
With current injection
–10
—
10
LSB
TUEIS1WINJ T
TUEIS1WWINJ
Total unadjusted error for IS1WINJ (single
ADC channels)
P Total unadjusted error for IS1WWINJ
T (double ADC channels)
1. VDD = 3.3 V, TJ = –40 to +150 °C, unless otherwise specified and analog input voltage from VAGND to VAREF.
2. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.
3. This is the maximum frequency that the analog portion of the ADC can attain. A sustained conversion at this frequency is
not possible.
4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the
sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample
clock tsample depend on programming.
5. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to
load the result register with the conversion result.
6. See Figure 9.
7. For the 144-pin package
8. No missing codes
3.16
Flash memory electrical characteristics
Table 27.
Flash memory program and erase electrical specifications
No.
Symbol
Parameter
TDWPROGRAM
*(4)
TPPROGRAM
*(5)
Page(128 bits) program
3
T16KPPERASE
*(5)
4
T48KPPERASE
*(5)
1
2
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Double word (64 bits) program time(4)
Initial
Lifetime
Typ Factory
Unit
Max
(1)
Avg
Max(3)
(2)
38
—
—
500
µs
45
53
160
500
µs
16 KB block pre-program and erase time
270
1000
500
5000
ms
48 KB block pre-program and erase time
625
1500
750
5000
ms
time(5)
Doc ID 15457 Rev 8
SPC56XL60/54
Table 27.
No.
5
6
7
Electrical characteristics
Flash memory program and erase electrical specifications
Symbol
Parameter
Initial
Lifetime
Typ Factory
Unit
Max
(1)
Avg
Max(3)
(2)
T64KPPERASE
*(5)
64 KB block pre-program and erase time
800
1800
900
5000
ms
T128KPPERASE
(5)
128 KB block pre-program and erase time
1500 2600
1300
7500
ms
(5)
256 KB block pre-program and erase time
3000 5200
2600
15000
ms
T256KPPERASE
*
*
1. Typical program and erase times represent the median performance and assume nominal supply values and
operation at 25C. These values are characterized, but not tested.I
2. Initial Max program and erase times provide guidance for time-out limits used in the factory and apply for <
100 program/erase cycles, nominal supply values and operation at 25C. These values are verified at production
test.
3. Lifetime Max program and erase times apply across the voltage, temperature, and cycling range of product
life. These values are characterized, but not tested.
4. Program times are actual hardware programming times and do not include software overhead.
5. Program times are actual hardware programming times and do not include software overhead.
Table 28.
Flash memory timing
Value
Symbol
Parameter
Unit
Min
Typ
Max
TRES
D
Time from clearing the MCR-ESUS or PSUS bit with EHV = 1
until DONE goes low
—
—
100
ns
TDONE
D
Time from 0 to 1 transition on the MCR-EHV bit initiating a
program/erase until the MCR-DONE bit is cleared
—
—
5
ns
TPSRT
D
Time between program suspend resume and the next program
suspend request.(1)
100
—
—
µs
TESRT
D
Time between erase suspend resume and the next erase
suspend request.(2)
10
ms
1. Repeated suspends at a high frequency may result in the operation timing out, and the flash module will
respond by completing the operation with a fail code (MCR[PEG] = 0), or the operation not able to finish
(MCR[DONE] = 1 during Program operation). The minimum time between suspends to ensure this does not
occur is TPSRT.
2. If Erase suspend rate is less than TESRT, an increase of slope voltage ramp occurs
during erase pulse. This improves erase time but reduces cycling figure due to
overstress
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Electrical characteristics
Table 29.
SPC56XL60/54
Flash memory module life
Value
No.
Symbol
Parameter
Unit
Minimum
1
P/E
Number of program/erase cycles per block for 16 KB,
C 48 KB, and 64 KB blocks over the operating temperature
range(1)
2
P/E
Number of program/erase cycles per block for 128 KB
C and 256 KB blocks over the operating temperature
range(1)
Minimum data retention at 85 °C average ambient
temperature(3)
3 Retention C Blocks with 0–1,000 P/E cycles
Blocks with 1,001–10,000 P/E cycles
Blocks with 10,001–100,000 P/E cycles
Typical Maximum
100000
—
—
cycles
1000
100000(2)
—
cycles
20
10
5
—
—
—
—
—
—
years
1. Operating temperature range is TJ from –40 °C to 150 °C. Typical endurance is evaluated at 25 °C.
2. Typical P/E cycles is 100,000 cycles for 128 KB and 256 KB blocks.
3. Ambient temperature averaged over duration of application, not to exceed product operating temperature range.
3.17
SWG electrical characteristics
Table 30.
MPC5643L SWG Specifications
Value
Symbol
Parameter
T
Input clock
T
Frequency Range
Peak(1)
T
Peak to
T
Peak to Peak variation(2)
(3)
Minimum
Typical
Maximum
12 MHz
16 MHz
20 MHz
1kHz
—
50 kHz
0.4 V
—
2.0V
-6%
—
6%
—
1.3 V
—
T
Common Mode
T
Common Mode variation
-6%
—
6%
T
SiNAD(4)
45 dB
—
—
T
Load C
25 pF
—
100 pF
T
Load I
0 µA
—
100 µA
230 Ω
—
360 Ω
T
ESD Pad Resistance
(5)
1. Peak to Peak value is measured with no R or I load.
2. Peak to Peak excludes noise, SiNAD must be considered.
3. Common mode value is measured with no R or I load.
4. SiNAD is measured at Max Peak to Peak voltage.
5. Internal device routing resistance. ESD pad resistance is in series and must be considered for max Peak to Peak voltages,
depending on application I load and/or R load.
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Electrical characteristics
3.18
AC specifications
3.18.1
Pad AC specifications
Table 31.
Pad AC specifications (3.3 V , IPP_HVE = 0 )(1)
No.
1
2
3
4
Tswitchon(1)
(ns)
Pad
Slow
Medium
Fast
Symmetric
Rise/Fall(2)
(ns)
Current slew(3)
(mA/ns)
Frequency
(MHz)
Load drive
(pF)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
3
—
40
—
—
40
—
—
4
0.01
—
2
25
3
—
40
—
—
50
—
—
2
0.01
—
2
50
3
—
40
—
—
75
—
—
2
0.01
—
2
100
3
—
40
—
—
100
—
—
2
0.01
—
2
200
1
—
15
—
—
12
—
—
40
2.5
—
7
25
1
—
15
—
—
25
—
—
20
2.5
—
7
50
1
—
15
—
—
40
—
—
13
2.5
—
7
100
1
—
15
—
—
70
—
—
7
2.5
—
7
200
1
—
6
—
—
4
—
—
72
3
—
40
25
1
—
6
—
—
7
—
—
55
7
—
40
50
1
—
6
—
—
12
—
—
40
7
—
40
100
1
—
6
—
—
18
—
—
25
7
—
40
200
1
—
8
—
—
5
—
—
50
3
—
25
25
T
T
T
T
1. Propagation delay from VDD_HV_IOx/2 of internal signal to Pchannel/Nchannel switch-on condition.
2. Slope at rising/falling edge.
3. Data based on characterization results, not tested in production.
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Electrical characteristics
SPC56XL60/54
VDDE/2
Pad
Data Input
Rising
Edge
Output
Delay
Falling
Edge
Output
Delay
VOH
Pad
Output
VOL
Figure 12. Pad output delay
3.19
Reset sequence
This section shows the duration for different reset sequences. It describes the different reset
sequences and it specifies the start conditions and the end indication for the reset
sequences.
3.19.1
Reset sequence duration
Table 32 specifies the minimum and the maximum reset sequence duration for the five
different reset sequences described in Section 3.19.2, Reset sequence description.
Table 32.
No.
RESET sequences
Symbol
Parameter
TReset
Conditions
Unit
Min
Typ
Max(1)
40
47
51
ms
500
4200
5000
µs
41
45
49
ms
1
TDRB
CC
Destructive Reset Sequence, BIST
enabled
2
TDR
CC
Destructive Reset Sequence, BIST
disabled
3
TERLB
CC
External Reset Sequence Long, BIST
enabled
4
TFRL
CC
Functional Reset Sequence Long
—
35
150
400
µs
5
TFRS
CC
Functional Reset Sequence Short
—
1
4
10
µs
—
1. The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET
by an external reset generator.
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SPC56XL60/54
3.19.2
Electrical characteristics
Reset sequence description
The figures in this section show the internal states of the chip during the five different reset
sequences. The doted lines in the figures indicate the starting point and the end point for
which the duration is specified in Table 32. The start point and end point conditions as well
as the reset trigger mapping to the different reset sequences is specified in Section 3.19.3,
Reset sequence trigger mapping.
With the beginning of DRUN mode the first instruction is fetched and executed. At this point
application execution starts and the internal reset sequence is finished.
The figures below show the internal states of the chip during the execution of the reset
sequence and the possible states of the signal pin RESET.
Note:
RESET is a bidirectional pin. The voltage level on this pin can either be driven low by an
external reset generator or by the chip internal reset circuitry. A high level on this pin can
only be generated by an external pull up resistor which is strong enough to overdrive the
weak internal pull down resistor. The rising edge on RESET in the following figures indicates
the time when the device stops driving it low. The reset sequence durations given in table
Table 32 are applicable only if the internal reset sequence is not prolonged by an external
reset generator keeping RESET asserted low beyond the last PHASE3.
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
RESET_B
PHASE0
PHASE1,2
Establish IRC
and PWR
Flash init
PHASE3
BIST
Device
Self Test
Config
Setup
MBIST
PHASE1,2
LBIST
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TDRB, min < TReset < TDRB, max
Figure 13. Destructive Reset Sequence, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE0
PHASE1,2
Establish IRC
and PWR
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TDR, min < TReset < TDR, max
Figure 14. Destructive Reset Sequence, BIST disabled
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Electrical characteristics
SPC56XL60/54
Reset Sequence Trigger
Reset Sequence Start Condition
RESET
RESET_B
PHASE1,2
Flash init
PHASE3
BIST
Device
Self Test
Config
Setup
MBIST
PHASE1,2
LBIST
PHASE3
Flash init
Device
Application
Config
Execution
TERLB, min < TReset < TERLB, max
Figure 15. External Reset Sequence Long, BIST enabled
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE1,2
Flash init
PHASE3
DRUN
Device
Application
Config
Execution
TFRL, min < TReset < TFRL, max
Figure 16. Functional Reset Sequence Long
Reset Sequence Trigger
Reset Sequence Start Condition
RESET_B
RESET
PHASE3
DRUN
Application
Execution
TFRS, min < TReset < TFRS, max
Figure 17. Functional Reset Sequence Short
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DRUN
SPC56XL60/54
Electrical characteristics
The reset sequences shown in Figure 16 and Figure 17 are triggered by functional reset
events. RESET is driven low during these two reset sequences only if the corresponding
functional reset source (which triggered the reset sequence) was enabled to drive RESET
low for the duration of the internal reset sequence(c).
3.19.3
Reset sequence trigger mapping
The following table shows the possible trigger events for the different reset sequences. It
specifies the reset sequence start conditions as well as the reset sequence end indications
that are the basis for the timing data provided in Table 32.
Table 33.
Reset sequence trigger — reset sequence
Reset Sequence
Reset
Sequence
Trigger
All internal
destructive reset
sources
(LVDs or
internal HVD
during power-up
and during
operation)
Reset
Sequence
Start
Condition
Reset
Sequence
End
Indication
Section ,
Destructive
reset
All internal
functional reset
sources
configured for
long reset
All internal
functional reset
sources
configured for
short reset
Functiona
l Reset
Sequenc
e Long
Functiona
l Reset
Sequenc
e Short
triggers
cannot
trigger
cannot
trigger
cannot
trigger
cannot trigger
triggers(4)
triggers(5)
triggers(6)
cannot trigger
cannot
trigger
triggers
cannot
trigger
cannot trigger
cannot
trigger
cannot
trigger
triggers
Destructiv
e Reset
Sequence,
BIST
disabled(1)
Release of
RESET(2)
Section ,
External
reset via
RESET
Assertion of
RESET(3)
External
Reset
Sequenc
e Long,
BIST
enabled
Destructiv
e Reset
Sequence,
BIST
enabled(1)
Sequence
starts with
internal
reset
trigger
Release of
RESET(7)
1. Whether BIST is executed or not depends on the chip configuration data stored in the shadow sector of the NVM.
2. End of the internal reset sequence (as specified in Table 32) can only be observed by release of RESET if it is not held low
externally beyond the end of the internal sequence which would prolong the internal reset PHASE3 till RESET is released
externally.
c.
See RGM_FBRE register for more details.
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Electrical characteristics
SPC56XL60/54
3. The assertion of RESET can only trigger a reset sequence if the device was running (RESET released) before. RESET
does not gate a Destructive Reset Sequence, BIST enabled or a Destructive Reset Sequence, BIST disabled. However, it
can prolong these sequences if RESET is held low externally beyond the end of the internal sequence (beyond PHASE3).
4. If RESET is configured for long reset (default) and if BIST is enabled via chip configuration data stored in the shadow sector
of the NVM.
5. If RESET is configured for long reset (default) and if BIST is disabled via chip configuration data stored in the shadow
sector of the NVM.
6. If RESET is configured for short reset
7. Internal reset sequence can only be observed by state of RESET if bidirectional RESET functionality is enabled for the
functional reset source which triggered the reset sequence.
3.19.4
Reset sequence — start condition
The impact of the voltage thresholds on the starting point of the internal reset sequence are
becoming important if the voltage rails / signals ramp up with a very slow slew rate
compared to the overall reset sequence duration.
Destructive reset
Figure 18 shows the voltage threshold that determines the start of the Destructive Reset
Sequence, BIST enabled and the start for the Destructive Reset Sequence, BIST disabled.
V
Supply Rail
Vmax
Vmin
TReset, max starts here
TReset, min starts here
Figure 18. Reset sequence start for Destructive Resets
Table 34.
Voltage Thresholds
Variable name
Vmin
Vmax
Supply Rail
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Value
Refer to Table 19
Refer to Table 19
VDD_HV_PMU
Doc ID 15457 Rev 8
t
SPC56XL60/54
Electrical characteristics
External reset via RESET
Figure 19 shows the voltage thresholds that determine the start of the reset sequences
initiated by the assertion of RESET as specified in Table 33.
V
RESET_B
RESET
0.65 * VDD_HV_IO
0.35 * VDD_HV_IO
t
TReset, max starts here
TReset, min starts here
Figure 19. Reset sequence start via RESET assertion
3.19.5
External watchdog window
If the application design requires the use of an external watchdog the data provided in
Section 3.19, Reset sequence can be used to determine the correct positioning of the
trigger window for the external watchdog. Figure 20 shows the relationships between the
minimum and the maximum duration of a given reset sequence and the position of an
external watchdog trigger window.
Watchdog needs to be triggered within this window
TWDStart, min
External Watchdog Window Closed
External Watchdog Window Open
TWDStart, max
External Watchdog Window Closed
External Watchdog Window Open
Watchdog trigger
TReset, min
Basic Application Init
Application Running
TReset, max
Earliest
Application
Start
Basic Application Init
Application Running
Latest
Application
Start
Application time required to
prepare watchdog trigger
Internal Reset Sequence
Start condition (signal or voltage rail)
Figure 20. Reset sequence - External watchdog trigger window position
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Electrical characteristics
3.20
SPC56XL60/54
AC timing characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows:
• TJ = –40 to 150 C
• Supply voltages as specified in Table 10
• Input conditions: All Inputs: tr, tf = 1 ns
• Output Loading: All Outputs: 50 pF
3.20.1
RESET pin characteristics
The SPC56XL60/54 implements a dedicated bidirectional RESET pin.
VDD
VDDMIN
RESET
VIH
VIL
device reset forced by RESET
device start-up phase
Figure 21. Start-up reset requirements
VRESET
hw_rst
VDD
‘1’
VIH
VIL
‘0’
filtered by
hysteresis
filtered by
lowpass filter
WFRST
filtered by
lowpass filter
unknown reset
state
WFRST
WNFRST
Figure 22. Noise filtering on reset signal
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device under hardware reset
SPC56XL60/54
Table 35.
No.
1
Electrical characteristics
RESET electrical characteristics
Symbol
Parameter
Conditions(1)
Min
Typ
Max
CL = 25pF
—
—
12
CL = 50pF
—
—
25
CL = 100pF
—
—
40
—
—
—
40
ns
—
500
—
—
ns
Output transition time output
D
pin(2)
Ttr
2
WFRST
3
WNFRST P nRESET input not filtered pulse
P nRESET input filtered pulse
Unit
ns
1. VDD = 3.3 V ± 10%, TJ = –40 to +150 °C, unless otherwise specified
2. CL includes device and package capacitance (CPKG < 5 pF).
3.20.2
WKUP/NMI timing
Table 36.
No.
WKUP/NMI glitch filter
Symbol
Parameter
Typ
Max
Unit
1
WFNMI
D
NMI pulse width that is rejected
—
—
45
ns
2
WNFNMI
D
NMI pulse width that is passed
205
—
—
ns
3.20.3
IEEE 1149.1 JTAG interface timing
Table 37.
JTAG pin AC electrical characteristics
No.
Min
Symbol
Parameter
Conditions
Min Max Unit
1
tJCYC
D TCK cycle time
—
62.5
—
ns
2
tJDC
D TCK clock pulse width (measured at VDDE/2)
—
40
60
%
3
tTCKRISE
D TCK rise and fall times (40%–70%)
—
—
3
ns
4
tTMSS, tTDIS
D TMS, TDI data setup time
—
5
—
ns
5
tTMSH, tTDIH D TMS, TDI data hold time
—
25
—
ns
6
tTDOV
D TCK low to TDO data valid
—
—
20
ns
7
tTDOI
D TCK low to TDO data invalid
—
0
—
ns
8
tTDOHZ
D TCK low to TDO high impedance
—
—
20
ns
11
tBSDV
D TCK falling edge to output valid
—
—
50
ns
12
tBSDVZ
D TCK falling edge to output valid out of high impedance
—
—
50
ns
13
tBSDHZ
D TCK falling edge to output high impedance
—
—
50
ns
14
tBSDST
D Boundary scan input valid to TCK rising edge
—
50
—
ns
15
tBSDHT
D TCK rising edge to boundary scan input invalid
—
50
—
ns
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Electrical characteristics
SPC56XL60/54
TCK
2
3
2
1
3
Figure 23. JTAG test clock input timing
TCK
4
5
TMS, TDI
6
8
7
TDO
Figure 24. JTAG test access port timing
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Electrical characteristics
TCK
11
13
Output
Signals
12
Output
Signals
14
15
Input
Signals
Figure 25. JTAG boundary scan timing
3.20.4
Nexus timing
Table 38.
Nexus debug port timing(1)
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
tMCYC
D MCKO Cycle Time
—
15.6
—
ns
2
tMDC
D MCKO Duty Cycle
—
40
60
%
3
tMDOV
D MCKO Low to MDO, MSEO, EVTO Data Valid(2)
—
–0.1
0.25
tMCY
4
5
C
tEVTIPW
D EVTI Pulse Width
tEVTOPW
D EVTO Pulse Width
—
4.0
—
tTCY
C
—
tMCY
1
C
6
tTCYC
D TCK Cycle
7
tTDC
8
tNTDIS,
tNTMSS
Time(3)
—
62.5
—
ns
D TCK Duty Cycle
—
40
60
%
D TDI, TMS Data Setup Time
—
8
—
ns
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Electrical characteristics
SPC56XL60/54
Nexus debug port timing(1) (continued)
Table 38.
No.
Symbol
9
tNTDIH,
tNTMSH
10
tJOV
Parameter
Conditions
Min
Max
Unit
D TDI, TMS Data Hold Time
5
—
ns
D TCK Low to TDO/RDY Data Valid
0
25
ns
1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured
from 50% of MCKO and 50% of the respective signal.
2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.
3. The system clock frequency needs to be four times faster than the TCK frequency.
1
2
MCKO
3
MDO
MSEO
EVTO
Output Data Valid
5
Figure 26. Nexus output timing
4
EVTI
Figure 27. Nexus EVTI Input Pulse Width
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Electrical characteristics
MCKO
MDO, MSEO
MDO/MSEO data are valid during MCKO rising and falling edge
Figure 28. Nexus Double Data Rate (DDR) Mode output timing
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Electrical characteristics
SPC56XL60/54
6
7
TCK
8
9
TMS, TDI
10
TDO/RDY
Figure 29. Nexus TDI, TMS, TDO timing
3.20.5
External interrupt timing (IRQ pin)
Table 39.
External interrupt timing
No.
Symbol
Parameter
Conditions
Min
Max
Unit
1
tIPWL
D
IRQ pulse width low
—
3
—
tCYC
2
tIPWH
D
IRQ pulse width high
—
3
—
tCYC
—
6
—
tCYC
3
tICYC
D
IRQ edge to edge
time(1)
1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both.
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SPC56XL60/54
Electrical characteristics
IRQ
1
2
3
Figure 30. External interrupt timing
3.20.6
DSPI timing
Table 40.
DSPI timing
No.
Symbol
Parameter
D
1
tSCK
D
Conditions
Master (MTFE = 0)
DSPI cycle time
Slave (MTFE = 0)
(1)
D
Slave Receive Only Mode
Min
Max
62
—
62
—
16
—
Unit
ns
2
tCSC
D
PCS to SCK delay
—
16
—
ns
3
tASC
D
After SCK delay
—
16
—
ns
4
tSDC
D
SCK duty cycle
—
5
tA
D
Slave access time
SS active to SOUT valid
—
40
ns
6
tDIS
D
Slave SOUT disable time
SS inactive to SOUT High-Z or
invalid
—
10
ns
7
tPCSC
D
PCSx to PCSS time
—
13
—
ns
8
tPASC
D
PCSS to PCSx time
—
13
—
ns
Master (MTFE = 0)
20
—
Slave
2
—
Master (MTFE = 1, CPHA = 0)
5
—
Master (MTFE = 1, CPHA = 1)
20
—
Master (MTFE = 0)
–5
—
Slave
4
—
Master (MTFE = 1, CPHA = 0)
11
—
Master (MTFE = 1, CPHA = 1)
–5
—
Master (MTFE = 0)
—
4
Slave
—
23
Master (MTFE = 1, CPHA = 0)
—
12
Master (MTFE = 1, CPHA = 1)
—
4
9
10
tSUI
tHI
11 tSUO
D
D
D
tSCK/2 - 10 tSCK/2 + 10 ns
ns
Data setup time for inputs
Data hold time for inputs
ns
Data valid (after SCK edge)
ns
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Electrical characteristics
Table 40.
No.
12
DSPI timing (continued)
Symbol
tHO
SPC56XL60/54
D
Parameter
Conditions
Min
Max
Master (MTFE = 0)
–2
—
Slave
6
—
Master (MTFE = 1, CPHA = 0)
6
—
Master (MTFE = 1, CPHA = 1)
–2
—
Data hold time for outputs
ns
1. Slave Receive Only Mode can operate at a maximum frequency of 60 MHz. In this mode, the DSPI can receive data on
SIN, but no valid data is transmitted on SOUT.
2
3
PCSx
1
4
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
10
9
SIN
First Data
Data
12
SOUT
First Data
Last Data
11
Data
Last Data
The numbers shown are referenced in Table 40.
Figure 31. DSPI classic SPI timing — master, CPHA = 0
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Unit
Doc ID 15457 Rev 8
SPC56XL60/54
Electrical characteristics
PCSx
SCK Output
(CPOL=0)
10
SCK Output
(CPOL=1)
9
Data
First Data
SIN
Last Data
12
SOUT
11
Data
First Data
Last Data
The numbers shown are referenced in Table 40.
Figure 32. DSPI classic SPI timing — master, CPHA = 1
3
2
SS
1
4
SCK Input
(CPOL=0)
4
SCK Input
(CPOL=1)
5
SOUT
First Data
9
SIN
12
11
Data
Last Data
Data
Last Data
6
10
First Data
The numbers shown are referenced in Table 40.
Figure 33. DSPI classic SPI timing — slave, CPHA = 0
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Electrical characteristics
SPC56XL60/54
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
SOUT
First Data
9
SIN
Data
Last Data
Data
Last Data
10
First Data
The numbers shown are referenced in Table 40.
Figure 34. DSPI classic SPI timing — slave, CPHA = 1
3
PCSx
4
1
2
SCK Output
(CPOL=0)
4
SCK Output
(CPOL=1)
9
SIN
First Data
10
12
SOUT
First Data
Last Data
Data
11
Data
Last Data
The numbers shown are referenced in Table 40.
Figure 35. DSPI modified transfer format timing — master, CPHA = 0
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Electrical characteristics
PCSx
SCK Output
(CPOL=0)
SCK Output
(CPOL=1)
10
9
SIN
First Data
Last Data
Data
12
First Data
SOUT
11
Last Data
Data
The numbers shown are referenced in Table 40.
Figure 36. DSPI modified transfer format timing — master, CPHA = 1
3
2
SS
1
SCK Input
(CPOL=0)
4
4
SCK Input
(CPOL=1)
SOUT
First Data
Data
First Data
6
Last Data
10
9
SIN
12
11
5
Data
Last Data
The numbers shown are referenced in Table 40.
Figure 37. DSPI modified transfer format timing – slave, CPHA = 0
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Electrical characteristics
SPC56XL60/54
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
11
5
6
12
First Data
SOUT
9
Last Data
Data
Last Data
10
First Data
SIN
Data
The numbers shown are referenced in Table 40.
Figure 38. DSPI modified transfer format timing — slave, CPHA = 1
8
7
PCSS
PCSx
The numbers shown are referenced in Table 40.
Figure 39. DSPI PCS strobe (PCSS) timing
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Package characteristics
4
Package characteristics
4.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
4.2
Package mechanical data
Figure 40. LQFP100 package mechanical drawing
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Package characteristics
Table 41.
SPC56XL60/54
LQFP100 mechanical data
inches(1)
mm
Symbol
Min
Typ
Max
Min
Typ
Max
A
—
—
1.600
—
—
0.0630
A1
0.050
—
0.150
0.0020
—
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
—
0.200
0.0035
—
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
—
12.000
—
—
0.4724
—
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
—
12.000
—
—
0.4724
—
e
—
0.500
—
—
0.0197
—
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
—
1.000
—
—
0.0394
—
k
0.0 °
3.5 °
7.0 °
0.0 °
3.5 °
7.0 °
Tolerance
mm
inches
ccc
0.080
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package characteristics
Figure 41. LQFP144 package mechanical drawing
Table 42.
LQFP144 mechanical data
inches(1)
mm
Symbol
Typ
Min
A
Max
Typ
Min
1.6
A1
0.05
0.15
Max
0.0630
0.0020
0.0059
A2
1.4
1.35
1.45
0.0551
0.0531
0.0571
b
0.22
0.17
0.27
0.0087
0.0067
0.0106
0.09
0.2
0.0035
0.0079
c
D
22
21.8
22.2
0.8661
0.8583
0.8740
D1
20
19.8
20.2
0.7874
0.7795
0.7953
D3
17.5
E
22
0.8583
0.8740
0.6890
21.8
22.2
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Package characteristics
Table 42.
SPC56XL60/54
LQFP144 mechanical data (continued)
inches(1)
mm
Symbol
Typ
Min
Max
Typ
Min
Max
E1
20
19.8
20.2
0.7874
0.7795
0.7953
E3
17.5
0.6890
e
0.5
0.0197
L
0.6
0.0177
0.0295
L1
1
k
3.5°
0.0°
7.0°
0.45
0.75
0.0236
0.0394
0.0°
7.0°
3.5°
Tolerance
mm
inches
ccc
0.08
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
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Package characteristics
Figure 42. LFBGA257 package mechanical drawing
Table 43.
LFBGA257 mechanical data
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Package characteristics
SPC56XL60/54
TITLE: LFBGA 14x14x1.7 257 F17x17 PITCH 0.8 BALL 0.4
PACKAGE CODE:
JEDEC/EIAJ REFERENCE NUMBER: JEDEC STANDARD NO.95 SECTION 4.5
(Fine pitch, Square Ball Grid Array Package Design Guide)
DIMENSIONS
DATABOOK
(mm)
REF.
MIN.
TYP.
A
A1
DRAWING
(mm)
MAX.
MIN.
TYP.
1.70
0.21
MAX.
NOTES
1.45
(1)
0.25
0.30
0.35
1.14
A2
1.085
1.03
1.085
A3
0.30
0.26
0.30
0.34
0.77
0.785
0.80
A4
0.80
b
0.35
0.40
0.45
0.35
0.40
0.45
D
13.85
14.00
14.15
13.85
14.00
14.15
13.85
14.00
14.15
13.85
14.00
D1
E
12.80
(2)
12.80
E1
12.80
12.80
e
0.80
0.80
F
0.6
14.15
0.6
ddd
0.12
eee
0.15
0.12
0.15
(3)
fff
0.08
0.08
(4)
NOTES:
(1) - LFBGA stands for Low profile Fine Pitch Ball Grid Array.
- Low Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component
- The maximum total package height is calculated by the following methodology:
A2 Typ+A1 Typ +¥ (A1²+A3²+A4² tolerance values)
- Low profile: 1.20mm < A ” 1.70mm / Fine pitch: e < 1.00mm pitch.
(2) – The typical ball diameter before mounting is 0.40mm.
(3) - The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position
with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie
within this tolerance zone.
(4) - The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position
as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
Each tolerance zone fff in the array is contained entirely in the respective zone eee above
The axis of each ball must lie simultaneously in both tolerance zones.
(5) - The terminal A1 corner must be identified on the top surface by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heatslug.
- A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1
corner. Exact shape of each corner is optional.
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5
Ordering information
Ordering information
Figure 43. Commercial product code structure(d)
Example code:
Product identifier Core Family Memory Package Temperature Device options Conditioning
SPC56
E
L
60
L5
C
B F
Q
Y
Y = Tray
R = Tape and Reel
Q = Quality management safety level
S = ASILD/SIL3 safety level
O = No FlexRay
F = FlexRay
C = 80 MHz
B = 120 MHz
B = –40 °C to 105 °C
C = –40 °C to 125 °C
L3 = LQFP100
L5 = LQFP144
60 = 1 MB flash memory
54 = 768 K flash memory
L = SPC56XL family
E = e200z4d dual core
4 = Single core
SPC56 = Power Architecture in 90 nm
d. Not all configurations are available on the market. Please contact your ST Sales Rappresentative to get the list of orderable
commercial part number.
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Revision history
SPC56XL60/54
6
Revision history
Table 44.
Document revision history
Date
Revision
02-Mar-2009
1
Initial release.
05-May-2009
2
Updated, Advance Information.
– Revised SINAD/SNR specifications.
– Updated pinout and pin multiplexing information.
3
Updated, Advance Information, Public release.
– Throughout this document, added information for LFBGA257 package.
– Updated feature summary.
– Updated Table 1, SPC56XL60/54 device summary.
– Updated Section 1.3, Feature Details.
– Updated pin-out and pin multiplexing tables.
– In Section 3, Electrical characteristics, added symbols for signal
characterization methods.
– In Table 9, updated maximum ratings.
– In Table 12 and Table 13, removed moving-air thermal characteristics.
– Updated Section 3.8, Voltage regulator electrical characteristics.
– Updated Section 3.14, ADC electrical characteristics.
– Updated Section 3.15, Flash memory electrical characteristics.
– Updated Section 3.17.1, RESET pin characteristics.
– Removed External interrupt timing (IRQ pin) timing specifications.
– Updated Section 3.17.6, DSPI timing.
Updated Section 5, Ordering information.
4
Editorial changes and improvements.
Revised the 257-pin package pin pitch (was 1.4 mm, is 0.8 mm).
Added information about the 100-pin LQFP.
In the Overview section:
– Renamed the peripheral bridge to “PBRIDGE”.
– Revised the information for FlexRay.
– Revised the “Clock, reset, power, mode and test control module” section.
– Revised the “Platform memory access time summary” table and replaced
TBDs by meaningful values.
Extensive revisions to signal descriptions and pin muxing information.
In the “Recommended operating conditions (3.3 V)” table, changed the
specification for VDD_HV_ADR0 and VDD_HV_ADR1 (was “...3.3 V”, is “...3.6 V”).
Revised the “EMI testing specifications” table.
In the “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD electrical
specifications” table, added a specification for the digital low voltage detector
upper threshold.
Revised the “FMPLL electrical characteristics” table.
29-Oct-2009
14-Jun-2010
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Changes
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Table 44.
Revision history
Document revision history (continued)
Date
14-Jun-2010
23-Nov-2010
Revision
4
(continued)
5
Changes
In the “Main oscillator electrical characteristics” table, changed the maximum
specification for gmXOSCHS (was 11 mA/V, is 11.8 mA/V).
Revised the “ADC electrical characteristics” section.In the “ADC conversion
characteristics” table:
– Changed the tADC_S specification (was TBD, is minimum of 383 ns).
– Added the footnote “No missing codes” to the DNL specification.
– Added specifications for SNR, THD, SINAD, and ENOB.
Revised the “Ordering information” section.
Editorial changes and improvements.
Revised the Overview section.
Replaced references to PowerPC with references to Power Architecture.
In the feature summary, changed “As much as 128 KB on-chip SRAM” to
“128 KB on-chip SRAM”.
In the “Feature details” section:
– In the “On-chip SRAM with ECC” section, added information about required
RAM wait states.
– In the PIT section, deleted “32-bit counter for real time interrupt, clocked from
main external oscillator” (not supported on this device).
– In the flash-memory section, changed “16 KB Test” to “16 KB test sector”,
revised the wait state information, and deleted the associated Review_Q&A
content.
– In the SRAM section, revised the wait state information.
In the 100-pin pinout diagram:
– Renamed pin 41 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
– Renamed pin 42 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
In the 144-pin pinout diagram:
– Renamed pin 58 (was VDD_HV_ADV0_ADV1, is VDD_HV_ADV).
– Renamed pin 59 (was VSS_HV_ADV0_ADV1, is VSS_HV_ADV).
Added the “LQFP100 pin function summary” table.
In the “LQFP144 pin function summary” table, for pin 39, changed VSS_LV_COR
to VDD_LV_COR.
In the “Supply pins” table:
– Changed the description for VDD_LV_COR (was “Voltage regulator supply
voltage”, is “Core logic supply”).
– Changed the description for VDD_HV_PMU (was “Core regulator supply”, is
“Voltage regulator supply”).
In the “Pin muxing” table:
– In the “Pad speed” column headings, changed “SRC = 0” to “SRC = 1” and
“SRC = 1” to “SRC = 0”
– For port B[6], changed the pad speed for SRC=0 (was M, is F).
In the “Thermal characteristics” section, added meaningful values to the
thermal-characteristics tables.
Added the “SWG electrical specifications” section.
In the “Voltage regulator electrical characteristics” section, changed the table
title (was “HPREG1, HPREG2, Main LVDs, Digital HVD, and Digital LVD
electrical specifications”, is “Voltage regulator electrical characteristics”) and
revised the table.
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Revision history
Table 44.
Document revision history (continued)
Date
23-Nov-2010
23-Mar-2011
152/160
SPC56XL60/54
Revision
Changes
5
(continued)
In the “BCP68 board schematic example” figure, removed the resistor at the
base of the BCP68 transistor.
In the “DC electrical characteristics” table:
– Changed the guarantee parameter for IINJ (was P, is T).
– Added a specification for input leakage current for shared ADC input-only
ports.
Revised the “Flash memory module life” table.
In the “FMPLL electrical characteristics” table, revised the footnote defining
fSCM and fVCO.
In the “Main oscillator electrical characteristics” table:
– Changed the max specification for gmXOSCHS (was 11.8 mA/V, is 13.25
mA/V).
– Revised the conditions for TXOSCHSSU.
In the ‘RC oscillator electrical characteristics” table, deleted the specification
for ΔRCMTRIM.
Revised the “ADC conversion characteristics” table.
In the “RESET pin characteristics” section, changed “nRSTIN” to “RESET”.
Added the “Reset sequence” section.
Revised the footnotes in the “Nexus debug port timing” table.
Added the mechanical drawing for the 100-pin package.
In the “Order codes” table, added a footnote about frequency modulation to the
“Speed (MHz)” column heading.
6
Editorial changes.
In the “Document overview” section, added information about how content
specific to silicon versions (“cut1” and “cut2”) is presented.
In the isometric miniature package drawings on the front page, removed the
third dimension.
Changed Symbol from P to D for “Conversion Time” in “ADC conversion
characteristics” table.
Added classification symbol “D” to seven entries in “Voltage regulator electrical
specifications“ table.
Removed irrelevant Flexcan specs.
Updated Table “Voltage Thresholds” to reference values specified in Table
“Voltage Regulator Electrical Specifications”.
RDY pin added for cut2.
In the “System pins” table, added a footnote about the MDO0 pad speed.
Updated Rsw1 values.
Added TUE-related spec information for single and double ADC channels.
Added AC Test Timing Conditions to the “AC timing characteristics” section.
Added a statement on the first page describing cut1 versus cut2.
Moved the first paragraph from the “Description” section to the beginning of the
“Document overview” section.
Changed pad speed from “M” to “SYM” for FlexRay pins in the “Pin Muxing”
table and added this pad type to the footnote.
Moved the newly added device current specification entries from the “DC
electrical characteristics“ table into a newly created “Supply current
characteristics“ table.
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Table 44.
Revision history
Document revision history (continued)
Date
23-Mar-2011
Revision
Changes
6
(continued)
Added symbol “CC” to the description in the “Introduction” section.
Updated “Input leakage current” specs in the “DC electrical characteristics”
table.
Changed TADC_S to Tsample and TADC_C toTconv in the “ADC conversion
characteristics” table and footnotes.
Removed “IINJ” from the “ADC conversion characteristics” table as this is
included in IS1WIKNJ and IS1WWiNJ.
Changed RESET_B to RESET in the "Reset sequence" section.
Added the “Flash memory timing” table.
Added cut2 specs for TDRB and TERLB to the “Reset sequences” table.
Added “WKUP/NMI Timing” subsection and “WKUP/NMI Glitch Filter” table to
the “AC timing characteristics” section.
Added “Nexus DDR Mode output timing” table to the “Nexus timing” section.
Removed the “CLKOUT” diagram from the “External interrupt timing (IRQ pin)”
section as it is not relevant.
Corrected an error in the IRQ timing in the “External interrupt timing” figure.
Updated the tSDC parameters in the “DSPI timing” table.
Renamed the “Electromagnetic Interference (EMI) characteristics” section (is
“Electromagnetic Interference (EMI) characteristics (cut1)”) and revised all
information in that section.
In the “Voltage regulator electrical characteristics” section, added the BCX68
from Infineon to the list of supported transistors.
Revised the “Voltage regulator electrical specifications” table to include cut1
and cut2 information.
Renamed the “Supply current characteristics” section (is “Supply current
characteristics (cut2)”) and revised it to show meaningful data.
In the footnotes of the “Main oscillator electrical characteristics” table, changed
SELMARGIN to XOSC_MARGIN.
In the “ADC conversion characteristics” table:
– Changed “LSB” to “Counts”.
– Created separate rows for the TUE specifications.
Removed the BGA row from the “Temperature” table entry.
Added bullet regarding HALT and STOP in the “Clock, reset, power, mode and
test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)“
subsection of the “Features“ section.
In the “Analog-to-Digital Converter module“ subsection of the “Feature Details”
section, changed “Motor control mode“ to “CTU mode“ to be consistent with
the nomenclature used in the Reference Manual.
Updated the JCOMP entries in the “Pin function summary“ table.
Added footnotes regarding pad pull devices to NMI, TMS, TCK, and JCOMP in
the “System pins“ table.
Added “Time constant of RC filter at LVD input” parameters to the “Main supply
LVD (LVD Main) specifications“ table.
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Table 44.
Document revision history (continued)
Date
23-Mar-2011
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SPC56XL60/54
Revision
Changes
6
(continued)
In the “Supply current characteristics (cut2)“ table:
– Changed “IDD_LV_MAX” to “IDD_LV_MAX“;
– Removed all “40-120 MHz” frequency ranges from the “Conditions” column;
– Updated the “Max” values column;
– Added parameter “IDD_LV_TYP + IDD_LV_PLL“ with “P” classification and
special footnote;
– Changed all “25°C“ temperature conditions to “ambient”;
– Added “TJ = 150 °C“ condition to parameters IDD_HV_ADC, IDD_HV_AREF.,
IDD_HV_OSC, and IDD_HV_FLASH.
Changed the timing diagram in the “Main oscillator electrical characteristics”
section to reference MTRANS assertion instead of VDDMIN.
Updated the jitter specs in the “FMPLL electrical characteristics“ table.
In the “ADC conversion characteristics“ table, changed all parameters with
units of “counts” to units of “LSB” and updated Min/Max values.
Changed IDD_LV_BIST + IDD_LV_PLL operating current (for both cases) to TBD.
In the “Supply current characteristics (cut2)” section, added a footnote that
IDD_HV_ADC and IDD_HV_AREF represent the total current of both ADCs in the
“Current consumption characteristics” table.
In the “ADC conversion characteristics” table:
– Changed DNL min from -2 to -1.
– Changed OFS min from -2 to -6.
– Changed OFS max from 2 to 6.
– Changed GNE min from -2 to -6.
– Changed GNE max from 2 to 6.
– Changed SNR min from 69 to 67.
– Changed TUE min (without current injection) from -6 to -8.
– Changed TUE max (without current injection) from 6 to 8.
– Changed TUE min (with current injection) from -8 to -10.
Changed TUE max (with current injection) from 8 to 10.
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Table 44.
Revision history
Document revision history (continued)
Date
14-Sep-2011
Revision
Changes
7
In the “Description” section, changed the first paragraph and its bullets to
paragraph form only.
In the “Voltage regulator electrical specifications“ table, changed the CV1V2 Min
value from “—“ to 300 nF, and changed the Max value from 300 nF to 900 nF.
In the “Supply current characteristics (cut2)“ table, corrected the “IDD_LV_TYP
+ IDD_LV_PLL“ values as follows:
– Changed the maximum value for “TJ = ambient“ from “279 mA+
2.10 mA*fCPU“ to “279 mA”.
– Changed the maximum value for “TJ = 150 °C“ from “318 mA+
2.30 mA*fCPU“ to 318 mA.
– Changed the frequency multiplier “fCPU” in the max value to read
“fCPU[MHz]“ for “IDD_LV_FULL + IDD_LV_PLL“ and “IDD_LV_TYP + IDD_LV_PLL“.
In the “JTAG pin AC electrical characteristics“ table:
– Changed tJCYC min from 100ns to 62.5ns.
– Changed tJDC units from “ns” to “%”.
In the “Nexus debug port timing“ table:
– Changed tTCYC min from 40ns to 62.5 ns.
– Changed tJOV parameter description from “TCK Low to TDO Data Valid“ to
“TCK Low to TDO/RDY Data Valid“.
Changed “DDR” to “Double Data Rate (DDR)“ in the “Nexus DDR Mode output
timing“ figure.
Changed “TDO” to “TDO/RDY” in the “Nexus TDI, TMS, TDO timing“ figure.
Removed “fmax” from the “DSPI timing” table.
Deleted “Order code” table.
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Revision history
Table 44.
Document revision history (continued)
Date
01-Aug-2012
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SPC56XL60/54
Revision
Changes
8
Editorial changes.
In the “Block diagram” section, removed one PMU from the figure.
In the 257-pin pinout figure, changed cut2 to cut2/3 in Notes.
In the pin function summary table, changed cut2 to cut2/3.
In the “System pins” table:
– Added Note regarding Open Drain Enable.
– Added description to RESET pin.
In the pin-muxing table:
– Added Note about Open Drain.
– Changed cut2 to cut2/3.
– Changed all entries of column 'Weak pull config during reset’ to ' - ' , except
for PCR[2], PCR[3], PCR[4] and PCR[21].
In the “Absolute maximum ratings” table:
– Removed the “VSS_HV_REG” row.
– Added the footnote “Internal structures hold the input voltage...” to the VIN
maximum specifications.
In the “Recommended operating conditions” table, removed the “VSS_HV_REG”
row.
In the “Thermal characteristics” section:
– Added the “Thermal characteristics for LQFP100 package“ table.
– Updated values and footnote 1 in the 144 package table.
– Updated footnote 1 in the 257 package table.
In the “Supply current characteristics“ table:
– Added footnote 1 to parameter “IDD_LV_TYP + IDD_LV_PLL“ (symbol “T”).
– Changed “IDD_LV_STOP” at 150C from 80mA to 72mA.
– Changed “IDD_LV_HALT” at 150C from 72mA to 80mA.
In the “FMPLL electrical characteristics” table:
– Deleted the footnote “This value is true when operating at frequencies above
60 MHz...” from the specification for fCS and fDS.
– Changed “fSYS” to “fFMPLLOUT” in the entries for the CJITTER, fLCK, fUL, fCS,
and fDS specifications.
In the “ADC conversion characteristics” table:
– Revised the entry for TUEIS1WINJ (was P/T and “Total unadjusted error for
IS1WINJ”, is T and “Total unadjusted error for IS1WINJ (single ADC
channels)”).
– Revised the entry for TUEIS1WWINJ (was “Total unadjusted error for
IS1WWINJ”, is “Total unadjusted error for IS1WWINJ (double ADC
channels)”).
In the “Temperature sensor electrical characteristics“ table, for TJ = TA to
125 °C, changed Min/Max from values -7/+7 to -10/+10.
In the “Input Impedance and ADC Accuracy“ section:
– Changed CS in the text from 3 pF to 7.5 pF.
– Changed Req in the text from 330 kΩ to 133 kΩ.
– Removed RL, RSW, and RAD from the external network design constraint
equation and the sentence immediately preceding it.
– Changed the CF constraint value equation constant from 2048 to 8192.
In the “ADC conversion characteristics“ table, changed INL Min/Max values
from -2/+2 to -3/+3.
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Table 44.
Revision history
Document revision history (continued)
Date
01-Aug-2012
Revision
Changes
8
(cont.)
– In Section 1.5.31, “eTimer module” changed text from “The MPC5643L
provides three eTimer modules on the 257 MAPBGA device, and two eTimer
modules on the 144 LQFP package” to “The MPC5643L provides three
eTimer modules (on the LQFP package eTimer_2 is available internally only
without any external I/O access)”.
– In Section 3.5, “Electromagnetic Interference (EMI) characteristics”,added
additional information at the end of this section.
– In Section 3.8, Voltage regulator electrical characteristics, added text related
to external ballast transistor.
– In Table 4 and Table 5 (LFBGA257 pin function summary), moved EVTI from
output function to input function.
– In Table 7 (System pins), changed the direction for EXTAL from “Output
Only” to “Input/Output”.
– InTable 7, added table footnote for symbol “EXTAL”.
– Changed the row (TVdd) in Table 9 (Absolute maximum ratings).
– In Table 9, Maximum value for “VDD_HV_IOX” and “VDD_HV_FLA” changed from
“3.6” to “4.0”.
– In Table 21 (Current consumption characteristics), added max value 250 and
290 mA for symbol IDD_LV_BIST+IDD_LV_PLL .
– Added five additional RunIDD parameters in Table 21 (Current consumption
characteristics).
– In Table 22 (Temperature sensor electrical characteristics), changed
condition for parameter “Accuracy” from “-40°C to 25°C” to “-40°C to 150°C”
– In Table 24 (FMPLL electrical characteristics),added ‘150’ to the max value
for ‘fSCM’ In Table 25 (RC oscillator electrical characteristics),changes done
are:
fRC symbol- Added min value ‘15.04’ and max value ‘16.96’.Removed condition
“TJ=25°C”
Removed row containing Δ RCMVAR symbol.
– In Figure 9, added the name ‘CS’ to the capacitor in the internal circuit
scheme.
– Removed references to Cut1 and Cut2:
Renamed Section ”Electromagnetic Interference (EMI) characteristics (cut1)” to
“Electromagnetic Interference (EMI) characteristics” .
In Table 26 (ADC conversion characteristics), removed reference to cut2 only
for symbol ‘IS1WINJ’ and ‘TUEIS1WWINJ’.
In Section 1.1, Document overview, modified text to remove references to
‘Cut1’.
– In Table 26 (ADC conversion characteristics), for tCONV added ‘60 MHz’ to
‘conditions’ and ‘600’ to the ‘Min’ value.
Separated SNR into two specifications with conditions Vref 3.3 V and 5.0 V
respectively.
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Revision history
Table 44.
Document revision history (continued)
Date
01-Aug-2012
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SPC56XL60/54
Revision
Changes
8
(cont.)
Changed min value to ‘-72’ for symbol ‘THD’.
– In Table 26 (ADC conversion characteristics), changed ADC specification
parameter ‘THD’ minimum limit from -72 to -65dB.
– In Table 27 (Flash memory program and erase electrical specifications),
changes done are as follows:
TDWPROGRAM, changed typical value from ‘39’ to ‘38’.
TPPROGRAM, changed typical value from ‘48’ to ‘45’ and intial max value from
‘100’ to ‘160’.
T16KPPERASE, inserted typical value ‘270’ and factory avg ‘1000’.
T48KPPERASE, inserted typical value ‘625’ and factory avg ‘1500’.
T64KPPERASE, inserted typical value ‘800’ and factory avg ‘1800’.
T128KPPERASE, inserted typical value ‘1500’ and factory avg ‘2600’.
T256KPPERASE, inserted typical value ‘3000’ and factory avg ‘5200’.
Updated table footnote and removed min column in Table 27 (Flash memory
program and erase electrical specifications)
– In Table 28 (Flash memory timing), added symbol TPSRT ,TESRT and added
table footnote for TPSRT ,TESRT .
– Added Table 30 (MPC5643L SWG Specifications)
– In Table 30 (MPC5643L SWG Specifications)
Added table footnote for Common Mode.
Changed text from “internal device pad resistance” to “internal device routing
resistance”.
– Added Figure 27 in Section 3.20.4, “Nexus timing”.
– In Table 31 (Pad AC specifications (3.3 V , IPP_HVE = 0 )), removed the row
of pad “Pull Up/Downc(3.6 V max)”.
– In Figure 43, updated part numbers (changed ‘PPC’ to ‘SPC’ and ‘F0’ to
‘F2’).
– Replaced Figure 41, Figure 42 with the new versions.
– InTable 19 (Voltage regulator electrical specifications),changed the symbol
of spec external decoupling capacitor from SR to Cext.
In Figure 5, changed the ESR range in note text to 1 mW to 100 mW from
30 mW to 150 mW.
– In Section 1.5.32, “Sine Wave Generator (SWG)” removed the following text:
Frequency range from 1kHz to 50kHz.
Sine wave amplitude from 0.47 V to 2.26 V.
– In Table 21 (Current consumption characteristics),changed symbol from ‘C’
to ‘T’ , added “operating current” to the parameter and updated the maximum
value for five additional RunIDD parameters.
– In Table 21 (Current consumption characteristics), changed “Conditions”
from ‘1.2 V supplies’ to ‘1.2 V supplies during LBIST (full LBIST
configuration)’ for all the parameters.
Removed Table “SWG electrical characteristics”.
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Table 44.
Revision history
Document revision history (continued)
Date
01-Aug-2012
Revision
Changes
8
(cont.)
– In Table 19 (Voltage regulator electrical specifications), changed the “Digital
supply high voltage detector upper threshold low limit (After a destructive
reset initialization phase completion)” from 1.43V to 1.38V.
– Added Table 18 (Recommended operating characteristics).
– Updated the IDD values in Table 21 (Current consumption characteristics).
Changed conditions text from “1.2 supplies during LBIST (full LBIST
configuration)” to “1.2 V supplies” for all the IDD parameters except
IDD_LV_BIST+IDD_LV_PLL. Added footnote in “Conditions” for the DPM mode.
– Removed Cut references from the whole document.
In Table 26 (ADC conversion characteristics), changed the sampling frequency
value from ‘1 MHz’ to ‘983.6 KHz’.
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