STA333W 2-channel high-efficiency digital audio system Sound Terminal™ Features Wide supply-voltage range (4.5 V - 20 V) 2 power output configurations – 2 channels of binary PWM (stereo mode) – 2 channels of ternary PWM (stereo mode) PowerSSO-36 with exposed pad down 2 channels of 24-bit DDX® 100-dB SNR and dynamic range Selectable 32- to 192-kHz input sample rates I2C control with selectable device address Digital gain -80 dB to +48 dB in 0.5-dB steps Software volume update Individual channel and master gain/attenuation Individual channel and master software and hardware mute Independent channel volume bypass Automatic zero-detect mute Automatic invalid input detect mute 2-channel I2S input data Interface Selectable clock input ratio Input channel mapping Automatic volume control for limiting maximum power 96-kHz internal processing sample rate, 24-bit precision Advanced AM interference frequency switching and noise suppression modes Thermal-overload and short-circuit protection embedded Video application: 576 * fS input mode support Table 1. PowerSSO-36 package with exposed pad down (EPD) Applications LCD DVD Cradle Digital speaker Wireless-speaker cradle Description The STA333W is an integrated circuit comprising digital audio processing, digital amplifier control and DDX® power output stage to create a highpower, single-chip DDX® solution for all-digital amplification with high quality and high efficiency. The STA333W power section consists of four independent half-bridges stages. These can be configured via digital control to operate in different modes. 2 channels can be provided by two full bridges, providing up to 20 W + 20 W of power. Also provided in the STA333W are new advanced AM radio interference reduction modes. The serial audio data input interface accepts all possible formats, including the popular I2S format. Three channels of DDX® processing are provided. The STA333W is part of the Sound Terminal™ family that provides full digital audio streaming to the speaker offering cost effectiveness, low power dissipation and sound enrichment. Device summary Order code Package Packaging STA333W PowerSSO-36 EPD Tube STA333W13TR PowerSSO-36 EPD Tape and reel January 2010 Doc ID 13365 Rev 2 1/49 www.st.com 49 Contents STA333W Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Electrical specifications - digital section . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 Electrical specifications - power section . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 Power-on/off sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 4.2 Functional pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 Power-down function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 Reset function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial audio interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 5 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 2/49 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 13365 Rev 2 STA333W 6 Contents 5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 6.2 Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Volume control registers (addr 0x06 to 0x09) . . . . . . . . . . . . . . . . . . . . . . 32 6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 32 6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.3 Channel volume (addr 0x08, 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.3 Automodes™ register (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 Channel configuration registers (addr 0x0E, 0x0F) . . . . . . . . . . . . . . . . . 35 6.5 Variable max power correction registers (addr 0x27, 0x28) . . . . . . . . . . . 35 6.6 Variable distortion compensation registers (addr 0x29, 0x2A) . . . . . . . . . 36 6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C) . . . . . . . . . . 36 6.8 Device status register (addr 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.9 Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) . . . . . . . . . . . . . . . . . 37 6.10 Postscale registers (addr 0x32, 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.11 Output limit register (addr 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.11.1 7 Thermal and overcurrent warning output limit register . . . . . . . . . . . . . 38 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.1 Applications scheme for power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.2 PLL filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.3 Typical output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Characterization data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 13365 Rev 2 3/49 Contents STA333W 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Trademarks and other acknowledgements . . . . . . . . . . . . . . . . . . . . . . 47 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4/49 Doc ID 13365 Rev 2 STA333W List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical characteristics for digital section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical specifications for power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 MCS bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interpolation ratio select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 IR bit settings as a function of input sample rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal warning recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Thermal warning adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Fault detect recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial audio input interface format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial data first bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Support serial audio input formats for MSB first (SAIFB = 0) . . . . . . . . . . . . . . . . . . . . . . . 25 Supported serial audio input formats for LSB-First (SAIFB = 1) . . . . . . . . . . . . . . . . . . . . . 26 Channel input mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DDX power output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DDX compensating pulse size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Overcurrent warning detect adjustment bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Zero detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Max power correction variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Max power correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Noise-shaper bandwidth selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AM mode enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PWM speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Distortion compensation variable enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Zero-crossing volume enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Invalid input detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Binary output mode clock loss detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 LRCK double trigger protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Auto EAPD on clock loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External amplifier power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Master mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Channel mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Master volume offset as a function of MV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Channel volume as a function of CxV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AM interference frequency switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Automodes™ AM switching frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Status bits description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Output limit values for thermal and overcurrent warnings. . . . . . . . . . . . . . . . . . . . . . . . . . 38 PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Doc ID 13365 Rev 2 5/49 List of figures STA333W List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. 6/49 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power-off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Current dead-time test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Left justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write-mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read-mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Applications diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PLL filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output configuration for stereo BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output power vs. supply voltage (THD = 1%) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FFT 0 dBfs (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FFT -60 dBfs (VCC = 12 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 THD vs. frequency (VCC = 12 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 FFT 0 dBfs (VCC = 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FFT -60 dBfs (VCC = 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 THD vs. frequency (VCC = 18 V, Po = 1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Double-layer PCB with two copper ground areas and 16 vias . . . . . . . . . . . . . . . . . . . . . . 44 Power derating curve for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Doc ID 13365 Rev 2 STA333W 1 Block diagram Block diagram Figure 1. Block diagram I2 C Protection current/thermal 2 I S interface Volume control Channel 1A Power control Logic Channel 1B DDX Channel 2A Regulators Channel 2B PLL Bias Digital DSP Power Doc ID 13365 Rev 2 7/49 Pin description STA333W 2 Pin description 2.1 Pin out Figure 2. Pin connection (package top view) GND_SUB 1 36 VDD_DIG SA 2 35 GND_DIG TEST_MODE 3 34 SCL VSS 4 33 SDA VCC_REG 5 32 INT_LINE OUT2B 6 31 RESET GND2 7 30 SDI VCC2 8 29 LRCKI OUT2A 9 28 BICKI OUT1B 10 27 XTI VCC1 11 26 GND_PLL GND1 12 25 FILTER_PLL VDD_PLL OUT1A 13 GND_REG 14 VDD_REG 15 24 EP exposed pad (down) 23 Connect to ground 22 CONFIG 16 21 VDD_DIG N.C. 17 20 N.C. N.C. 18 19 N.C. PWRDN GND_DIG D05AU1638 2.2 Pin list Table 2. Pin description Number 8/49 Type Name Description 1 PWR GND_SUB Substrate ground 2 I SA I2C select address 3 I TEST_MODE This pin must be connected to ground 4 I/O VSS Internal reference at VCC - 3.3 V 5 I/O VCC_REG Internal VCC reference 6 O OUT2B Output half bridge 2B 7 PWR GND2 Power negative supply 8 PWR VCC2 Power positive supply 9 O OUT2A Output half bridge 2A Doc ID 13365 Rev 2 STA333W Pin description Table 2. Pin description (continued) Number Type Name Description 10 O OUT1B Output half bridge 1B 11 PWR VCC1 Power positive supply 12 PWR GND1 Power negative supply 13 O OUT1A Output half bridge 1A 14 PWR GND_REG Internal ground reference 15 PWR VDD_REG Internal 3.3-V reference voltage 16 I CONFIG Paralleled mode command 17 - N.C. No internal connection 18 - N.C. No internal connection 19 - N.C. No internal connection 20 - N.C. No internal connection 21 PWR VDD_DIG Positive supply digital 22 PWR GND_DIG Digital ground 23 I PWRDN Power down: 0: power stage is switched off then the PLL is also switched off (this operation take 13 million clock cycles) 1: normal operation 24 PWR VDD_PLL Positive supply for PLL 25 I FILTER_PLL Connection to PLL filter 26 PWR GND_PLL Negative supply for PLL 27 I XTI PLL input clock, 256 * fS, or 384 * fS 28 I BICKI I2S serial clock 29 I LRCKI I2S left/right clock 30 I SDI I2S serial data channel 31 I RESET Reset: 0: reset state, power stage is switched off, all registers are set to default value 1: normal operation 32 O INT_LINE Fault interrupt 33 I/O SDA I2C serial data, used as SDA_OUT 34 I SCL I2C serial clock 35 PWR GND_DIG Digital ground 36 PWR VDD_DIG Digital supply - - EP Exposed pad for ground-plane heatsink, to be connected to GND Doc ID 13365 Rev 2 9/49 Pin description 2.3 STA333W Thermal data Table 3. Symbol Thermal data Parameter RTh(j-case) Thermal resistance junction to case (thermal pad) 10/49 Min Typ Max Unit - 1.5 2.0 °C/W Tsd Thermal-shutdown junction temperature 140 150 160 °C Tw Thermal-warning temperature - 130 - °C Thsd Thermal-shutdown hysteresis 18 20 22 °C Doc ID 13365 Rev 2 STA333W Electrical specification 3 Electrical specification 3.1 Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Typ Max Unit VCC Analog supply voltage (pins VCCx) - - 23 V VDD Digital supply voltage (pins VDD_DIG) - - 4.0 V IL Logic input interface -0.3 - 4.0 V Top Operating junction temperature 0 - 150 °C Tstg Storage temperature -40 - 150 °C Warning: 3.2 Min Stresses beyond those listed in Table 4: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Table 5: Recommended operating conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. In the real application, a power supply with nominal value rated within the limits of the recommended operating conditions, may experience some rising beyond the maximum operating conditions for a short time when no or very low current is being sinked (amplifier in mute state). In this case the reliability of the device is guaranteed, provided that the absolute maximum ratings are not exceeded. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC Analog supply voltage (VCCx) 4.5 - 20.0 V VDD Digital supply voltage (VDD_DIG) 2.7 3.3 3.6 V IL Logic input interface 2.7 3.3 3.6 V Tamb Ambient temperature 0 - 70 °C Doc ID 13365 Rev 2 11/49 Electrical specification 3.3 STA333W Electrical specifications - digital section Table 6. Electrical characteristics for digital section Symbol Iil Conditions Min Typ Max Unit Input current, no pull-up or pull-down resistor Vi = 0 V - - ±10 µA Vi = VDD = 3.6 V - - ±10 µA Vil Low-level input voltage - - - 0.2 * VDD V Vih High-level input voltage - 0.8 * VDD - - V Vol Low-level output voltage Iol = 2 mA - - 0.4 * VDD V Voh High-level output voltage Ioh = 2 mA 0.8 * VDD - - V Ipu Pull-up current - 25 66 125 µA Rpu Equivalent pull-up resistance - - 50 - kΩ Iih 3.4 Parameter Electrical specifications - power section The specifications in Table 7 below are given for the conditions VCC = 18 V, VDD = 3.3 V, fSW = 384 kHz, Tamb = 25 °C and RL = 8 Ω, unless otherwise specified. Table 7. Electrical specifications for power section Symbol Po 12/49 Parameter Conditions Min Typ Max THD = 1% - 16 - THD = 10% - 20 - Output power BTL Unit W RdsON Power P-channel/N-channel ld = 1 A MOSFET (total bridge) - 180 250 mΩ ldss Power P-channel/N-channel VCC = 18 V leakage - - 10 µA gP Power P-channel RdsON matching ld = 1 A 95 - - % gN Power N-channel RdsON matching ld = 1 A 95 - - % ILDT Low-current dead time (static) Resistive load, refer to Figure 5 - 5 10 ns IHDT High-current dead time (dynamic) Refer to Figure 6 - 10 20 ns tr Rise time Resistive load, refer to Figure 5 - 8 10 ns tf Fall time Resistive load, refer to Figure 5 - 8 10 ns Doc ID 13365 Rev 2 STA333W Electrical specification Table 7. Symbol VCC IVCC IVDD_DIG Electrical specifications for power section (continued) Parameter Conditions Min Typ Max Unit Supply voltage - 4.5 - 20 V Supply current from VCC in power down PWRDN = 0 30 60 200 µA Supply current from VCC in operation PCM input signal = -60 dBfs Switching frequency = 384 kHz No LC filters - 30 50 mA Supply current for DDX Internal clock = 49.152 MHz processing (reference only) 10 30 50 mA Supply current in standby 8 11 25 mA 2.2 3.5 4.3 A (1) ILIM Overcurrent limit Non-linear output ISCP Short-circuit protection High-impedance output (2) 2.7 3.8 5.0 A VUVP Undervoltage protection threshold - - 3.5 4.3 V tmin Output minimum pulse width No load 20 30 60 ns THD+N Total harmonic distortion and noise DXX stereo mode, Po = 1 W, f = 1 kHz - 0.05 0.2 % DR Dynamic range - - 100 - dB Signal to noise ratio in ternary mode A-weighted - 100 - Signal to noise ratio in binary mode A-weighted - 90 - - 80 - dB SNR dB PSRR DXX stereo mode, < 5 kHz, Power supply rejection ratio VRIPPLE = 1 V RMS audio input = dither only XTALK Crosstalk DXX stereo mode, < 5 kHz, One channel driven at 1 W the other channel measured - 80 - dB η Peak efficiency in DXX mode Po = 2 x 20 W into 8 Ω - 90 - % 1. The ILIM data is for 1 channel of BTL configuration, thus, 2 * ILIM drives the 2-channel BTL configuration. The current limit is active when OCRB = 0 (see Table 23: Overcurrent warning detect adjustment bypass on page 28. When OCRB = 1 then ISC applies. 2. The ISCP current limit data is for 1 channel of BTL configuration, thus, 2 * ISCP drives the 2-channel BTL configuration. The short-circuit current is applicable when OCRB = 1 (see Table 23: Overcurrent warning detect adjustment bypass on page 28. Doc ID 13365 Rev 2 13/49 Electrical specification 3.5 STA333W Power-on/off sequences The power-on/off sequences shown in Figure 3 and Figure 4 below ensure a pop-free turn on and turn off. Figure 3. Power-on sequence No specific VCC and VDD_DIG turn-on sequence is required VCC VCC Don’t care VDD_Dig VDD_DIG XTI XTI Don’t care Reset RESET TR PWRDN PWRDN Bit EAPD Soft EAPD Register Reg. 0x050x05 TC Bit 7 = 1 TR = mimimum time between XTI master clock stable and reset removal: 1 ms TC = minimum time between reset removal and I2C program sequence start: 1 ms Clock stable means: fmax - fmin < 1 MHz Figure 4. Power-off sequence No specific VCC and VDD_DIG turn-off sequence is required VCC VCC Don’t care VDD_DIG VDD_Dig XTI XTI MuteMute Soft Register Reg. 0x07 0x07 Data 0xFE Don’t care Don’t care FE Bit EAPD Soft EAPD Register 0x05 Reg. 0x05 Bit 7 = 0 14/49 Doc ID 13365 Rev 2 Don’t care STA333W 3.6 Electrical specification Testing Figure 5. Test circuit OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTxY INxY R 8Ω M57 + - V67 = vdc = Vcc/2 gnd Figure 6. D03AU1458 Current dead-time test circuit High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q2 Q1 OUTA INA L67 22µ Q3 C69 470nF M64 DTin(B) OUTB INB L68 22µ Iout=4A Lout = 1.5 A M57 DTout(B) Rload=8Ω Iout=4A Lout = 1.5 A C71 470nF C70 470nF Q4 Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure Doc ID 13365 Rev 2 M63 D03AU1517 15/49 Functional description STA333W 4 Functional description 4.1 Functional pins 4.1.1 Power-down function Pin PWRDN (23) is used to power down the STA333W. PWRDN = 0 (0 V): power-down state. PWRND = 1 (VDD): normal operation. During the power-down sequence the output begins to mute. After the mute condition is reached the power stage is switched off and the output becomes high impedance. Then the master clock to all internal hardware blocks is gated off. The PLL is also switched off. The complete power-down sequence takes 13 million cycles. 4.1.2 Reset function Pin RESET (31) is used to reset the STA333W. RESET = 0 (0 V): reset state. RESET = 1 (VDD): normal operation. When pin RESET is forced to 0 the power stage is switched off (with high-impedance output) and the master clock to all internal hardware blocks is gated off. Note: 16/49 Reset has a higher priority than power down. Doc ID 13365 Rev 2 STA333W Functional description 4.2 Serial audio interface description 4.2.1 Serial audio interface protocols The STA333W serial audio input was designed to interface with standard digital audio components and to accept serial data formats. The STA333W always acts as a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using 3 input pins: left/right clock LRCKI (pin 29), serial clock BICKI (pin 28), and serial data SDI (pin 30). The available formats are showed in Table 7 and Table 8, and set through register CONFB on page 24. Figure 7. I2 S LRCLKI BICKI SDI Figure 8. 11 2 33 n-1 n 1 2 3 n-1 n Left justified LRCLKI BICKI SDI 1 2 3 n-1 n 1 2 Doc ID 13365 Rev 2 3 n-1 n 17/49 I2C bus specification 5 STA333W I2C bus specification The STA333W supports the I2C protocol via the input ports SCL and SDA. This protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the other as the slave. The master always starts the transfer and provides the serial clock for synchronization. The STA333W is always a slave device in all of its communications. It supports up to 400 kb/s (fast-mode bit rate). 5.1 Communication protocol 5.1.1 Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high is used to identify a START or STOP condition. 5.1.2 Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. 5.1.3 Stop condition STOP is identified by low to high transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A STOP condition terminates communication between STA333W and the bus master. 5.1.4 Data input During the data input the STA333W samples the SDA signal on the rising edge of clock SCL. For correct device operation the SDA signal must be stable during the rising edge of the clock and the data can change only when the SCL line is low. 5.2 Device addressing To start communication between the master and the STA333W, the master must initiate a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device-select address and read or write mode. The 7 most significant bits are the device address identifiers, corresponding to the I2C bus definition. In the STA333W the I2C interface has two device addresses depending on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1. The 8th bit (LSB) identifies read or write operation RW, this bit is set to 1 for read mode and 0 for write mode. After a START condition the STA333W identifies the device address on the SDA bus and if a match is found, acknowledges the identification during the 9th bit time. The byte following the device identification byte is the internal space address. 18/49 Doc ID 13365 Rev 2 I2C bus specification STA333W 5.3 Write operation Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and then waits for the byte of internal address. After receiving the internal byte address the STA333W again responds with an acknowledgement. 5.3.1 Byte write In the byte write mode the master sends one data byte, this is acknowledged by the STA333W. The master then terminates the transfer by generating a STOP condition. 5.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 9. Write-mode sequence ACK ACK DEV-ADDR BYTE WRITE SUB-ADDR RW START STOP ACK MULTIBYTE WRITE ACK DATA IN ACK DEV-ADDR START SUB-ADDR ACK DATA IN ACK DATA IN STOP RW 5.4 Read operation 5.4.1 Current address byte read Following the START condition the master sends a device select code with the RW bit set to 1. The STA333W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. 5.4.2 Current address multi-byte read The multi-byte read modes can start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then generates a STOP condition terminating the transfer. 5.4.3 Random address byte read Following the START condition the master sends a device select code with the RW bit set to 0. The STA333W acknowledges this and then the master writes the internal address byte. After receiving, the internal byte address the STA333W again responds with an acknowledgement. The master then initiates another START condition and sends the device select code with the RW bit set to 1. The STA333W acknowledges this and then responds by sending one byte of data. The master then terminates the transfer by generating a STOP condition. Doc ID 13365 Rev 2 19/49 I2C bus specification 5.4.4 STA333W Random address multi-byte read The multi-byte read modes could start from any internal address. Sequential data bytes are read from sequential addresses within the STA333W. The master acknowledges each data byte read and then generates a STOP condition to terminate the transfer. Figure 10. Read-mode sequence ACK CURRENT ADDRESS READ DEV-ADDR NO ACK DATA RW START STOP ACK RANDOM ADDRESS READ DEV-ADDR SUB-ADDR RW RW= ACK HIGH START SEQUENTIAL CURRENT READ ACK DEV-ADDR ACK DEV-ADDR START RW ACK DATA NO ACK DATA STOP ACK DATA NO ACK DATA STOP START ACK SEQUENTIAL RANDOM READ DEV-ADDR START 20/49 ACK SUB-ADDR RW ACK DEV-ADDR START ACK DATA RW Doc ID 13365 Rev 2 ACK DATA NO ACK DATA STOP STA333W 6 Register description Register description Table 8. Addr Register summary Name D7 D6 D5 D4 D3 D2 D1 D0 0x00 CONFA FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0x01 CONFB C2IM C1IM Reserved SAIFB SAI3 SAI2 SAI1 SAI0 0x02 CONFC OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 0x03 CONFD Reserved ZDE 0x04 CONFE SVE ZCE DCCV PWMS AME NSBW MPC MPCV 0x05 CONFF EAPD PWDN ECLE LDTE BCLE IDE 0x06 MUTE 0x07 MVOL MV7 MV6 MV5 MV4 0x08 C1VOL C1V7 C1V6 C1V5 0x09 C2VOL C2V7 C2V6 C2V5 0x0C AUTO 0x0E C1CFG Reserved C1VBP Reserved 0x0F C2CFG Reserved C2VBP Reserved 0x27 MPCC1 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0x28 MPCC2 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 0x29 DCC1 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 0x2A DCC2 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0x2B FDRC1 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 0x2C FDRC2 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 0x2D STATUS PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN 0x2E BIST1 Reserved RO1BACT R5BACT R4BACT R3BACT R2BACT R1BACT 0x2F BIST2 Reserved R01BEND R5BEND R4BEND R3BEND R2BEND R1BEND 0x30 BIST3 R5BBAD R4BBAD R3BBAD R1BBAD R1BBAD 0x31 TSTCTL 0x32 C1PS C1PS7 C1PS6 C1PS5 C1PS4 C1PS3 C1PS2 C1PS1 C1PS0 0x33 C2PS C2PS7 C2PS6 C2PS5 C2PS4 C2PS3 C2PS2 C2PS1 C2PS0 0x34 OLIM OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0 Reserved Reserved C2M C1M MMUTE MV3 MV2 MV1 MV0 C1V4 C1V3 C1V2 C1V1 C1V0 C2V4 C2V3 C2V2 C2V1 C2V0 AMAM2 AMAM1 AMAM0 AMAME Reserved Reserved Reserved Reserved Doc ID 13365 Rev 2 21/49 Register description STA333W 6.1 Configuration registers (addr 0x00 to 0x05) 6.1.1 Configuration register A (addr 0x00) D7 D6 D5 D4 D3 D2 D1 D0 FDRB TWAB TWRB IR1 IR0 MCS2 MCS1 MCS0 0 1 1 0 0 0 1 1 Master clock select Table 9. Master clock select Bit R/W RST Name 0 R/W 1 MCS0 1 R/W 1 MCS1 2 R/W 0 MCS2 Description Master clock select: Selects the ratio between the input I2S sample frequency and the input clock. The STA333W supports sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz, 176.4 kHz, and 192 kHz. Therefore the internal clock is: z 32.768 MHz for 32 kHz z 45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz z 49.152 MHz for 48 kHz, 96 kHz, and 192 kHz The external clock frequency provided to the XTI pin must be a multiple of the input sample frequency (fS). The relationship between the input clock and the input sample rate is determined by both the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor generating the internal clock and the IR bit determines the oversampling ratio used internally. Table 10. MCS bits Input sample rate fS (kHz) 22/49 MCS[2:0] IR 101 100 011 010 001 000 32, 44.1, 48 00 576 * fS 128 * fS 256 * fS 384 * fS 512 * fS 768 * fS 88.2, 96 01 NA 64 * fS 128 * fS 192 * fS 256 * fS 384 * fS 176.4, 192 1X NA 32 * fS 64 * fS 96 * fS Doc ID 13365 Rev 2 128 * fS 192 * fS STA333W Register description Interpolation ratio select Table 11. Bit 4:3 Interpolation ratio select R/W R/W RST 00 Name IR [1:0] Description Interpolation ratio select: Selects internal interpolation ratio based on input I2S sample frequency. The STA333W has variable interpolation (oversampling) settings such that internal processing and DDX output rates remain consistent. The first processing block interpolates by either 2 times or 1 time (pass-through) or provides a 2-times downsample. The oversampling ratio of this interpolation is determined by the IR bits. Table 12. IR bit settings as a function of input sample rate Input sample rate fS (kHz) IR 1st stage interpolation ratio 32 00 2-times oversampling 44.1 00 2-times oversampling 48 00 2-times oversampling 88.2 01 Pass-through 96 01 Pass-through 176.2 10 2-times downsampling 192 10 2-times downsampling Thermal warning recovery bypass Table 13. Bit 5 Thermal warning recovery R/W R/W RST 1 Name TWRB Description Thermal warning recovery bypass: 0: thermal warning recovery enabled 1: thermal warning recovery disabled If the thermal warning adjustment is enabled (TWAB = 0), then the thermal warning recovery determines if the -3 dB output limit is removed when thermal warning is negative. If TWRB = 0 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit is removed and the gain is added back to the system. If TWRB = 1 and TWAB = 0, then when a thermal warning disappears the -3 dB output limit remains until TWRB is changed to zero or the device is reset. Doc ID 13365 Rev 2 23/49 Register description STA333W Thermal warning adjustment bypass Table 14. Bit 6 Thermal warning adjustment R/W RST R/W 1 Name Description Thermal warning adjustment bypass: 0: thermal warning adjustment enabled 1: thermal warning adjustment disabled TWAB The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The TWARN input is used to indicate a thermal warning condition. When TWARN is asserted (set to 0) for a period of time greater than 400 ms, the power control block will force a -3dB output limit (determined by TWOCL in coefficient RAM) to the modulation limit in an attempt to eliminate the thermal warning condition. Once the thermal warning output limit adjustment is applied, it remains in this state until reset, unless FDRB = 0. Fault detect recovery bypass Table 15. Bit 7 Fault detect recovery R/W RST R/W 0 Name Description Fault detect recovery bypass: 0: fault detect recovery enabled 1: fault detect recovery disabled FDRB The on-chip STA333W power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either overcurrent or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the 3-state output (setting it to 0 which directs the power output block to begin recovery), holding it at 0 for period of time in the range of 0.1 ms to 1 second as defined by the fault detect recovery constant register (FDRC registers 0x2B, 0x2C), then toggling it back to 1. This sequence is repeated as log as the fault indication exists. This feature is enabled by default but can be bypassed by setting the FDRB control bit to 1. 6.1.2 24/49 Configuration register B (addr 0x01) D7 D6 D5 D4 D3 D2 D1 D0 C2IM C1IM Reserved SAIFB SAI3 SAI2 SAI1 SAI0 1 0 0 0 0 0 0 0 Doc ID 13365 Rev 2 STA333W Register description Serial audio input interface format Table 16. Bit Serial audio input interface format R/W RST Name 0 R/W 0 SAI0 1 R/W 0 SAI1 2 R/W 0 SAI2 3 R/W 0 SAI3 Description Determines the interface format of the input serial digital audio interface. Serial data interface The STA333W audio serial input interfaces with standard digital audio components and accepts a number of serial data formats. STA333W always acts a slave when receiving audio input from standard digital audio components. Serial data for two channels is provided using three inputs: left/right clock LRCKI, serial clock BICKI, and serial data SDI. Bits SAI and bit SAIFB are used to specify the serial data format. The default serial data format is I2S, MSB first. Available formats are shown in the tables and figure that follow. Serial data first bit Table 17. Serial data first bit SAIFB Format 0 MSB-first 1 LSB-first Table 18. Support serial audio input formats for MSB first (SAIFB = 0) BICKI 32 * fS 48* fS SAI [3:0] SAIFB Interface format 0000 0 I2S 15-bit data 0001 0 Left/right justified 16-bit data 0000 0 I2S 16- to 23-bit data 0001 0 Left justified 16- to 24-bit data 0010 0 Right justified 24-bit data 0110 0 Right justified 20-bit data 1010 0 Right justified 18-bit data 1110 0 Right justified 16-bit data Doc ID 13365 Rev 2 25/49 Register description Table 18. STA333W Support serial audio input formats for MSB first (SAIFB = 0) (continued) 64* fS Table 19. 48* fS 48* fS 64* fS 26/49 0 I2S 16- to 24-bit data 0001 0 Left justified 16- to 24-bit data 0010 0 Right justified 24-bit data 0110 0 Right justified 20-bit data 1010 0 Right justified 18-bit data 1110 0 Right justified 16-bit data Supported serial audio input formats for LSB-First (SAIFB = 1) BICKI 32* fS 0000 SAI[3:0] SAIFB Interface format 1100 1 I2S 15-bit data 1110 1 Left/right justified 16-bit data 0100 1 I2S 23-bit data 0100 1 I2S 20-bit data 1000 1 I2S 18-bit data 1100 1 LSB first I2S 16-bit data 0001 1 Left justified 24-bit data 0101 1 Left justified 20-bit data 1001 1 Left justified 18-bit data 1101 1 Left justified 16-bit data 0010 1 Right justified 24-bit data 0110 1 Right justified 20-bit data 1010 1 Right justified 18-bit data 1110 1 Right justified 16-bit data 0000 1 I2S 24-bit data 0100 1 I2S 20-bit data 1000 1 I2S 18-bit data 1100 1 LSB First I2S 16-bit data 0001 1 Left justified 24-bit data 0101 1 Left justified 20-bit data 1001 1 Left justified 18-bit data 1101 1 Left justified 16-bit data 0010 1 Right justified 24-bit data 0110 1 Right justified 20-bit data 1010 1 Right justified 18-bit data 1110 1 Right justified 16-bit data Doc ID 13365 Rev 2 STA333W Register description Channel input mapping Table 20. Bit Channel input mapping R/W RST Name Description 6 R/W 0 C1IM 0: processing channel 1 receives left I2S input 1: processing channel 1 receives right I2S input 7 R/W 0 C2IM 0: processing channel 2 receives left I2S input 1: processing channel 2 receives right I2S input Each channel received via I2S can be mapped to any internal processing channel via the channel input mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 6.1.3 Configuration register C (addr 0x02) D7 D6 D5 D4 D3 D2 D1 D0 OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 0 0 1 0 1 1 1 DDX power output mode Table 21. Bit DDX power output mode R/W RST Name 0 R/W 1 OM0 1 R/W 1 OM1 Description The DDX power output mode selects the configuration of the DDX output: 00: drop compensation 01: discrete output stage: tapered compensation 10: full-power mode 11: variable drop compensation (CSZx bits) DDX compensation pulse size register Table 22. Bit DDX compensating pulse size R/W RST Name 2 R/W 1 CSZ0 3 R/W 0 CSZ1 4 R/W 1 CSZ2 5 R/W 0 CSZ3 Description When OM[1:0] = 11, this register determines the size of the DDX compensating pulse from 0 to 15 clock periods: 0000: 0 ns (0 ticks) compensating pulse size 0001: 20 ns (1 tick) clock period compensating pulse size ..... 1111: 300 ns (15 ticks) clock period compensating pulse size Doc ID 13365 Rev 2 27/49 Register description STA333W Overcurrent warning detect adjustment bypass Table 23. Bit 7 Overcurrent warning detect adjustment bypass R/W RST R/W 1 Name Description 0: overcurrent warning adjustment enabled 1: overcurrent warning adjustment disabled OCRB The status bit OCWARN is used to warn of an overcurrent condition. When OCWARN is asserted (set to 0), the power control block forces an adjustment to the modulation limit (default -3dB) in an attempt to eliminate the overcurrent warning condition. Once the overcurrent warning volume adjustment is applied, it remains applied until the device is reset. The overcurrent limit can be changed via register OLIM (Output limit register (addr 0x34) on page 38). 6.1.4 Configuration register D (addr 0x03) D7 D6 Reserved ZDE D5 0 1 D4 D3 D2 D1 D0 0 0 0 Reserved 0 0 0 Zero-detect mute enable Table 24. Bit 6 Zero detect mute enable R/W RST R/W 1 Name Description ZDE 1: enable the automatic zero-detect mute Setting the ZDE bit enables the zero-detect automatic mute. The zero-detect circuit looks at the data for each processing channel at the output of the crossover (bass management) filter. If any channel receives 2048 consecutive zero value samples (regardless of fS) then that individual channel is muted if this function is enabled. 6.1.5 Configuration register E (addr 0x04) D7 D6 D5 D4 D3 D2 D1 D0 SVE ZCE DCCV PWMS AME NSBW MPC MPCV 1 1 0 0 0 0 1 0 Max power correction variable Table 25. Bit 0 28/49 Max power correction variable R/W R/W RST 0 Name MPCV Description 0: use standard MPC coefficient 1: use MPCC bits for MPC coefficient Doc ID 13365 Rev 2 STA333W Register description Max power correction Table 26. Bit 1 Max power correction R/W R/W RST 1 Name MPC Description 1: enable power bridge correction for THD reduction near maximum power output. Setting the MPC bit turns on special processing that corrects the STA333W power device at high power. This mode lowers the THD+N of a full DDX system at maximum power output and slightly below. If enabled, MPC is operational in all output modes except tapered (OM[1:0] = 01) and binary. When OCFG = 00, MPC does not affect channels 3 and 4, the line-out channels. Noise-shaper bandwidth selection Table 27. Bit 2 Noise-shaper bandwidth selection R/W R/W RST 0 Name NSBW Description 1: 3rd order NS 0: 4th order NS AM mode enable Table 28. Bit 3 AM mode enable R/W R/W RST 0 Name AME Description 0: normal DDX operation 1: AM reduction mode DDX operation The STA333W features a DDX processing mode that minimizes the amount of noise generated in frequency range of AM radio. This mode is intended for use when DDX is operating in a device with an AM tuner active. The SNR of the DDX processing is reduced to approximately 83 dB in this mode, which is still greater than the SNR of AM radio. PWM speed mode Table 29. Bit 4 PWM speed mode R/W R/W RST 0 Name PWMS Description 0: normal speed (384 kHz) all channels 1: odd speed (341.3 kHz) all channels Distortion compensation variable enable Table 30. Bit 5 Distortion compensation variable enable R/W R/W RST 0 Name DCCV Description 0: uses preset DC coefficient. 1: uses DCC coefficient. Doc ID 13365 Rev 2 29/49 Register description STA333W Zero-crossing volume enable Table 31. Bit 6 Zero-crossing volume enable R/W RST R/W 1 Name Description 1: volume adjustments will only occur at digital zero-crossings 0: volume adjustments will occur immediately ZCE The ZCE bit enables zero-crossing volume adjustments. When volume is adjusted on digital zero-crossings no clicks will be audible. Soft volume update enable Table 32. Bit 7 6.1.6 Zero-crossing volume enable R/W RST R/W 1 Name Description 1: volume adjustments ramp according to SVR settings 0: volume adjustments will occur immediately SVE Configuration register F (addr 0x05) D7 D6 D5 D4 D3 D2 EAPD PWDN ECLE LDTE BCLE IDE 0 1 0 1 1 1 D1 D0 Reserved 0 0 Invalid Input detect mute enable Table 33. Bit 2 Invalid input detect mute enable R/W R/W RST 1 Name IDE Description 1: enables the automatic invalid input detect mute Setting the IDE bit enables this function, which looks at the input I2S data and will automatically mute if the signals are perceived as invalid. Binary output mode clock loss detection Table 34. Bit 3 Binary output mode clock loss detection R/W R/W RST 1 Name BCLE Description Binary output mode clock loss detection enable Detects loss of input MCLK in binary mode and outputs 50% of the duty cycle. 30/49 Doc ID 13365 Rev 2 STA333W Register description LRCK double trigger protection Table 35. Bit 4 LRCK double trigger protection R/W R/W RST 1 Name Description LDTE LRCLK double trigger protection enable Actively prevents double trigger of LRCLK. Auto EAPD on clock loss Table 36. Bit 5 Auto EAPD on clock loss R/W R/W RST 0 Name ECLE Description Auto EAPD on clock loss When active will issue a power device power-down signal (EAPD) on clock loss detection. IC power down Table 37. Bit 6 Power down R/W R/W RST 1 Name PWDN Description 0: power down, low-power condition 1: normal operation The PWDN register is used to put the IC in a low-power state. When PWDN is 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted to power down the power stage, then the master clock to all internal hardware except the I2C block is gated. This puts the IC in a very low power consumption state. External amplifier power down Table 38. Bit 7 External amplifier power down R/W R/W RST 1 Name EAPD Description 0: external power stage power down active 1: normal operation The EAPD register directly disables/enables the internal power circuitry. When EAPD = 0, the internal power section is placed in a low-power state (disabled). Doc ID 13365 Rev 2 31/49 Register description STA333W 6.2 Volume control registers (addr 0x06 to 0x09) 6.2.1 Mute/line output configuration register (addr 0x06) D7 D6 D5 D4 D3 Reserved 0 0 0 0 0 D2 D1 D0 C2M C1M MMUTE 0 0 0 Master mute Table 39. Bit 0 Master mute R/W R/W RST 0 Name MMUTE Description 0: normal operation 1: all channels are in mute condition Channel mute Table 40. Bit 32/49 Channel mute R/W RST Name Description 1 R/W 0 C1M Channel 1 mute: 0: not muted, it is possible to set the channel volume 1: hardware muted 2 R/W 0 C2M Channel 2 mute: 0: not muted, it is possible to set the channel volume 1: hardware muted Doc ID 13365 Rev 2 STA333W 6.2.2 6.2.3 Register description Master volume register (addr 0x07) D7 D6 D5 D4 D3 D2 D1 D0 MV7 MV6 MV5 MV4 MV3 MV2 MV1 MV0 1 1 1 1 1 1 1 1 Channel volume (addr 0x08, 0x09) D7 D6 D5 D4 D3 D2 D1 D0 C1V7 C1V6 C1V5 C1V4 C1V3 C1V2 C1V1 C1V0 0 1 1 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 C2V7 C2V6 C2V5 C2V4 C2V3 C2V2 C2V1 C2V0 0 1 1 0 0 0 0 0 Volume setting The volume structure of the STA333W consists of individual volume registers for each channel and a master volume register that provides an offset to each channels volume setting. The individual channel volumes are adjustable in 0.5-dB steps from +48 dB to -80 dB. As an example if C3V = 0x00 or +48 dB and MV = 0x18 or -12 dB, then the total gain for channel 3 = +36 dB. The master mute when set to 1 will mute all channels at once, whereas the individual channel mutes (CxM) mute only that channel. Both the master mute and the channel mutes provide a “soft mute” with the volume ramping down to mute in 4096 samples from the maximum volume setting at the internal processing rate (about 96 kHz). A hard mute can be obtained by commanding a value of all 1’s (255) to any channel volume register or the master volume register. When volume offsets are provided via the master volume register any channel that whose total volume is less than -80 dB is muted. All changes in volume take place at zero-crossings when ZCE = 1 (configuration register F) on a per channel basis as this creates the smoothest possible volume transitions. When ZCE = 0, volume updates will occur immediately. Table 41. Master volume offset as a function of MV MV[7:0] Volume offset from channel value 00000000 (0x00) 0 dB 00000001 (0x01) -0.5 dB 00000010 (0x02) -1 dB … … 01001100 (0x4C) -38 dB … … 11111110 (0xFE) -127.5 dB 11111111 (0xFF) Hard master mute Doc ID 13365 Rev 2 33/49 Register description STA333W Table 42. Channel volume as a function of CxV CxV[7:0] 6.3 Volume 00000000 (0x00) +48 dB 00000001 (0x01) +47.5 dB 00000010 (0x02) +47 dB … … 01011111 (0x5F) +0.5 dB 01100000 (0x60) 0 dB 01100001 (0x61) -0.5 dB … … 11010111 (0xD7) -59.5 dB 11011000 (0xD8) -60 dB 11011001 (0xD9) -61 dB 11011010 (0xDA) -62 dB … … 11101100 (0xEC) -80 dB 11101101 (0xED) Hard channel mute … … 11111111 (0xFF) Hard channel mute Automodes™ register (0x0C) D7 D6 D5 D4 Reserved 0 0 0 D3 D2 D1 D0 AMAM2 AMAM1 AMAM0 AMAME 0 0 0 0 0 AM interference frequency switching Table 43. Bit 0 AM interference frequency switching R/W R/W RST 0 Name AMAME Description 0: switching frequency determined by PWMS setting 1: switching frequency determined by AMAM setting AMAM bits Table 44. Automodes™ AM switching frequency selection AMAM[2:0] 34/49 48 kHz / 96 kHz input fS 44.1 kHz / 88.2 kHz input fS 000 0.535 MHz - 0.720 MHz 0.535 MHz - 0.670 MHz 001 0.721 MHz - 0.900 MHz 0.671 MHz - 0.800 MHz Doc ID 13365 Rev 2 STA333W Register description Table 44. 6.4 Automodes™ AM switching frequency selection 010 0.901 MHz - 1.100 MHz 0.801 MHz - 1.000 MHz 011 1.101 MHz - 1.300 MHz 1.001 MHz - 1.180 MHz 100 1.301 MHz - 1.480 MHz 1.181 MHz - 1.340 MHz 101 1.481 MHz - 1.600 MHz 1.341 MHz - 1.500 MHz 110 1.601 MHz - 1.700 MHz 1.501 MHz - 1.700 MHz Channel configuration registers (addr 0x0E, 0x0F) D7 D6 0 0 D7 D6 D5 D4 D3 0 0 0 D5 D4 D3 Reserved 0 0 D1 C1VBP Reserved 0 D2 Reserved 0 0 D2 D1 C2VBP 0 0 0 D0 0 D0 Reserved 0 0 Volume bypass Each channel contains an individual channel volume bypass. If a particular channel has volume bypassed via the CxVBP = 1 register then only the channel volume setting for that particular channel affects the volume setting, the master volume setting will not affect that channel. 6.5 Variable max power correction registers (addr 0x27, 0x28) MPCC bits determine the 16 MSBs of the MPC compensation coefficient. This coefficient is used in place of the default coefficient when MPCV = 1. D7 D6 D5 D4 D3 D2 D1 D0 MPCC15 MPCC14 MPCC13 MPCC12 MPCC11 MPCC10 MPCC9 MPCC8 0 0 0 1 1 0 1 0 D7 D6 D5 D4 D3 D2 D1 D0 MPCC7 MPCC6 MPCC5 MPCC4 MPCC3 MPCC2 MPCC1 MPCC0 1 1 0 0 0 0 0 0 Doc ID 13365 Rev 2 35/49 Register description 6.6 STA333W Variable distortion compensation registers (addr 0x29, 0x2A) D7 D6 D5 D4 D3 D2 D1 D0 DCC15 DCC14 DCC13 DCC12 DCC11 DCC10 DCC9 DCC8 1 1 1 1 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 DCC7 DCC6 DCC5 DCC4 DCC3 DCC2 DCC1 DCC0 0 0 1 1 0 0 1 1 DCC bits determine the 16 MSBs of the distortion compensation coefficient. This coefficient is used in place of the default coefficient when DCCV = 1. 6.7 Fault detect recovery constant registers (addr 0x2B, 0x2C) D7 D6 D5 D4 D3 D2 D1 D0 FDRC15 FDRC14 FDRC13 FDRC12 FDRC11 FDRC10 FDRC9 FDRC8 0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 FDRC7 FDRC6 FDRC5 FDRC4 FDRC3 FDRC2 FDRC1 FDRC0 0 0 0 0 1 1 0 0 FDRC bits specify the 16-bit fault detect recovery time delay. When status register bit FAULT is asserted, the tristate output is immediately asserted low and held low for the time period specified by this constant. A value of 0x0001 in this register is approximately 0.083 ms. The default value of 0x000C gives approximately 0.1 ms. Note: 0x0000 is a reserved value for this register pair. This value must not be used. 6.8 Device status register (addr 0x2D) D7 D6 D5 D4 D3 D2 D1 D0 PLLUL FAULT UVFAULT Reserved OCFAULT OCWARN TFAULT TWARN This read-only register provides the fault, warning and PLL status from the power control block. Table 45. Bit 36/49 Status bits description R/W RST Name Description 0 RO - TWARN Thermal warning: 0: junction temperature is close to the fault condition 1: normal operation 1 RO - TFAULT Thermal fault: 0: junction temperature limit detection 1: normal operation Doc ID 13365 Rev 2 STA333W Register description Table 45. Bit 6.9 Status bits description (continued) R/W RST Name Description 2 RO - OCWARN Overcurrent warning: 0: warning 1: normal operation 3 RO - OCFAULT Overcurrent fault: 0: fault detected 1: normal operation 4 - - - Reserved 5 RO - UVFAULT Undervoltage warning: 0: VCCx below lower voltage threshold 1: normal operation 6 RO - FAULT Power bridge fault: 0: fault detected 1: normal operation 7 RO - PLLUL PLL lock: 0: locked 1: not locked Reserved registers (addr 0x2E, 0x2F, 0x30, 0x31) These registers are not to be used. 6.10 Postscale registers (addr 0x32, 0x33) D7 D6 D5 D4 D3 D2 D1 D0 C1PS7 C1PS6 C1PS5 C1PS4 C1PS3 C1PS2 C1PS1 C1PS0 0 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 C2PS7 C2PS6 C2PS5 C2PS4 C2PS3 C2PS2 C2PS1 C2PS0 0 1 1 1 1 1 1 1 Postscale The STA333W provides one additional multiplication after the last interpolation stage and the distortion compensation on each channel, which can be used to limit the maximum modulation index and therefore the peak current through the power device. The register values represent an 8-bit signed fractional number. This number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on that channel. An independent postscale is provided for each channel but all channels can use channel 1 postscale factor by setting the postscale link bit. By default, all postscale factors are set to 0x7F (pass-through). Doc ID 13365 Rev 2 37/49 Register description STA333W 6.11 Output limit register (addr 0x34) 6.11.1 Thermal and overcurrent warning output limit register D7 D6 D5 D4 D3 D2 D1 D0 OLIM7 OLIM6 OLIM5 OLIM4 OLIM3 OLIM2 OLIM1 OLIM0 0 1 0 1 1 0 1 0 The STA333W provides a simple mechanism for reacting to a thermal or overcurrent warning in the power device. When the TWARN or OCWARN status bit is asserted, the output is limited to the OLIM setting. The limit can be adjusted by modifying the thermal warning/overcurrent output limit value. As for the normal postscale, the register value represents an 8-bit signed fractional number. This number is extended to a 24-bit number, by adding zeros to the right, and then directly multiplied by the data on both channels. The scaling value range is from 0x80 = -1 to 0x7F = 0.992. To avoid phase changes in the output signal only the positive range is used (0x00 to 0x7F). The default setting of 0x5A provides a -3-dB limit. If the cause of the limiting is a thermal warning, the output limiting is removed when the thermal warning situation disappears. If the cause of the limiting is an overcurrent warning, output limiting remains in effect until the device is reset. Table 46. Output limit values for thermal and overcurrent warnings OLIM[7:0] 38/49 Attenuation (dB) 0x7F 0.06 0x7E 0.13 .... .... 0x5A 3.0 .... .... 0x40 6.0 .... .... 0x28 10 .... .... 0x01 42 0x00 Inf Doc ID 13365 Rev 2 STA333W Applications information 7 Applications information 7.1 Applications scheme for power supplies Figure 11 below shows a typical applications scheme for STA333W. Special care has to be taken with regard to the power supplies when laying out the PCB. In particular the 3.3-Ω resistors on the digital supplies (VDD_DIG) have to be placed as close as possible to the device. This prevents unwanted oscillation on the digital parts of the device due to the inductive effects of the PCB tracks. The same rule also applies to all the decoulpling capacitors; they should be placed as close as possible to the device in order to limit the effect of spikes on the supplies. Figure 11. Applications diagram 3R3 1 + 1000uF 35V 100nF 1uF 35V OUT2B SA 3 TEST_MODE SCL 34 4 VSS SDA 33 5 VCC_REG OUT2B 7 GND2 RESET 31 SDI 30 VCC2 LRCKI 29 BICKI 28 OUT2A 9 OUT2A VCC OUT1B 10 100nF OUT1B 11 VCC1 12 GND1 13 OUT1A 1uF 35V OUT1A 14 100nF GND_REG 100nF SCL PWRDN 16 CONFIG 17 NC VDD_DIG 21 NC 20 18 NC NC 19 RESET 1nF LRCKI BICKI GND_DIG XTI BEAD PLL_FILT 100nF PLL_GND BEAD 23 VDD 10K RESET GND_DIG 3V3 PWDN GND_DIG 22 15 GND_DIG DATA XTI 27 PLL_GND 26 FILTER_PLL 25 VDD_PLL 24 3V3 SDA INTL INT_LINE 32 6 100nF 3V3 VDD_DIG 36 GND_DIG 35 2 8 7.2 GND_SUB 3R3 100nF GND_DIG 3V3 PLL filter It is recommended to use the circuit in Figure 12 below for the PLL loop filter to achieve the best performance from the device in general applications. Note that the ground of this filter has to be connected to the ground of the PLL without any resistive path. For the component values, it should be remembered that the greater the filter bandwidth, the shorter the lock time but the higher the PLL output jitter. Doc ID 13365 Rev 2 39/49 Applications information STA333W Figure 12. PLL filter circuit F IL T E R _ P L L 2K2 680pF 100pF 4 .7 n F BEAD G N D _ D IG 7.3 PLL_G ND Typical output configuration Figure 13 below shows a typical output configuration used for BTL stereo mode. Figure 13. Output configuration for stereo BTL mode 22uH OUT1A 100nF 6.2 22 6.2 330pF 100nF 470nF LEFT 470nF RIGHT 100nF 100nF OUT1B 22uH 22uH OUT2A 100nF 6.2 22 6.2 330pF 100nF OUT2B 22uH 40/49 Doc ID 13365 Rev 2 100nF 100nF STA333W Characterization data The following characterizations were made with RL = 8 Ω and f = 1 kHz unless otherwise stated. Figure 14. Output power vs. supply voltage (THD = 1%) 30 RKP 25 Output power, W 8 Characterization data 20 6 Ω RKP 4Ω 15 8 Ω RKP 10 16 Ω RKP 5 0 5 7 9 11 13 15 17 19 Supply voltage, V Figure 15. FFT 0 dBfs (VCC = 12 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Doc ID 13365 Rev 2 41/49 Characterization data STA333W Figure 16. FFT -60 dBfs (VCC = 12 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 17. THD vs. frequency (VCC = 12 V, Po = 1 W) 1 0.5 6ohm 6 0.2 % 4ohm 4Ω Ω 0.1 0.05 8Ω 8ohm 0.02 0.01 20 50 100 200 500 1k Hz 42/49 Doc ID 13365 Rev 2 2k 5k 10k 20k STA333W Characterization data Figure 18. FFT 0 dBfs (VCC = 18 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 1k 2k 5k 10k 20k 10k 20k Hz Figure 19. FFT -60 dBfs (VCC = 18 V) +10 +0 -10 -20 -30 -40 -50 d B r -60 A -80 -70 -90 -100 -110 -120 -130 -140 -150 20 50 100 200 500 Hz Figure 20. THD vs. frequency (VCC = 18 V, Po = 1 W) 1 0.5 6ohm 6Ω 4ohm 4 Ω 0.2 0.1 % 0.05 8ohm 8 0.02 Ω 0.01 20 50 100 200 500 1k 2k 5k Hz Doc ID 13365 Rev 2 43/49 Package thermal characteristics 9 STA333W Package thermal characteristics A thermal resistance of 25 °C/W can be achieved by mounting the device on a PCB which has two copper ground areas of 3 x 3 cm and 16 vias (see Figure 21). Given that the amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level the maximum estimated dissipated power for the STA333W is 3 W. With the above suggested board as heatsink, a maximum junction temperature rise, ∆Tj, of 75 °C is possible. In consumer environments where 50 °C is the maximum ambient temperature this provides some safety margin before the intervention of the thermal protection (Tj = 150 °C). Figure 21. Double-layer PCB with two copper ground areas and 16 vias Figure 22 shows the power derating curve for the PowerSSO-36 package on PCBs with copper areas of 2 x 2 cm2 and 3 x 3 cm2. Figure 22. Power derating curve for PCB used as heatsink Pd (W) 8 7 Copper Area 3x3 cm and via holes 6 5 STA333W STA333W 4 PSSO36 PowerSSO-36 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 Tamb ( °C) 44/49 Doc ID 13365 Rev 2 100 120 140 160 STA333W Package mechanical data The STA333W comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 23 below shows the package outline and Table 47 gives the dimensions. Figure 23. PowerSSO-36 EPD outline drawing h x 45° 10 Package mechanical data Doc ID 13365 Rev 2 45/49 Package mechanical data Table 47. STA333W PowerSSO-36 EPD dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.47 0.085 - 0.097 A2 2.15 - 2.40 0.085 - 0.094 a1 0.00 - 0.10 0.000 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees 0 - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 46/49 Doc ID 13365 Rev 2 STA333W 11 Trademarks and other acknowledgements Trademarks and other acknowledgements DDX is a registered trademark of Apogee Technology Inc. Automodes is a trademark of Apogee Technology Inc. ECOPACK is a registered trademark of STMicroelectronics. Sound Terminal is a trademark of STMicroelectronics. Doc ID 13365 Rev 2 47/49 Revision history 12 STA333W Revision history Table 48. Document revision history Date Revision 25-May-2007 1 Initial release. 2 Updated features for operating voltage range, digital gain increments and maximum power control on page 1 Updated description on page 1 Updated electrical specifications Table 4, Table 3 and Table 5 on page 11 Added Section 3.3: Electrical specifications - digital section on page 12 Added chapter Functional description on page 16 Updated usage of pin name SDA in first paragraph of Chapter 5: I2C bus specification on page 18 Added Section 5.4: Read operation on page 19 Removed PSL (register add 0x03) in Table 8: Register summary on page 21 Updated text concerning overcurrent warning for register CONFC on page 27 Removed bit PSL in Configuration register D (addr 0x03) on page 28 Corrected reset value for register bit MPCV in Table 25 on page 28 Updated bit names and added register description table in Device status register (addr 0x2D) on page 36 Updated text and added OLIM attenuation table in Output limit register (addr 0x34) on page 38 Deleted mention of appsnote in Section 7.3 on page 40 Updated package Y (Min) dimension in Table 47 on page 46 Removed references to STA50x/51x throughout the document 21-Jan-2010 48/49 Changes Doc ID 13365 Rev 2 STA333W Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 13365 Rev 2 49/49