SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 D D D D D D D Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process B-Port Outputs Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages NOTE: For tape and reel order entry: The DGGR package is abbreviated to GR. description This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH162268 is used for applications in which data must be transferred from a narrow high-speed bus to a wide, lower-frequency bus. The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line is synchronous with CLK and selects 1B or 2B input data for the A outputs. DGG OR DL PACKAGE (TOP VIEW) OEA CLKEN1B 2B3 GND 2B2 2B1 VCC A1 A2 A3 GND A4 A5 A6 A7 A8 A9 GND A10 A11 A12 VCC 1B1 1B2 GND 1B3 CLKEN2B SEL 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OEB CLKENA2 2B4 GND 2B5 2B6 VCC 2B7 2B8 2B9 GND 2B10 2B11 2B12 1B12 1B11 1B10 GND 1B9 1B8 1B7 VCC 1B6 1B5 GND 1B4 CLKENA1 CLK For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of these inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA, OEB). These control terminals are registered, so bus direction changes are synchronous with CLK. The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and undershoot. To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 description (continued) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH162268 is characterized for operation from –40°C to 85°C. Function Tables OUTPUT ENABLE INPUTS OUTPUTS CLK OEA OEB A ↑ H H Z 1B, 2B Z ↑ H L Z Active ↑ L H Active Z ↑ L L Active Active A-TO-B STORAGE (OEB = L) INPUTS OUTPUTS CLKENA1 CLKENA2 CLK A 1B 1B0‡ 2B 2B0‡ H H X X L L ↑ L L† H† L L ↑ H X X L ↑ L X L X L ↑ H X H X † Two CLK edges are needed to propagate data. ‡ Output level before the indicated steady-state input conditions were established B-TO-A STORAGE (OEA = L) INPUTS OUTPUT A CLKEN1B CLKEN2B CLK SEL 1B 2B H X X H X X X H X L X X L L ↑ H L X L L L ↑ H H X H X L ↑ L X L L X L ↑ L X H H A0‡ A0‡ ‡ Output level before the indicated steady-state input conditions were established 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 logic diagram (positive logic) 29 CLK 2 CLKEN1B 27 CLKEN2B CLKENA1 30 55 C1 CLKENA2 56 1D OEB C1 SEL 28 1D 1 OEA CE 1D C1 1D C1 G1 A1 1B1 CE C1 1 8 23 1 1D 1D 6 2B1 CE CE C1 C1 1D 1D CE C1 1D 1 of 12 Channels POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MIN MAX 1.65 3.6 2 0.35 × VCC Low-level input voltage VI VO Input voltage 0 Output voltage 0 0.7 VCC = 2.7 V to 3.6 V IOH High level output current (B port) High-level Low level output current (A port) Low-level IOL Low level output current (B port) Low-level ∆t/∆v V 1.7 VIL High level output current (A port) High-level V V –4 –12 –12 VCC = 1.65 V VCC = 2.3 V –2 –24 mA –6 VCC = 2.7 V VCC = 3 V –12 VCC = 1.65 V VCC = 2.3 V 12 –8 4 VCC = 2.7 V VCC = 3 V 12 VCC = 1.65 V VCC = 2.3 V 2 Input transition rise or fall rate V 0.8 VCC VCC VCC = 2.7 V VCC = 3 V VCC = 2.7 V VCC = 3 V V 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 1.65 V VCC = 2.3 V UNIT 24 mA 6 8 12 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA 1.65 V IOH = –6 mA A port IOH = –12 mA IOH = –24 mA IOH = –100 µA VOH A port 2.4 2 1.7 3V 2.4 IOH = –8 mA IOH = –12 mA 2.7 V 2 3V 2 IOL = 100 µA IOL = 4 mA 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.4 2.3 V 0.7 IOH = –6 6 mA IOL = 6 mA 2.7 V 0.4 3V 0.55 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.4 2.3 V 0.55 3V 0.55 IOL = 8 mA IOL = 12 mA 2.7 V 0.6 3V 0.8 VI = VCC or GND VI = 0.58 V 3.6 V ±5 IOL = 6 mA 1 65 V 1.65 23V 2.3 3V VI = 2 V VI = 0 to 3.6 V‡ IOZ§ ICC VO = VCC or GND VI = VCC or GND, ∆ICC Ci One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND VI = VCC or GND VO = VCC or GND UNIT V 1.9 VI = 1.7 V VI = 0.8 V Control inputs 2.2 3V 2.3 V VI = 1.07 V VI = 0.7 V II(hold) ( ) 2.7 V 2.3 V IOL = 2 mA IOL = 4 mA II 1.7 1.65 V IOL = 24 mA IOL = 100 µA B port MAX VCC–0.2 1.2 IOL = 12 mA VOL 2 2.3 V 3V TYP† VCC–0.2 1.2 2.3 V 1.65 V to 3.6 V IOH = –2 mA IOH = –4 mA B port MIN V µA 25 –25 45 µA –45 75 –75 3.6 V ±500 3.6 V ±10 µA 3.6 V 40 µA 3 V to 3.6 V 750 µA 3.3 V 3.5 pF Cio A or B ports 3.3 V 9 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. § For I/O ports, the parameter IOZ includes the input leakage current. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) VCC = 1.8 V MIN fclock tw tsu th Clock frequency Hold time MIN MAX VCC = 2.7 V MIN 120 MAX VCC = 3.3 V ± 0.3 V MIN 150 3.3 3.3 3.3 A data before CLK↑ † 4.5 4 3.4 B data before CLK↑ † 0.8 1.2 1 SEL before CLK↑ † 1.4 1.6 1.3 CLKENA1 or CLKENA2 before CLK↑ † 3.6 3.4 2.8 CLKENB1 or CLKENB2 before CLK↑ † 3.2 3 2.5 OE before CLK↑ † 4.2 3.9 3.2 A data after CLK↑ † 0 0 0.2 B data after CLK↑ † 1.3 1.2 1.3 SEL after CLK↑ † 1 1 1 CLKENA1 or CLKENA2 after CLK↑ † 0.1 0.1 0.4 CLKENB1 or CLKENB2 after CLK↑ † 0.1 0 0.5 OE after CLK↑ after CLK↑ † 0 0 0.2 UNIT MAX 125 † Pulse duration, CLK high or low Setup time MAX † VCC = 2.5 V ± 0.2 V MHz ns ns ns † This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) PARAMETER VCC = 1.8 V TO (OUTPUT) MIN † fmax tpd d CLK TYP VCC = 2.5 V ± 0.2 V MIN MAX 120 VCC = 2.7 V MIN MAX 125 VCC = 3.3 V ± 0.3 V MIN UNIT MAX 150 MHz B † 1.6 6.1 5.9 1.8 5.4 A (1B) † 1.6 5.8 5.4 1.7 4.8 A (2B) † 1.6 5.8 5.3 1.8 4.8 A (SEL) † 2.5 7.3 6.5 2.4 5.8 ns ten CLK B † 2.7 7.2 6.8 2.6 6.1 ns tdis CLK B † 2.8 7.2 6.1 2.5 5.9 ns 2 6.2 5.6 1.8 5.1 ns 2 6.5 5.4 2.1 5 ns ten CLK A † tdis CLK A † † This information was not available at the time of publication. operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS Outputs enabled Outputs disabled CL = 50 pF, pF VCC = 1.8 V TYP † f = 10 MHz † VCC = 2.5 V TYP VCC = 3.3 V TYP 87 120 80.5 118 UNIT pF † This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 × VCC S1 1 kΩ From Output Under Test Open GND CL = 30 pF (see Note A) 1 kΩ TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALVCH162268 12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS SCES018G – AUGUST 1995 – REVISED JUNE 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V 0V tPLZ tPZL 2.7 V 1.5 V 0V tPLH Output VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 0V 0V tsu Input 1.5 V Input Output Waveform 1 S1 at 6 V (see Note B) VOL + 0.3 V VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 2 S1 at GND (see Note B) VOL tPHZ tPZH tPHL 1.5 V 3V 1.5 V 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated