STW82100B RF down converter with embedded integer-N synthesizer Datasheet −production data Features ■ High linearity: – IIP3: +25.5 dBm – 2FRF-2FLO spurious rejection: 77 dBc ■ Noise figure: – NF: 10.5 dB Applications ■ Conversion gain – CG: 8 dB ■ RF range: 1620 MHz to 2400 MHz ■ Wide IF amplifier frequency range: 70 MHz to 400 MHz ■ Integrated RF balun with internal matching ■ Dual differential integrated VCOs with automatic center frequency calibration: – LOA: 1650 to 1950 MHz – LOB: 2050 to 2370 MHz ■ Embedded integer-N synthesizer – Dual modulus programmable prescaler (16/17 or 19/20) – Programmable reference frequency divider (10 bits) – Adjustable charge pump current – Digital lock detector – Excellent integrated phase noise – Fast lock time: 150 µs ■ Integrated DAC with dual current output ■ Supply: 3.3 V and 5 V analog, 3.3 V Digital ■ Dual digital bus interface: SPI and I2C bus (fast mode) with 3 bit programmable address (1101A2A1A0) ■ Process: 0.35 µm BICMOS SiGe ■ Operating temperature range -40 to +85oC ■ 44-lead exposed pad VFQFPN package7x7x1.0 mm May 2012 This is information on a product in full production. VFQFPN-44 ■ Cellular infrastructure equipment: – IF sampling receivers – Digital PA linearization loops ■ Other wireless communication systems. Table 1. Device summary Part number Package Packaging STW82100B VFQFPN-44 Tray STW82100BTR VFQFPN-44 Tape and reel Description The STMicroelectronics STW82100B is an integrated down converter providing 8 dB of gain, 10.5 dB NF, and a very high input linearity by means of its passive mixer. Embedding two wide band auto calibrating VCOs and an integer-N synthesizer, the STW82100B is suitable for both Rx and Tx requirements for Cellular infrastructure equipment. The integrated RF balun and internal matching permit direct 50 ohm single-ended interface to RF port. The IF output is suitable for driving 200-ohm impedance filters. By embedding a DAC with dual current output to drive an external PIN diode attenuator, the STW82100B replaces several costly discrete components and offers a significant footprint reduction. The STW82100B device is designed with STMicroelectronics advanced 0.35 µm SiGe process. Its performance is specified over a -40 °C to +85 °C temperature range. Doc ID 018355 Rev 5 1/67 www.st.com 1 Contents STW82100B Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 2/67 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.2 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.3 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.4 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.5 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1.6 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.7 Mute until lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1.9 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1.10 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.11 External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1.12 Mixer and IF amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.1.13 Dual output current DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 018355 Rev 5 STW82100B 9 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1 9.2 9.3 9.4 10 Contents I2C general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1.2 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.3 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1.4 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.5 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.6 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1.7 Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I2C timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.1 Data and clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2.2 I2C START and STOP timing specification . . . . . . . . . . . . . . . . . . . . . . 36 9.2.3 I2C acknowledge timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.1 I2C register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3.2 I2C register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Device calibration through the I2C interface . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.1 VCO calibration procedure (I2C interface) . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.2 Power ON sequence (I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4.3 VCO calibration auto-restart procedure (I2C interface) . . . . . . . . . . . . . 46 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 SPI general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.2 SPI timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.2.1 10.3 10.4 Data, clock and load timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3.1 SPI register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.3.2 SPI register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Device calibration through the SPI interface . . . . . . . . . . . . . . . . . . . . . . 53 10.4.1 VCO calibration procedure (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.2 Power ON sequence (SPI interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.4.3 VCO calibration auto-restart procedure (SPI interface) . . . . . . . . . . . . . 54 Doc ID 018355 Rev 5 3/67 Contents 11 STW82100B Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.2 Standard Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.3 Diversity mode operation with same LO frequency . . . . . . . . . . . . . . . . . 58 11.4 Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . 59 11.5 External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.6 External VCO diversity mode operation with same LO . . . . . . . . . . . . . . 61 12 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4/67 Doc ID 018355 Rev 5 STW82100B List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Down converter mixer and IF amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . 15 Pin diode attenuator driver (dual output current DAC) electrical characteristics. . . . . . . . . 16 Integer-N synthesizer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase noise performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Current values for CPSEL[2:0] selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VCOA performance against amplitude setting (frequency = 3.6 GHz) . . . . . . . . . . . . . . . . 30 VCOB performance against amplitude setting (frequency = 4.3 GHz) . . . . . . . . . . . . . . . . 30 Suggested CAP[2:0] values for LO Frequency range mixer . . . . . . . . . . . . . . . . . . . . . . . . 31 Linearity performance against IFAMP[1:0] configuration (typical condition) . . . . . . . . . . . . 32 I2C data and clock timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 I2C START and STOP timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C acknowledge timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 SPI timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI register list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Application circuit component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Evaluation kit order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 VFQFPN-44 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Doc ID 018355 Rev 5 5/67 List of figures STW82100B List of figures Figure 1. STW82100B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. STW82100B pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 3. Conversion gain against RF frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. Noise figure against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 5. IIP3 against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 6. 2RF-2LO response against RF frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 1.8 GHz (FSTEP = 200 kHz, ICP = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 8. LOB (VCOB div. by 2) closed-loop phase noise at 2.2 GHz (FSTEP = 200 kHz, ICP = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 12. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. VCO typical sub-band characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14. Data validity waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 15. START and STOP condition waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 16. Byte format and acknowledge waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 17. I2C data and clock waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 18. I2C START and STOP timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 19. I2C acknowledge timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 20. I2C first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 21. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 22. SPI data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 23. SPI timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 24. SPI first programming timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 25. Typical STW82100B application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 26. Standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 27. Diversity mode operation with same LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 28. Diversity mode operation with different LO frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 29. External VCO standard mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 30. External VCO diversity mode operation with same LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 31. VFQFPN-44 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6/67 Doc ID 018355 Rev 5 VSS_IFAMP VDD_IFAMP TEST1 VDD_DAC I_PINDRV2 VSS_ALC VDD_RFESD TEST2 STW82100B block diagram REXT_DAC Figure 1. I_PINDRV1 Block diagram VDD_ALC 1 TEST_ALC Block diagram VSS_DAC STW82100B DAC VSS_RFESD RF_IN IF_OUTP IF AMP RF_VSS IF_OUTN RF_CT MIXDRV_CT DBUS_SEL VDD_MIXDRV MIX DRV VSS_MIXDRV SDA/DATA SCL/CLK DBUS VDD_DIV LOAD VSS_DIV ADD0 ADD1 ADD2 VCO calibrator VDD_OUTBUF VSS_OUTBUF LO OUT DIV2 CAL_VCO VDD_DIG OUTBUFN VSS_DIG OUTBUFP LOCK_DET LO/2xLO OUT VCO divider EXTVCO_INP EXTVCO_INN EXT LO/VCO BUF UP PFD DN CHP ICP REF divider VDD_VCO VCO BUFF VSS_VCO VDD_PLL VDD_IO BUF VSS_IO VSS_PLL Doc ID 018355 Rev 5 REXT_CP VSS_CP VDD_CP EXT_PD REF_CLK VCTRL VSS_PSCBUF VDD_PSCBUF CAL_VCO 7/67 Pin description STW82100B 8/67 44 43 42 41 40 39 38 37 36 35 34 VDD_ALC MIXDRV_CT VDD_RFESD RF_IN RF_CT TEST_ALC TEST1 TEST2 STW82100B pin configuration VDD_MIXDRV Figure 2. I_PINDRV1 Pin description I_PINDRV2 2 VDD_IFAMP 33 REXT_DAC IF_OUTP 32 3 VDD_DIV IF_OUTN 31 4 VDD_VCO NC 30 5 EXTVCO_INN LOAD 29 SCL/CLK 28 1 VDD_DAC 2 STW82100B VFQFPN44 ADD1 DBUS_SEL 25 10 ADD0 VDD_PLL 24 11 VDD_IO REF_CLK 23 LOCK_DET 9 VDD_CP 26 REXT_CP VDD_DIG ICP ADD2 VCTRL 8 OUTBUFP 27 OUTBUFN SDA/DATA VDD_OUTBUF EXT_PD NC 7 NC EXTVCO_INP VDD_PSCBUF 6 12 13 14 15 16 17 18 19 20 21 22 Doc ID 018355 Rev 5 STW82100B Table 2. Pin description Pin list Pin No Name Description Observation 1 VDD_DAC DAC power supply Vsupply analog1= 3.3 V 2 REXT_DAC External resistance connection for DAC - 3 VDD_DIV Divider by 2 power supply Vsupply analog1= 3.3 V 4 VDD_VCO VCOs and External VCO Buffer power supply Vsupply analog1= 3.3 V 5 EXTVCO_INN External VCO (LO) negative input Diversity Slave Mode and External VCO Modes; otherwise it must be connected to GND 6 EXTVCO_INP External VCO (LO) positive input Diversity Slave Mode and External VCO Modes; otherwise it must be connected to GND 7 EXT_PD Hardware power down: ‘0’ device ON; ‘1’ device OFF CMOS Input 8 ADD2 I2CBUS address select pin CMOS Input 9 ADD1 I2CBUS address select pin CMOS Input 2CBUS address select pin CMOS Input 10 ADD0 I 11 VDD_IO Digital IO power supply Vsupply digital = 3.3 V 12 VDD_PSCBUF Prescaler input buffer power supply Vsupply analog1= 3.3 V 13 NC Not connected - 14 NC Not connected - 15 VDD_OUTBUF Power supply for LO buffer Vsupply analog1=3.3 V 16 OUTBUFN LO Output buffer negative output Open collector @3.3 V 17 OUTBUFP LO Output buffer positive output Open collector @ 3.3 V 18 VCTRL Control voltage for VCOs - 19 ICP PLL charge pump output - 20 REXT_CP External resistance connection for PLL charge pump current - 21 VDD_CP Power supply for charge pump Vsupply analog1= 3.3 V 22 LOCK_DET Lock detector CMOS Output 23 REF_CLK Reference frequency input - 24 VDD_PLL PLL digital power supply Vsupply analog1= 3.3 V 25 DBUS_SEL Digital Bus Interface select CMOS Input 26 VDD_DIG Power supply for digital bus interface Vsupply digital = 3.3 V SDA/DATA I 2CBUS /SPI data line CMOS Bidir Schmitt triggered 28 SCL/CLK I2CBUS /SPI clock line CMOS Input Schmitt triggered 29 LOAD SPI load line CMOS Input Schmitt triggered 30 NC Not connected - 31 IF_OUTN IF amplifier negative output Open collector @ 5 V(1) 27 Doc ID 018355 Rev 5 9/67 Pin description Table 2. Pin No STW82100B Pin list (continued) Name Description Observation 32 IF_OUTP IF Amplifier positive output Open collector @ 5 V(1) 33 VDD_IFAMP IF Amplifier power supply Vsupply analog1 = 3.3 V 34 TEST2 Test input 2 Test purpose only; it must be connected to GND 35 TEST1 Test input 1 Test purpose only; it must be connected to GND 36 TEST_ALC Test output Test purpose only; it must be connected to GND 37 RF_CT RF balun central tap - 38 RF_IN RF input - 39 VDD_RFESD RF ESD positive rail power supply Vsupply analog1 = 3.3 V 40 MIXDRV_CT Mixer driver balun central tap Vsupply analog2 = 5 V(1) 41 VDD_ALC ALC power supply Vsupply analog1 = 3.3 V 42 VDD_MIXDRV Mixer driver power supply Vsupply analog1 = 3.3 V 43 I_PINDRV1 DAC current output for external PIN Diode attenuator PMOS Open drain 44 I_PINDRV2 DAC current output for external PIN Diode attenuator PMOS Open drain 1. Supply voltage @ 3.3 V in low-current mode operation 10/67 Doc ID 018355 Rev 5 STW82100B Absolute maximum ratings 3 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Values Unit AVCC1 Analog Supply voltage 0 to 4.6 V AVCC2 Analog Supply voltage 0 to 6 V DVCC Digital Supply voltage 0 to 4.6 V Tstg Storage temperature +150 °C HBM on pins 16, 17, 31, 32, 37, 40 ESD (Electro-static discharge) 0.8 HBM on pin 38 1 HBM on all remaining pins 2 kV CDM-JEDEC Standard on pin 38 0.25 CDM-JEDEC Standard on all remaining pins 0.5 MM 0.2 Doc ID 018355 Rev 5 11/67 Operating conditions STW82100B 4 Operating conditions Table 4. Operating conditions Symbol Parameter Test conditions Min Typ Max Unit AVCC1 Analog Supply voltage - 3.15 3.3 3.45 V AVCC2 Analog Supply voltage - 4.75 5 5.25 V DVCC Digital Supply voltage - 3.15 3.3 3.45 V Standard mode - 130 150 mA External VCO standard mode - 110 130 mA Diversity slave mode - 105 120 mA Diversity master mode - 155 180 mA External VCO diversity master mode - 140 160 mA High current mode at 5 V - 170 195 mA Low current mode at 3.3 V - 100 115 mA ICC3.3V Current Consumption at 3.3 V ICC5V Current Consumption TA Operating ambient temperature - -40 85 °C TJ Maximum junction temperature - - 125 °C ΘJA Junction to ambient package thermal resistance(1) Multi-layer JEDEC board - 33 - °C/W ΘJB Junction to board package thermal resistance(1) Multi-layer JEDEC board - 19 - °C/W ΘJC Junction to case package thermal resistance(1) Multi-layer JEDEC board - 3 - °C/W ΨJB Thermal characterization parameter junction to board(1) Multi-layer JEDEC board - 18 - °C/W ΨJT Thermal characterization parameter junction to top case(1) Multi-layer JEDEC board - 0.3 - °C/W 1. Refer to JEDEC standard JESD 51-12 for a detailed description of the thermal resistances and thermal parameters. Data here presented are referring to a Multi-layer board according to JEDEC standard. TJ = TA + ΘJA * Pdiss (in order to estimate TJ if ambient temperature TA and dissipated power Pdiss are known) TJ = TB + ΨJB * Pdiss (in order to estimate TJ if board temperature TB and dissipated power Pdiss are known) TJ = TT + ΨJT * Pdiss (in order to estimate TJ if top case temperature TT and dissipated power Pdiss are known) 12/67 Doc ID 018355 Rev 5 STW82100B Table 5. Symbol Operating conditions T Digital logic levels Parameter Test conditions Min Typ Max Unit Vil Low level input voltage - - - 0.2*Vdd V Vih High level input voltage - 0.8*Vdd - - V Vhyst Schmitt trigger hysteresis - 0.8 - - V Vol Low level output voltage - - - 0.4 V Voh High level output voltage - 0.85*Vdd - - V Doc ID 018355 Rev 5 13/67 Test conditions 5 STW82100B Test conditions Unless otherwise specified the following test conditions are applied: ● Vsupply digital = 3.3 V ● Vsupply analog1 = 3.3 V ● Vsupply analog2 = 5 V ● FIF = 150 MHz ● MIX = 0111 ● T ambient = 27 ° C Refer also to Section 11: Application information. 14/67 Doc ID 018355 Rev 5 STW82100B Electrical characteristics 6 Electrical characteristics Note: Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, FRF = 2100 MHz, FLO = 1950 MHz, TA = +25 *C, RF power = 0 dBm, unless otherwise specified. Table 6. Down converter mixer and IF amplifier electrical characteristics(1) Symbol ) Parameter Conditions Min Typ Max Unit - 1620 - 2400 MHz VCOA divided by 2 1650 - 1950 MHz VCOB divided by 2 2050 - 2370 MHz FRF RF Frequency FLO LO Frequency FIF IF Center Frequency(2) FIF = ABS(FLO-FRF) 70 - 400 MHz CG Power Conversion Gain Rin = 50 ohm, Rout = 200 ohm RFin = 0 dBm 7.5 8 8.5 dB CGΔT Power Conversion Gain over Temperature(3) T= -40 to +85 °C - ±0.7 - dB High current Mode - 13.5 - IP1dB Input P1dB Low current Mode - 8 - Third-order input intercept point(4) High current Mode 24.5 25.5 - IIP3 Low current Mode 18.5 19.5 - T= -40 to +85 °C - ±0.5 - dB 2FRF-2FLO FRFin = -5 dBm, FIF = 150 MHz - 77 - dBc 3FRF-3FLO FRFin = -5 dBm, FIF = 150 MHz - 77 - dBc High-current mode, MIX = 0011 - 10.5 11 dB Low-current mode, MIX = 0011 - 10.5 11 dB 1xLO - -35 - dBm IIP3ΔT IIP3 variation over temperature(3) nFRF-nFLO Spurious rejection at IF(3) NFSSB Noise figure - LO to IF Leakage dBm dBm 2xLO -33 - LO to RF Leakage - - -29 - dBm - RF to IF Isolation - - 58 - dB RFRL RF Return Loss Matched to 50 ohm - 20 - dB IFRL IF Return Loss Matched to 200 ohm - 25 - dB Maximum deviation from Fc over ±10 MHz. For any Fc within each TX observation path band. -0.05 - +0.05 dB Maximum deviation from Fc over ±30 MHz. For any Fc within each TX observation path band. -0.10 - +0.10 dB - Gain Flatness for TX observation path(5) Doc ID 018355 Rev 5 15/67 Electrical characteristics Table 6. Symbol STW82100B Down converter mixer and IF amplifier electrical characteristics(1) (continued) Parameter Phase Flatness for TX observation path(5) - Conditions Min Typ Max Unit Maximum deviation from linear phase at Fc over ±10 MHz. For any Fc within each TX observation path band. -0.3 - +0.3 deg Maximum deviation from linear phase at Fc over ±30 MHz. For any Fc within each TX observation path band. -0.7 - +0.7 deg - Gain Flatness for RX path(5) Maximum ripple over a 4 MHz band. For any Fc within each RX path band. - - 0.1 dB pk-pk - Phase Flatness for RX path(5) Maximum ripple over a 4 MHz band. For any Fc within each RX path band. - - 0.6 deg pk-pk Mixer Driver Current Consumption 3.3 V Supply (pin 41, 42) - 49 - mA 5 V Supply (pin 40) - 60 - mA Mixer Driver Current Consumption (Low Current Mode) 3.3 V Supply (pin 41, 42) - 20 - mA 3.3 V Supply (pin 40) - 35 - mA 3.3 V Supply (pin 33) - 10 - mA 5 V Supply (pin 31, 32) - 108 - mA 3.3 V Supply (pin 33) - 6 - mA 3.3 V Supply (pin 31, 32) - 55 - mA ICCMD IFAMP Current Consumption ICCIFAM IFAMP Current Consumption (Low Current Mode) 1. All linearity and NF performances are intended at maximum LO amplitude (LO_A[1:0]=[11]), tuning capacitors (CAP[2:0]) programmed according to the selected frequency, mixer bias (MIX[3:0]) set to maximize performance and the device operated in high current mode. The performances of conversion gain, NF and linearity are intended at the SMA connectors of a typical application board. 2. The IF frequency range supported by the IF Amplifier is from 70 to 400 MHz. The exact IF frequency range supported for a specific RF frequency can be calculated as FIF = ABS(FLO-FRF) where FLO is inside the specified LO frequency range. 3. Guaranteed by design and characterization 4. RFin = 0 dBm/tone, RF tone spacing = 5 MHz 5. Guaranteed by design Table 7. Symbol Pin diode attenuator driver (dual output current DAC) electrical characteristics Parameters Conditions Min Typ Max Unit R Resolution - - 10 - Bit DNL Differential non linearity - -0.05 - 0.05 LSB INL Integral non linearity - -0.45 - 0.45 LSB (1) - 0.28 - 2.8 mA IFS Full Scale current - Current Mismatch - - - 2 % - Output voltage compliance range - 0 - 3 V VREXT_DAC Voltage Reference - - 1.19 REXT_DAC REXT DAC Range - 10 - 100 kΩ Iccstatic Static current consumption (Iout = 0 mA; pin 1) - 2.5 - mA 1. See relationship between IDAC and REXT_DAC in the Circuit Description section (Dual Output Current DAC) 16/67 Doc ID 018355 Rev 5 V STW82100B Table 8. Electrical characteristics Integer-N synthesizer electrical characteristics Symbol Parameter Conditions Min Typ Max Unit Prescaler 16/17 256 - 65551 - Prescaler 19/20 361 - 77836 - VCO dividers N VCO Divider Ratio (N) Reference clock and phase frequency detector Fref Reference input frequency - 10 19.2 200 MHz - Reference input sensitivity - 0.35 1 1.5 Vpeak R Reference Divider Ratio - 2 - 1023 FPFD PFD input frequency - - - 16 Prescaler 16/17 FLO/ 65551 - FLO/ 256 Hz Prescaler 19/20 FLO/ 77836 - FLO/ 361 Hz - - 5 mA FSTEP Frequency step (1) MHz Charge pump ICP ICP sink/source (2) 3bit programmable VOCP Output voltage compliance range - 0.4 - - Spurious(3) - - -70 - dBc Higher frequency range - 100 - MHz/V Intermediate frequency range - 85 - MHz/V Lower frequency range - 70 - MHz/V Higher frequency range - 75 - MHz/V Intermediate frequency range - 65 - MHz/V Lower frequency range - 55 - MHz/V CALTYPE [0] - - 125 °C CALTYPE [1] - - 125 °C Vdd-0.3 V VCOs KVCOA KVCOB VCOA sensitivity VCOB sensitivity ΔTLKA VCOA Maximum Temperature variation for continuous lock (4) ΔTLKB VCOB Maximum Temperature variation for continuous lock (4) CALTYPE [0] - - 95 °C CALTYPE [1] - - 125 °C VCO A Pushing - - 8 - MHz/V VCO B Pushing - - 14 - MHz/V VCTRL VCO control voltage - 0.4 - LO Harmonic Spurious - - IVCO VCO and VCO buffer current consumption Amplitude [11] (pin 4) - IDIV2 DIVIDER by 2 consumption (pin 3) - - Doc ID 018355 Rev 5 Vdd-0.3 V -20 dBc 35 - mA 20 - mA 17/67 Electrical characteristics Table 8. STW82100B Integer-N synthesizer electrical characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit 2 x LO output buffer (test purpose only) FOUT Frequency range - 3.3 - 4.74 GHz POUT Output level - - 0 - dBm RL Return Loss Matched to 50ohm - 15 - dB I2LOBUF Current Consumption (pin 15, 16, 17) - 26 - mA LO output buffer FOUT Frequency range - 1.65 - 2.37 GHz POUT Output level - - 3 - dBm RL Return Loss Matched to 50ohm - 14 - dB ILOBUF Current Consumption (pin 15, 16, 17) - 26 - mA External VCO (LO) buffer fINVCO Frequency range - 1.65 - 2.37 GHz PIN Input level - - 0 - dBm IEXTBUF Current Consumption External VCO Buffer (pin 4) - 25 - mA PLL miscellaneous IPLL PLL Current Consumption Input Buffer, Prescaler, Digital Dividers, misc. (pin 24) - 8 - mA IPRE Prescaler input buffer Current Consumption (pin 12) - 3 - mA ICP Charge Pump Current Consumption CPSEL=[111], REXT_CP = 4.7 kΩ (pin 21) - 4 - mA tLOCK Lock up time(5) 25 kHz PLL bandwidth; within 1ppm of frequency error - 150 - µs 1. The frequency step is related to the PFD input frequency as follows: FSTEP=FPFD/2) 2. See relationship between ICP and REXT_CP in the Circuit Description section (Charge Pump) 3. The level of spurs may change depending on PFD frequency, Charge Pump current, selected channel and PLL loop BW. 4. When setting a specified output frequency, the VCO calibration procedure must be run first in order to select the best subrange for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating temperature range (-40 oC to +85 oC), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by ΔTLKA or ΔTLKB, provided that the final temperature T1 is still inside the nominal range. 5. Frequency jump form 1950 to 1800 MHz; it includes the time required by the VCO calibration procedure (7 x FPFD cycles =17.5 µs with FPFD =400 kHz)) 18/67 Doc ID 018355 Rev 5 STW82100B Table 9. Electrical characteristics Phase noise performance(1) Parameters Conditions Min. Typ. Max. - -230 - Unit In band phase noise floor, closed loop(2) Normalized In Band Phase Noise I =4 mA, PLL BW = 50 kHz CP Floor (LO) (including reference clock In Band Phase Noise Floor (LO) contribution) dBc/Hz -230+20log(N)+10log(FPFD) dBc/Hz PLL integrated phase noise Integrated Phase Noise (single sided) 100 Hz to 40 MHz FLO=2.200 GHz, FSTEP=200 kHz, ICP=3 mA, PLL BW = 25 kHz - -45 - dBc - 0.48 - ° rms LOA (1650 MHz to 1950 MHz) – open loop Phase Noise @ 1 kHz - - -69 - dBc/Hz Phase Noise @ 10 kHz - - -95 - dBc/Hz Phase Noise @ 100 kHz - - -118 - dBc/Hz Phase Noise @ 1 MHz - - -139 - dBc/Hz Phase Noise @ 10 MHz - - -152 - dBc/Hz Phase Noise Floor @ 40 MHz - - -154 - dBc/Hz LOB (2050 MHz to 2370 MHz) – open loop Phase Noise @ 1 kHz - - -62 - dBc/Hz Phase Noise @ 10 kHz - - -88 - dBc/Hz Phase Noise @ 100 kHz - - -112 - dBc/Hz Phase Noise @ 1 MHz - - -134 - dBc/Hz Phase Noise @ 10 MHz - - -150 - dBc/Hz Phase Noise Floor @ 40 MHz - - -153 - dBc/Hz 1. Phase Noise SSB. VCO amplitude set to maximum value [11]. All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of -144 dBc/Hz @1 kHz offset, -157 dBc/Hz @10 kHz offset and -168 dBc/Hz of noise floor. 2. Normalized PN = Measured LO PN – 20log(N) – 10log(FPFD) where N is the VCO divider ratio (N=B*P+A) and FPFD is the comparison frequency at the PFD input Doc ID 018355 Rev 5 19/67 Typical performance characteristics STW82100B 7 Typical performance characteristics Note: Vsupply digital = 3.3 V, Vsupply analog1 = 3.3 V, Vsupply analog2 = 5 V, FIF = 150 MHz, TA = +25 °C, RF power = 0 dBm, unless otherwise specified. Conversion gain against RF frequency Conversion gain (dB) Figure 3. RF frequency (MHz) Noise figure against RF frequency Noise figure (dB) Figure 4. RF frequency (MHz) 20/67 Doc ID 018355 Rev 5 STW82100B Typical performance characteristics IIP3 against RF frequency IIP3 (dBm) Figure 5. RF frequency (MHz) 2RF-2LO response against RF frequency 2RF-2LO response (dB) Figure 6. RF frequency (MHz) Doc ID 018355 Rev 5 21/67 Typical performance characteristics 22/67 STW82100B Figure 7. LOA (VCOA div. by 2) closed-loop phase noise at 1.8 GHz (FSTEP = 200 kHz, ICP = 2 mA) Figure 8. LOB (VCOB div. by 2) closed-loop phase noise at 2.2 GHz (FSTEP = 200 kHz, ICP = 2 mA) Doc ID 018355 Rev 5 STW82100B 8 General description General description The STW82100B (see Figure 1: STW82100B block diagram on page 7) consists of a high linearity passive CMOS mixer with integrated RF balun, an IF amplifier, a 10-bit current steering DAC with dual output, and an integrated integer-N synthesizer. The synthesizer embeds 2 internal low-noise VCOs with buffer blocks, a divider by 2, a low noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a dual-modulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P+A. The device is controlled through a digital interface (I2C bus interface or SPI digital interface). All internal devices operate with a power supply of 3.3 V except for the IF Amplifier output stage and the mixer driver stage operating at 5 V power supply in order to maximize the linearity performance. If the application requires a reduced linearity and noise figure performance the device is programmed in a low-current mode by using the minimum LO amplitude and the minimum biasing current in the IF amplifier. In low-current mode operation the device can use only the 3.3 V power supply thus dissipating less power. 8.1 Circuit description 8.1.1 Reference input stage The reference input stage is shown in Figure 9. The resistor network feeds a DC bias at the Fref input while the inverter used as the frequency reference buffer is AC coupled. Figure 9. Reference frequency input buffer VDD Fref Inverter Buffer Power Down Doc ID 018355 Rev 5 23/67 General description 8.1.2 STW82100B Reference divider The 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the PFD. The division ratio is programmed through the digital interface. 8.1.3 Prescaler The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus (P) is programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. 8.1.4 A and B counters The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by the following formulae: N = B× P+A ( B × P + A ) × F ref F VCO = ----------------------------------------------R where: FVCO: VCO output frequency. P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface). B: division ratio of the main counter. A: division ratio of the swallow counter. Fref: input reference frequency. R: division ratio of the reference counter. N: division ratio of the PLL The following points should be noted: 24/67 ● For the VCO divider to work correctly, B must be higher than A. ● A can take any value from 0 to 31. ● Two PLL division ratio (N) ranges are possible, depending on the value of P: – 256 to 65551 (when P=16) – 361 to 77836 (when P=19). Doc ID 018355 Rev 5 STW82100B General description Figure 10. VCO divider diagram VCOBUFVCOBUF+ Prescaler 16/17 or 19/20 To PFD modulus 12-bit B counter 5-bit A counter 8.1.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 11 is a simplified schematic of the PFD. Figure 11. PFD diagram VDD D Q Up Fref_DIV R Delay R FVCO_div VDD D Q Down ABL Doc ID 018355 Rev 5 25/67 General description 8.1.6 STW82100B Lock detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked. The Lock Detector consumes current only during PLL transients. 8.1.7 Mute until lock This (software controlled) function shuts down the following elements until the PLL achieves the lock status: ● RF output stage ● LO output buffer ● mixer ● IF amplifier circuitry Under this setting there is no signal at the IF output stage or the LO output during a frequency jump. 8.1.8 Charge pump This block drives two matched current sources, Iup and Idown, which are controlled respectively by the UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and the selection of one of 8 possible values by a 3-bit word. The minimum value of the output current is: IMIN = 2*VBG/REXT_CP (VBG~1.17 V) Table 10. Note: 26/67 Current values for CPSEL[2:0] selection CPSEL2 CPSEL1 CPSEL0 Current Value for REXT=4.7 kΩ 0 0 0 IMIN 0.5 mA 0 0 1 2*IMIN 1.00 mA 0 1 0 3*IMIN 1.50 mA 0 1 1 4*IMIN 2.00 mA 1 0 0 5*IMIN 2.50 mA 1 0 1 6*IMIN 3.00 mA 1 1 0 7*IMIN 3.50 mA 1 1 1 8*IMIN 4.00 mA The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2. Doc ID 018355 Rev 5 STW82100B General description Figure 12. Loop filter connection VDD VCTRL C3 Buffer Charge pump R3 ICP R1 C2 C1 Buffer Cal bit 8.1.9 Voltage controlled oscillators VCO selection Within the STW82100B two low-noise VCOs are integrated to cover a wide band from 1650 MHz to 1950 MHz, and from 2050 MHz to 2370 MHz after the division by 2: ● VCO A frequency range is 3300 MHz to 3900 MHz ● VCO B frequency range is 4100 MHz to 4740 MHz VCO frequency calibration Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variations on the VCO center frequency. An automatic range selection is performed when the bit SERCAL rises from ‘0’ to ‘1’ . The charge pump is inhibited and the pins ICP and VCTRL are set at a fixed calibration voltage (VCAL). The frequency ranges are then tested to select the nearest one to the desired output frequency (FOUT= N*Fref/R) with VCAL input voltage applied. After this selection, the charge pump is once again enabled and the PLL performs a fine adjustment around VCAL on the loop filter voltage to lock FOUT, thus enabling a fast settling time. Two calibration algorithms are selectable by setting the CALTYPE bit. Setting the CALTYPE to ’1’ guarantees the PLL lock versus temperature variations. Once programmed at the initial temperature, T0, within the operating temperature range (-40 °C to +85 °C), the synthesizer is able to maintain the lock status if the temperature drift (in either direction) is within the limit specified by ΔTLK, and provided that the final temperature, T1, is still inside the nominal range. Setting the CALTYPE bit to ‘0’ fixes VCAL to the mid point of the charge pump output (VDD/2). Optimum PLL phase noise performance versus temperature variations with a reduced ΔTLK is guaranteed in this case. The ΔTLK parameter, specific to each VCO and calibration type, in the STW82100B is specified in Table 8: Integer-N synthesizer electrical characteristics. Doc ID 018355 Rev 5 27/67 General description STW82100B Figure 13. VCO typical sub-band characteristics FREQ (Hz) 00000 00001 01111 11111 Calibrator lock range 0.50 0.00 1.00 1.50 2.00 2.50 3.00 3.50 VCTRL (V) The SERCAL bit should be set to ’1’ at each division ratio change. The calibration takes approximately 7 periods of the Comparison Frequency and the SERCAL bit is automatically reset to ’0’ at the end of each calibration. The maximum allowed FPFD to perform the calibration process is 1 MHz. If a higher FPFD is used the following procedure should be adopted: 1. Calibrate the VCO at the desired frequency with an FPFD lower than 1 MHz 2. Set the A, B and R dividers ratio for the desired FPFD For calibration details refer to Section 9.4.1: VCO calibration procedure (I2C interface) or Section 10.4.1: VCO calibration procedure (SPI interface). 28/67 Doc ID 018355 Rev 5 STW82100B General description VCO calibration auto-restart feature The VCO Calibration Auto-Restart feature, once activated, allows the calibration procedure to be restarted when the Lock Detector reports that the PLL has moved to an unlock condition (trigger on ‘1’ to ‘0’ transition of Lock Detector signal). This situation could happen if the device experiences a significant temperature variation and the CALTYPE bit is set for optimum PLL phase noise performance (CALTYPE [0]). By enabling the VCO Calibration Auto-Restart feature (through the AUTO_CAL bit), the device re-selects the proper VCO frequency sub-range without any external user command. This feature can be enabled only when the FPFD is lower than 1 MHz. VCO voltage amplitude control The voltage swing of the VCOs can be adjusted over 4 levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). This setting trades current consumption with phase noise performances of the VCO. Higher amplitudes provide best phase noise while lower ones save power. Doc ID 018355 Rev 5 29/67 General description STW82100B Table 11 and Table 12 give the current consumption and the phase noise at 1 MHz. Table 11. VCOA performance against amplitude setting (frequency = 3.6 GHz) PLL_A[1:0] Table 12. 8.1.10 Current Consumption (mA) PN @ 1 MHz 00 23 -127 01 24 -128 10 32 -131 11 35 -132 VCOB performance against amplitude setting (frequency = 4.3 GHz) PLL_A[1:0] Current Consumption (mA) PN @ 1 MHz 00 16 -124 01 18 -126 10 27 -128 11 30 -129 Output stage The differential output signal of the synthesizer after the Divider by 2 is available on pins 16 and 17. The output stage is selected by programming the PD[4:0] bits. The output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the PCB. See Figure 27: Diversity mode operation with same LO frequencies. 8.1.11 External VCO buffer Although the STW82100B includes two wideband and low-noise VCOs, external VCO use capability is also provided. The external VCO buffer can be used to manage a signal coming from an external VCO in order to build a local oscillator signal by using the STW82100B internal synthesizer as a PLL. This is only possible when External VCO standard mode or External VCO diversity master mode operation are selected. See Figure 29: External VCO standard mode operation and Figure 30: External VCO diversity mode operation with same LO. If the STW82100B is operated in Diversity slave mode, the external VCO buffer manage the signal coming from the synthesizer output stage of another STW82100B device See Figure 27: Diversity mode operation with same LO frequencies and Figure 30: External VCO diversity mode operation with same LO. The selection of the external VCO buffer is done by setting the PD[4:0] bits. The external VCO signal can range from 1650 MHz to 2370 MHz and its minimum power level must be -10 dBm. 30/67 Doc ID 018355 Rev 5 STW82100B 8.1.12 General description Mixer and IF amplifier LO mixer driver The LO signal is fed through a driver in order to achieve the high power level needed to drive the passive mixer for maximum performance of linearity and NF. The LO Mixer Driver is coupled to the mixer with an integrated LO balun. The LO signal level is adjusted by means of an Automatic Level Control loop (ALC) controlled by the bits LO_A[1:0]. In low current mode the configuration LO_A[1:0]=’00’ (minimum LO amplitude) should be selected and the power supply on pin 40 can be set to 3.3 V. The LO balun resonating frequency can be adjusted by means of the bits CAP[2:0] in order to match the selected LO frequency. Table 13. Suggested CAP[2:0] values for LO Frequency range mixer CAP[2:0] LO frequency range 000 2225MHz ÷ 2370MHz 001 2100MHz ÷ 2225MHz 010 2000MHz ÷ 2100MHz 011 1900MHz ÷ 2000MHz 100 1825MHz ÷ 1900MHz 101 1750MHz ÷ 1825MHz 110 1700MHz ÷ 1750MHz 111 1650MHz ÷ 1700MHz Mixer A doubly balanced CMOS passive mixer is internally driven by the high level LO signal in order to achieve high linearity and low noise performance. The RF integrated balun permits the removal of external components and it is internally matched to 50 ohms. The gate bias of the CMOS devices in the mixer is programmable with 4 bits (MIX[3:0]) to optimize the input matching and the gain of the signal chain. Higher values of gate bias (higher decimal values of MIX[3:0]) are suggested to maximize linearity and lower values to maximize the performance of Gain and NF. Doc ID 018355 Rev 5 31/67 General description STW82100B IF amplifier The integrated IF stage permits a 200-ohm load to be driven (typically a SAW filter) ensuring high linearity. It is an open collector stage (pin 31, 32) and should be biased to 5 V with choke inductors. The typical output impedance is 200 ohms. The linearity performances are controlled by the bits IFAMP[1:0]. In low current mode the configuration IFAMP[1:0]=’00’ (minimum linearity) should be selected and the open collector stage can be biased to 3.3 V with choke inductors. Table 14. 8.1.13 Linearity performance against IFAMP[1:0] configuration (typical condition) IFAMP[1:0] Linearity performance 00 19.5 dB 01 21.5 dB 10 23.5dB 11 25.5dB Dual output current DAC The STW82100B embeds a 10-bit Dual Output steering current DAC especially suited to drive an external PIN diode attenuator. This provides power level calibration capability at the RF input for the TX observation path applications. The current sourced by the DAC is related to the REXT_DAC resistor according to the following formulae (where VREXT_DAC is approximately 1.19 V): 1 3 × VR EXT_DAC 1 IDAC LSB = --- × ---------------------------------------- × -----R EXT_DAC 2 64 LSB DAC current 1 3 × VR EXT_DAC 1023 IDAC FS = --- × ---------------------------------------- × ------------R EXT_DAC 2 64 Full scale current With a 10 kΩ REXT_DAC the FS current is approximately 2.8 mA. 32/67 Doc ID 018355 Rev 5 STW82100B 9 I2C bus interface I2C bus interface The I2C bus interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 0 V. Data transmission from a microprocessor to the STW82100B takes place through the 2 wires (SDA and SCL) I2C-bus interface. The STW82100B is always a slave device. The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. The device that controls the data transfer is known as the master and the others as slaves. The master always initiates the transfer and provides the serial clock for synchronization. The STW82100B I2C bus supports Fast Mode operation (clock frequency up to 1 MHz). 9.1 I2C general features 9.1.1 Data validity Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH identify START or STOP conditions. Figure 14. Data validity waveform SDA SCL Data line stable data valid Change data allowed Doc ID 018355 Rev 5 33/67 I2C bus interface 9.1.2 STW82100B START and STOP conditions Figure 15. START and STOP condition waveform SCL SDA START STOP START condition A START condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer. STOP condition A STOP condition is identified by a transition of the data bus SDA from LOW to HIGH while the clock signal SCL is stable in the HIGH state.. A STOP condition terminates communications between the STW82100B and the Bus Master. 9.1.3 Byte format and acknowledge Every byte (8 bits long) transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. An acknowledge bit indicates a successful data transfer. The transmitter, either master or slave, releases the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits of data. Figure 16. Byte format and acknowledge waveform SCL 1 SDA MSB 2 3 7 8 Acknowledgement from receiver START STOP 34/67 9 Doc ID 018355 Rev 5 STW82100B 9.1.4 I2C bus interface Device addressing To start the communication between the Master and the STW82100B, the master must initiate with a START condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The first 7 MSBs are the device address identifier, corresponding to the I2C-Bus definition. For the STW82100B the address is set as ’1101A2A1A0’, 3-bits programmable. The 8th bit (LSB) is the read or write operation bit (the RW bit is set to 1 in read mode and to 0 in write mode). After a START condition the STW82100B identifies the device address on the bus and, if matched, it acknowledge the identification on SDA bus during the 9th clock pulse. 9.1.5 Single-byte write mode Following a START condition the master sends a device select code with the RW bit set to 0. The STW82100B gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers. After reception of the internal byte sub-address the STW82100B again responds with an acknowledge. A single-byte write to sub-address 0x00 would affect DATA_OUT[47:40], a single-byte write with sub-address 0x04 would affect DATA_OUT[15:8] and so on. S 9.1.6 1101A2A1A0 0 sub-address byte ack ack DATA IN ack P Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a STOP condition. The sub-address determines the starting byte. For example, a multi-byte write with subaddress 0x01 and 4 DATA_IN bytes affects 4 bytes starting at address 0x01 (registers at addresses 0x01, 0x02, 0x03 and 0x04 are modified). S 9.1.7 1101A2A1A0 0 ack sub-address byte ack DATA IN ack .. DATA IN ack P Current byte address read In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW82100B acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. S 1101A2A1A0 1 ack Doc ID 018355 Rev 5 DATA OUT No ack P 35/67 I2C bus interface STW82100B 9.2 I2C timing specifications 9.2.1 Data and clock timing specification Figure 17. I2C data and clock waveforms SDA SCL tcwl tcs Table 15. tcwh I2C data and clock timing parameters Symbol 9.2.2 tch Parameter Min Tcs Data to clock set up time 2 Tch Data to clock hold time 2 Tcwh Clock pulse width high 10 Tcwl Clock pulse width low 5.5 ns I2C START and STOP timing specification Figure 18. I2C START and STOP timing waveforms SDA SCL tstart 36/67 Unit Doc ID 018355 Rev 5 tstop STW82100B I2C bus interface Table 16. I2C START and STOP timing parameters Symbol Parameter Min Tstart Clock to data start time 2 Tstop Data to clock down stop time 2 Unit ns 9.2.3 I2C acknowledge timing specification Figure 19. I2C acknowledge timing waveforms SDA SCL 9 8 td1 Table 17. td2 I2C acknowledge timing parameters Symbol Parameter Max Td1 Ack begin delay 2 Td2 Ack end delay 2 Unit ns Doc ID 018355 Rev 5 37/67 I2C bus interface 9.3 STW82100B I2C registers STW82100B has 9 write-only registers and 1 read-only register. 9.3.1 I2C register summary The following table gives a short description of the write-only registers list. Table 18. Offset I2C register list Register name Description Page 0x00 FUNCTIONAL_MODE Functional mode register on page 39 0x01 B_COUNTER B counter register on page 39 0x02 A_COUNTER A counter register on page 40 0x03 REF_DIVIDER Reference clock divider ratio register on page 40 0x04 CONTROL PLL control register on page 41 0x05 MUTE_&_CALIBRATION Mute and calibration control register on page 42 0x06 DAC_CONTROL DAC control register on page 42 0x07 MIXER_CONTROL Mixer control register on page 43 0x08 IFAMP_LO_CONTROL IF amplifier LO control register on page 43 0x09 READ_ONLY_REGISTER Device ID and calibration status register on page 44 38/67 Doc ID 018355 Rev 5 STW82100B I2C bus interface I2C register definitions 9.3.2 FUNCTIONAL_MODE Functional mode register 7 6 ALC_PD PKD_EN 5 PD[4:0] B11 W W W W Address: 0x00 Type: W Reset: 0x00 4 3 2 1 0 [7] ALC_PD: for test purpose only must be set to ’0’. (ALC ON) [6] PKD_EN: for test purpose only must be set to ’0’. (Peak detector output on pin 36 OFF) [5:1] PD[4:0]: bits used to select different functional modes for the STW82100B according to the following table 00000: (0 decimal) Power down mode 00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON) 00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON) 00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON; internal synthesizer OFF) 00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output buffer ON) 00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output buffer ON) 00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO input buffer ON) 00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO input buffer and LO output buffer ON) [0] B11: B counter value (bits B[10:0] in the B_COUNTER and A_COUNTER registers) B_COUNTER 7 B counter register 6 5 4 3 2 1 0 B[10:3] W Address: 0x01 Type: W Reset: 0x00 Description: Most significant bits of the B counter value [7:0] B[10:3]: B counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[2:0] in the A_COUNTER register) Doc ID 018355 Rev 5 39/67 I2C bus interface STW82100B A_COUNTER A counter register 7 6 5 4 3 2 B[2:0] A[4:0] W W Address: 0x02 Type: W Reset: 0x00 Description: Least significant bits of the B-counter value. A-counter value. 1 0 [7:5] B[2:0]: B Counter value (bit B11 in the FUNCTIONAL_MODE register, bits B[10:3] in the B_COUNTER register). [4:0] A[4:0]: A counter value REF_DIVIDER 7 Reference clock divider ratio register 6 5 4 3 2 1 R[9:2] W Address: 0x03 Type: W Reset: 0x00 Description: Most significant bits of the reference clock divider ratio value. [7:0] R[9:2]: Reference clock divider ratio (bits R[1:0] in the CONTROL register) 40/67 Doc ID 018355 Rev 5 0 STW82100B I2C bus interface CONTROL 7 PLL control register 6 5 4 3 2 1 0 [R1:0] PLL_A[1:0] CPSEL[2:0] PSC_SEL W W W W Address: 0x04 Type: W Reset: 0x00 Description: Least significant bits of the reference clock divider ratio value and PLL control bits. [7:6] R[1:0]: Reference clock divider ratio (bits R[9:2] in the REF_DIVIDER register) [5:4] PLL_A[1:0]: VCO amplitude [3:1] CPSEL[2:0]: Charge Pump output current [0] PSC_SEL: Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19) The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula: F ref F LO = D R ⋅ ( B ⋅ P + A ) ⋅ ---------R where DR equals 0.5 (VCOs output frequency divided by 2) and P is the selected Prescaler Modulus Doc ID 018355 Rev 5 41/67 I2C bus interface STW82100B MUTE_&_CALIBRATION MUTE_IFAMP_EN 0 MUTE_MIX_EN 1 MUTE_LOOUT_EN 2 MUTE_TYPE 3 MUTE_EN 4 SELEXTCAL 5 SERCAL 6 CALTYPE 7 Mute and calibration control register W W W W W W W W Address: 0x05 Type: W Reset: 0x00 Description: For test purposes only [7] CALTYPE: Calibration algorithm selection 0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the ΔTLK range [6] SERCAL: 1: starts the VCO auto-calibration (automatically reset to ’0’ at the end of calibration) [5] SELEXTCAL: test purpose only; must be set to ‘0’ [4] MUTE_EN: 0: mute function disabled 1: mute function enabled [3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute the IF output on Unlock state) [2] MUTE_LOOUT_EN: To be set to ’1’ to mute the LO output buffer [1] MUTE_MIX_EN: To be set to ’1’ mute the Mixer circuitry [0] MUTE_IFAMP_EN: To be set to '1' to mute the IF amplifier circuitry DAC_CONTROL 7 6 DAC control register 5 4 3 2 1 DAC[9:2] W Address: 0x06 Type: W Reset: 0x00 Description: Most significant bits of the DAC control word [7:0] DAC[9:2]: DAC input word for DAC current control (bits DAC[1:0] in the MIXER_CONTROL register). 42/67 Doc ID 018355 Rev 5 0 STW82100B I2C bus interface MIXER_CONTROL 3 2 1 0 CAL_AUTOSTART_EN 4 PD_DAC 5 MIX[3:0] 6 DAC[1:0] 7 Mixer control register W W W W Address: 0x07 Type: W Reset: 0x00 Description: Least significant bits of DAC control word and mixer control bit fields [7:6] DAC[1:0]: DAC input word for DAC current control (bits DAC[9:2] in the DAC_CONTROL register) [5:2] MIX[3:0]: Mixer bias control value [1] PD_DAC: DAC power down [0] CAL_AUTOSTART_EN: VCO calibration auto-restart enable (’1’ active), permits to automatically restart the VCO calibration procedure in case of PLL unlock IFAMP_ LO_CONTROL 7 6 IF amplifier LO control register 5 4 3 2 1 0 IFAMP[1:0] CAP[2:0] LO_A[1:0] LPMUX_EN W W W W Address: 0x08 Type: W Reset: 0x00 [7:6] IFAMP[1:0]: power consumption/linearity control [5:3] CAP[2:0]: Tuning capacitors control [2:1] LO_A[1:0]: LO amplitude control [0] LPMUX_EN: for test purpose only (low power mode for MUX). Must be set to ’0’ Doc ID 018355 Rev 5 43/67 I2C bus interface STW82100B READ-ONLY REGISTER 7 6 Device ID and calibration status register 5 4 3 2 ID[1:0] LOCK_DET INTCAL[4:0] R R R 1 0 Address: 0x09 Type: R Reset: 0x00 Description: This register is automatically addressed in the ‘current byte address read mode’ [7:6] ID[1:0]: device identification ’00’ for STW82100B [5] LOCK_DET: ’1’ when PLL is locked [4:0] INTCAL[4:0]: internal value of the VCO calibration control word 44/67 Doc ID 018355 Rev 5 STW82100B I2C bus interface 9.4 Device calibration through the I2C interface 9.4.1 VCO calibration procedure (I2C interface) The calibration of the VCO center frequency is activated by setting the SERCAL bit of the MUTE & CALIBRATION register to ’1’. To program the device ensuring a correct VCO calibration, the following procedure is required before every channel change: 1. 2. Program all the Registers using a multi-byte write sequence with the desired setting: – Functional Mode – B and A counters – R counter – VCO amplitude – Charge Pump – Prescaler Modulus – DAC – Mixer and LO Control – all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’. Program the MUTE & CALIBRATION register using a single-byte write sequence (subaddress 0x05) with the SERCAL bit set to ’1’. The maximum allowed PFD frequency (FPFD) to perform the calibration process is 1 MHz. If the desired FPFD is higher than 1 MHz the following steps are needed: 9.4.2 3. Perform all the step of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that FPFD results lower than 1 MHz. 4. Once calibration is completed, program all the Registers by using a multi-byte write sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the desired VCO and PFD frequencies. Power ON sequence (I2C interface) At power-on the device is configured in power-down mode. In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed: 1. Power up the device 2. Provide the Reference clock 3. Implement the first programming sequence with a proper delay time between the STOP condition of the multi-byte write sequence and that of the single-byte write sequence (see Figure 20). The Tdelay value must respect the following condition: 1 T delay > 1023 × ---------F ref Fref is the reference clock frequency. Doc ID 018355 Rev 5 45/67 I2C bus interface STW82100B Figure 20. I2C first programming timing START STOP START STOP CLK Tdelay > 1023/Fref MSB DATA LSB Multi-byte sequence 9.4.3 LSB MSB Single-byte sequence VCO calibration auto-restart procedure (I2C interface) The VCO calibration auto-restart feature is enabled in two steps: 46/67 1. Set the desired frequency ensuring VCO calibration procedure as described above (Section 9.4.1). 2. Program the MIXER_CONTROL register (sub-address 0x07) using a single-byte write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping the others unchanged. Doc ID 018355 Rev 5 STW82100B SPI digital interface 10 SPI digital interface 10.1 SPI general features The SPI digital interface is selected by hardware connection of the pin 25 (DBUS_SEL) to 3.3 V. The STW82100B IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wires bus can be clocked at a frequency as high as 100 MHz to allow fast programming of the registers containing the data for RF IC configuration. The programming of the chip is done through serial words with whole length of 26 bits. The first 2 MSB represent the address of the registers. The others 24 LSB represent the value of the registers. Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal. On the rising edge of the LOAD signal the outputs of the selected register are sent to the device. Figure 21. SPI input and output bit order Last bit sent (LSB) 0 1 23 2 25 (MSB) 24 DATA A1 LOAD Address decoder LOAD #4 00 (LSB) Reg. #0 Reg. #1 Doc ID 018355 Rev 5 Reg. #4 47/67 SPI digital interface STW82100B Figure 22. SPI data structure LSB MSB Address A1 Data for register (24 bits) A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Note: MSB is sent first Table 19. Address decoder and outputs Address Outputs DATABITS No A1 A0 0 0 24 0 ST1 DAC, Mixer, Tuning capacitors, LO_amplitude 0 1 24 1 ST2 Reference divider, VCO amplitude, VCO Calibration, Charge Pump current, Prescaler Modulus, Mute functions 1 0 24 2 ST3 Functional modes, VCO dividers 1 1 24 3 ST4 Reserved 48/67 D23-D0 Name Function Doc ID 018355 Rev 5 STW82100B SPI digital interface 10.2 SPI timing specification 10.2.1 Data, clock and load timing Figure 23. SPI timing waveforms tsetup thold MSB DATA MSB - 1 LSB CLOCK tclk_loadr tclk LOAD tload Table 20. tclk_loadf SPI timing parameters Parameter Description Min. Typ. Max. Unit 1 - - ns tsetup DATA to CLOCK setup time thold DATA to clock hold time 0.5 - - ns tclk CLOCK cycle period 10 - - ns tload LOAD pulse width 3 - - ns tclk_loadr CLOCK to LOAD rising edge 0.6 - - ns tclk_loadf CLOCK to LOAD falling edge 2.5 - - ns Doc ID 018355 Rev 5 49/67 SPI digital interface STW82100B 10.3 SPI registers 10.3.1 SPI register summary Table 21. SPI register list Offset Register name Description Page 0x00 ST1 SPI register 1 on page 50 0x01 ST2 SPI register 2 on page 51 0x10 ST3 SPI register 3 on page 52 10.3.2 SPI register definitions ST1 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 W W W W W W W W Address: 0x00 Type: W Reset: 0x00 [23:14] DAC[9:0]: DAC input word [13:10] MIX[3:0]: Mixer bias control [9] PWD_DAC: DAC power down [8] CAL_AUTOSTART_EN: VCO calibration auto-restart enable [7:6] IF[1:0]: Power consumption/linearity control [5:3] CAP[2:0]: Tuning capacitors control [2:1] LO_A[1:0]: LO amplitude control [0] LPMUX_EN: For test purpose only. Must be set to ‘0’ 50/67 5 LPMUX_EN 16 LO_A[1:0] 17 CAP[2:0] 18 IF[1:0] 19 CAL_AUTOSTART_EN 20 PWD_DAC 21 MIX[3:0] 22 DAC[9:0] 23 SPI register 1 Doc ID 018355 Rev 5 STW82100B SPI digital interface ST2 11 10 9 8 7 6 5 4 3 2 1 0 MUTE_IFAMP_EN 12 MUTE_MIX_EN 13 MUTE_LOOUT_EN 14 MUTE_TYPE 15 MUTE_EN 16 SELEXTCAL 17 SERCAL 18 CAL_TYPE 19 PSC_SEL 20 CPSEL[2:0] 21 PLL_A[1:0] 22 R[9:0] 23 SPI register 2 W W W W W W W W W W W W Address: 0x01 Type: W Reset: 0x00 [23:14] R[9:0]: Reference clock divider ratio [13:12] PLL_A[1:0]: VCO amplitude control [11:9] CPSEL[2:0]: Charge pump output current control [8] PSC_SEL: Prescaler modulus select (‘0’ for P=16, ‘1’ for P=19) [7] CAL_TYPE: Calibration algorithm selection 0: standard calibration to optimize the phase noise versus temperature 1: enhanced calibration to maximize the ΔTLK range [6] SERCAL: at ‘1’ starts the VCO auto-calibration (automatically reset to ‘0’ at the end of calibration) [5] SELEXTCAL: test purpose only. Must be set to ‘0’ [4] MUTE_EN: 0: mute function disabled 1: mute function enabled [3] MUTE_TYPE: must be set to '1' while the mute function is enabled (mute the IF output on Unlock state) [2] MUTE_LOOUT_EN: To be set to ’1’ to mute the LO output buffer [1] MUTE_MIX_EN: To be set to ’1’ to mute the Mixer circuitry [0] MUTE_IFAMP_EN: To be set to ’1’ to mute the IF amplifier circuitry Doc ID 018355 Rev 5 51/67 SPI digital interface STW82100B ST3 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A[4:0] 19 B[11:0] 20 PD[4:0] 21 PKD_EN 22 ALC_PD 23 SPI register 3 W W W W W Address: 0x10 Type: W Reset: 0x00 1 0 [23] ALC_PD: Test purpose only; must be set to ‘0’ (ALC ON) [22] PKD_EN: for test purpose only; must be set to ‘0’ [21:17] PD[4:0]: 00000: (0 decimal) Power down mode 00001: (1 decimal) Standard Mode VCOA (VCOA and RX chain ON) 00010: (2 decimal) Standard Mode VCOB (VCOB and RX chain ON) 00011: (3 decimal). Diversity Slave Mode (ExtVCO/LO input buffer and RX Chain ON; internal synthesizer OFF) 00100: (4 decimal) Diversity Master Mode VCOA (VCOA, RX Chain and LO output buffer ON) 00101: (5 decimal) Diversity Master Mode VCOB (VCOB, RX Chain and LO output buffer ON) 00110: (6 decimal) External LO Standard Mode (RX Chain ON; PLL and ExtVCO/LO input buffer ON) 00111: (7 decimal) External LO Diversity Master Mode (RX Chain ON; PLL, ExtVCO/LO input buffer and LO output buffer ON) [16:5] B[11:0]: B counter bits [4:0] A[4:0]: A Counter Bits 52/67 Doc ID 018355 Rev 5 STW82100B SPI digital interface 10.4 Device calibration through the SPI interface 10.4.1 VCO calibration procedure (SPI interface) The calibration of the VCO center frequency is activated by setting to ’1’ the SERCAL bit (ST2 Register bit [6]). In order to program properly the device while ensuring the VCO calibration, the following procedure is required before every channel change: 1. Program the ST1 Register with the desired setting (DAC, Mixer, LO Control) 2. Program the ST3 Register with the desired setting (Functional mode, B and A counters) 3. Program the ST2 Register with the desired setting (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to ’1’ The maximum allowed PFD frequency (FPFD) to perform the calibration process is 1 MHz; if the desired FPFD is higher than 1 MHz the following steps are needed: 10.4.2 4. Perform all the steps of the above calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that FPFD results lower than 1 MHz. 5. Once calibration is completed program the device with the proper setting for the desired VCO and PFD frequencies according to the following steps: a) Program the ST3 Register with the desired setting (Functional mode, B and A counters) b) Program the ST2 Register with the desired setting (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) with the SERCAL bit set to ’0’. Power ON sequence (SPI interface) At power-on the device is configured in power-down mode. In order to guarantee correct setting of the internal circuitry after the power on, the following steps must be followed: 1. Power up the device 2. Provide the reference clock 3. Implement the first programming sequence with a proper delay time between the ST3 and ST2 load rising edges (see Figure 24). The Tdelay value must respect the following condition: 1 T delay > 1023 × ---------F ref Fref is the reference clock frequency. Doc ID 018355 Rev 5 53/67 SPI digital interface STW82100B Figure 24. SPI first programming timing ST2 ST3 DATA MSB MSB-1 LSB-1 LSB MSB LSB-1 MSB-1 LSB Tdelay > 1023/Fref LOAD 10.4.3 VCO calibration auto-restart procedure (SPI interface) The VCO calibration auto-restart feature is enabled in two steps: 54/67 1. Set the desired frequency ensuring VCO calibration as described in Section 10.4.1. 2. Program the ST1 register with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others. Doc ID 018355 Rev 5 STW82100B Application information 11 Application information 11.1 Application circuit Figure 25. Typical STW82100B application circuit 3.3V_LN4 C1 C2 C3 RF_IN 5V_1 C19 C1 C2 C3 C1 C2 C3 3.3V_LN1 3.3V_LN1 RF_IN RF_CT 36 35 34 TEST2 37 TEST1 39 38 TEST_ALC 40 VDD_RFESD REXT_DAC 41 VDD_ALC VDD_DAC 2 42 MIXDRV_CT 1 I_PINDRV1 I_PINDRV2 44 43 VDD_MIXDRV C1 C2 C3 3.3V_LN3 C1 C2 C3 VDD_IFAMP 33 U3 5V_2 32 IF_OUTP C4 NC 3 C5 X4 6 EXTVCO_INP 7 EXT_PD VFQFPN-44 IF_OUTN 31 NC 30 LOAD 29 SLC/CLK 28 SDA/DATA 27 C18 L4 C14 C12 8 ADD2 VDD_DIG 26 3.3V_LN1 SPI DBUS_SEL 13 14 15 16 17 18 19 LOCK_DET 12 REXT_CP VDD_IO VDD_CP ADD0 11 ICP 10 VCTRL ADD1 OUTBUFP 9 20 21 22 24 REF_CLK 23 1 2 NC 4 3 R10 SLC/CLK R9 SDA/DATA 3.3V_LN2 3.3V_LN2 C1 C2 C3 I2C 3.3V_LN2 REF_CLK C11 C1 C2 C3 R7 LOCK_DET 3.3V_LN1 C1 C2 C3 25 VDD_PLL IF_out 6 5 LOAD C13 R8 VDD_OUTBUF 2 EXTVCO_INN OUTBUFN X2 1 5 R1 NC X3 4 VDD_VCO VDD_PSCBUF X1 External VCO 5 VDD_DIV 4 NC 6 U1 3 L3 C15 C16 C17 C1 C2 C3 3.3V_LN1 R6 3.3V_LN1 3.3V_LN1 C1 C2 C3 C1 C2 C3 R2 R3 L1 L2 R4 C9 C1 C2 C3 C10 C8 R5 C6 C7 3 4 2 5 1 6 NC U2 X5 X6 X7 X8 LO_Output Doc ID 018355 Rev 5 55/67 Application information Table 22. STW82100B Application circuit component values Designation Quantity Description Supplier C1, C15 2 4.7 µF capacitors COG (0402) C2, C11 2 1 nF capacitors COG (0402) C3 1 10 pF capacitor COG (0402) C4,C5 2 3.6 pF capacitors COG (0402) C6, C7, C19 3 6.8 pF capacitors COG (0402) C8 1 270 pF capacitor COG (0402) C9 1 2.7 nF capacitor COG (0402) C10 1 68 pF capacitor COG (0402) C12, C13, C14 3 15 pF capacitors COG (0402) C16 1 100 nF capacitor COG (0402) C17 1 100 pF capacitor COG (0402) C18 1 180 pF capacitor COG (0402) R1, R8, R9, R10 4 100 Ohm resistors (0402) - R2, R3, R7 3 51 Ohm resistors (0402) - R4 1 2.2 kohm resistor (0402) - R5 1 8.2 kohm resistor (0402) - R6 1 4.7 kohm resistor (0402) - U1 1 Balun JTI - 2450BL15B100 U2 1 Balun JTI - 1600BL15B100 U3 1 Balun ADT4-5WT Mini Circuits X1, X8 2 3.3 nH inductors CS (0402) Coilcraft, Inc X2 1 1.2 pF capacitor COG (0402) Murata Manufacturing Co., Ltd X3 1 0 Ohm resistor (0402) - X4 0 NC - X5 1 1.6 pF capacitor COG (0402) Murata Manufacturing Co., Ltd X6 1 3.9 nH inductor CS (0402) Coilcraft, Inc X7 1 2 pF capacitor COG (0402) Murata Manufacturing Co., Ltd L1, L2 2 3.7 nH inductors HQ (0402) L3, L4 2 220 nH inductors CS (1206) Murata Manufacturing Co., Ltd JOHANSON TECHNOLOGY Coilcraft, Inc Note: 56/67 1 For optimum performance a low-noise 3.3 V power supply must be used. 2 The 3.3 V and 5 V power supplies are split in order to maximize the isolation between RF, LO, IF and digital sections. Doc ID 018355 Rev 5 STW82100B 11.2 Application information Standard Mode Operation The STW82100B can be used in Standard Mode for both RX path and TX observation path (RX Chain ON and Synthesizer ON). In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device. REXT_DAC Figure 26. Standard mode operation I_PINDRV1 STW82100B DAC I_PINDRV2 5V RF_IN2 RF_IN IF_OUTP RF_IN IF AMP RF_VSS IF_OUTN 4:1 IF_OUT 50 Ω RF_CT DBUS_SEL 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT VCO calibrator MIX DRV CAL_VCO REF_CLK BUF DIV2 LOCK_DET UP PLL PFD DN CHP REXT_CP VCO BUFF CAL_VCO VCTRL ICP Doc ID 018355 Rev 5 57/67 Application information 11.3 STW82100B Diversity mode operation with same LO frequency The STW82100B supports the Diversity mode with the same LO frequency by using one STW82100B in Master Mode (RX Chain ON, Synthesizer ON and LO output buffer ON) and the other in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON). This operation mode is suitable for antenna diversity. Figure 27. Diversity mode operation with same LO frequencies 5V RF_IN_M STW82100B Master RF_IN 4:1 IF_OUTP IF AMP RF_VSS IF_M 50 Ω IF_OUTN RF_CT DBUS_SEL to DAC 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT VCO calibrator MIX DRV CAL_VCO 3.3V REF_CLK 50 Ω 50 Ω OUTBUFP BUF LO OUT DIV2 OUTBUFN LOCK_DET UP PFD PLL DN CHP REXT_CP VCO BUFF CAL_VCO VCTRL STW82100B Slave EXTVCO_INP EXT LO/VCO BUF 100 Ω ICP EXTVCO_INN DBUS_SEL DBUS SDA/DATA SCL/CLK LOAD MIX DRV 5V 5V MIXDRV_CT RF_IN_S RF_IN IF_OUTP IF AMP RF_VSS RF_CT 58/67 Doc ID 018355 Rev 5 IF_OUTN 4:1 IF_S 50 Ω STW82100B 11.4 Application information Diversity mode operation with different LO frequencies The STW82100B is particularly suitable for Diversity schemes using different LO frequencies such as the Interferer Diversity. In these schemes two STW82100Bs are used, each one set in Standard Mode and with different LO frequencies. Figure 28. Diversity mode operation with different LO frequencies 5V RF_IN1 STW82100B Master RF_IN 4:1 IF_OUTP RF_VSS IF AMP IF_OUT1 50 Ω IF_OUTN RF_CT LO1 DBUS_SEL 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT VCO calibrator MIX DRV CAL_VCO REF_CLK BUF DIV2 LOCK_DET UP PFD PLL DN CHP REXT_CP VCO BUFF CAL_VCO ICP VCTRL 5V RF_IN2 RF_IN STW82100B Diversity IF_OUTP RF_VSS IF AMP IF_OUTN 4:1 IF_OUT2 50 Ω RF_CT LO2 DBUS_SEL 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT VCO calibrator MIX DRV CAL_VCO REF_CLK BUF DIV2 LOCK_DET UP PFD PLL DN CHP REXT_CP VCO BUFF CAL_VCO VCTRL ICP Doc ID 018355 Rev 5 59/67 Application information 11.5 STW82100B External VCO standard mode operation The STW82100B can be used in Ext VCO Mode for both RX path and TX observation path (RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON and with an external VCO). In such a case the 10-bit internal DAC can drive an external PIN diode attenuator in order to calibrate the signal level at the input of the device. REXT_DAC Figure 29. External VCO standard mode operation I_PINDRV1 STW82100B DAC I_PINDRV2 5V RF_IN2 RF_IN IF_OUTP RF_IN IF AMP RF_VSS IF_OUTN RF_CT DBUS_SEL 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT MIX DRV REF_CLK BUF LOCK_DET UP PLL PFD DN CHP REXT_CP EXT LO/VCO BUF EXTVCO_INP EXTVCO_INN EXTERNAL VCO 60/67 Doc ID 018355 Rev 5 ICP 4:1 IF_OUT 50 Ω STW82100B 11.6 Application information External VCO diversity mode operation with same LO The STW82100B can be used in Diversity mode using one STW82100B in Master Mode (RX Chain ON, Synthesizer ON, EXT VCO/LO buffer ON, LO output buffer ON and with an external VCO) and the other one in Slave Mode (RX Chain ON, Synthesizer OFF and EXT VCO/LO buffer ON). Figure 30. External VCO diversity mode operation with same LO STW82100B Master RF_IN_M 5V 4:1 IF_OUTP RF_IN IF AMP RF_VSS IF_M 50 Ω IF_OUTN RF_CT to DAC DBUS_SEL 5V SDA/DATA SCL/CLK LOAD DBUS MIXDRV_CT MIX DRV REF_CLK 3.3V BUF 50 Ω 50 Ω OUTBUFP OUTBUFN LO/2xLO OUT LOCK_DET UP PLL PFD CHP DN REXT_CP VCO BUFF EXTVCO_INP ICP EXTVCO_INN EXTERNAL VCO EXTVCO_INP STW82100B Slave EXT LO/VCO BUF 100 Ω EXTVCO_INN DBUS_SEL DBUS SDA/DATA SCL/CLK LOAD MIX DRV 5V 5V MIXDRV_CT RF_IN_S RF_IN IF_OUTP IF AMP RF_VSS IF_OUTN 4:1 IF_S 50 Ω RF_CT Doc ID 018355 Rev 5 61/67 Evaluation kit 12 STW82100B Evaluation kit An evaluation kit can be delivered upon request, including the following: ● Evaluation board ● GUI (graphical user interface) to program the device ● PLLSim software for PLL loop filter design and noise simulation When ordering, please specify the following order code: Table 23. Evaluation kit order code Part number STW82100B-EVB 62/67 Description STW82100B evaluation kit, 1.6 to 2.4 GHz RF frequency range Doc ID 018355 Rev 5 STW82100B 13 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 31. VFQFPN-44 package outline Doc ID 018355 Rev 5 63/67 Package mechanical data Table 24. STW82100B VFQFPN-44 package dimensions Dimensions in mm Symbol Note: 64/67 Min Typ Max A 0.80 0.90 1.00 A1 - 0.02 0.05 A2 - 0.65 1.00 A3 - 0.200 - b 0.18 0.25 0.30 D 6.85 7.00 7.15 D1 - 6.750 - D2 3.80 3.90 4.00 D3 - 4.90 - E 6.85 7.00 7.15 E1 - 6.750 - E2 3.80 3.90 4.00 E3 - 4.90 - e - 0.50 - L 0.35 0.55 0.75 P - - 0.60 K (degree) - - 12 ddd - - 0.08 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin: A=1.00 Max. 2 Details of terminal 1 identifier are optional but must be located on the top surface of the package by using either a mold or marked features. Doc ID 018355 Rev 5 STW82100B Revision history 14 Revision history Table 25. Document revision history Date 14-Jan-2011 07-Mar-2011 29-Jun-2011 10-Jan-2012 Revision Changes 1 First release 2 Corrected cover-page description paragraph tag Table 11 and Table 12: – corrected introductory sentence – aligned titles with corporate rules 3 Corrected RF range on cover page and in Table 6: Down converter mixer and IF amplifier electrical characteristics Updated description of bitfield MUTE_TYPE in Mute and calibration control register Removed Section 4.4.1: Default configuration Added Section 9.4.2: Power ON sequence (I2C interface) Updated Figure 23: SPI timing waveforms Updated Table 20: SPI timing parameters Updated description of bitfield MUTE_TYPE in SPI register 2 Updated description of bitfield PD[4:0] in SPI register 3 Removed Section 5.4.1: Default configuration Added Section 10.4.2: Power ON sequence (SPI interface) 4 Removed ‘Preliminary Data’ tags from cover page. Table 3 moved to new Section 3: Absolute maximum ratings Section 2.1 becomes Section 4: Operating conditions Secction 2.2 becomes Section 5: Test conditions Section 2.3 becomes Section 6: Electrical characteristics Table 3: Absolute maximum ratings pins 31 and 32 changed from 0.7 to 0.8 kV ESD rating. Table 4: Operating conditions updated current consumption: – ICC3.3V. Updated typical values for Diversity Master mode and external VCO diversity master mode. Added maximum values. – ICC5V. Added maximum values. Section 6: Electrical characteristics. Added note about Vsupply, RF frequency range, ambient temperature and RF power conditons. Table 6: Down converter mixer and IF amplifier electrical characteristics : – added Max value for CG – added Min values for IIP3 – modified typical value of nFRF-nFLO at 3FRF-3FLO FRFin = -5 dBm, FIF = 150 MHz condition. – modified LO to IF leakage typical value – modified IFRL typical value – modified ICCMD typical value on 3.3 V supply (pin 41, 42) Doc ID 018355 Rev 5 65/67 Revision history Table 25. Date 10-Jan-2012 10-May-2012 66/67 STW82100B Document revision history (continued) Revision Changes 4 Table 8: Integer-N synthesizer electrical characteristics updated: – KVCOA and KVCOB value – ΔTLK split into ΔTLK A and ΔTLK B (for VCOA and VCOB). Specified as maximum values. – I2LOBUF, ILOBUF, IPLL and IPRE values – Added table footnote 4 Table 9: Phase noise performance updated values of: – Integrated Phase Noise (single sided) 100 Hz to 40 MHz – LOA open-loop phase noise @ 1 kHz and 10 kHz – LOB open-loop phase noise @ 1 kHz and 100 kHz Added Section 7: Typical performance characteristics. Modified sub-sections; – VCO frequency calibration – VCO calibration auto-restart feature Updated description of bitfield CALTYPE in registers – MUTE_&_CALIBRATION – ST2 Added Section 12: Evaluation kit. 5 Corrected RF range lower value on cover page. Replaced occurrences of ‘STI register’ with ‘SPI register’ in section headers: – Section 10.3: SPI registers – Section 10.3.1: SPI register summary – Section 10.3.2: SPI register definitions. Doc ID 018355 Rev 5 STW82100B Please Read Carefully: Information in this document is provided solely in connection with ST products. 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