TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 6-CHANNEL POWER MGMT IC WITH TWO STEP-DOWN CONVERTERS AND 4 LOW-INPUT VOLTAGE LDOs FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • Up To 95% Efficiency Output Current for DC/DC Converters: – TPS65050: 2 x 0.6 A – TPS65051: DCDC1 = 1 A; DCDC2 = 0.6 A – TPS65052: DCDC1 = 1 A; DCDC2 = 0.6 A – TPS65054: 2 x 0.6 A – TPS65056: DCDC1 = 1 A; DCDC2 = 0.6 A Output Voltages for DC/DC Converters – TPS65050: Externally Adjustable – TPS65051: Externally Adjustable – TPS65052: DCDC1 = Fixed at 3.3 V; DCDC2 = 1 V / 1.3 V for Samsung Application Processors – TPS65054: DCDC1 = Externally Adjustable; DCDC2 = 1.3 V / 1.05 V for OMAP™1710 Processor – TPS65056: DCDC1 = Fixed at 3.3 V; DCDC2 = 1 V / 1.3 V for Samsung Application Processors VI Range for DC/DC Converters From 2.5 V to 6 V 2.25-MHz Fixed Frequency Operation Power Save Mode at Light Load Current 180° Out-of-Phase Operation Output Voltage Accuracy in PWM mode ±1% Low Ripple PFM Mode Total Typical 32-µA Quiescent Current for Both DC/DC Converters 100% Duty Cycle for Lowest Dropout Two General-Purpose 400-mA, High PSRR LDOs Two General-Purpose 200-mA, High PSRR LDOs VI range for LDOs from 1.5 V to 6.5 V Digital Voltage Selection for the LDOs Available in a 4 mm x 4 mm 32-Pin QFN Package • • Cell Phones, Smart-Phones WLAN PDAs, Pocket PCs OMAP™ and Low-Power TMS320™ DSP Supply Samsung S3C24xx application processor Supply Portable Media Players DESCRIPTION The TPS6505x are integrated Power Management ICs for applications powered by one Li-Ion or Li-Polymer cell, which require multiple power rails. The TPS6505x provides two efficient, 2.25-MHz step-down converters targeted at providing the core voltage and I/O voltage in a processor based system. Both step-down converters enter a low power mode at light load for maximum efficiency across the widest possible range of load currents. For low noise applications, the devices can be forced into fixed frequency PWM mode by pulling the MODE pin high. In the shutdown mode, the current consumption is reduced to less than 1 µA. The devices allow the use of small inductors and capacitors to achieve a small solution size. TPS6505x provides an output current of up to 1 A on each DC/DC converter. The TPS6505x also integrate two 400-mA LDO and two 200-mA LDO voltage regulators, which can be turned on/off using separate enable pins on each LDO. Each LDO operates with an input voltage range between 1.5 V and 6.5 V allowing them to be supplied from one of the step-down converters or directly from the main battery. Four digital input pins are used to set the output voltage of the LDOs from a set of 16 different combinations for LDO1 to LDO4 on TPS65050 and TPS65052. In TPS65051, TPS65054 and TPS65056, the LDO voltages are adjustable using external resistor dividers. The TPS6505x come in a small 32-pin leadless package (4 mm x 4 mm QFN) with a 0.4 mm pitch. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OMAP, TMS320, PowerPAD are trademarks of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007, Texas Instruments Incorporated TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA OPTION OUTPUT CURRENT for DC/DC CONVERTERS TPS65050 LDO voltages according to Table 1 DC/DC converters externally adjustable 2 x 600 mA 65050 TPS65051 LDO voltages externally adjustable DC/DC converters externally adjustable DCDC1 = 1 A DCDC2 = 600 mA 65051 TPS65052 LDO voltages according to Table 1 DCDC1 = 3.3 V; DCDC2 = 1 V / 1.3 V DCDC1 = 1 A DCDC2 = 600 mA TPS65054 LDO voltages externally adjustable DCDC1 = externally adjustable DCDC2 = 1.3 V / 1.05 V 2 x 600 mA 65054 TPS65056 LDO voltages externally adjustable DCDC1 = 3.3 V DCDC2 = 1.0 V / 1.3 V DCDC1 = 1A DCDC2 = 600 mA 65056 -40°C to 85°C (1) QFN (1) PACKAGE (2) PART NUMBER PACKAGE MARKING 65052 RSM The RSM package is available in tape and reel. Add the R suffix (TPS65050RSMR) to order quantities per reel. Add the T suffix (TPS65050RSMT) to order quantities of 250 parts per reel. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. (2) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNITS Input voltage range on all pins except AGND, PGND, and EN_LDO1 pins with respect to AGND VI -0.3 V to 7 V Input voltage range on EN_LDO1 pins with respect to AGND -0.3 V to VCC + 0.5 V Current at VINDCDC1/2, L1, PGND1, L2, PGND2 II 1800 mA Current at all other pins 1000 mA Continuous total power dissipation TA Operating free-air temperature TJ Maximum junction temperature Tstg Storage temperature range (1) See the dissipation rating table –40°C to 85°C 125°C –65°C to 150°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS (1) PACKAGE RθJA (1) POWER RATING TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C RSM 58 K/W 1.7 W 17 mW/K 0.95 W 0.68 W The thermal resistance junction to case of the RSM package is 4 K/W measured on a high K board RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VI VO VI 2 NOM MAX UNIT Input voltage range for step-down converters, VINDCDC1/2 2.5 6 V Output voltage range for step-down converter, VDCDC1 0.6 VINDCDC1/2 V Output voltage range for step-down converter, VDCDC2 0.6 VINDCDC1/2 V Input voltage range for LDOs, VINLDO1, VINLDO2, VINLDO3/4 1.5 6.5 V Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN VO IO CO MAX UNIT Output voltage range for LDO1 and LDO2 1 VINLDO1, VINLDO2 V Output voltage range for LDO3 and LDO4 1 VINLDO3/4 V Output current at L1 (DCDC1) for TPS65051, TPS65052 1000 mA Output current at L1 (DCDC1) for TPS65050, TPS65054 600 mA Output current at L1 (DCDC2) 600 mA Output current at VLDO1, VLDO2 400 mA Output current at VLDO3, VLDO4 200 mA Inductor at L1, L2 (1) 1.5 2.2 µH Output capacitor at VDCDC1, VDCDC2 (2) 10 22 µF Output capacitor at VLDO1, VLDO2, VLDO3, VLDO4 (2) Input capacitor at VCC (2) Input capacitor at VINLDO1/2 (2) CI NOM Input capacitor at VINLDO3/4 (2) 2.2 µF 1 µF 2.2 µF µF 2.2 TA Operating ambient temperature range -40 85 °C TJ Operating junction temperature range -40 125 °C 10 Ω Resistor from battery voltage to VCC used for (1) (2) (3) filtering (3) 1 See the Application Information section of this data sheet for more details. See the Application Information section of this data sheet for more details. Up to 2 mA can flow into VCC when both converters are running in PWM, this resistor causes the UVLO threshold to be shifted accordingly. ELECTRICAL CHARACTERISTICS VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VI IQ IQ Input voltage range at VINDCDC1/2 Operating quiescent current Total current into VCC, VINDCDC1/2, VINLDO1, VINLDO2, VINLDO3/4 Operating quiescent current into VCC 2.5 6 V 20 30 µA Two converters, IO = 0 mA PFM mode enabled (Mode = 0) device not switching, EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND 32 40 µA One converter, IO = 0 mA. PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = VI 180 250 µA One converter, IO = 0 mA. Switching with no load (Mode = VI), PWM operation EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND 0.85 mA Two converters, IO = 0 mA Switching with no load (Mode = VI), PWM operation EN_DCDC1 = VI AND EN_DCDC2 = VI; EN_LDO1 = EN_LDO2 = EN_LDO3/4 = GND 1.25 mA One converter, IO = 0 mA. PFM mode enabled (Mode = GND) device not switching, EN_DCDC1 = VI OR EN_DCDC2 = VI; EN_LDO1= EN_LDO2 = EN_LDO3/4 = GND I(SD) Shutdown current EN_DCDC1 = EN_DCDC2 = GND EN_LDO1 = EN_LDO2 = EN_LDO3 = EN_LDO4 = GND V(UVLO) Undervoltage lockout threshold for DCDC converters and LDOs Voltage at VCC Submit Documentation Feedback 9 12 µA 1.8 2 V 3 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.2 VCC V 0 0.4 V 1 µA 100 nA EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 VIH High-level input voltage MODE/DATA, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 VIL Low-level input voltage MODE/DATA, EN_DCDC1, EN_DCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4, DEFDCDC2 IlB MODE/DATA = GND or VI MODE/DATA, EN_DCDC1, EN_DCDC2, DEFDCDC2, DEFLDO1, DEFLDO2, DEFLDO3, DEFLDO4, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 Input bias current 0.01 TPS65051 and TPS65052 only V_FB_LDOx = 1 V FB_LDO1, FB_LDO2, FB_LDO3, FB_LDO4 POWER SWITCH DCDC1 rDS(on) P-channel MOSFET on resistance DCDC2 Ilkg P-channel leakage current N-channel MOSFET on resistance DCDC2 Ilkg I(LIMF) N-channel leakage current Forward Current Limit PMOS (High-Side) and NMOS (Low side) DCDC1: DCDC2: 280 VINDCDC1/2 = 2.5 V 400 VINDCDC1/2 = 3.6 V 280 VINDCDC1/2 = 2.5 V 400 VINDCDC1/2 = 3.6 V 220 VINDCDC1/2 = 2.5 V 320 VINDCDC1/2 = 3.6 V 220 VINDCDC1/2 = 2.5 V 320 VDCDCx = V(DS) = 6 V DCDC1 rDS(on) VINDCDC1/2 = 3.6 V TPS65051, TPS65052, TPS65056 TPS65050 - TPS65056 630 1 VDCDCx = V(DS) = 6 V TPS65050 TPS65054 630 2.5 V ≤ VINDCDC1/2 ≤ 6 V 2.5 V ≤ VINDCDC1/2 ≤ 6 V mΩ µA 450 450 7 10 0.85 1 1.15 1.19 1.4 1.65 0.85 1 1.15 mΩ µA A A Thermal shutdown Increasing junction temperature 150 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C OSCILLATOR fSW 4 Oscillator frequency 2.025 Submit Documentation Feedback 2.25 2.475 MHz TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT VO Output voltage range for DCDC1, DCDC2 externally adjustable versions Vref Reference voltage externally adjustable versions DC output voltage accuracy VO DCDC1, DCDC2 (1) VINDCDC 1/2 0.6 600 V mV VINDCDC1/2 = 2.5 V to 6 V 0 mA < IO = < IO(max) Mode = GND, PFM operation -2% 0 2% VINDCDC1/2 = 2.5 V to 6 V 0 mA < IO = < IO(max) Mode = VI, PWM operation -1% 0 1% ∆VO Power save mode ripple voltage (2) IO = 1 mA, Mode = GND, VO = 1.3 V, Bandwith = 20 MHz 25 mVPP tStart Start-up time time from active EN to Start switching 170 µs tRamp VOUT Ramp up Time time to ramp from 5% to 95% of VO 750 RESET delay time Input voltage at threshold pin rising PB-ONOFF debounce time VOL RESET, PB_OUT output low voltage IOL RESET, PB_OUT sink current RESET, PB_OUT output leakage current Vth 80 100 26 32 IOL = 1 mA, Vhysteresis < 1 V, Vthreshold < 1 V ms 38 ms 0.2 After PB_IN has been pulled high once; Vthreshold > 1 V and Vhysteresis > 1 V, VOH = 6 V Vthreshold, Vhysteresis threshold µs 120 0.98 V 1 mA 10 nA 1 1.02 V 1.5 6.5 V VLDO1, VLDO2, VLDO3 and VLDO4 Low Dropout Regulators VI Input voltage range for LDO1, LDO2, LDO3, LDO4 VO LDO1 output voltage range TPS65050, TPS65052 only 1.2 3.3 V LDO2 output voltage range TPS65050, TPS65052 only 1.8 3.3 V LDO3 output voltage range TPS65050, TPS65052 only 1.1 3.3 V LDO4 output voltage range TPS65050, TPS65052 only 1.2 2.85 V V(FB) Feedback voltage for FB_LDO1, FB_LDO2, FB_LDO3, and FB_LDO4 TPS65051, TPS65054 and TPS65056 only IO Maximum output current for LDO1, LDO2 400 mA Maximum output current for LDO3, LDO4 200 mA I(SC) 1 V LDO1 short-circuit current limit VLDO1 = GND 750 mA LDO2 short-circuit current limit VLDO2 = GND 850 mA LDO3 and LDO4 short-circuit current limit VLDO3 = GND, VLDO4 = GND 420 mA Dropout voltage at LDO1 IO = 400 mA, VINLDO = 3.4 V 400 mV Dropout voltage at LDO2 IO = 400 mA, VINLDO = 1.8 V 280 mV Dropout voltage at LDO3, LDO4 IO = 200 mA, VINLDO = 1.8 V 280 mV Ilkg Leakage current from VinLDOx to VLDOx LDO enabled, VINLDO = 6.5 V, VO = 1 V, at TA = 140°C VO Output voltage accuracy for LDO1, LDO2, LDO3, LDO4 IO = 10 mA -2% 1% Line regulation for LDO1, LDO2, LDO3, LDO4 VINLDO1,2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5V, VINLDO3,4 = VLDO3,4 + 0.5 V (min. 2.5 V) to 6.5V, IO = 10 mA -1% 1% Load regulation for LDO1, LDO2, LDO3, LDO4 IO = 0 mA to 400 mA for LDO1, LDO2 IO = 0 mA to 200 mA for LDO3, LDO4 -1% 1% Regulation time for LDO1, LDO2, LDO3, LDO4 Load change from 10% to 90% 10 µs Power supply rejection ratio f = 10 kHz; IO = 50 mA; VI = VO + 1 V 70 dB PSRR (1) (2) µA 3 Output voltage specification does not include tolerance of external voltage programming resistors. In Power Save Mode, operation is typically entered at IPSM = VI / 32 Ω. Submit Documentation Feedback 5 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 ELECTRICAL CHARACTERISTICS (continued) VCC = VINDCDC1/2 = 3.6 V, EN = VCC, MODE = GND, L = 2.2 µH, CO = 10 µF. TA = -40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted). PARAMETER R(DIS) 6 TEST CONDITIONS MIN TYP MAX UNIT Internal discharge resistor at VLDO1, VLDO2, VLDO3, VLDO4 active when LDO is disabled 350 R Thermal shutdown Increasing junction temperature 140 °C Thermal shutdown hysteresis Decreasing junction temperature 20 °C Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 PIN ASSIGNMENTS VINLDO1 VLDO4 L2 BP AGND VCC VINLDO2 PGND2 VDCDC2 DEFDCDC2 VINLDO3/4 VLDO3 FB3 PGND2 VDCDC2 DEFDCDC2 FB_DCDC1 PGND1 L1 VINDCDC1/2 VLDO2 DEFLDO2 PB_IN GND EN_DCDC1 EN_DCDC2 EN_LDO1 EN_LDO2 VLDO4 VLDO1 FB1 MODE VINLDO3/4 VLDO3 DEFLDO3 BP AGND VCC VINLDO2 VLDO1 DEFLDO1 MODE EN_LDO4 EN_LDO3 RESET FB4 TPS65051 TPS65054 TPS65056 FB2 THRESHOLD HYSTERESIS VINLDO1 L2 FB_DCDC1 PGND1 L1 VINDCDC1/2 PGND2 VDCDC2 DEFDCDC2 EN_DCDC1 EN_DCDC2 EN_LDO1 EN_LDO2 EN_LDO4 EN_LDO3 PB_OUT DEFLDO4 TPS65050 VLDO2 EN_DCDC1 EN_DCDC2 EN_LDO1 EN_LDO2 L2 FB_DCDC1 PGND1 L1 VINDCDC1/2 RSM PACKAGE (TOP VIEW) EN_LDO4 EN_LDO3 RESET DEFLDO4 TPS65052 VINLDO1 VLDO4 VLDO2 DEFLDO2 THRESHOLD HYSTERESIS VINLDO3/4 VLDO3 DEFLDO3 BP AGND VCC VINLDO2 VLDO1 DEFLDO1 MODE TERMINAL FUNCTIONS TERMINAL NAME I/O DESCRIPTION 3 I Power supply for digital and analog circuitry of DCDC1, DCDC2 and LDOs. This pin must be connected to the same voltage supply as VINDCDC1/2. 24 I Input to adjust output voltage of converter 1 between 0.6 V and VI. Connect external resistor divider between VOUT1, this pin, and GND. TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 VCC 3 3 3 3 FB_DCDC1 24 24 24 24 MODE 32 32 32 32 32 I Select between Power Safe Mode and forced PWM Mode for DCDC1 and DCDC2. In Power Safe Mode, PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then the device operates in Power Safe Mode. VINDCDC1/2 21 21 21 21 21 I Input voltage for VDCDC1 and VDCDC2 step-down converter. This must be connected to the same voltage supply as VCC. VDCDC2 18 18 18 18 18 I Feedback voltage sense input, connect directly to the output of converter 2. DEFDCDC2 17 17 17 17 17 I TPS65050 and TPS65051: Feedback pin for converter 2. Connect DEFDCDC2 to the center of the external resistor divider. TPS65052 and TPS65056: Select pin of converter 2 output voltage. High = 1.3 V, Low = 1 V TPS65054: Select pin of converter 2 output voltage. High = 1.05 V, Low = 1.3 V L1 22 22 22 22 22 O Switch pin of converter 1. Connected to Inductor . Submit Documentation Feedback 7 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TERMINAL FUNCTIONS (continued) TERMINAL 8 I/O DESCRIPTION NAME TPS65050 TPS65051 TPS65052 TPS65054 TPS65056 PGND1 23 23 23 23 23 I GND for converter 1 PGND2 19 19 19 19 19 I GND for converter 2 AGND 2 2 2 2 2 I Analog GND, connect to PGND and PowerPad™ L2 20 20 20 20 20 O Switch Pin of converter 2. Connected to Inductor. EN_DCDC1 25 25 25 25 25 I Enable Input for converter 1, active high EN_DCDC2 26 26 26 26 26 I Enable Input for converter 2, active high VINLDO1 29 29 29 29 29 I Input voltage for LDO1 VINLDO2 4 4 4 4 4 I Input voltage for LDO2 VINLDO3/4 11 11 11 11 11 I Input voltage for LDO3 and LDO4 VLDO1 30 30 30 30 30 O Output voltage of LDO1 VLDO2 5 5 5 5 5 O Output voltage of LDO2 VLDO3 10 10 10 10 10 O Output voltage of LDO3 VLDO4 12 12 12 12 12 O Output voltage of LDO4 DEFLDO1 31 -- 31 -- -- I Digital input, used to set the default output voltage of LDO1 to LDO4; LSB FB1 -- 31 -- 31 31 I Feedback input for the external voltage divider. DEFLDO2 6 -- 6 -- -- I Digital input, used to set the default output voltage of LDO1 to LDO4. FB2 -- 6 -- 6 6 I Feedback input for the external voltage divider. DEFLDO3 9 -- 9 -- -- I Digital input, used to set the default output voltage of LDO1 to LDO4. FB3 -- 9 -- 9 9 I Feedback input for the external voltage divider. DEFLDO4 13 -- 13 -- -- I Digital input, used to set the default output voltage of LDO1 to LDO4; MSB FB4 -- 13 -- 13 13 I Feedback input for the external voltage divider. EN_LDO1 27 27 27 27 27 I Enable input for LDO1. Logic high enables the LDO, logic low disables the LDO. EN_LDO2 28 28 28 28 28 I Enable input for LDO2. Logic high enables the LDO, logic low disables the LDO. EN_LDO3 15 15 15 15 15 I Enable input for LDO3. Logic high enables the LDO, logic low disables the LDO. EN_LDO4 16 16 16 16 16 I Enable input for LDO4. Logic high enables the LDO, logic low disables the LDO. THRESHOLD -- 7 7 7 7 I Reset input PB_IN 7 -- -- -- -- I Input for the pushbutton ON-OFF function HYSTERESIS -- 8 8 8 8 I Input for hysteresis on reset threshold GND 8 -- -- -- -- - Connect to GND RESET -- 14 14 14 14 O Open drain active low reset output, 100 ms reset delay time. PB_OUT 14 -- -- -- -- O Open drain output. Active low after the supply voltage (VCC) exceeded the undervoltage lockout threshold. The pin can be toggled pulling PB_IN high. I Input for bypass capacitor for internal reference. BP 1 1 1 1 1 PowerPAD™ -- -- -- -- -- Connect to GND Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 FUNCTIONAL BLOCK DIAGRAM TPS65050 VINDCDC1/2 1W Vbat VCC 10 mF 1 mF 2.2 mH DCDC1 (I/O) L1 EN_DCDC1 ENABLE STEP-DOWN CONVERTER 600 mA MODE DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 FB_DCDC1 PGND1 R1 Cff 10 mF R2 Interface L2 DCDC2 (core) STEP-DOWN CONVERTER 600 mA EN_DCDC2 ENABLE VLDO2 EN_LDO2 ENABLE PGND2 VIN_LDO3/4 VLDO3 ENABLE ENABLE R4 4.7 mF VLDO2 4.7 mF 400-mA LDO VIN 10 mF 400-mA LDO VIN_LDO2 VIN R3 DEFDCDC2 VLDO1 EN_LDO1 ENABLE 2.2 mH VLDO1 VIN_LDO1 VIN VDCDC2 VLDO3 BP EN_LDO3 200-mA LDO EN_LDO4 VLDO4 2.2 mF 0.1 mF VLDO4 2.2 mF 200-mA LDO I/Ovoltage Vbat PB_IN default turned on Flipflop with 32-ms debounce PB_OUT R19 AGND Submit Documentation Feedback 9 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TPS65051 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 2.2 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 1A FB_DCDC1 PGND1 R1 Cff 10 mF R2 MODE L2 DCDC2 (core) ENABLE VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 VDCDC2 2.2 mH R3 DEFDCDC2 PGND2 10 mF R4 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.7 mF R6 VIN ENABLE VIN_LDO2 VLDO2 EN_LDO2 400-mA LDO VLDO2 FB2 R7 4.7 mF R8 VIN ENABLE VIN_LDO3/4 VLDO3 EN_LDO3 200-mA LDO VLDO3 FB3 BP 0.1 mF ENABLE EN_LDO4 VLDO4 200-mA LDO R9 R10 VLDO4 FB4 R11 R12 THRESHOLD RESET RESET HYSTERESIS AGND 10 Submit Documentation Feedback 2.2 mF 2.2 mF I/Ovoltage R19 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TPS65052 VINDCDC1/2 1W Vbat VCC 10 mF 1 mF 3.3 mH DCDC1 (I/O) ENABLE MODE DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 EN_DCDC1 STEP-DOWN CONVERTER 1A L1 FB_DCDC1 Interface L2 DCDC2 (core) 2.2 mH VDCDC2 ENABLE 1 V/1.3 V VIN ENABLE VIN ENABLE VIN ENABLE ENABLE 10 mF PGND1 STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 4.7 mF 400-mA LDO VIN_LDO2 VLDO2 EN_LDO2 VLDO2 4.7 mF 400-mA LDO VIN_LDO3/4 VLDO3 VLDO3 BP EN_LDO3 200-mA LDO EN_LDO4 VLDO4 2.2 mF 0.1 mF VLDO4 2.2 mF 200-mA LDO I/Ovoltage THRESHOLD RESET R19 RESET HYSTERESIS AGND Submit Documentation Feedback 11 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TPS65054 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 2.2 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 600 mA FB_DCDC1 PGND1 R1 Cff 10 mF R2 MODE L2 DCDC2 (core) 2.2 mH VDCDC2 ENABLE 1.3 V/1.05 V VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.7 mF R6 VIN ENABLE VIN_LDO2 VLDO2 EN_LDO2 400-mA LDO VLDO2 FB2 R7 4.7 mF R8 VIN ENABLE VIN_LDO3/4 VLDO3 EN_LDO3 200-mA LDO VLDO3 FB3 BP 0.1 mF ENABLE EN_LDO4 VLDO4 200-mA LDO R9 R10 VLDO4 FB4 R11 R12 THRESHOLD RESET RESET HYSTERESIS AGND 12 Submit Documentation Feedback 2.2 mF 2.2 mF I/Ovoltage R19 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TPS65056 VINDCDC1/2 1W Vbat VCC 22 mF 1 mF 3.3 mH DCDC1 (I/O) ENABLE L1 EN_DCDC1 STEP-DOWN CONVERTER 1A FB_DCDC1 10 mF PGND1 MODE L2 2.2 mH DCDC2 (core) ENABLE 1 V / 1.3 V VIN ENABLE STEP-DOWN CONVERTER 600 mA EN_DCDC2 DEFDCDC2 VDCDC2 10 mF PGND2 VLDO1 VIN_LDO1 VLDO1 EN_LDO1 400-mA LDO FB1 R5 4.7 mF R6 VIN ENABLE VIN_LDO2 VLDO2 EN_LDO2 400-mA LDO VLDO2 FB2 R7 4.7 mF R8 VIN ENABLE VIN_LDO3/4 VLDO3 EN_LDO3 200-mA LDO VLDO3 FB3 BP 0.1 mF ENABLE EN_LDO4 VLDO4 200-mA LDO R9 R10 VLDO4 FB4 R11 R12 THRESHOLD 2.2 mF RESET 2.2 mF I/Ovoltage R19 RESET HYSTERESIS AGND Submit Documentation Feedback 13 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Efficiency converter 1 vs Output current Figure 1 Efficiency converter 2 vs Output current Figure 2 Efficiency converter 1 vs Output current Figure 3 Efficiency converter 2 vs Output current Figure 4 Output voltage ripple PWM/PFM mode = low Figure 5 Output voltage ripple PWM mode = high Figure 6 DCDC1 startup timing Figure 7 LDO1 to LDO4 startup timing Figure 8 DCDC1 load transient response PWM mode = high Figure 9 DCDC1 load transient response PFM mode = low Figure 10 DCDC2 load transient response PWM mode = high Figure 11 DCDC2 load transient response PFM mode = low Figure 12 DCDC1 line transient response Figure 13 DCDC2 line transient response Figure 14 LDO1 load transient response Figure 15 LDO4 load transient response Figure 16 LDO1 line transient response Figure 17 Power supply rejection ratio vs Frequency Figure 18 EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 90 90 80 70 5V 60 4.2 V 50 3.8 V 70 Efficiency − % Efficiency − % 80 3.4 V 40 30 VO = 3.3 V TA = 25oC PWM/PFM Mode 10 50 3.4 V 40 0.1 0.001 0.01 IO − Output Current − A 1 20 10 10 0 0.0001 Figure 1. 14 5V 4.2 V 30 20 0 0.0001 3.8 V 60 VO = 3.3 V TA = 25oC PWM Mode 0.1 0.001 0.01 IO − Output Current − A Figure 2. Submit Documentation Feedback 1 10 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 3.3 V 90 90 80 80 70 3.8 V 60 Efficiency − % 4.2 V 50 5V 40 30 3.3 V 40 4.2 V 20 VO = 1.3 V o TA = 25 C PFM Mode 10 0.1 0.001 0.01 IO − Output Current − A 10 0 0.0001 1 0.1 0.001 0.01 IO − Output Current − A Figure 3. Figure 4. OUTPUT VOLTAGE RIPPLE PWM/PFM MODE = LOW OUTPUT VOLTAGE RIPPLE PWM MODE = HIGH 1 o VI = 4.2 V, TA = 25oC CH1 (VDCDC2 = 1.5 V) CH4 (IL DCDC1 = 600 mA) 200 mA/div 100 mA/div CH2 (VDCDC2 = 1.5 V) CH1 (VDCDC1 = 3.3 V) 20 mV/div VI = 4.2 V, TA = 25 C 20 mV/div CH1 (VDCDC1 = 3.3 V) 20 mV/div 20 mV/div 5V 50 30 20 0 0.0001 3.8 V 60 100 mA/div Efficiency − % 70 VO = 1.3 V TA = 25oC PWM Mode CH3 (IL DCDC2 = 600 mA) CH4 (IL DCDC1 = 80 mA) 200 mA/div CH3 (IL DCDC2 = 80 mA) t − Time = 500 ns/div t − Time = 2 ms/div Figure 5. Figure 6. Submit Documentation Feedback 15 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) LDO1 TO LDO4 STARTUP TIMING VI = 3.6 V EN CH1 (VLDO1) o TA = 25 C Mode = Low 1 V/div 1 V/div 1 V/div CH2 (VLDO2) CH3 (VLDO3) CH3 (VDCDC2 = 1.5 V) CH2 (VDCDC1 = 3.3 V) Load DCDC1 = 600 mA Load DCDC2 = 600 mA 1 V/div 1 V/div CH4 (VLDO4) VI = 3.6 V o TA = 25 C ILDO1/2/3/4 = 100 mA Mode = Low t − Time = 20 ms/div Figure 7. Figure 8. DCDC1 LOAD TRANSIENT RESPONSE DCDC1 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div t − Time = 200 ms/div CH1 (VDCDC1) CH1 (VDCDC1) VI = 4.2 V VI = 4.2 V TA = 25oC Mode = Low TA = 25oC Mode = High CH2 I(DCDC1) VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 60 mA to 540 mA 200 mA/div 200 mA/div CH2 I(DCDC1) t − Time = 100 ms/div t − Time = 100 ms/div Figure 9. 16 VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 60 mA to 540 mA Figure 10. Submit Documentation Feedback 1 V/div CH4 (VLDO1) 1 V/div CH1 (EN) 5 V/div 5 V/div DCDC1 STARTUP TIMING TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) DCDC2 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div DCDC2 LOAD TRANSIENT RESPONSE CH1 (VDCDC2) VI = 3.6 V CH1 (VDCDC2) VI = 3.6 V o TA = 25 C Mode = High TA = 25oC Mode = Low CH2 I(DCDC2) 200 mA/div 200 mA/div CH2 I(DCDC2) VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 60 mA to 540 mA VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 60 mA to 540 mA t − Time = 100 ms/div Figure 11. Figure 12. DCDC1 LINE TRANSIENT RESPONSE DCDC2 LINE TRANSIENT RESPONSE CH1 VIN (VDCDC1) VI = 3.6 V to 4.5 V to 3.6 V o TA = 25 C Mode = High VDCDC1 = 3.3 V ENDCDC1 = High ENDCDC2 = Low Load Current = 600 mA 20 mV/div 20 mV/div CH1 VIN (VDCDC2) 500 mV/div 500 mV/div t − Time = 100 ms/div CH2 (VDCDC1) CH2 (VDCDC2) VI = 3.4 V to 4.4 V to 3.4 V TA = 25oC Mode = High VDCDC2 = 1.5 V ENDCDC1 = Low ENDCDC2 = High Load Current = 600 mA t − Time = 100 ms/div t − Time = 100 ms/div Figure 13. Figure 14. Submit Documentation Feedback 17 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 TYPICAL CHARACTERISTICS (continued) LDO4 LOAD TRANSIENT RESPONSE 50 mV/div 50 mV/div LDO1 LOAD TRANSIENT RESPONSE CH1 (VLDO1) CH1 (VLDO4) VI = 3.6 V VLDO4 = 1.3 V VLDO4 = 20 mA to 180 mA o TA = 25 C VI = 3.6 V o TA = 25 C VLDO1 = 3.3 V VLDO1 = 40 mA to 360 mA CH2 I(LDO4) 200 mA/div 200 mA/div CH2 I(LDO1) t − Time = 100 ms/div t − Time = 100 ms/div Figure 15. Figure 16. LDO1 LINE TRANSIENT RESPONSE POWER SUPPLY REJECTION RATIO vs FREQUENCY 100 90 80 Rejection Ratio − dB 20 mV/div 500 mV/div CH1 VIN (LDO1) CH2 (VLDO1) 70 60 50 40 30 VI = 3.6 V to 4.2 V to 3.6 V o TA = 25 C 20 VLDO1 = 3.3 V VLDO1 = 100 mA Mode = High 10 t − Time = 100 ms/div 0 10 Figure 17. 18 100 100k 10k 1k f − Frequency − Hz Figure 18. Submit Documentation Feedback 1M 10M TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 DETAILED DESCRIPTION Operation The TPS6505x include each two synchronous step-down converters. The converters operate with 2.25-MHz (typical) fixed frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the converters automatically enter Power Save Mode and operate with PFM (Pulse Frequency Modulation). During PWM operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on, and the inductor current ramps up until the current comparator trips, and the control logic turns off the switch. The current limit comparator turns off the switch if the current limit of the P-channel switch is exceeded. After the adaptive dead time, which prevents shoot through current, the N-channel MOSFET rectifier is turned on, and the inductor current ramps down. The next cycle is initiated by the clock signal turning off the N-channel rectifier, and turning on the on the P-channel switch. The two DC/DC converters operate synchronized to each other, with converter 1 as the master. A 180° phase shift between converter 1 and converter 2 decreases the input RMS current. Therefore, smaller input capacitors can be used. DCDC1 Converter The converter 1 output voltage is set by an external resistor divider connected to FB_DCDC1 pin for TPS65050, TPS65051 and TPS65054. For TPS65052, the output voltage is fixed to 3.3 V and this pin needs to be directly connected to the output. See the Application Information section for more details. The maximum output current on DCDC1 is 600 mA for TPS65050 and TPS65054. For TPS65051, TPS65052 and TPS65056, the maximum output current is 1 A. DCDC2 Converter The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter output voltage is selected via the DEFDCDC2 pin. TPS65050 and TPS65051: The output voltage is set with an external resistor divider. Connect the DEFDCDC2 pin to the external resistor divider. TPS65052, TPS65054 and TPS65056: The DEFDCDC2 pin can either be connected to GND, or to VCC. The converter 2 output voltage defaults to: Device DEFDCDC2 = low DEFDCDC2 = high TPS65052 , TPS65056 1V 1.3 V TPS65054 1.3 V 1.05 V Submit Documentation Feedback 19 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Power-Save Mode The Power Save Mode is enabled with the Mode pin set to 0. If the load current decreases, the converters enters Power Save Mode operation automatically. During Power Save Mode, the converters operate with reduced switching frequency in PFM mode, and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step. To optimize the converter efficiency at light load, the average current is monitored. If in PWM mode, the inductor current remains below a certain threshold, then Power Save Mode is entered. The typical threshold is calculated according to Equation 1: VINDCDC I(PFM_enter) = 32 W (1) A. Average output current threshold to enter PFM mode. I(PSMDCDC_leave) = A. VINDCDC 24 W (2) Average output current threshold to leave PFM mode. During the Power Save Mode, the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp), the P-channel switch turns on, and the converter effectively delivers a constant current. If the load is below the delivered current, the output voltage rises until the skip comp threshold is crossed again, then all switching activity ceases, reducing the quiescent current to a minimum until the output voltage has dropped below the threshold. If the load current is greater than the delivered current, the output voltage falls until it crosses the skip comparator low (Skip Comp Low) threshold set to 1% below nominal VO, then Power Save Mode is exited, and the converter returns to PWM mode These control methods reduce the quiescent current to 12 µA per converter, and the switching frequency to a minimum achieving the highest converter efficiency. The PFM mode operates with low output voltage ripple. The ripple depends on the comparator delay, and the size of the output capacitor; increasing capacitor values decreases the output ripple voltage. The Power Save Mode can be disabled by driving the MODE pin high. In forced PWM mode, both converters operate with fixed frequency PWM mode regardless of the load. Dynamic Voltage Positioning This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is activated in Power Save Mode operation when the converter runs in PFM Mode. It provides more headroom for both, the voltage drop at a load step and the voltage increase at a load throw-off. This improves load transient behavior. At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1% higher than the nominal value. In the event of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to -1% below the nominal value and enters PWM mode. During a release from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the N-channel switch. Smooth Increased Load +1% PFM Mode Light Load Fast Load Transient PFM Mode Light Load VOUT_NOM PFM Mode Medium/Heavy Load PFM Mode Medium/Heavy Load -1% COMP_LOW Threshold Figure 19. Dynamic Voltage Positioning 20 Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Soft Start The two converters have an internal soft start circuit that limits the inrush current during start-up. During soft start, the output voltage ramp up is controlled as shown in Figure 20. EN 95% 5% VOUT tStart tRAMP Figure 20. Soft Start 100% Duty Cycle Low Dropout Operation The converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range. (i.e. The minimum input voltage to maintain regulation depends on the load current and output voltage) and can be calculated as: VI (min) = VO (max) + IO (max) x (rDS(on) (max) + RL) (3) with: • IO max = maximum output current plus inductor ripple current • rDS(on) max = maximum P-channel switch rDS(on). • RL = DC resistance of the inductor • VO (max) = nominal output voltage plus maximum output voltage tolerance Undervoltage Lockout The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables all internal circuitry. The undervoltage lockout threshold, sensed at the VCC pin is typically 1.8 V, max 2 V. Mode Selection The MODE pin allows mode selection between forced PWM Mode and power Safe Mode for both converters. Connecting this pin to GND enables the automatic PWM and power save mode operation. The converters operates in fixed frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, maintaining high efficiency over a wide load current range. Submit Documentation Feedback 21 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Pulling the MODE pin high forces both converters to operate constantly in the PWM mode even at light load currents. The advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. In this mode, the efficiency is lower compared to the power save mode during light loads. For additional flexibility, it is possible to switch from power save mode to forced PWM mode during operation. This allows efficient power management by adjusting the operation of the converter to the specific system requirements. Enable To start up each converter independently, the device has a separate enable pin for each DC/DC converter and for each LDO. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, EN_LDO3, EN_LDO4 are set to high, the corresponding converter starts up with soft start as previously described. Pulling the enable pin low forces the device into shutdown, with a shutdown quiescent current as defined in the electrical characteristics. In this mode, the P and N-Channel MOSFETs are turned-off, the and the entire internal control circuitry is switched-off. If disabled, the outputs of the LDOs are pulled low by internal 350Ω resistors, actively discharging the output capacitor. For proper operation, the enable pins must be terminated and must not be left unconnected. RESET The TPS65051, TPS65052, TPS65054 and TPS65056 contain circuitry that can generate a reset pulse for a processor with a 100 ms delay time. The input voltage at a comparator is sensed at an input called threshold. When the voltage exceeds the threshold, the output goes high with a 100-ms delay time. A hysteresis can be defined with an external resistor connected to the hysteresis input. This circuitry is functional as soon as the supply voltage at VCC exceeds the undervoltage lockout threshold. Therefore, the TPS6505x has a shutdown current (all DCDC converters and LDOs are off) of 9 µA in order to supply bandgap and comparator. Vbat HYSTERESIS RESET THRESHOLD + - 100 ms Delay Vref = 1 V Vbat THRESHOLD THRESHOLD - HYSTERESIS Comparator Output (Internal) tNRESET RESET Figure 21. RESET Pulse Circuit 22 Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Push-Button ON-OFF (PB-ON-OFF) The TPS65050 provides a PB-ON-OFF functionality instead of supervising a voltage with the threshold and hysteresis inputs. The output at PB_OUT is held low after voltage is applied at VCC. Only after the input at PB-IN is pulled high once, the output driver at PB_OUT goes to its inactive state, driven high with its external pullup resistor. Further low-high pulses at PB-IN toggles the status of the PB_OUT output, and can be used to shutdown and start the converter with a single push on a button by connecting the PB_OUT output to the enable input of the converters. Vbat PB_IN Debounce 32 ms JKFlipflop Default Low PB_OUT Min Pulse Width 32 ms PB_IN RESPWRON 32 ms Figure 22. Push-Button Circuit Short-Circuit Protection All outputs are short-circuit protected with a maximum output current as defined in the Electrical Characteristics. Thermal Shutdown As soon as the junction temperature, TJ, exceeds 150°C (typically) for the DC/DC converters, the device goes into thermal shutdown. In this mode, the P and N-Channel MOSFETs are turned-off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC/DC converters disables both converters simultaneously. The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be used to power an external voltage never heats up the chip high enough to turn off the DC/DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turns off simultaneously. Submit Documentation Feedback 23 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Low Dropout Voltage Regulators The low dropout voltage regulators are designed to operate well with small ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3 and EN_LDO4 pin. In TPS65050 and TPS65052, the output voltage of the LDOs is set using 4 pins. The DEFLDO1 to DEFLDO4 pins can either be connected to GND or Vbat (VCC) to define a set of output voltages for LDO1 to LDO4 according to table 1. Connecting the DEFLDOx pins to a voltage different from GND or VCC causes increased leakage current into VCC. In TPS65051 and TPS65054, the output voltage of the LDOs is set using external resistor dividers. TPS65050 and TPS65052 default voltage options adjustable with DEFLDO4…DEFLDO1 according to Table 1. Table 1. Default Options DEFLDO1 24 DEFLDO2 DEFLDO3 DEFLDO4 VLDO1 VLDO2 VLDO3 VLDO4 400 mA LDO 400 mA LDO 200 mA LDO 200 mA LDO 1.8 V - 5.5 V Input 1.8 V - 5.5 V Input 1.5 V - 5.5 V Input 1.5 V - 5.5 V Input 0 0 0 0 3.3 V 3.3 V 1.85 V 1.85 V 0 0 0 1 3.3 V 3.3 V 1.5 V 1.5 V 0 0 1 0 3.3 V 2.85 V 2.85 V 2.7 V 0 0 1 1 3.3 V 2.85 V 2.85 V 2.5 V 0 1 0 0 3.3 V 2.85 V 2.85 V 1.85 V 0 1 0 1 3.3 V 2.85 V 1.85 V 1.85 V 0 1 1 0 3.3 V 2.85 V 1.5 V 1.5 V 0 1 1 1 3.3 V 2.85 V 1.5 V 1.3 V 1 0 0 0 3.3 V 2.85 V 1.1 V 1.3 V 1 0 0 1 2.85 V 2.85 V 1.85 V 1.85 V 1 0 1 0 2.7 V 3.3 V 1.2 V 1.2 V 1 0 1 1 2.5 V 3.3 V 1.5 V 1.5 V 1 1 0 0 2.5 V 3.3 V 1.5 V 1.3 V 1 1 0 1 1.85 V 1.85 V 1.35 V 1.35 V 1 1 1 0 1.8 V 2.5 V 3.3 V 2.85 V 1 1 1 1 1.2 V 1.8 V 1.1 V 1.3 V Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 APPLICATION INFORMATION Output Voltage Setting Converter 1 (DCDC1) The output voltage of converter 1 can be set by an external resistor network. The output voltage can be calculated using Equation 4. R1 VO = Vref x 1 + R2 (4) ( ) with an internal reference voltage Vref, 0.6 V . Setting the total resistance of R1 + R2 to less than 1 MΩ is recommended. The resistor network connects to the input of the feedback amplifier, therefore, requiring a small feedforward capacitor in parallel to R1. A typical value of 47 pF is sufficient. Converter 2 (DCDC2) The output voltage of converter 2 can be selected as following: • Adjustable output voltage defined with external resistor network on pin DEFDCDC2. This option is available for TPS65050 and TPS65051. • Two default fixed output voltages selectable by pin DEFDCDC2, see Table 2. This option is available for TPS65052 and TPS65054. Table 2. Default Fixed Output Voltages Converter 2 DEFDCDC2 = low DEFDCDC2 = high TPS65050 -- -- TPS65051 -- -- TPS65052 1V 1.3 V TPS65054 1.3 V 1.05 V TPS65056 1V 1.3 V The adjustable output voltage can be calculated similar to the DCDC1 converter. Setting the total resistance of R3 + R4 to less than 1 MΩ is recommended. Route the DEFDCDC2 line separate from noise sources, such as the inductor or the L2 line. The VDCDC2 line needs to be directly connected to the output capacitor. As the VDCDC2 line is the feedback to the internal amplifier, no feedforward capacitor at R3 is needed. Using an external resistor divider at DEFDCDC2: 1W VCC Vbat 1 mF VDCDC2 L CO ENDCDC2 VO L2 VINDCDC1/2 CI R3 DEFDCDC2 R4 AGND PGND Figure 23. External Resistor Divider Submit Documentation Feedback 25 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 V(DEFDCDC2) = 0.6 V VO = V(DEFDCDC2) x R3 + R4 R4 R3 = R4 x ( VO V(DEFDCDC2) ) - R4 (5) See Table 3 for typical resistor values: Table 3. Typical Resistor Values OUTPUT VOLTAGE R1 R2 NOMINAL VOLTAGE Typical CFF 3.3 V 680 kΩ 150 kΩ 3.32 V 47 pF 3V 510 kΩ 130 kΩ 2.95 V 47 pF 2.85 V 560 kΩ 150 kΩ 2.84 V 47 pF 2.5 V 510 kΩ 160 kΩ 2.51 V 47 pF 1.8 V 300 kΩ 150 kΩ 1.8 v 47 pF 1.6 V 200 kΩ 120 kΩ 1.6 V 47 pF 1.5 V 300 kΩ 200 kΩ 1.5 V 47 pF 1.2 V 330 kΩ 330 kΩ 1.2 V 47 pF Output Filter Design (Inductor and Output Capacitor) Inductor Selection The two converters operate with 2.2-µH output inductor. Larger or smaller inductor values can be used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its dc resistance and saturation current. The dc resistance of the inductance directly influences the efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest efficiency. The minimum inductor value is 1.5 µH, but an output capacitor of 22 µF minimum is needed in this case. For an output voltage above 2.8 V, an inductor value of 3.3 µH minimum is recommended. Lower values result in an increased output voltage ripple in PFM mode. Equation 6 calculates the maximum inductor current under static load conditions. The saturation current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 6. This is recommended because during heavy load transient the inductor current rises above the calculated value. VO 1 VI DIL DIL = VO x IL(max) = IO (max) + 2 L x ¦ (6) with: • f = Switching Frequency (2.25-MHz typical) • L = Inductor Value • ∆ IL= Peak-to-peak inductor ripple current • ILmax = Maximum Inductor current The highest inductor current occurs at maximum VI. Open core inductors have a soft saturation characteristic, and they can normally handle higher inductor currents versus a comparable shielded inductor. A more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. Consideration must be given to the difference in the core material from inductor to inductor which has an impact on the efficiency especially at high switching frequencies. See Table 4 and the typical applications for possible inductors. 26 Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Table 4. Tested Inductors Inductor Type Inductor Value Supplier LPS3010 2.2 µH Coilcraft LPS3015 3.3 µH Coilcraft LPS4012 2.2 µH Coilcraft VLF4012 2.2 µH TDK Output Capacitor Selection The advanced Fast Response voltage mode control scheme of the two converters allow the use of small ceramic capacitors with a value of 22-µF (typical), without having large output voltage undershoots and overshoots during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage ripple, and are recommended. If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. For completeness, the RMS ripple current is calculated as: VO 1 VI 1 x I(RMSCout) = VO x 2 x Ö3 L x ¦ (7) At nominal load current, the inductive converters operate in PWM mode, and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor: VO 1 VI 1 x + ESR DVO = VO x 8 x CO x ¦ L x ¦ ( ) (8) Where the highest output voltage ripple occurs at the highest input voltage VI. At light load currents, the converters operate in Power Save Mode and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage. Input Capacitor Selection Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. The converters need a ceramic input capacitor of 10 µF. The input capacitor can be increased without any limit for better input voltage filtering. Table 5. Possible Capacitors Capacitor Value Size Supplier Type 2.2 µF 0805 TDK C2012X5R0J226MT Ceramic 2.2 µF 0805 Taiyo Yuden JMK212BJ226MG Ceramic 10 µF 0805 Taiyo Yuden JMK212BJ106M Ceramic 10 µF 0805 TDK C2012X5R0J106M Ceramic 10 µF 0603 Taiyo Yuden JMK107BJ106MA Ceramic Submit Documentation Feedback 27 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 Low Drop Out Voltage Regulators (LDOs) The output voltage of all 4 LDOs in TPS65051, TPS65054 and TPS65056 are set by an external resistor network. The output voltage is calculated using Equation 9: R5 VO = Vref x 1 + R6 (9) ( ) with an internal reference voltage, Vref, 1 V (typical) Setting the total resistance of R5 + R6 to less than 1 MΩ is recommended. Typically, there is no feedforward capacitor needed at the voltage dividers for the LDOs. VO = V(FB_LDOs) x R5 + R6 R6 R5 = R6 x ( VO V(FB_LDOs) ) - R6 (10) Typical resistor values: Table 6. Typical Resistor Values OUTPUT VOLTAGE R5 R6 NOMINAL VOLTAGE 3.3 V 300 kΩ 130 kΩ 3.31 V 3V 300 kΩ 150 kΩ 3V 2.85 V 240 kΩ 130 kΩ 2.85 V 2.8 V 260 kΩ 200 kΩ 2.8 V 2.5 V 300 kΩ 200 kΩ 2.5 V 1.8 V 240 kΩ 300 kΩ 1.8 v 1.5 V 150 kΩ 300 kΩ 1.5 V 1.3 V 36 kΩ 120 kΩ 1.3 V 1.2 V 100 kΩ 510 kΩ 1.19 V 1.1 V 33 kΩ 330 kΩ 1.1 V LAYOUT CONSIDERATIONS Application Circuits PB-ONOFF and Sequencing The PB-ONOFF output can be used to enable one or several converters. After power up, the PB_OUT pin is low, and pulls down the enable pins connected to PB_OUT; EN_DCDC1, and EN_LDO1 in Figure 24. When PB_IN is pulled to VCC for longer than 32 ms, the PB_OUT pin is turned off, hence the enable pins pulled high using a pull-up resistor to VCC. This enables the DCDC1 converter and LDO1. The output voltage of DCDC1 (VOUT1) is used as the enable signal for DCDC2 and LDO2 to LDO4. LDO1 with its output voltage of 3.3 V and LDO2 for an output voltage of 2.5 V are powered from the battery (V(bat)) directly. To save power, the input voltage for the lower voltage rails at LDO3 and LDO4 are derived from the output of the step-down converters, keeping the voltage drop at the LDOs low to increase efficiency. As LDO3 and LDO4 are powered from the output of DCDC1, the total output current on VOUT1, LDO3 and LDO4 must not exceed the maximum rating of DCDC1. Figure 25 shows the power up timing for this application. 28 Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 LAYOUT CONSIDERATIONS (continued) 1W Vbat VINDCDC1/2 VCC Vbat 10 mF 1 mF 2.2 mH L1 GND GND GND Vbat Vbat FB_DCDC1 MODE Vout1 = 2.85 V 10 mF DEFLDO1 DEFLDO2 DEFLDO3 DEFLDO4 PGND1 R2 2.2 mH TPS65050 Vbat Vbat Cff R1 L2 Vout2 = 1.575 V VDCDC2 PB_IN R3 DEFDCDC2 PGND2 PB_OUT VLDO1 10 mF R4 VLDO1 = 3.3 V 4.7 mF EN_DCDC1 EN_LDO1 VLDO2 VDCDC1 EN_DCDC2 VLDO2 = 2.5 V 4.7 mF EN_LDO2 VLDO3 EN_LDO3 VLDO3 = 1.5 V 2.2 mF EN_LDO4 Vbat Vbat VIN_LDO1 VIN_LDO2 Vout1 VIN_LDO3/4 VLDO4 BP AGND VLDO4 = 1.3 V 2.2 mF 0.1 mF Figure 24. PB_ON/OFF Circuit Submit Documentation Feedback 29 TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 LAYOUT CONSIDERATIONS (continued) Vbat PB_IN 32 ms EN_DCDC1 EN_LDO1 Vout1 32 ms 1.2V VLDO1 170 ms EN_DCDC2 EN_LDO3 EN_LDO4 EN_LDO2 Vout2 170 ms VLDO2 VLDO3 VLDO4 Figure 25. Power Up Timing RESET TPS65051, TPS65052, TPS65054 and TPS65056 contain a comparator that are used to supervise a voltage connected to an external voltage divider, and generate a reset signal if the voltage is lower than the threshold. The rising edge is delayed by 100 ms at the open drain RESET output. The values for the external resistors R3 to R5 are calculated as follows: VL = lower voltage threshold VH = higher voltage threshold VREF = reference voltage (1 V) Example: • VL = 3.3 V • VH = 3.4 V Set R5 = 100 kΩ → R3 + R4 = 240 kΩ → R4 = 3.03 kΩ → R3 = 237 kΩ 30 Submit Documentation Feedback TPS65050, TPS65051, TPS65052 TPS65054, TPS65056 www.ti.com SLVS710 – JANUARY 2007 LAYOUT CONSIDERATIONS (continued) ( R3 + R4 = R5 x VH Vref ) - 1 VH - VL R4 = R5 x VL 1W Vbat (11) VINDCDC1/2 VCC 2.2 mH 2.2 mH 1 mF L1 FB_DCDC1 R1 Cff Vout1 = 2.85 V 10 mF PGND1 R2 TPS65051 L2 VDCDC2 Vbat Vout1 R3 R4 1 MW 2.2 mH R3 DEFDCDC2 HYSTERESIS PGND2 THRESHOLD VLDO1 R5 10 mF R4 R5 FB1 Vout2 = 1.575 V VLDO1 = 3.3 V 4.7 mF RESET R6 Vbat VLDO2 EN_DCDC1 R7 FB2 EN_DCDC2 VLDO2 = 1.8 V 4.7 mF R8 EN_LDO1 EN_LDO2 VLDO3 EN_LDO3 Vbat Vbat Vout1 Vbat R9 FB3 EN_LDO4 BP VIN_LDO1 VIN_LDO2 VIN_LDO3/4 VLDO3 = 1.2 V 2.2 mF R10 0.1 mF VLDO4 MODE FB4 AGND R11 VLDO4 = 1.3 V 2.2 mF R12 Figure 26. RESET Circuit Submit Documentation Feedback 31 www.ti.com 40 WWW.TI.COM PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS65050RSMR ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65050RSMRG4 ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65050RSMT ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65050RSMTG4 ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65051RSMR ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65051RSMRG4 ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65051RSMT ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65051RSMTG4 ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65052RSMR ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65052RSMRG4 ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65052RSMT ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65052RSMTG4 ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65054RSMR ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65054RSMRG4 ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65054RSMT ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65054RSMTG4 ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65056RSMR ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65056RSMRG4 ACTIVE QFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65056RSMT ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS65056RSMTG4 ACTIVE QFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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