STMICROELECTRONICS TDA7491LP13TR

TDA7491LP
2 x 5-watt dual BTL class-D audio amplifier
Features
■
5 W + 5 W continuous output power:
RL = 8 Ω, THD = 10% at VCC = 9 V
■
5 W + 5 W continuous output power:
RL = 4 Ω, THD = 10% at VCC = 6.6 V
■
Wide range single supply operation (5 V - 14 V)
■
High efficiency (η = 90%)
■
Four selectable, fixed gain settings of
nominally 20 dB, 26 dB, 30 dB and 32 dB
■
Differential inputs minimize common-mode
noise
■
Filterless operation
■
No ‘pop’ at turn-on/off
■
Standby and mute features
■
Short-circuit protection
■
Thermal overload protection
■
Externally synchronizable
PowerSSO-36 with
exposed pad down
Description
The TDA7491LP is a dual BTL class-D audio
amplifier with single power supply designed for
LCD TVs and monitors.
Thanks to the high efficiency and
exposed-pad-down (EPD) package no separate
heatsink is required.
Furthermore, the filterless operation allows a
reduction in the external component count.
The TDA7491LP is pin-to-pin compatible with the
TDA7491P and TDA7491HV.
Table 1.
Device summary
Order code
Operating temperature
Package
Packaging
TDA7491LP
-40 to 85 °C
PowerSSO-36 EPD
Tube
TDA7491LP13TR
-40 to 85 °C
PowerSSO-36 EPD
Tape and reel
March 2011
Doc ID 13541 Rev 5
1/37
www.st.com
37
Contents
TDA7491LP
Contents
1
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
4
5
2.1
Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
With 4-Ω load at VCC = 6.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
With 8-Ω load at VCC = 9 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3
Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4
Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6
6
2/37
5.5.1
Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5.2
Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6.1
Reconstruction low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.6.2
Filterless modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.7
Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.8
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.9
Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.10
Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 13541 Rev 5
TDA7491LP
7
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 13541 Rev 5
3/37
List of tables
TDA7491LP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
4/37
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-36 EPD dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 13541 Rev 5
TDA7491LP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Internal block diagram (one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connection (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
THD vs. output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
THD vs. output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power supply rejection ratio vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power dissipation and efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Attenuation vs. voltage on pin MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current consumption vs. voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Attenuation vs. voltage on pin STBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD vs. output power (1 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
THD vs. output power (100 Hz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FFT (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
FFT (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power supply rejection ratio vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power dissipation and efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Applications circuit for class-D amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Turn-on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Unipolar PWM output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Typical LC filter for an 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Typical LC filter for a 4-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Filterless application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power derating curves for PCB used as heatsink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Test board (TDA7491LP) layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSSO-36 EPD outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 13541 Rev 5
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Device block diagram
1
TDA7491LP
Device block diagram
Figure 1 shows the block diagram of one of the two identical channels of the TDA7491LP.
Figure 1.
6/37
Internal block diagram (one channel only)
Doc ID 13541 Rev 5
TDA7491LP
Pin description
2
Pin description
2.1
Pin out
Figure 2.
Pin connection (top view, PCB view)
SUB_GND
1
36
VSS
OUTPB
2
35
SVCC
OUTPB
3
34
VREF
PGNDB
4
33
INNB
PGNDB
5
32
INPB
PVCCB
6
31
GAIN1
PVCCB
7
30
GAIN0
OUTNB
8
29
SVR
OUTNB
9
28
DIAG
OUTNA
10
27
SGND
OUTNA
11
26
VDDS
PVCCA
12
25
SYNCLK
PVCCA
13
24
ROSC
23
INNA
22
INPA
EP
exposed pad down
Connect to ground
PGNDA
14
PGNDA
15
OUTPA
16
21
MUTE
OUTPA
17
20
STBY
PGND
18
19
VDDPW
Doc ID 13541 Rev 5
7/37
Pin description
2.2
TDA7491LP
Pin list
Table 2.
Pin description list
Number
8/37
Name
Type
Description
1
SUB_GND
POWER
Connect to the frame
2,3
OUTPB
OUT
Positive PWM output for right channel
4,5
PGNDB
POWER
Power stage ground for right channel
6,7
PVCCB
POWER
Power supply for right channel
8,9
OUTNB
OUT
Negative PWM output for right channel
10,11
OUTNA
OUT
Negative PWM output for left channel
12,13
PVCCA
POWER
Power supply for left channel
14,15
PGNDA
POWER
Power stage ground for left channel
16,17
OUTPA
OUT
Positive PWM output for left channel
18
PGND
POWER
Power stage ground
19
VDDPW
OUT
3.3-V (nominal) regulator output referred to ground for power
stage
20
STBY
INPUT
Standby mode control
21
MUTE
INPUT
Mute mode control
22
INPA
INPUT
Positive differential input of left channel
23
INNA
INPUT
Negative differential input of left channel
24
ROSC
OUT
Master oscillator frequency-setting pin
25
SYNCLCK
IN/OUT
Clock in/out for external oscillator
26
VDDS
OUT
3.3-V (nominal) regulator output referred to ground for signal
blocks
27
SGND
POWER
Signal ground
28
DIAG
OUT
Open-drain diagnostic output
29
SVR
OUT
Supply voltage rejection
30
GAIN0
INPUT
Gain setting input 1
31
GAIN1
INPUT
Gain setting input 2
32
INPB
INPUT
Positive differential input of right channel
33
INNB
INPUT
Negative differential input of right channel
34
VREF
OUT
Half VDDS (nominal) referred to ground
35
SVCC
POWER
Signal power supply
36
VSS
OUT
3.3-V (nominal) regulator output referred to power supply
-
EP
-
Exposed pad for ground-plane heatsink, to be connected to
GND
Doc ID 13541 Rev 5
TDA7491LP
Electrical specifications
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol
3.2
Parameter
Value
Unit
VCC
DC supply voltage
18
V
VI
Voltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN0, GAIN1
-0.3 to 3.6
V
Top
Operating temperature
-40 to 85
°C
Tj
Operating junction temperature
-40 to 150
°C
Tstg
Storage temperature
-40 to 150
°C
Thermal data
Refer also to Section 5.9: Heatsink requirements on page 32.
Table 4.
Thermal data
Symbol
Parameter
Min
Typ
Max
Rth j-case
Thermal resistance, junction to case
-
2
3
Rth j-amb
Thermal resistance, junction to ambient
-
24
-
Unit
°C/W
Doc ID 13541 Rev 5
9/37
Electrical specifications
3.3
TDA7491LP
Electrical specifications
Unless otherwise stated, the results in Table 5 below are given for the conditions: VCC = 9 V,
RL (load) = 8Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 20 dB, and Tamb = 25 °C.
Table 5.
Electrical specifications
Symbol
Condition
Min
Typ
Max
Unit
VCC
Supply voltage
-
5
-
14
V
Iq
Total quiescent current
Without LC filter
-
26
35
mA
IqSTBY
Quiescent current in standby
-
-
-
10
µA
Play mode
-100
-
100
mV
VOS
Output offset voltage
Mute mode
-60
-
60
mV
IOCP
Overcurrent protection threshold RL = 0 Ω
3
-
-
A
Tj
Junction temperature at thermal
shutdown
-
-
150
-
°C
Ri
Input resistance
Differential input
54
68
-
kΩ
VUVP
Undervoltage protection
threshold
-
-
-
4.5
V
High side
-
0.2
-
RdsON
Power transistor on resistance
Low side
-
0.2
-
THD = 10%
-
5.0
-
Po
Output power
THD = 1%
-
4.0
-
RL = 4 Ω, THD = 10%,
VCC = 6.6 V
-
5.0
-
RL = 4 Ω, THD = 1%,
VCC = 6.6 V
-
4.0
-
Po
Ω
W
Output power
W
PD
Dissipated power
Po = 5 W + 5 W,
THD = 10%
-
1.0
-
W
η
Efficiency
Po = 5 W + 5 W,
RL = 8 Ω, THD = 10%,
VCC = 9 V
-
90
-
%
THD
Total harmonic distortion
Po = 1 W
-
0.1
-
%
GAIN0 = L, GAIN1 = L
18
20
22
GAIN0 = L, GAIN1 = H
24
26
28
GAIN0 = H, GAIN1 = L
28
30
32
GAIN0 = H, GAIN1 = H
30
32
34
GV
10/37
Parameter
Closed loop gain
dB
ΔGV
Gain matching
-
-1
-
1
dB
CT
Crosstalk
f = 1 kHz, Po = 1 W
-
70
-
dB
15
-
Total input noise
A Curve, GV = 20 dB
-
eN
f = 22 Hz to 22 kHz
-
20
-
Doc ID 13541 Rev 5
µV
TDA7491LP
Electrical specifications
Table 5.
Symbol
Electrical specifications (continued)
Parameter
Condition
Min
Typ
Max
Unit
SVRR
Supply voltage rejection ratio
fr = 100 Hz, Vr = 1 Vpp,
CSVR = 10 µF
-
50
-
dB
Tr, Tf
Rise and fall times
-
-
40
-
ns
fSW
Switching frequency
Internal oscillator,
master mode
290
320
350
kHz
fSWR
Switching frequency range
(1)
250
-
400
kHz
VinH
Digital input high (H)
2.3
-
-
VinL
Digital input low (L)
-
-
0.8
AMUTE
Mute attenuation
-
80
-
VMUTE = low,
VSTBY = high
Function
Standby, mute and play modes
mode
V
dB
VSTBY < 0.5 V
VMUTE = X
Standby
-
VSTBY > 2.9 V
VMUTE < 0.8 V
Mute
-
VSTBY > 2.9 V
VMUTE > 2.9 V
Play
-
1. Refer to Section 5.5: Internal and external clocks on page 27.
Doc ID 13541 Rev 5
11/37
Characterization curves
4
TDA7491LP
Characterization curves
The following characterization curves were made using the TDA7491LP demo board. The
LC filter for the 4-Ω load uses components of 15 µH and 470 nF and that for the 8-Ω load
uses 33 µH and 220 nF.
4.1
With 4-Ω load at VCC = 6.6 V
Figure 3.
Output power vs. supply voltage
6
Test Condition :
Vcc = 5~6.6V
5
THD =10%
4
THD =1%
RL = 4 ohm,
Po ( W )
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25°C
3
2
Specification Limit:
Typical:
Vs =6.6V, Rl = 4 ohm
Po =5W @THD =10%
Po =3.7W @THD =1%
1
0
5
5. 4
5. 8
6. 2
Supply voltage (V)
Figure 4.
THD vs. output power (1 kHz)
THD(%)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25°C
Specification Limit:
Typical:
Po =5W @ THD =10%
Po per Channel (W)
12/37
Doc ID 13541 Rev 5
6. 6
TDA7491LP
Characterization curves
Figure 5.
THD vs. output power (100 Hz)
THD(%)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f =100Hz,
Gv =30dB,
Tamb =25°C
Specification Limit:
Typical:
Po =5W @ THD =10%
Po per Channel (W)
Figure 6.
THD vs. frequency
THD(%)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25°C
Specification Limit:
Typical: THD<0.5%
Frequency (Hz)
Doc ID 13541 Rev 5
13/37
Characterization curves
Figure 7.
TDA7491LP
Frequency response
Amplitude (dB)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Po =1W
Tamb =25°C
Cin = 1uF
Specification Limit:
Max: +/-3dB
@20Hz to 20kHz
Frequency (Hz)
Figure 8.
Crosstalk vs. frequency
Crosstalk (dB)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f = 1kHz,
Gv=30dB,
Po=1W
Tamb=25°C
Specification Limit:
Typical: >50dB (@ f =1kHz)
Frequency (Hz)
14/37
Doc ID 13541 Rev 5
TDA7491LP
Characterization curves
Figure 9.
FFT (0 dB)
FFT (dB)
FFT (0 dB)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f = 1kHz,
Gv =30dB,
Po =1W
Tamb =25°C
Specification Limit:
Typical: >60dB
for the harmonic
frequency
Frequency (Hz)
Figure 10. FFT (-60 dB)
FFT (dB)
FFT (-60 dB)
Test Condition:
Vcc =6.6V,
RL= 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Po = -60dB (@ 1W =0dB)
Tamb =25°C
Specification Limit:
Typical: > 90dB
for the harmonic
frequency
Frequency (Hz)
Doc ID 13541 Rev 5
15/37
Characterization curves
TDA7491LP
Figure 11. Power supply rejection ratio vs. frequency
PSRR (dB)
Test Condition :
Vcc = 6.6V,
RL = 4 ohm,
Rosc =39kΩ, Cosc =100nF,
Vin=0,
Gv =30dB,
Tamb =25°C
Vr = 500mVrms
Fr = 100Hz
Frequency (Hz)
Figure 12. Power dissipation and efficiency vs. output power
Test Condition :
90
2
80
1. 8
Vcc = 6.6V,
1. 6
70
Gv =30dB,
Tamb =25°C
Efficiency (%)
Rosc =39kΩ, Cosc =100nF,
1. 4
60
1. 2
50
1
40
0. 8
30
0. 6
20
0. 4
10
0. 2
0
0
0
1
2
3
Po per channel (W)
16/37
Doc ID 13541 Rev 5
4
5
Pd (W)
RL = 4 ohm,
TDA7491LP
Characterization curves
Figure 13. Attenuation vs. voltage on pin MUTE
Test Condition :
RL = 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f=1kHz,
[email protected]=1kHz, Po=1w,
Gv =30dB,
Tamb =25°C
Attenuation (dB)
Vcc = 6.6V,
5
0
-5
- 10
- 15
- 20
- 25
- 30
- 35
- 40
- 45
- 50
- 55
- 60
- 65
- 70
- 75
- 80
0
0. 5
1
1. 5
Vmute (V)
2
2. 5
3
3. 5
3
3. 5
Figure 14. Current consumption vs. voltage on pin STBY
0. 025
Test Condition :
Vcc = 6.6V,
0. 02
RL = 4 ohm,
Rosc =39kΩ, Cosc =100nF,
Gv =30dB,
Tamb =25°C
Iq (A)
Vin=0,
0. 015
0. 01
0. 005
0
0
0. 5
1
1. 5
2
2. 5
Vstby (V)
Doc ID 13541 Rev 5
17/37
Characterization curves
TDA7491LP
Figure 15. Attenuation vs. voltage on pin STBY
10
0
Test Condition :
RL = 4 ohm,
Rosc =39kΩ, Cosc =100nF,
f=1kHz,
[email protected]=1kHz, Po=1w,
Gv =30dB,
Tamb =25°C
Attenuation (dB)
Vcc = 6.6V,
- 10
- 20
- 30
- 40
- 50
- 60
- 70
- 80
- 90
0
18/37
0. 5
1
Doc ID 13541 Rev 5
1. 5
2
Vstby (V)
2. 5
3
3. 5
TDA7491LP
With 8-Ω load at VCC = 9 V
Figure 16. Output power vs. supply voltage
Test Condition :
Vcc = 5~9V,
RL = 8 ohm,
Rosc =39kΩ, Cosc =100nF,
f =1kHz,
Gv =30dB,
Tamb =25°C
Specification Limit:
Typical:
Vs =9V,Rl = 8 ohm
Output power (W)
4.2
Characterization curves
Po =5W @THD =10%
Po =4W @THD =1%
6
5. 5
5
4. 5
4
3. 5
3
2. 5
2
1. 5
1
0. 5
0
THD =10%
Rl =8 ohm
f =1kHz
THD =1%
5
6
7
8
9
Supply voltage (V)
Figure 17. THD vs. output power (1 kHz)
THD (%)
10
Test Condition:
5
Vcc =9V,
RL= 8 ohm,
2
Rosc =39kΩ, Cosc =100nF,
1
f =1kHz,
0.5
Gv =30dB,
Tamb =25°C
0.2
0.1
Specification Limit:
0.05
Typical:
Po =5W @ THD =10%
0.02
0.01
100m
200m
300m 400m
600m 800m 1
2
3
4
5
6
Output Power (W)
Doc ID 13541 Rev 5
19/37
Characterization curves
TDA7491LP
Figure 18. THD vs. output power (100 Hz)
THD (%)
10
Test Condition:
Vcc =9V,
5
2
RL= 8 ohm,
Rosc =39kΩ, Cosc =100nF,
f =100Hz,
Gv =30dB,
1
0.5
0.2
Tamb =25°C
0.1
Specification Limit:
Typical:
Po =5W @ THD =10%
0.05
0.02
0.01
0.005
100m
200m
300m 400m
600m 800m 1
2
3
4
5
6
Output Power (W)
Figure 19. THD vs. frequency
THD (%)
1
Test Condition:
Vcc =9V,
0.5
RL= 8 ohm,
Rosc =39kΩ, Cosc =100nF,
0.2
f =1kHz,
0.1
Gv =30dB,
Po =1W
0.05
Tamb =25°C
0.02
Specification Limit:
0.01
Typical: THD<0.5%
0.005
20
50
100
200
500
1k
Frequency (Hz)
20/37
Doc ID 13541 Rev 5
2k
5k
10k
20k
TDA7491LP
Characterization curves
Figure 20. Frequency response
Ampl (dB)
+2
Test Condition:
Vcc =9V,
+1
RL= 8 ohm,
Rosc =39kΩ, Cosc =100nF,
-0
f =1kHz,
-1
Gv =30dB,
Po =1W
-2
Tamb =25°C
-3
Specification Limit:
Max: +/-3dB
-4
@20Hz to 20kHz
-5
10
20
50
100
200
500
1k
2k
5k
10k
30k
Frequency (Hz)
Figure 21. Crosstalk vs. frequency
Crosstalk (dB)
-60
Test Condition:
-65
Vcc =9V,
-70
RL= 8 ohm,
-75
Rosc =39kΩ, Cosc =100nF,
-80
f = 1kHz,
-85
Gv=30dB,
-90
Po=1W
Tamb=25°C
-95
-100
-105
Specification Limit:
-110
Typical: >50dB (@ f =1kHz)
-115
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency (Hz)
Doc ID 13541 Rev 5
21/37
Characterization curves
TDA7491LP
Figure 22. FFT (0 dB)
FFT (0 dB)
FFT (dB)
+10
+0
Test Condition:
-10
Vcc =9V,
-20
RL= 8 ohm,
-30
Rosc =39kΩ, Cosc =100nF,
-40
-50
f = 1kHz,
Gv =30dB,
Po =1W
Tamb =25°C
-60
-70
-80
-90
-100
-110
Specification Limit:
Typical: >60dB
for the harmonic
frequency
-120
-130
-140
-150
20
50
100
200
500
1k
2k
5k
10k
20k
2k
5k
10k
20k
Frequency (Hz)
Figure 23. FFT (-60 dB)
FFT (dB)
FFT (-60 dB)
+0
Test Condition:
-10
Vcc =9V,
-20
RL= 8 ohm,
-30
Rosc =39kΩ, Cosc =100nF,
-40
f =1kHz,
-50
-60
Gv =30dB,
Po = -60dB (@ 1W =0dB)
Tamb =25°C
-70
-80
-90
-100
Specification Limit:
-110
Typical: > 90dB
-120
for the harmonic
frequency
-130
-140
-150
20
50
100
200
500
1k
Frequency (Hz)
22/37
Doc ID 13541 Rev 5
TDA7491LP
Characterization curves
Figure 24. Power supply rejection ratio vs. frequency
Test Condition :
Vcc = 9V,
RL = 8 ohm,
Rosc =39kΩ, Cosc =100nF,
Ripple frequency=100Hz
Vin=0,
Ripple voltage=500mV
Gv =30dB,
Tamb =25°C
Figure 25. Power dissipation and efficiency vs. output power
90
Vcc = 9V,
80
Rosc =39kΩ, Cosc =100nF,
Vin=0,
Gv =30dB,
Tamb =25°C
Efficiency (%)
RL = 8 ohm,
2. 5
2
70
60
1. 5
50
40
1
Vcc=9V
30
Rload=8ohm
20
Gain=30dB
10
f=1kHz
0. 5
Power dissipation (W)
Test Condition :
0
0
0
1
2
3
4
5
Output power per channel (W)
Doc ID 13541 Rev 5
23/37
Applications information
TDA7491LP
5
Applications information
5.1
Applications circuit
Figure 26. Applications circuit for class-D amplifier
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TDA7491LP
5.2
Applications information
Mode selection
The three operating modes, defined below, of the TDA7491LP are set by the two inputs
STBY (pin 20) and MUTE (pin 21) as shown in Table 6.
●
Standby mode: all circuits are turned off, very low current consumption.
●
Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
●
Play mode: the amplifiers are active.
The protection functions of the TDA7491LP are implemented by pulling down the voltages of
the STBY and MUTE inputs shown in Figure 27. The input current of the corresponding pins
must be limited to 200 µA.
Table 6.
Mode settings
Mode
Voltage level on pin STBY
L (1)
Standby
Mute
H
Play
H
Voltage level on pin MUTE
X (don’t care)
(1)
L
H
1. Refer to VSTBY and VMUTE in Table 5: Electrical specifications on page 10 for the drive levels for L and H
Figure 27. Standby and mute circuits
Standby
STBY
3.3 V
0V
R2
30 kΩ
C7
2.2 µF
R4
30 kΩ
C15
2.2 µF
Mute
MUTE
3.3 V
0V
TDA7491LP
Figure 28. Turn-on/off sequence for minimizing speaker “pop”
Doc ID 13541 Rev 5
25/37
Applications information
5.3
TDA7491LP
Gain setting
The gain of the TDA7491LP is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin 31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
Table 7.
Gain settings
Voltage level on pin GAIN0
Voltage level on pin GAIN1
Nominal gain, Gv (dB)
L(1)
H(1)
20
L
H
26
H
L
30
H
H
32
1. Refer to VinL and VinH in Table 5: Electrical specifications on page 10 for the drive levels for L and H
5.4
Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 68 kΩ (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 29. For Ci = 220 nF the high-pass filter cut-off frequency is below 20 Hz:
fc = 1 / (2 * π * Ri * Ci)
Figure 29. Device input circuit and frequency response
Rf
Input
signal
26/37
Ci
Input
pin
Ri
Doc ID 13541 Rev 5
TDA7491LP
5.5
Applications information
Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7491LP as master clock, while the other devices are in slave mode, that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
5.5.1
Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, ROSC, connected to pin ROSC:
fSW = 106 / ((16 * ROSC + 182) * 4) kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin, whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given
below in Table 8.
5.5.2
Slave mode (external clock)
In order to accept an external clock input, pin ROSC must be left open, that is, floating. This
forces pin SYNCLK to be internally configured as an input as given in Table 8.
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Table 8.
How to set up SYNCLK
Mode
ROSC
SYNCLK
Master
ROSC < 60 kΩ
Output
Slave
Floating (not connected)
Input
Figure 30. Master and slave connection
Master
Slave
TDA7491LP
TDA7491LP
ROSC
SYNCLK
Output
Cosc
100 nF
SYNCLK
ROSC
Input
Rosc
39 kΩ
Doc ID 13541 Rev 5
27/37
Applications information
5.6
TDA7491LP
Modulation
The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM).
The differential output voltages change between 0 V and +VCC and between 0 V and -VCC.
This is in contrast to the traditional bipolar PWM outputs which change between +VCC
and -VCC.
An advantage of this scheme is that it effectively doubles the switching frequency of the
differential output waveform on the load then reducing the current ripple accordingly. The
OUTP and OUTN are in the same phase almost overlapped when the input is zero under
this condition, then the switching current is low and the related losses in the load are low. In
practice, a short delay is introduced between these two outputs in order to avoid the BTL
outputs switching simultaneously when the input is zero.
Figure 31 shows the resulting differential output voltage and current when a positive, zero
and negative input signal is applied. The resulting differential voltage on the load has a
double frequency with respect to outputs OUTP and OUTN then resulting in reduced current
ripple.
Figure 31. Unipolar PWM output
INP
INN
OUTP
OUTN
Differential
OUT
28/37
Doc ID 13541 Rev 5
TDA7491LP
5.6.1
Applications information
Reconstruction low-pass filter
Standard applications use a low-pass filter before the speaker. The cut-off frequency should
be higher than 22 kHz and much lower than the output switching frequency. It is necessary
to choose the L-C component values depending on the loud speaker impedance. Some
typical values, which give a cut-off frequency of 27 kHz, are shown in Figure 32 and
Figure 33 below.
Figure 32. Typical LC filter for an 8-Ω speaker
Figure 33. Typical LC filter for a 4-Ω speaker
5.6.2
Filterless modulation
TDA7491LP can be used without a filter at the IC outputs, because the frequency of the
TDA7491LP output is beyond the audio frequency, the audio signal can be recovered by the
inherent inductance of the speaker and natural filter of the human ear.
The reconstruction of the audio signal on the load is usually achieved using a complete LC
filter (such as a Butterworth) solution that guarantees good audio performance, high
efficiency and EMI suppression. The LC component values should be computed by
considering the target audio band and the PWM switching frequency. The cut-off frequency
must lie well below the switching frequency and above the upper audio frequency. In
particular, the following schematic gives a guideline for a cut-off frequency of about 30 kHz
for both 6- and 8-Ω speakers.
Thanks to its advanced modulation approach, aimed to improve both driving efficiency and
radiating emissions, the device is even able to drive a load with a very low component count.
With this cost-saving filtering scheme the TDA7491P complies with the EMI specifications
FCC class B. Figure 34 on page 30 shows the simplified schematic adopted for the test and
the relevant emission curve at full output power.
Doc ID 13541 Rev 5
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Applications information
TDA7491LP
Emission tests have been performed with a 1-m length of twisted speaker wire with ferrite
beads. Changing the type of the ferrite bead requires care due to factors such as its
effectiveness in the EMC frequency range and impedance stability over the rated current
range. An output snubber network further improves the emissions and this should be tuned
according to the actual PCB, layout and component characteristics.
Figure 34. Filterless application schematic
AM045140v1
30/37
Doc ID 13541 Rev 5
TDA7491LP
5.7
Applications information
Protection functions
The TDA7491LP is fully protected against undervoltages, overcurrents and thermal
overloads as explained here.
Undervoltage protection (UVP)
If the supply voltage drops below the value of VUVP given in Table 5: Electrical specifications
on page 10 the undervoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage recovers the device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value of IOCP given in Table 5: Electrical specifications on
page 10 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, TOC, is determined
by the R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominal), the device goes to mute mode and
the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature reaches the value for Tj given in Table 5: Electrical specifications on page 10
the device shuts down and the output is forced to the high impedance state. When the
device cools sufficiently the device restarts.
5.8
Diagnostic output
The output pin DIAG is an open drain transistor. When the protection is activated it is in the
high-impedance state. The pin can be connected to a power supply (<18 V) by a pull-up
resistor whose value is limited by the maximum sinking current (200 µA) of the pin.
Figure 35. Behavior of pin DIAG for various protection conditions
VDD
TDA7491LP
R1
DIAG
Protection logic
VDD
Restart
Restart
UV, OT
protection
Overcurrent
protection
Doc ID 13541 Rev 5
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Applications information
5.9
TDA7491LP
Heatsink requirements
Due to the high efficiency of the class-D amplifier a 2-layer PCB can easily provide the
heatsinking capability for low to medium power outputs.
Using such a PCB with a copper ground layer of 3 x 3 cm2 and 16 vias connecting it to the
contact area for the exposed pad, a thermal resistance, junction to ambient (in natural air
convection), of 24 °C/W can be achieved.
The dissipated power within the device depends primarily on the supply voltage, load
impedance and output modulation level. With the TDA7491LP driving 2 x8 Ω with a supply
of 9 V then the maximum device dissipation is approximately 1 W.
When this power is dissipated at the maximum ambient temperature of 85 °C and the device
is mounted on the above PCB then the junction temperature could reach:
Tj = Tamb + Pd * Rj-amb = 85 + 1 * 24 = 109 °C
However, this temperature is sufficiently low to avoid triggering thermal warning.
With a musical program the dissipated power is about 40% less than the above maximum
value. This leads to a junction temperature of around only 99 °C with the 9 cm2 copper
ground. A commensurately smaller heatsink can thus be used.
Figure 36 shows the power derating curve for the PowerSSO-36 package on PCBs with
copper areas of 2 x 2 cm2 and 3 x 3 cm2.
Figure 36. Power derating curves for PCB usedgas heatsink
Pd (W)
8
7
Copper Area 3x3 cm
and via holes
6
5
TDA7491LP
TDA7491P
PowerSSO-36
PSSO36
4
3
Copper Area 2x2 cm
and via holes
2
1
0
0
20
40
60
80
Tamb ( °C)
32/37
Doc ID 13541 Rev 5
100
120
140
160
TDA7491LP
5.10
Applications information
Test board
Figure 37. Test board (TDA7491LP) layout
Doc ID 13541 Rev 5
33/37
Package mechanical data
6
TDA7491LP
Package mechanical data
The TDA7491LP comes in a 36-pin PowerSSO package with exposed pad down (EPD).
Figure 38 below shows the package outline and Table 9 gives the dimensions.
Table 9.
PowerSSO-36 EPD dimensions
Dimensions in mm
Dimensions in inches
Symbol
Min
Typ
Max
Min
Typ
Max
A
2.15
-
2.47
0.085
-
0.097
A2
2.15
-
2.40
0.085
-
0.094
a1
0.00
-
0.10
0.000
-
0.004
b
0.18
-
0.36
0.007
-
0.014
c
0.23
-
0.32
0.009
-
0.013
D
10.10
-
10.50
0.398
-
0.413
E
7.40
-
7.60
0.291
-
0.299
e
-
0.5
-
-
0.020
-
e3
-
8.5
-
-
0.335
-
F
-
2.3
-
-
0.091
-
G
-
-
0.10
-
-
0.004
H
10.10
-
10.50
0.398
-
0.413
h
-
-
0.40
-
-
0.016
k
0
-
8 degrees
0
-
8 degrees
L
0.60
-
1.00
0.024
-
0.039
M
-
4.30
-
-
0.169
-
N
-
-
10 degrees
-
-
10 degrees
O
-
1.20
-
-
0.047
-
Q
-
0.80
-
-
0.031
-
S
-
2.90
-
-
0.114
-
T
-
3.65
-
-
0.144
-
U
-
1.00
-
-
0.039
-
X
4.10
-
4.70
0.161
-
0.185
Y
6.50
-
7.10
0.256
-
0.280
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
34/37
Doc ID 13541 Rev 5
TDA7491LP
Figure 38. PowerSSO-36 EPD outline drawing
h x 45°
Doc ID 13541 Rev 5
Package mechanical data
35/37
Revision history
7
TDA7491LP
Revision history
Table 10.
Document revision history
Date
Revision
02-Jul-2007
1
Initial release.
15-Oct-2008
2
Updated characterization curves.
3
Updated text concerning oscillator R and C in Section 3.3:
Electrical specifications on page 10
Updated condition for Iq test, added VUVP maximum value,
updated THD maximum value, updated STBY and MUTE
voltages in Table 5: Electrical specifications on page 10
Updated equation for fSW on page 11 and on page 27
Updated Figure 26: Applications circuit for class-D amplifier on
page 24
Updated Section 5.7: Protection functions on page 31.
4
Added text for exposed pad in Figure 2 on page 7
Added text for exposed pad in Table 2 on page 8
Updated exposed pad Y (Min) dimension in Table 9 on page 34
Updated supply voltage for pin DIAG pull-up resistor in
Section 5.8 on page 31.
5
Updated operating temperature range in Table 1 on page 1
Modified description of pins 10, 11 in Table 2 on page 8
Added VI and updated operating temperature range in Table 3:
Absolute maximum ratings on page 9
Updated Table 4: Thermal data on page 9
Updated Table 5: Electrical specifications on page 10
Updated introduction and characterization curves in Section 4
on page 12
Moved test board layout to Section 5.10 on page 33
Moved package mechanical data to Section 6 on page 34
Updated applications circuit in Figure 26 on page 24
Updated Table 7: Gain settings on page 26
Updated Section 5.6: Modulation on page 28
Added Figure 34: Filterless application schematic on page 30
Removed overvoltage protection from Section 5.7: Protection
functions on page 31
Updated Section 5.9: Heatsink requirements on page 32
Updated exposed pad dimension Y in Table 9 on page 34
23-Jun-2009
04-Sep-2009
23-Mar-2011
36/37
Changes
Doc ID 13541 Rev 5
TDA7491LP
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