TDA7512F FM car-radio tuner IC with intelligent selectivity system (ISS) Features FM part ■ RF AGC generation by RF and IF detection ■ I/Q mixer for 1st FM IF 10.7 MHz with image rejection ■ 2 programmable IF-gain stages ■ Mixer for 2nd IF 450 kHz ■ Internal 450 kHz bandpass filter with three bandwidths controlled by ISS ■ Fully integrated FM-demodulator with noise cancellation LQFP64 Additional features ■ VCO for world tuning range ■ High performance fast PLL for RDS-system ■ IF counter with search stop signal ■ Quality detector for level, deviation, adjacent channel and multipath ■ Quality detection informations as analog signals external available ■ ISS (intelligent selectivity system) for cancellation of adjacent channel and noise influences ■ Adjacent channel mute ■ Fully electronic alignment ■ All functions I2C bus controlled Description The TDA7512F is a high performance tuner circuit for FM car-radio. It contains mixer, IF amplifier, demodulator, quality detection, ISS filter and PLL synthesizer with IF counter on a single chip. Use of BiCMOS technology allows the implementation of several tuning functions and a minimum of external components. Table 1. Device summary June 2009 Order code Package Packing E-TDA7512F LQFP64 Tray E-TDA7512FTR LQFP64 Tape and reel Doc ID 12668 Rev 2 1/45 www.st.com 1 Contents TDA7512F Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 3.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 Mixer 1, AGC and 1.IF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Mixer 2, limiter and demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 Quality detection and ISS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.1 Fieldstrength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.2 Adjacent channel detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3.3 Multipath detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.4 450 kHz IF narrow bandpass filter (ISS filter) . . . . . . . . . . . . . . . . . . . . 18 4.3.5 Deviation detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.6 ISS switch logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Soft Mute control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 PLL and IF counter section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 4.5.1 PLL frequency synthesizer block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.2 Frequency generation for phase comparison . . . . . . . . . . . . . . . . . . . . 19 4.5.3 Three state phase comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.4 Charge pump current generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.5 Inlock detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5.6 Low noise CMOS op-amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5.7 IF counter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5.8 Sampling timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5.9 Intermediate frequency main counter . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5.10 Adjustment of the measurement sequence time . . . . . . . . . . . . . . . . . . 21 4.5.11 Adjust of the frequency value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.1 2/45 Data transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 12668 Rev 2 TDA7512F 5 6 Contents 4.6.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.5 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.6 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.7 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Software specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Address organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Control register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Appendix A Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Appendix B Application notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 12668 Rev 2 3/45 List of tables TDA7512F List of tables Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. 4/45 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Control register function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Addr 0 charge pump control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Addr 1 PLL counter 1 (LSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Addr 2 PLL counter 2 (MSB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Addr 3,4 TV1,2 (offset refered to tuning voltage PIN 28) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Addr 5 IF counter control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Addr 6 IF Counter Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Addr 7 not valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Addr 8 quality ISS filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Addr 9 quality detection adjacent channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Addr 10 quality detection multipath. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Addr 11 quality deviation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Addr 12 soft mute control 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Addr 13 soft mute control 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Addr 14 VCODIV/PLLREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Addr 15 FM AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Addr 16 not valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Addr 17 FM demodulator fine adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Addr 18 s-meter slider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Addr 19 IF GAIN/XTAL adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Addr 20 tank adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Addr 21 I/Q mixer 1 adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Addr 22 test control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Addr 23 test control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Addr 24 Test control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Addr 25 test control 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Block diagram quality detection principle (without overdeviation correction) . . . . . . . . . . . 41 Input signals modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Part list (application- and measurment circuit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 12668 Rev 2 TDA7512F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP64 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Block diagram I/Q mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Block diagram VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Block diagram keying AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Block diagram ISS function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 12668 Rev 2 5/45 Block diagram 1 Block diagram Figure 1. 6/45 TDA7512F Block Diagram Doc ID 12668 Rev 2 TDA7512F 2 Pin description Pin description Figure 2. Pin connection (top view) Table 2. Pin description Pin # Pin name Function 1 nu not used - to be left open 2 nu not used - to be left open 3 nu not used - to be left open 4 nu not used - to be left open 5 nu not used - to be left open 6 PINDR PIN Diode Driver Output 7 MIX1IN1 Input1 Mixer1 8 GNDRF RF Ground 9 MIX1IN2 Input2 Mixer1 10 AGCTC AGC Time Constant 11 TV1 Tuning Voltage Preselection1 12 TV2 Tuning Voltage Preselection2 13 ADJCH 14 FSU 15 ISSTC Ident. Adjacent Channel Output Unweighted Fieldstrength Output Time Constant for ISS Filter Switch Doc ID 12668 Rev 2 7/45 Pin description Table 2. 8/45 TDA7512F Pin description (continued) Pin # Pin name Function 16 VCCVCO VCO Supply 17 GNDVCO VCO Ground 18 VCOB VCO Input Base 19 VCOE VCO Output Emitter 20 DEVTC Deviation Detector Time Constant 21 XTALG Xtal Oscillator to MOS Gate 22 XTALD Xtal Oscillator to MOS Drain 23 GNDVCC3 24 SSTOP 25 SDA I2C-Bus Data 26 SCL I2C-Bus Clock 27 VCC3 28 LPOUT Op Amp Output to PLL Loop Filters 29 VREF2 Voltage Reference for PLL Op Amp 30 nu 31 LPF 32 LPHC 33 GNDVCC1 34 MP 35 FSW Weighted Fieldstrength Output 36 VCC1 Digital Supply 37 MPX MPX Output 38 nu not used - to be left open 39 nu not used - to be left open 40 nu not used - to be left open 41 IICADDR Hardwired IIC-Address PIN 42 MUTETC Softmute Time Constant 43 nu not used - to be left open 44 REFDEMC Demodulator Reference 45 MIX2IN2 MIX2 Input1 46 MIX2IN1 MIX2 Input2 47 GNDDEM Ground Demodulator 48 VREF1 49 GNDVCC2 50 IF1AMP2OUT VCC3 Ground Search Stop Output Supply Tuning Voltage not used - to be left open Op Amp Input to PLL Loop Filter High Current PLL Loop Filter Input Digital Ground Ident. Multipath Output Reference 5V Analog Ground IF1 Amplifier2 Output Doc ID 12668 Rev 2 TDA7512F Pin description Table 2. Pin description (continued) Pin # Pin name Function 51 VCC2 52 IF1AMP2IN 53 IF1REF 54 IF1AMP1OUT 55 nc not used - has to be connected versus VCC2 56 nc not used - has to be connected versus VCC2 57 IF1AMP1IN IF1 Amplifier1 Input 58 ISSSTATUS ISS Filter Status 59 GNDIF1 IF1 Ground 60 IFAGCIN IF AGC Input 61 VCCIF1 IF1 Supply 62 nu 63 MIX1OUT2 MIX Tank 10.7MHz 64 MIX1OUT1 MIX Tank 10.7MHz Analog Supply IF1 Amplifier2 Input IF1 Amplifier Reference IF1 Amplifier1 Output not used - to be left open Doc ID 12668 Rev 2 9/45 Electrical specifications TDA7512F 3 Electrical specifications 3.1 Thermal data Table 3. Thermal data Symbol Rth(j-amb) 3.2 Parameter Thermal resistance junction-to-ambient Unit 68 max. °C/W Value Unit 10.5 V Absolute maximum ratings Table 4. Absolute maximum ratings Symbol VS 3.3 Value Parameter Supply voltage Tamb Ambient temperature -40 to 85 °C Tstg Storage temperature -55 to +150 °C Electrical characteristics Tamb = +25 °C, VCC1 = VCC2 = VCC3 = VCCVCO = VCCMIX1 = VCCIF1 = 8.5 V, fRF = 98 MHz, dev. = 40 kHz, fMOD = 1 kHz, fIF1 = 10.7 MHz, fIF2 = 450 kHz, fXtal = 10.25 MHz, in application circuit, unless otherwise specified. Table 5. Symbol Electrical characteristics Parameter Test conditions Min. Typ. Max. Unit Supply VCC1 Digital supply voltage - 7.5 8.5 10 V VCC2 Analog supply voltage - 7.5 8.5 10 V VCC3 Analog tuning voltage - 7.5 8.5 10 V VCCVCO VCO supply voltage - 7.5 8.5 10 V VCCMIX1 MIX1 supply voltage - 7.5 8.5 10 V IF1 supply voltage - 7.5 8.5 10 V ICC1 Supply current - - 7.5 - mA ICC2 Supply current VCO:3 - 70 - mA ICC3 Supply current - - 2 - mA ICCVCO Supply current - - 9 - mA ICCMIX1 Supply current - - 8 - mA ICCIF1 Supply current - - 6 - mA VCCIF1 10/45 Doc ID 12668 Rev 2 TDA7512F Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Reference voltages VREF1 Internal reference voltage IREF1 = 0 mA - 5 - V VREF2 Internal reference voltage IREF2 = 0 mA - 2.5 - V Wide band RF AGC V7-9 Lower threshold start V10 = 2.5 V - 85 - dBµV V7-9 Upper threshold start V10 = 2.5 V - 96 - dBµV Narrow band IF & keying AGC V60 Lower threshold start KAGC = off, V7-9 = 0 mVRMS - 86 - dBµV V60 Upper threshold start KAGC = off, V7-9 = 0 mVRMS - 98 - dBµV V60 Lower threshold start with KAGC ΔfIF KAGC = max, V7-9 = 0 mVRMS, = 300 kHz - 98 - dBµV V35 Start point KAGC KAGC = max, V7-9 = 0 mVRMS, 300 kHz fIF1 generate FSW level at V35 - 3.6 - V Control range KAGC ΔV35= - 16 - dB RIN Input resistance - - 10 - kΩ CIN Input capacitance - - 2.5 - pF D ΔfIF = +0.4 V AGC time constant output V10 Max. AGC output voltage V7-9 = 0 mVRMS - VREF1 +VBE V V10 Min. AGC output voltage V7-9 = 50 mVRMS - 0.5 V I10 Min. AGC charge current V7-9 = 0 mVRMS,; V10 = 2.5 V - -12.5 - µA I10 Max. AGC discharge current V7-9 = 50 mVRMS,; V10 = 2.5 V - 1.25 - mA AGC pin diode driver output I6 AGC OUT, current min. V7-9 = 0 mVRMS, V6 = 2.5 V - 50 - µA I6 AGC OUT, current max. V7-9 = 50 mVRMS, V6 = 2.5 V - -20 - mA I/Q mixer 1 (10.7MHz) RIN Input resistance differential - 10 - kΩ CIN Input capacitance differential - 4 - pF ROUT Output resistance differential 100 - kΩ V7,9 Input dc bias - - 3.2 - V gm Conversion transconductance - - 17 - mS Noise figure 400 Ω generator resistance - 3 - dB F Doc ID 12668 Rev 2 11/45 Electrical specifications Table 5. Electrical characteristics (continued) Symbol CP1dB TDA7512F Parameter Test conditions Min. Typ. Max. Unit 1dB compression point referred to diff. mixer input - 100 - dBµV IIP3 3rd order intermodulation - - 122 - dBµV IQG I/Q gain adjust G -1 - +1 % IQP I/Q phase adjust PH -7 - +8 DEG IRR Image rejection ratio ratio wanted/image 30 40 - dB IRR Image rejection ratio with gain and phase adjust 40 46 - dB IF1 Amplifier1,2 (10.7 MHz) G1min Min. gain IFG, referred to 330 Ω - 9 - dB G1max Max. gain IFG, referred to 330 Ω - 15 - dB G2min Min. gain IFG, referred to 330 Ω - 9 - dB G2max Max. gain IFG, referred to 330 Ω - 11 - dB Input resistance - - 330 - Ω ROUT Output resistance - - 330 - Ω CP1dB 1dB compression point referred to 330 Ω input - 105 - dBµV 3rd order Intermodulation referred to 330 Ω input - 126 - dBµV RIN IIP3 Mixer 2 (450 kHz) RIN Input impedance - - 330 - W V46 Max. input voltage - - 900 - mVRMS V48 Limiting sensitivity S/N = 20dB - 25 - µV Mixer gain - - 18 - dB - - 80 - dB G Limiter 1 (450 kHz) GLimiter Gain Demodulator, audio output THD Total harmonic distortion Dev.= 75 kHz, V46 = 10 mVRMS - - 0.1 % VMPX MPX output signal Dev.= 75 kHz - 500 - mVRMS ROUT Output resistance - - 50 - Ω |ΔV|min DC offset fine adjust DEM, MENA = 1 - 8.5 - mV |ΔV|max DC offset fine adjust DEM, MENA = 1 - 264 - mV Signal to noise Dev.= 40 kHz,V46 = 10 mVRMS - 76 - dB S/N Quality detection S-meter, unweighted fieldstrength V46 Min. input voltage MIX2 - - 10 - µV V14 Fieldstrength output V46 = 0 VRMS - 0.1 - V 12/45 Doc ID 12668 Rev 2 TDA7512F Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit V14 Fieldstrength output V46 = 1 VRMS - 4.9 - V ΔV14 voltage per decade SMSL = 0 - 1 - V ΔV14 voltage per decade SMSL = 1 - 1.5 - V ΔV14 S-meter offset SL, SMSL=1 15 dB ROUT Output resistance - - 200 - W Temp coeff. - - 0 - ppm/K TK -15 S-meter, weighted fieldstrength V35 Fieldstrength output V46 = 0 VRMS - 2.5 - V V35 Fieldstrength output V46 = 1 VRMS - 4.9 - V Output resistance - - 12 - kΩ ROUT Adjacent channel gain Gmin Gain minimum ACG=0 - 32 - dB Gmax Gain maximum ACG=1 - 38 - dB Adjacent channel filter fHP -3dB frequency highpass ACF=0 - 100 - kHz fBP Centre frequency ACF=1 - 100 - kHz f-20dB Attenuation 20dB - - 70 - kHz Adjacent channel output V13 Output voltage low - - 0.1 - V V13 Output voltage high - - 4.9 - V Output resistance - - 4 - kΩ ROUT Multipath channel gain Gmin Gain minimum MPG=0 - 12 - dB Gmax Gain maximum MPG=1 - 23 - dB Multipath bandpass filter fLower Centre frequency low MPF=0 - 19 - kHz fUpper Centre frequency up MPF=1 - 31 - kHz Quality factor - 5 10 - Q Multipath output V34 Output voltage low - - 0.1 - V V34 Output voltage high - - 4.9 - V Output resistance - - 2.5 - kΩ ROUT Doc ID 12668 Rev 2 13/45 Electrical specifications Table 5. TDA7512F Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit ISS (intelligent selectivity system) Filter 450 kHz fcentre Centre frequency fREF_intern = 450 kHz - 450 - kHz BW 3dB Bandwidth, -3dB ISS80 = 1 - 80 - kHz BW 20dB Bandwidth, -20dB ISS80 = 1 - 150 - kHz BW 3dB Bandwidth, -3dB ISS80 = 0 - 120 - kHz BW 20dB Bandwidth, -20dB ISS80 = 0 - 250 - kHz BW 3dB Bandwidth weather band ISS30 = 1 - 30 - kHz BW 20dB -20dB weather band ISS30 = 1 - 80 - kHz Adjacent channel ISS filter threshold VNTH Internal low threshold ACNTH - 0 - V VNTH Internal high threshold ACNTH - 0.3 - V VWTH Internal low threshold ACWTH - 0.25 - V VWTH Internal high threshold ACWTH - 0.95 - V Multipath threshold VTHMP Internal low threshold MPTH - 0.50 - V VTHMP Internal high threshold MPTH - 1.25 - V ISS filter time constant I15 Charge current low mid TISS, ISSCTL = 1 - -74 - µA I15 Charge current high mid TISS, ISSCTL = 1 - -60 - µA I15 Charge current low narrow TISS, ISSCTL = 1 - -124 - µA I15 Charge current high narrow TISS, ISSCTL = 1 - -110 - µA I15 Discharge current low TISS, ISSCTL = 0 - 1 - µA I15 Discharge current high TISS, ISSCTL = 0 - 15 - µA V15 Low voltage ISSCTL = 0 - 0.1 - V V15 High voltage ISSCTL = 1 - 4.9 - V ISS filter switch threshold V15 Threshold ISS on ISSCTL = 0 - 3 - V V15 Threshold ISS off ISSCTL = 0 - 1 - V V15 Threshold ISS narrow on ISSCTL = 0 - 4 - V V15 Threshold ISS narrow off ISSCTL = 0 - 2 - V I20 Charge current low TDEV - -20 - µA I20 Charge current high TDEV - -34 - µA 14/45 Doc ID 12668 Rev 2 TDA7512F Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit I20 Discharge current low TDEV - 6 - µA I20 Discharge current high TDEV - 20 - µA DEVWTH Internal low threshold DWTH - 30 - kHz DEVWTH Internal high threshold DWTH - 75 - kHz RATIOmin Referred to threshold DTH - 1 - - RATIOmax Referred to threshold DTH - 1.5 - - VANT Upper startpoint SMTH, SMD, SLOPE = 0 - 10 - dBµV VANT lower startpoint SMTH, SMD, SLOPE = 0 - 3 - dBµV aSMmin Min. softmute depth SMD, SLOPE = 0, SMTHUpper - 18 - dB aSMmax Max. softmute depth SMD, SLOPE = 0, SMTHUpper - 36 - dB Mute depth threshold for ISS filter on SMCTH 0.2 - 2 dB Internal AC mute threshold ACM 60 - 340 mV aSMAC AC mute depth ACMD 4 - 10 dB I42 Charge current - - -47.5 - µA I42 Discharge current - - 2.5 - µA Signal to noise VANT_min = 60 dBµV, dev.= 40 kHz,LP=15 kHz deemphasis t = 50 µs 66 - - dB 0.5 - VCC30.5 V Softmute aSMTHISS VACTH S/N over all S/N Additional parameters Output of Tuning Voltages (TV1,TV2) VOUT Output voltage TVO ROUT Output impedance - - 20 - kΩ Reference frequency CLoad = 15 pF - 10.25 - MHz CStep Min. cap step XTAL - 0.75 - pF Cmax Max. cap XTAL - 23.25 - pF Δf/f Deviation versus VCC2 ΔVCC2 =1V - 1.5 - ppm/V Δf/f Deviation versus temp -40°C < T < +85 °C - 0.2 - ppm/K Xtal reference oscillator fLO I 2C bus interface fSCL Clock frequency - - - 400 kHz VIL Input low voltage - - - - V Doc ID 12668 Rev 2 15/45 Electrical specifications Table 5. Symbol TDA7512F Electrical characteristics (continued) Parameter Test conditions Min. Typ. Max. Unit VIH Input high voltage - 3 - - V IIN Input current - -5 - 5 µA VO Output acknowledge voltage IO = 1.6 mA - - 0.4 V Loop filter input/output -IIN Input leakage current VIN = GND, PDOUT = Tristate -0.1 - 0.1 µA IIN Input leakage current VIN = VREF1 PDOUT = Tristate -0.1 - 0.1 µA VOL Output voltage Low IOUT = -0.2 mA - 0.05 0.5 V VOH Output voltage High IOUT = 0.2 mA VCC30.5 VCC30.05 - V IOUT Output current, sink VOUT = 1 V to VCC3-1 V - - 10 mA IOUT Output current, source VOUT = 1 V to VCC3-1 V -10 - - mA Voltage controlled oscillator (VCO) fVCOmin Minimum VCO frequency - 160 - - MHz fVCOmax Maximum VCO frequency - - - 260 MHz Carrier to Noise fVCO= 200 MHz, Δf=1 kHz, B=1 Hz, closed loop - 80 - dBc C/N SSTOP output (open collector) V24 Output voltage low I24 = -200 µA - 0.2 0.5 V V24 Output voltage high - - - 5 V -I24 Output leakage current V24 = 5 V -0.1 - 0.1 µA I24 Output current, sink V24 = 0.5 - 5 V - - 1 mA ISSSTATUS output (open drain) V58 Output voltage low, ISSFilter “ON” I24 = -200 µA - 0.2 0.5 V V58 Output voltage high, ISSFilter “OFF” - - - 5 V -I58 Output leakage current V24 = 5 V -0.1 - 0.1 µA I58 Output current, sink V24 = 0.5 - 5 V - - 300 µA 16/45 Doc ID 12668 Rev 2 TDA7512F Functional description 4 Functional description 4.1 Mixer 1, AGC and 1.IF FM quadrature I/Q-mixer converts RF to IF1 of 10.7MHz. The mixer provides inherent image rejection and wide dynamic range with low noise and large input signal performance. The mixer1 tank can be adjusted by software (IF1T). For accurate image rejection the gain- and phase-error generated as well in mixer as VCO stage can be compensated by software (G,PH) It is capable of tuning the US FM, US weather, Europe FM, Japan FM and East Europe FM bands ● US FM = 87.9 to 107.9 MHz ● US weather = 162.4 to 162.55 MHz ● Europe FM = 87.5 to 108 MHz ● Japan FM = 76 to 91 MHz ● East Europe FM = 65.8 to 74 MHz The AGC operates on different sensitivities and bandwidths in order to improve the input sensitivity and dynamic range. AGC thresholds are programmable by software (RFAGC,IFAGC,KAGC). The output signal is a controlled current for double pin diode attenuator. Two 10.7 MHz programmable amplifiers (IFG1, IFG2) correct the IF ceramic insertion loss and the costumer level plan application. 4.2 Mixer 2, limiter and demodulator In this 2. mixer stage the first 10.7 MHz IF is converted into the second 450 kHz IF. A multistage limiter generates signals for the complete integrated demodulator without external tank. MPX output DC offset versus noise DC level is correctable by software (DEM). 4.3 Quality detection and ISS 4.3.1 Fieldstrength Parallel to mixer 2 input a 10.7 MHz limiter generates a signal for digital IF counter and a fieldstrength output signal. This internal unweighted fieldstrength is used for keying AGC, adjacent channel and multipath detection and is available at PIN14 (FSU) after +6dB buffer stage. The behaviour of this output signal can be corrected for DC offset (SL) and slope (SMSL). The internal generated unweighted fieldstrength is filtered at PIN35 and used for softmute function and generation of ISS filter switching signal for weak input level (sm). 4.3.2 Adjacent channel detector The input of the adjacent channel detector is AC coupled from internal unweighted fieldstrength. A programmable highpass or bandpass (ACF) and amplifier (ACG) as well as rectifier determines the influences. This voltage is compared with adjustable comparator1 thresholds (ACWTH, ACNTH). The output signal of this comparator generates a DC level at PIN15 by programmable time constant. Time control (TISS) for a present adjacent channel is made by charge and discharge current after comparator1 in an external capacitance. The Doc ID 12668 Rev 2 17/45 Functional description TDA7512F charge current is fixed and the discharge current is controlled by I2C Bus. This level produces digital signals (ac, ac+) in an additional comparator4. The adjacent channel information is available as analog output signal after rectifier and +8 dB output buffer. 4.3.3 Multipath detector The input of the multipath detector is AC coupled from internal unweighted fieldstrength. A programmable bandpass (MPF) and amplifier (MPG) as well as rectifier determines the influences. This voltage is compared with an adjustable comparator2 thresholds (MPTH). The output signal of this comparator 2 is used for the "Milano" effect. In this case the adjacent channel detection is switched off. The "Milano" effect is selectable by I2C bus (MPOFF). The multipath information is available as analog output signal after rectifier and +8 dB output buffer. 4.3.4 450 kHz IF narrow bandpass filter (ISS filter) The device gets an additional second IF narrow bandpass filter for suppression of noise and adjacent channel signal influences. This narrow filter has three switchable bandwidthes, narrow range of 80 kHz, mid range of 120 kHz and 30 kHz for weather band information. Without ISS filter the IF bandwidth (wide range) is defined only by ceramic filter chain. The filter is switched in after mixer 2 before 450 kHz limiter stage. The centre frequency is matching to the demodulator center frequency. 4.3.5 Deviation detector In order to avoid distortion in audio output signal the narrow ISS filter is switched OFF for present overdeviation. Hence the demodulator output signal is detected. A lowpass filtering and peak rectifier generates a signal that is defined by software controlled current (TDEV) in an external capacitance. This value is compared with a programmable comparator3 thresholds (DWTH, DTH) and generates two digital signals (dev, dev+). For weak signal condition deviation threshold is proportinal to FSU. 4.3.6 ISS switch logic All digital signals coming from adjacent channel detector, deviation detector and softmute are acting via switching matrix on ISS filter switch. The IF bandpass switch mode is controlled by software (ISSON, ISS30, ISS80, CTLOFF). The switch ON of the IF bandpass is also available by external manipulation of the voltage at PIN15. Two application modes are available (APPM). The conditions are described in table 34. 4.4 Soft Mute control The external fieldstrength signal at PIN 35 is the reference for mute control. The startpoint and mute depth are programmable (SMTH, SMD) in a wide range. The time constant is defined by external capacitance. Additional adjacent channel mute function is supported. A highpass filter with -3 dB threshold frequency of 100 kHz, amplifier and peak rectifier generates an adjacent noise signal from MPX output with the same time constant for 18/45 Doc ID 12668 Rev 2 TDA7512F Functional description softmute. This value is compared with comparator5 thresholds (ACM). For present strong adjacent channel the MPX signal is additional attenuated (ACMD). 4.5 PLL and IF counter section 4.5.1 PLL frequency synthesizer block This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only one VCO is required to build a complete PLL system for FM world tuning . For auto search stop operation an IF counter system is available. The counter works in a two stages configuration. The first stage is a swallow counter with a two modulus (32/33) precounter. The second stage is an 11-bit programmable counter. The circuit receives the scaling factors for the programmable counters and the values of the reference frequencies via an I2C bus interface.The reference frequency is generated by an adjustable internal (XTAL) oscillator followed by the reference divider. The main reference and step-frequencies are free selectable (RC, PC). Output signals of the phase detector are switching the programmable current sources. The loop filter integrates their currents to a DC voltage. The values of the current sources are programmable by 6 bits also received via the I2C Bus (A, B, CURRH). To minimize the noise induced by the digital part of the system, a special guard configuration is implemented. The loop gain can be set for different conditions by setting the current values of the chargepump generator. 4.5.2 Frequency generation for phase comparison The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5bit A-divider. The 5-bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler connects to an 11-bit B-divider. The 11-bit PC register (PC5 to PC15) controls this divider Dividing range: fVCO = [33 x A + (B + 1 - A) x 32] x fREF fVCO = (32 x B + A + 32) x fREF Important: For correct operation: A ≤ 32; B ≥ A 4.5.3 Three state phase comparator The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator. 4.5.4 Charge pump current generator This system generators signed pulses of current. The phase error signal decides the duration and polarity of those pulses. The current absolute values are programmable by A register for high current and B register for low current. Doc ID 12668 Rev 2 19/45 Functional description 4.5.5 TDA7512F Inlock detector Switching the chargepump in low current mode can be done either via software or automatically by the inlock detector, by setting bit LDENA to "1". After reaching a phase difference about lower than 40nsec the chargepump is forced in low current mode. A new PLL divider alternation by I2C-Bus will switch the chargepump in the high current mode. 4.5.6 Low noise CMOS op-amp An internal voltage divider at pin VREF2 connects the positive input of the low noise opamp. The charge pump output connects the negative input. This internal amplifier in cooperation with external components can provide an active filter. While the high current mode is activated LPHC output is switched on. 4.5.7 IF counter block The aim of IF counter is to measure the intermediate frequency of the tuner. The input signal is the 10.7MHz IF level after limiter. The grade of integration is adjustable by eight different measuring cycle times. The tolerance of the accepted count value is adjustable, to reach an optimum compromise for search speed and precision of the evaluation. 4.5.8 Sampling timer A sampling timer generates the gate signal for the main counter. The basically sampling time are in FM mode 6.25kHz (tTIM=160μs). This is followed by an asynchronous divider to generate several sampling times. 4.5.9 Intermediate frequency main counter This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are programmable to have the possibility for an adjust to the centre frequency of the IF-filter. The counter length is automatic adjusted to the chosen sampling time. At the start the counter will be loaded with a defined value which is an equivalent to the divider value (tSample x fIF). If a correct frequency is applied to the IF counter frequency input at the end of the sampling time the main counter is changing its state from 0h to 1FFFFFh. This is detected by a control logic and an external search stop output is changing from LOW to HIGH. The frequency range inside which a successful count result is adjustable by the EW bits. + 1696 + 1 t CNT = CF ------------------------------------f IF Counter result succeeded: tTIM ≥ tCNT - tERR tTIM ≤ tCNT + tERR Counter result failed: tTIM > tCNT + tERR 20/45 Doc ID 12668 Rev 2 TDA7512F Functional description tTIM < tCNT - tERR tTIM = IF timer cycle time (sampling time) tCNT = IF counter cycle time tERR = discrimination window (controlled by the EW registers) The IF counter is only started by inlock information from the PLL part. It is enabled by software (IFENA). 4.5.10 Adjustment of the measurement sequence time The precision of the measurements is adjustable by controlling the discrimination window. This is adjustable by programming the control registers EW. The measurement time per cycle is adjustable by setting the registers IFS. 4.5.11 Adjust of the frequency value The center frequency of the discrimination window is adjustable by the control registers CF. 4.6 I2C bus interface The TDA7512F supports the I2C bus protocol. This protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device that controls the transfer is a master and device being controlled is the slave. The master will always initiate data transfer and provide the clock to transmit or receive operations. 4.6.1 Data transition Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions while SCL is HIGH will be interpreted as START or STOP condition. 4.6.2 Start condition A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level. This "START" condition must precede any command and initiate a data transfer onto the bus. The device continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this condition has not been met. 4.6.3 Stop condition A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH level. This condition terminates the communication between the devices and forces the bus-interface of the device into the initial condition. 4.6.4 Acknowledge Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it receive the eight bits of data. Doc ID 12668 Rev 2 21/45 Functional description 4.6.5 TDA7512F Data transfer During data transfer the device samples the SDA line on the leading edge of the SCL clock. Therefore, for proper device operation the SDA line must be stable during the SCL LOW to HIGH transition. 4.6.6 Device addressing To start the communication between two devices, the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6 bits of the slave address are the device type identifier. The TDA7512F device type is fixed as "110001". The next significant bit is used to address a particular device of the previous defined type connected to the bus. The state of the hardwired PIN 41 defines the state of this address bit. So up to two devices could be connected on the same bus. When PIN 41 is connected to VCC2 the address bit “1” is selected. When PIN 41 is left open the address bit “0” is selected. Therefor a double FM tuner concept is possible. The last bit of the start instruction defines the type of operation to be performed: – When set to "1", a read operation is selected – When set to "0", a write operation is selected The TDA7512F connected to the bus will compare their own hardwired address with the slave address being transmitted, after detecting a START condition. After this comparison, the TDA7512F will generate an "acknowledge" on the SDA line and will do either a read or a write operation according to the state of R/W bit. 4.6.7 Write operation Following a START condition the master sends a slave address word with the R/W bit set to "0". The device will generate an "acknowledge" after this first transmission and will wait for a second word (the word address field). This 8-bit address field provides an access to any of the 32 internal addresses. Upon receipt of the word address the TDA7512F slave device will respond with an "acknowledge". At this time, all the following words transmitted to the TDA7512F will be considered as Data. The internal address will be automatically incremented. After each word receipt the TDA7512F will answer with an "acknowledge". 4.6.8 Read operation If the master sends a slave address word with the R/W bit set to "1", the TDA7512F will transit one 8-bit data word. This data word includes the following informations: bit0 (ISS filter, 1 = ON, 0 = OFF) bit1 (ISS filter bandwidth, 1 = 80kHz, 0 = 120kHz) bit2 (MPOUT,1 = multipath present, 0 = no multipath) 22/45 Doc ID 12668 Rev 2 TDA7512F Functional description bit3 (1 = PLL is locked in , 0 = PLL is locked out). bit4 (fieldstrength indicator, 1 = lower as softmute threshold, 0 = higher as softmute threshold) bit5 (adjacent channel indicator, 1 = adjacent channel present, 0 = no adjacent channel) bit6 (deviation indicator, 1 = strong overdeviation present, 0 = no strong overdeviation) bit7 (deviation indicator, 1 = overdeviation present, 0 = no overdeviation) Doc ID 12668 Rev 2 23/45 Software specification 5 TDA7512F Software specification The interface protocol comprises: – start condition (S) – chip address byte – subaddress byte – sequence of data (N bytes + Acknowledge) – stop condition (P) Figure 3. Interface protocol S = Start P = Stop ACK = Acknowledge D = Device Address X = R/W bit I = Pagemode A = Subaddress 5.1 Address organization Table 6. Address organization Function Addr 7 6 5 4 3 2 1 0 CHARGEPU MP 0 LDENA CURRH B1 B0 A3 A2 A1 A0 PLL COUNTER 1 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 2 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 TV1 3 TV1O7 TV1O6 TV1O5 TV1O4 TV1O3 TV1O2 TV1O1 TV1O0 TV2 4 TV2O7 TV2O6 TV2O5 TV2O4 TV2O3 TV2O2 TV2O1 TV2O0 IFC CTRL 1 5 LM CASF - - IFENA IFS2 IFS1 IFS0 IFC CTRL 2 6 EW2 EW1 EW0 CF4 CF3 CF2 CF1 CF0 not valid 7 - - - - - - - - QUALITYISS 8 TISS2 TISS1 TISS0 TVWB ISS30 ISS80 ISSON CTLOFF QUALITY AC 9 ACNTH1 ACNTH0 ACG ACF - QUALITY MP 10 MPAC APPM2 MPG MPF MPOFF 24/45 ACWTH2 ACWTH1 ACWTH0 APPM1 MPTH1 Doc ID 12668 Rev 2 MPTH0 TDA7512F Table 6. Software specification Address organization (continued) Function Addr 7 6 5 4 3 2 1 0 QUALITYDEV 11 BWCTL DTH1 DTH0 DWTH1 DWTH0 TDEV2 TDEV1 TDEV0 MUTE1 12 MENA SMD3 SMD2 SMD1 SMD0 SMTH2 SMTH1 SMTH0 MUTE2 13 F100K ACM3 ACM2 ACM1 ACM0 ACMD1 ACMD0 SMCTH VCO/PLLREF 14 - - RC2 RC1 RC0 VCOD2 VCOD1 VCOD0 FMAGC 15 - KAGC2 KAGC1 KAGC0 IFAGC1 IFAGC0 RFAGC1 RFAGC0 not valid 16 - - - - - - - - DEM ADJ 17 DNB1 DNB0 DEM5 DEM4 DEM3 DEM2 DEM1 DEM0 LEVEL 18 ODSW - SMSL SL4 SL3 SL2 SL1 SL0 IF1/XTAL 19 XTAL4 XTAL3 XTAL2 XTAL1 XTAL0 IFG11 IFG10 IFG2 TANK ADJ 20 IF1T3 IF1T2 IF1T1 IF1T0 - - - - I/Q ADJ 21 ODCUR - G1 G0 PH3 PH2 PH1 PH0 TESTCTRL1 22 - ISSIN TOUT TIN CLKSEP TEST3 TEST2 TEST1 TESTCTRL2 23 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0 TESTCTRL3 24 - TINACM TINMP TINAC OUT11 OUT10 OUT9 OUT8 TESTCTRL4 25 - - - OUT16 OUT15 OUT14 OUT13 OUT12 5.2 Control register function Table 7. Control register function Register Name A Function Charge pump high current ACF Adjacent channel filter select ACG Adjacent channel filter gain ACM Threshold for startpoint adjacent channel mute ACMD Adjacent channel mute depth ACNTH Adjacent channel narrow band threshold ACWTH Adjacent channel wide band threshold APPM B BWCTL CASF CF Application mode quality detection Charge pump low current ISS filter fixed bandwith (ISS80) in automatic control Check alternative station frequency Center frequency IF counter CLKSEP Clock separation (only for testing) CTLOFF Switch off automatic control of ISS filter CURRH Set current high charge pump Doc ID 12668 Rev 2 25/45 Software specification Table 7. TDA7512F Control register function (continued) Register Name DEM Demodulator offset DNB Demodulator noise spike blanking DTH Deviation detector threshold for ISS filter “OFF” DWTH EW F100K G IF1T Deviation detector threshold for ISS filter narrow/wide Frequency error window IF counter Corner frequency of AC-mute high pass filter I/Q mixer gain adjust Miixer1 tank adjust IFAGC IF AGC IFENA IF counter enable IFG IF1 amplifier gain (10.7MHz) IFS IF counter sampling time ISSIN Test input for ISS filter ISSON ISS filter “ON” ISS30 ISS filter 30KHz weather band ISS80 ISS filter narrow/mid switch KAGC Keying AGC LDENA Lock detector enable LM Local mode seek stop MENA Softmute enable MPAC Adjacent channel control by multipath MPF Multipath filter frequency MPG Multipath filter gain MPOFF MPTH Multipath control “OFF” Multipath threshold ODCUR Current for overdeviation-correction ODSW Overdeviation-correction enable OUT Test output (only for testing) PC Counter for PLL (VCO frequency) PH I/Q mixer phase adjust RC Reference counter PLL RFAGC SL SMCTH SMD 26/45 Function RF AGC S meter slider Softmute capacitor threshold for ISS “ON” Softmute depth threshold Doc ID 12668 Rev 2 TDA7512F Software specification Table 7. Control register function (continued) Register Name SMSL S meter slope SMTH Softmute startpoint threshold TDEV Time constant for deviation detector TEST Testing PLL/IFC (only for testing) TIN Switch FSU PIN to TEST input (only for testing) TINAC Test input adjacent channel (only for testing) TINACM Test input adjacent channel mute (only for testing) TINMP Test input multipath(only for testing) TISS Time constant for ISS filter “ON”/”OFF” TOUT Switch FSU PIN to Test output (only for testing) TVO Table 8. Function Tuning voltage offset for prestage TVWB Tuning voltage offset for prestage (weather band mode) VCOD VCO divider XTAL Xtal frequency adjust Subaddress MSB LSB Function - - I A4 A3 A2 A1 A0 - - - 0 0 0 0 0 Charge pump control - - - 0 0 0 0 1 PLL lock detector - - - - - - - - - - - - 1 0 1 0 1 I/Q ADJ - - 0 - - - - - Page mode “OFF” - - 1 - - - - - Page mode enable 5.3 Data byte specification Table 9. Addr 0 charge pump control MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - 0 0 0 0 High current = 0 mA - - - - 0 0 0 1 High current = 0.5 mA - - - - 0 0 1 0 High current = 1 mA - - - - 0 0 1 1 High current = 1.5 mA - - - - - - - - - Doc ID 12668 Rev 2 27/45 Software specification Table 9. TDA7512F Addr 0 charge pump control (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - 1 1 1 1 High current = 7.5 mA - - 0 0 - - - - Low current = 0 µA - - 0 1 - - - - Low current = 50 µA - - 1 0 - - - - Low current = 100 µA - - 1 1 - - - - Low current = 150 µA - 0 - - - - - - Select low current - 1 - - - - - - Select high current 0 - - - - - - - Lock detector disable 1 - - - - - - - Lock detector enable Table 10. Addr 1 PLL counter 1 (LSB) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 LSB = 0 0 0 0 0 0 0 0 1 LSB = 1 0 0 0 0 0 0 1 0 LSB = 2 - - - - - - - - - 1 1 1 1 1 1 0 0 LSB = 252 1 1 1 1 1 1 0 1 LSB = 253 1 1 1 1 1 1 1 0 LSB = 254 1 1 1 1 1 1 1 1 LSB = 255 Table 11. Addr 2 PLL counter 2 (MSB) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 MSB = 0 0 0 0 0 0 0 0 1 MSB = 256 0 0 0 0 0 0 1 0 MSB = 512 - - - - - - - - - 1 1 1 1 1 1 0 0 MSB = 64768 1 1 1 1 1 1 0 1 MSB = 65024 1 1 1 1 1 1 1 0 MSB = 65280 1 1 1 1 1 1 1 1 MSB = 65536 Note: 28/45 Swallow mode: fVCO/fSYN = LSB + MSB + 32 Doc ID 12668 Rev 2 TDA7512F Table 12. Software specification Addr 3,4 TV1,2 (offset refered to tuning voltage PIN 28) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - 0 0 0 0 0 0 0 Tuning Voltage Offset = 0 - 0 0 0 0 0 0 1 TVO = 25mV - 0 0 0 0 0 1 0 TVO = 50mV - - - - - - - - - - 1 1 1 1 1 1 1 TVO = 3175mV 0 - - - - - - - -TVO 1 - - - - - - - +TVO Table 13. Addr 5 IF counter control 1 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - 0 0 0 tSample = 20.48 ms (FM)128 ms (AM ) - - - - - 0 0 1 tSample = 10.24 ms (FM)64 ms (AM ) - - - - - 0 1 0 tSample = 5.12 ms (FM)32 ms (AM ) - - - - - 0 1 1 tSample = 2.56 ms (FM)16 ms (AM ) - - - - - 1 0 0 tSample = 1.28 ms (FM)8 ms (AM ) - - - - - 1 0 1 tSample = 640 µs (FM)4 ms (AM ) - - - - - 1 1 0 tSample = 320 µs (FM)2 ms (AM) - - - - - 1 1 1 tSample = 160 µs (FM)1 ms (AM ) - - - - 0 - - - IF counter disable / stand by - - - - 1 - - - IF counter enable - - 0 1 - - - - has to be set - 0 - - - - - - Disable mute & AGC on hold - 1 - - - - - - Enable mute & AGC on hold 0 - - - - - - - Disable local mode 1 - - - - - - - Enable local mode (PIN diode current = 0.5 mA) “ON” Table 14. Addr 6 IF Counter Control 2 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - 0 0 0 0 0 fCenter = 10.60625 MHz - - - 0 0 0 0 1 fCenter = 10.61250 MHz - - - - - - - - - - - - 0 1 0 1 1 fCenter = 10.67500 MHz Doc ID 12668 Rev 2 29/45 Software specification Table 14. TDA7512F Addr 6 IF Counter Control 2 (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - 0 1 1 0 0 fCenter = 10.68125 MHz - - - 0 1 1 0 1 fCenter = 10.68750 MHz - - - 0 1 1 1 0 fCenter = 10.69375 MHz - - - 0 1 1 1 1 fCenter = 10.70000 MHz - - - - - - - - - - - - 1 1 1 1 1 fCenter = 10.80000 MHz 0 0 0 - - - - - Not valid 0 0 1 - - - - - Not valid 0 1 0 - - - - - Not valid 0 1 1 - - - - - Δf = 6.25kHz 1 0 0 - - - - - Δf = 12.5kHz 1 0 1 - - - - - Δf = 25kHz 1 1 0 - - - - - Δf = 50kHz 1 1 1 - - - - - Δf = 100kHz Table 15. Addr 7 not valid MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 Table 16. has to be set Addr 8 quality ISS filter MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - 0 ISS filter control “ON” - - - - - - 1 ISS filter control “OFF” - - - - - - 0 - Switch ISS filter “OFF” - - - - - - 1 - Switch ISS filter “ON” - - - - - 0 - - Switch “OFF” ISS filter 120kHz - - - - - 1 - - Switch “ON” ISS filter 80kHz - - - - 0 - - - Switch “OFF” ISS filter 30KHz for weatherband - - - - 1 - - - Switch “ON” ISS filter 30KHz for weatherband - - - 0 - - - - Disable TV offset for weather band - - - 1 - - - - Enable TV offset for weather band (+4V) 0 0 0 - - - - - discharge current1μA, charge current mid 74μΑ narrow124μΑ 30/45 Doc ID 12668 Rev 2 TDA7512F Table 16. Software specification Addr 8 quality ISS filter (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 - - - - - discharge current 3µA, charge current mid 72µA narrow 122µA 0 1 0 - - - - - discharge current 5µA, charge current mid 70 µA narrow 120µA 0 1 1 - - - - - discharge current 7µA, charge current mid 68µA narrow 118µA - - - - - - - - - 1 1 1 - - - - - discharge current 15µA,charge current mid 60µA narrow 110µA Table 17. Addr 9 quality detection adjacent channel MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - 0/1 - - - - - - 0 - AC highpass frequency 100 kHz - - - - - - 1 - AC bandpass frequency 100 kHz - - - - - 0 - - AC gain 32 dB - - - - - 1 - - AC gain 38 dB - - 0 0 0 - - - AC wide band threshold 0.25 V - - 0 0 1 - - - AC wide band threshold 0.35 V - - 0 1 0 - - - AC wide band threshold 0.45 V - - - - - - - - - - - 1 1 1 - - - AC wide band threshold 0.95 V 0 0 - - - - - - AC narrow band threshold 0.0 V 0 1 - - - - - - AC narrow band threshold 0.1 V 1 0 - - - - - - AC narrow band threshold 0.2 V 1 1 - - - - - - AC narrow band threshold 0.3 V Table 18. Not valid Addr 10 quality detection multipath MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - 0 Multipath control “ON” - - - - - - - 1 Multipath control “OFF” - - - - - - 0 - MP bandpass frequency 19 kHz - - - - - - 1 - MP bandpass frequency 31 kHz - - - - - 0 - - MP gain 12 dB - - - - - 1 - - MP gain 23 dB - - - 0 0 - - - MP threshold 0.50 V Doc ID 12668 Rev 2 31/45 Software specification Table 18. TDA7512F Addr 10 quality detection multipath (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - 0 1 - - - MP threshold 0.75 V - - - 1 0 - - - MP threshold 1.00 V - - - 1 1 - - - MP threshold 1.25 V - 0 0 - - - - - Application mode 1 - 0 1 - - - - - Application mode 2 0 - - - - - - - Multipath eliminates ac 1 - - - - - - - Multipath eliminates ac and ac+ Table 19. Addr 11 quality deviation detection MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - 0 0 0 charge current 34 µA, discharge current 6 µA - - - - - 0 0 1 charge current 32 µA, discharge current 8 µA - - - - - 0 1 0 charge current 30 µA, discharge current 10 µA - - - - - 0 1 1 charge current 28 µA, discharge current 12 µA - - - - - - - - - - - - - - 1 1 1 charge current 20 µA, discharge current 20 µA - - - 0 0 - - - DEV threshold for ISS narrow/wide 30 kHz - - - 0 1 - - - DEV threshold for ISS narrow/wide 45 kHz - - - 1 0 - - - DEV threshold for ISS narrow/wide 60 kHz - - - 1 1 - - - DEV threshold for ISS narrow/wide 75 kHz - 0 0 - - - - - DEV threshold for ISS filter “OFF” ratio 1.5 - 0 1 - - - - - DEV threshold for ISS filter “OFF” ratio 1.4 - 1 0 - - - - - DEV threshold for ISS filter “OFF” ratio 1.3 - 1 1 - - - - - DEV threshold for ISS filter “OFF” ratio 1 0 - - - - - - - Disable ISS filter to fixed bandwith (ISS80) in automatic control 1 - - - - - - - Enable ISS filter to fixed bandwith (ISS80) in automatic control Table 20. Addr 12 soft mute control 1 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - 0 0 0 Startpoint mute 0 in application about 3dBµV antenna level - - - - - 0 0 1 Startpoint mute 1in application about 4dBµV antenna level 32/45 Doc ID 12668 Rev 2 TDA7512F Table 20. Software specification Addr 12 soft mute control 1 (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - - - - - - - - 1 1 1 Startpoint mute 7in application about 10dBμV antenna level - 0 0 0 0 - - - Mute depth 0 in application 18d B - 0 0 0 1 - - - Mute depth 1 in application 20 dB - 0 0 1 0 - - - Mute depth 2 in application 22 dB - 0 0 1 1 - - - Mute depth 3 in application 24 dB - - - - - - - - - (logarithmically behaviour) - 1 1 1 1 - - - Mute depth 15 in application 36 dB 0 - - - - - - - Mute disable 1 - - - - - - - Mute enable Table 21. Addr 13 soft mute control 2 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - 0 Disable mute threshold for ISS filter “ON” - - - - - - - 1 Enable mute threshold for ISS filter “ON” - - - - - 0 0 - AC mute depth 10 dB - - - - - 0 1 - AC mute depth 8 dB - - - - - 1 0 - AC mute depth 6 dB - - - - - 1 1 - AC mute depth 4 dB - 0 0 0 0 - - - AC mute threshold 60 mV - 0 0 0 1 - - - AC mute threshold 80 mV - 0 0 1 0 - - - AC mute threshold 100 mV - - - - - - - - - - 0 1 1 1 - - - AC mute threshold 340 mV - 1 1 1 1 - - - AC mute “OFF” 0 - - - - - - - AC mute filter 110 kHz 1 - - - - - - - AC mute filter 100 kHz Table 22. Addr 14 VCODIV/PLLREF MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - 0 0 not valid (only for testing) - - - - - - 0 1 VCO frequency divided by 2 Doc ID 12668 Rev 2 33/45 Software specification Table 22. TDA7512F Addr 14 VCODIV/PLLREF (continued) MSB LSB Function d7 d6 d5 d4 d3 - - - - - - - - - - d1 d0 - 1 0 VCO frequency divided by 3 - - 1 1 original VCO frequency - - - 0 - - VCO” I” signal 0 °C - - - - 1 - - VCO “I” signal 180 °C - - 1 0 0 - - - PLL reference frequency 50 kHz - - 1 0 1 - - - PLL reference frequency 25 kHz - - 1 1 0 - - - PLL reference frequency 10 kHz - - 1 1 1 - - - PLL reference frequency 9 kHz - - 0 0 0 - - - PLL reference frequency 2 kHz 0 0 - - - - - - has to be set Table 23. d2 Addr 15 FM AGC MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - 0 0 RFAGC threshold V7-9TH= 85 (77 ANT) dBµV - - - - - - 0 1 RFAGC threshold V7-9TH= 90 (82 ANT) dBµV - - - - - - 1 0 RFAGC threshold V7-9TH= 94 (86 ANT) dBµV - - - - - - 1 1 RFAGC threshold V7-9TH= 96 (88 ANT) dBµV - - - - 0 0 - - IFAGC threshold V60TH= 86 (60 ANT) dBµV - - - - 0 1 - - IFAGC threshold V60TH= 92 (66 ANT) dBµV - - - - 1 0 - - IFAGC threshold V60TH= 96 (70 ANT) dBµV - - - - 1 1 - - IFAGC threshold V60TH= 98 (72 ANT) dBµV - 0 0 0 - - - - KAGC threshold 80 dBµV - 0 0 1 - - - - KAGC threshold 82 dBµV - 0 1 0 - - - - KAGC threshold 84 dBµV - 0 1 1 - - - - KAGC threshold 86 dBµV - 1 0 0 - - - - KAGC threshold 88 dBµV - 1 0 1 - - - - KAGC threshold 90 dBµV - 1 1 0 - - - - KAGC threshold 92 dBµV - 1 1 1 - - - - Keying AGC “OFF” 0 - - - - - - - has to be “0” 34/45 Doc ID 12668 Rev 2 TDA7512F Table 24. Software specification Addr 16 not valid MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 1 Table 25. has to be set Addr 17 FM demodulator fine adjust MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - 0 0 0 0 0 0 0 mV - - 0 0 0 0 0 1 +8.5 mV - - 0 0 0 0 1 0 +17 mV - - - - - - - - - - - 0 1 1 1 1 1 +263.5 mV - - 1 0 0 0 0 0 0 mV - - 1 0 0 0 0 1 -8.5 mV - - 1 0 0 0 1 0 -17 mV - - - - - - - - - - - 1 1 1 1 1 1 -263.5 mV 0 0 - - - - - - Spike cancelation ”OFF” 0 1 - - - - - - Threshold for spike cancelation 270 mV 1 0 - - - - - - Threshold for spike cancelation 520 mV 1 1 - - - - - - Threshold for spike cancelation 750 mV Table 26. Addr 18 s-meter slider MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - 0 0 0 0 S meter slider offset SL=0dB - - - - 0 0 0 1 S meter offset SL=1dB - - - - 0 0 1 0 S meter offset SL=2dB - - - - - - - - - - - - - 1 1 1 1 S meter offset SL=15dB - - - 0 - - - - S meter offset -SL - - - 1 - - - - S meter offset +SL - - 0 - - - - - S Meter slope 1 V/decade - - 1 - - - - - S meter slope 1.5 V/decade - 1 - - - - - - has to be set Doc ID 12668 Rev 2 35/45 Software specification Table 26. TDA7512F Addr 18 s-meter slider (continued) MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 0 - - - - - - - Overdeviation correction “ON” 1 - - - - - - - Overdeviation correction “OFF” Table 27. Addr 19 IF GAIN/XTAL adjust MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - 0 IF1 gain2 9d B - - - - - - - 1 IF1 gain2 11 dB - - - - - 0 0 - IF1 gain1 9 dB - - - - - 0 1 - IF1 gain1 11 dB - - - - - 1 0 - IF1 gain1 12 dB - - - - - 1 1 - IF1 gain1 15 dB 0 0 0 0 0 - - - CLoad 0 pF 0 0 0 0 1 - - - CLoad 0.75 pF 0 0 0 1 0 - - - CLoad 1.5 pF 0 0 0 1 1 - - - CLoad 2.25 pF 0 0 1 0 0 - - - CLoad 3 pF - - - - - - - - - 1 1 1 1 1 - - - CLoad 23.25 pF Table 28. Addr 20 tank adjust MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - 0 0 0 0 has to be set 0 0 0 0 - - - - 10.7 MHz 0 pF 0 0 0 1 - - - - 10.7 MHz 0.55 pF 0 0 1 0 - - - - 10.7 MHz 1.1 pF 0 0 1 1 - - - - 10.7 MHz 1.65 pF - - - - - - - - - 1 1 1 1 - - - - 10.7 Hz 8.25 pF 36/45 Doc ID 12668 Rev 2 TDA7512F Table 29. Software specification Addr 21 I/Q mixer 1 adjust MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 - - - - 0 0 0 0 -7 °C - - - - 0 0 0 1 -6 °C - - - - 0 0 1 0 -5 °C - - - - - - - - - - - - - 0 1 1 1 0 °C - - - - 1 0 0 0 +1 °C - - - - 1 0 0 1 +2 °C - - - - - - - - - - - - - 1 1 1 1 +8 °C - - 0 0 - - - - 0% - - 0 1 - - - - -1 % - - 1 0 - - - - +1 % - - 1 1 - - - - 0% - x - - - - - - not used 0 - - - - - - - Overdeviation correction current max = 45 µA 1 - - - - - - - Overdeviation correction current max = 90 µA Table 30. Addr 22 test control 1 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x Table 31. Only for testing ( have to be set to 0) Addr 23 test control 2 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x Table 32. Only for testing ( have to be set to 0) Addr 24 Test control 3 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x Table 33. Only for testing ( have to be set to 0) Addr 25 test control 4 MSB LSB Function d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x Only for testing ( have to be set to 0) Doc ID 12668 Rev 2 37/45 Package information 6 TDA7512F Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 4. LQFP64 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. A MIN. TYP. 1.60 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.22 0.27 0.006 0.055 0.057 B 0.17 C 0.09 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 0.0066 0.0086 0.0106 0.0035 D3 7.50 0.295 e 0.50 0.0197 E 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 0.45 0.60 0.75 0.0177 0.0236 0.0295 E3 7.50 L OUTLINE AND MECHANICAL DATA MAX. 0.295 L1 1.00 K 0˚ (min.), 3.5˚ (typ.), 7˚ (max.) 0.0393 ccc 0.080 LQFP64 (10 x 10 x 1.4mm) 0.0031 D D1 A D3 A2 A1 48 33 49 32 0.08mm ccc E E1 E3 B B Seating Plane 17 64 1 16 C L L1 e K 0051434 F 38/45 Doc ID 12668 Rev 2 TDA7512F Block diagrams Appendix A Block diagrams Figure 5. Block diagram I/Q mixer Figure 6. Block diagram VCO Doc ID 12668 Rev 2 39/45 Block diagrams 40/45 TDA7512F Figure 7. Block diagram keying AGC Figure 8. Block diagram ISS function Doc ID 12668 Rev 2 TDA7512F Block diagrams Table 34. Block diagram quality detection principle (without overdeviation correction) Signal Table 35. Low High ac No adjacent channel Adjacent channel present ac+ No strong adjacent channel Adjacent channel higher as ac sm Fieldstrength higher as softmute threshold Fieldstrength lower as softmute threshold dev Deviation lower as threshold DWTH Deviation higher as threshold DWTH dev+ Deviation lower as threshold DTH*DWTH Deviation higher as threshold DTH*DWTH inton ISS filter off by logic (wide) ISS filter on by logic int80 ISS filter 120kHz (mid) ISS filter 80kHz (narrow) Input signals modes Input signals Mode 1 Mode 2 0ac 0ac+ 0sm 0dev 0dev+ 0inton 0int80 0Function 0inton 0int80 0Function 0 0 0 0 0 0 0 wide 0 0 wide 0 0 0 1 0 0 0 wide 0 0 wide 0 0 0 1 1 0 0 wide 0 0 wide 0 0 1 0 0 1 1 narrow 1 1 narrow 0 0 1 1 0 0 0 wide 1 0 mid 0 0 1 1 1 0 0 wide 0 0 wide 1 0 0 0 0 1 1 narrow 1 0 mid 1 1 0 0 0 1 1 narrow 1 1 narrow 1 0 0 1 0 1 0 mid 1 0 mid 1 1 0 1 1 1 0 mid 1 1 narrow 1 0 1 0 0 1 1 narrow 1 1 narrow 1 1 1 0 0 1 1 narrow 1 1 narrow 1 0 1 1 0 1 0 mid 1 0 mid 1 1 1 1 0 1 0 mid 1 1 narrow 1 0 1 1 1 1 0 mid 1 0 mid 1 1 1 1 1 1 0 mid 1 1 narrow Doc ID 12668 Rev 2 41/45 Block diagrams TDA7512F Table 36. Part list (application- and measurment circuit) Item F1 TOKO 5KM 396INS-A542EK F2 TOKO MC152 E558CN-100021 F3 TOKO 7PSG 826RC-5134N L1 TOKO LQH31 L2 TOKO LL 2012-680 CF1 TOKO CFSK107M3-AE-20X CF2 TOKO CFSK107M4-AE-20X D1,D2 Figure 9. 42/45 Description TOKO KP2311E D3 TOKO KV1370NT D4 PHILIPS BB156 Application circuit Doc ID 12668 Rev 2 TDA7512F Application notes Appendix B Application notes Following items are important to get highest performance of TDA7512F in application: 1. In order to avoid leakage current from PLL loop filter input to ground a guardring is recommended around loop filter PIN’s with PLL reference voltage potential. 2. Distance between Xtal and VCO input PIN 18 should be far as possible and Xtal package should get a shield versus ground. 3. Blocking of VCO supply should be near at PIN 16 and PIN 17. 4. Wire lenght to FM mixer1 input and output should be symetrically and short. 5. FM demodulator capacitance at PIN 44 should be sense connected as short as possible versus demodulator ground at PIN 47. 6. With respect to THD capacitive coupling from PIN 20 to VCO should be avoided. Capacitance at PIN 20 has be connected versus VCC2 ground. Doc ID 12668 Rev 2 43/45 Revision history 7 TDA7512F Revision history Table 37. 44/45 Document revision history Date Revision Changes 05-Sep-2006 1 Initial release. 24-Jun-2009 2 Updated Section 6: Package information on page 38. Doc ID 12668 Rev 2 TDA7512F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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