TDA7565 Quad power amplifier with integrated step-up converter Features ■ Multipower BCD technology ■ DMOS power output ■ Non-switching high efficiency amplifier ■ Switching high efficiency voltage converter ■ High output power capability: – 4 x 41 W max @ Vs = 14.4 V – 4 x 59 W @ Vs = 14.4 V and PWM = 17.5 V ■ Full I2C bus driving: – Standby – Independent front/rear soft play/mute – Selectable gain 26 dB - 12 dB (for low noise line output function) – High efficiency enable/disable – Voltage converter enable/disable – Regulated voltage selection – Switching frequency selection ■ Hardware mute function ■ Full fault protection ■ DC offset detection ■ Four independent short circuit protection ■ Clipping detector with selectable threshold (1 % / 10 %) via I2C bus Table 1. Flexiwatt27 Description The TDA7565 is a new BCD technology quad bridge type of car radio amplifier in Flexiwatt27 package specially intended for car radio applications. Thanks to the DMOS output stage the TDA7565 has a very low distortion allowing a clear powerful sound. The built-in voltage converter control block assures a very high output power with an extremely low number of added components. Furthermore, the converter makes the TDA7565 compliant to the most recent OEM specifications for low voltage operation (so called 'start-stop' battery profile during engine stop), helping car manufacturers to reduce the overall emissions and thus contributing to environment protection. Device summary Order code Package Packing TDA7565 Flexiwatt27 Tube February 2010 Doc ID 9800 Rev 4 1/19 www.st.com 1 Contents TDA7565 Contents 1 Block and pin connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Low voltage "start-stop" operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 9800 Rev 4 TDA7565 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DB4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Doc ID 9800 Rev 4 3/19 List of figures TDA7565 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. 4/19 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Demoboard schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledge on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Worst case condition for a start-stop system diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 17 Doc ID 9800 Rev 4 TDA7565 1 Block and pin connection diagrams Block and pin connection diagrams Figure 1. Block diagram VS MUTE CLK VCC1 DATA VCC2 I2C BUS CC GND CLIP DETECTOR MUTE1 MUTE2 IN RF VOLTAGE CONVERTER CONTROL MG VOLTAGE CONVERTER EXTERNAL CIRCUIT F OUT RF+ 12/26dB OUT RF- IN RR SHORT CIRCUIT PROTECTION R OUT RR+ 12/26dB OUT RR- IN LF SHORT CIRCUIT PROTECTION F OUT LF+ 12/26dB OUT LF- IN LR SHORT CIRCUIT PROTECTION R OUT LR+ 12/26dB OUT LRSHORT CIRCUIT PROTECTION SVR AC_GND RF RR LF LR TAB D00AU1232A PW_GND Figure 2. S_GND Pin connection (top view) 27 MUTE 26 DATA 25 PW_GND RR 24 OUT RR- 23 CK 22 OUT RR+ 21 VCC2 20 OUT RF- 19 PW_GND RF 18 OUT RF+ 17 AC_GND 16 IN RF 15 IN RR 14 S_GND 13 IN LR 12 IN LF 11 SVR 10 OUT LF+ 9 PW_GND LF 8 OUT LF- 7 VCC1 6 OUT LR+ 5 CC GND 4 OUT LR- 3 PW_GND LR 2 MG 1 TAB D00AU1233A Doc ID 9800 Rev 4 5/19 Electrical specification TDA7565 2 Electrical specification 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Unit Operating supply voltage, converter off 18 V Vopc ON Operating supply voltage, converter on 25 V DC supply voltage 28 V Vpeak Peak supply voltage (for t = 50 ms) 50 V VCK CK pin voltage 6 V Data pin voltage 6 V IO Output peak current (not repetitive t = 100 µs) 8 A IO Output peak current (repetitive f > 10 Hz) 6 A Power dissipation Tcase = 70 °C 80 W -55 to 150 °C Value Unit 1 °C/W VDATA Ptot Tstg, Tj Storage and junction temperature Thermal data Table 3. Thermal data Symbol Rth j-case 2.3 Value Vopc OFF VS 2.2 Parameter Description Thermal resistance junction to case Max. Electrical characteristics Refer to the test circuit, VS = 14.4 V; RL = 4 Ω; f = 1 kHz; voltage converter disabled (VCOff); Tamb = 25 °C; unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Power amplifier VS Supply voltage range - 8 - 18 V Id Total quiescent drain current - - 250 300 mA Id Total quiescent drain current (VCon) - - 350 - mA Max power(1) - 41 - W PO Output power (VCoff) V = 14.4 V THD = 10 % THD = 1 % 22 18 27 22 - W W 6/19 Doc ID 9800 Rev 4 TDA7565 Table 4. Electrical specification Electrical characteristics (continued) Symbol PO THD Parameter Test condition (1) Max power Min. Typ. Max. Unit - 59 - W 32 25 39 31 - W W Output power (VCon) V = 14.4V, PWM = 17.5V THD = 10 % THD = 1 % - 0.03 0.03 0.1 0.1 Total harmonic distortion PO = 1 W to 12 W; STDmode HE mode; PO = 1-2 W HE mode; PO = 4-12 W % % % PO = 1-12 W, f = 10 kHz - 0.15 0.5 % CT Cross talk f = 1 kHz to 10 kHz, RG = 600 Ω 50 55 - dB RIN Input impedance - 60 100 130 KΩ GV1 Voltage gain 1 - 25.5 26 26.5 dB Voltage gain match 1 - -1 - 1 dB Voltage gain 2 - 11.5 12 12.5 dB ΔGV2 Voltage gain match 2 - -1 - 1 dB EIN1 Output noise voltage 1 Rg = 600 Ω; GV = 26 dB filter 20 Hz to 22 kHz - 60 70 μV EIN2 Output noise voltage 2 Rg = 600 Ω; GV = 26 dB filter 20 Hz to 12 kHz - 15 25 μV SVR Supply voltage rejection f = 100 Hz to 10 kHz; Vr = 1V pk; Rg = 600 Ω 50 60 - dB BW Power bandwidth (-3 dB) 75 - - KHz ASB Standby attenuation - 70 100 ISB Standby current - - - AM Mute attenuation - 70 90 VOS Offset voltage Mute and play -100 - 100 mV VAM Min. supply voltage threshold - 6.5 7 7.5 V Slew rate - 1.5 - - V/μs TON Turn on delay D2/D1 (IB1) 0 to 1 - 10 40 ms TOFF Turn off delay D2/D1 (IB1) 1 to 0 - 10 40 ms Thermal foldback junction temperature - 155 170 185 °C D0 (IB1) = 0 0 1 2 % D0 (IB1) = 1 5 10 15 % ±1.5 ±2 ±2.5 V - 165 - °C ΔGV1 GV2 - CDTHD dB 50 μA dB Clip det thd. level VO Offset detection Power amplifier = play AC Input = 0 Thw Thermal warning - Doc ID 9800 Rev 4 7/19 Electrical specification Table 4. TDA7565 Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit I2C bus interface fSCL Clock frequency - - - 400 KHz VIL Input low voltage - - - 1.5 V VIH Input high voltage - 2.3 - - V - - 1.5 V VMin(pin27) Mute in threshold voltage Amp. mute VMout(pin27) Mute out threshold voltage - 3.5 - - V AM(pin 27) Mute attenuation - 80 90 - - - V kHz Voltage converter Converter output voltage (VC = ON) VS = 14 V D3 (IB2) = 0; D6 (IB2) = 0 D3 (IB2) = 1; D6 (IB2) = 0 D3 (IB2) = 0; D6 (IB2) = 1 D3 (IB2) = 1; D6 (IB2) = 1 - Voltage converter switching frequency D6 (IB1) = 0; D7 (IB1) = 0 D6 (IB1) = 1; D7 (IB1) = 0 D6 (IB1) = 0; D7 (IB1) = 1 D6 (IB1) = 1; D7 (IB1) = 1 90 135 230 360 - 120 175 300 470 Vmgl MOS gate output low voltage Io = 200 mA - 1 2 V 11 - V MOS gate output high voltage Io = 20 mA - Vmgh Io = 200 mA - 9.5 - V Io = 5 mA - 11.5 - V Vcc1, Vcc2 Fs Vmgclamp MOS gate output clamp voltage tf Fall time Co = 1 nF - 20 - ns tr Rise time Co = 1 nF - 50 - ns MOS gate output voltage with voltage converter disabled Io = 5 mA - - 0.5 V Vmgl (VCoff) 1. Saturated square wave output. 8/19 15 16.5 17.5 18.5 Doc ID 9800 Rev 4 TDA7565 Electrical specification Figure 3. Demoboard schematic C10 2.2nF VS (Vbatt) C7 2200μF R5 10 1W L1 100μH STPS30L40CT C8 220nF D1 DGND SCL SDA 23 26 VCC C11 3300μF C12 100nF C13 10μF R1 50Ω C9 10nF R4 3.3 1W Q1 R3 10Ω 2 7 5 21 OUT RF+ 18 STP60NE06 C1 220nF 20 16 IN RF OUT RFOUT RR+ 22 C2 220nF 15 IN RR 24 TDA7565 OUT RROUT LF+ C3 220nF 10 12 IN LF 8 C4 220nF IN LR 13 MUTE 27 OUT LFOUT LR+ 6 4 11 14 17 C6 10μF Doc ID 9800 Rev 4 C5 1μF 9 3 19 25 1 OUT LR- D00AU1224B 9/19 I2C bus interface 3 TDA7565 I2C bus interface Data transmission from microprocessor to the TDA7565 and vice versa takes place through the 2 wires I2C bus interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data validity As shown by Figure 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and stop conditions As shown by Figure 5 a start condition is a high to low transition of the SDA line while SCL is HIGH. The stop condition is a low to high transition of the SDA line while SCL is high. 3.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The transmitter* puts a resistive high level on the SDA line during the acknowledge clock pulse (see Figure 6). The receiver** the acknowledges has to pull-down (low) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. * Transmitter – master (μP) when it writes an address to the TDA7565 – slave (TDA7565) when the μP reads a data byte from TDA7565 ** Receiver – slave (TDA7565) when the μP writes an address to the TDA7565 – master (µP) when it reads a data byte from TDA7565 Figure 4. Data validity on the I2C bus SDA SCL DATA LINE STABLE, DATA VALID 10/19 CHANGE DATA ALLOWED Doc ID 9800 Rev 4 D99AU1031 I2C bus interface TDA7565 Figure 5. Timing diagram on the I2C bus SCL I2CBUS SDA D99AU1032 START Figure 6. STOP Acknowledge on the I2C bus SCL 1 2 3 7 8 9 SDA MSB START D99AU1033 Doc ID 9800 Rev 4 ACKNOWLEDGMENT FROM RECEIVER 11/19 Software specifications 4 TDA7565 Software specifications All the functions of the TDA7565 are activated by I2C interface. The bit 0 of the "ADDRESS BYTE" defines if the next bytes are write instruction (from µP to TDA7565) or read instruction (from TDA7565 to µP). Table 5. Chip address Bit Instruction D7 Address bit D6 Address bit D5 Address bit D4 Address bit D3 Address bit D2 Address bit D1 Address bit D0(R/W) Read/Write bit 0 = Write instruction 1 = read instruction If R/W = 0, the µP sends 2 "Instruction Bytes": IB1 and IB2. Table 6. IB1 Bit 12/19 Instruction D7 Sel. freq. switch 1 D6 Sel. freq. switch 2 D5 Offset detection start (D5 = 1) Offset detection stop (D5 = 0) (off) D4 Front channel Gain = 26dB (D4 = 0) Gain = 12dB (D4 = 1) D3 Rear channel Gain = 26dB (D3 = 0) Gain = 12dB (D3 = 1) D2 Mute front channels (D2 = 0) Unmute front channels (D2 = 1) D1 Mute rear channels (D1 = 0) Unmute rear channels (D1 = 1) D0 CD 1% (D0 = 0) CD 10% (D0 = 1) Doc ID 9800 Rev 4 TDA7565 Software specifications Table 7. IB2 Bit Instruction D7 Voltage converter enabled (D7 = 1) Voltage converter disabled (D7 = 0) D6 Regulated voltage selection 1 D5 Test speed D4 Stand-by on - amplifier not working - (D4 = 0) Stand-by off - amplifier working - (D4 = 1) D3 Regulated voltage selection 0) D2 To be forced to “Level 1” D1 Right channel Power amplifier working in standard mode (D1 = 0) Power amplifier working in Hi Eff. mode(D1 = 1) D0 Left channel Power amplifier working in standard mode (D0 = 0) Power amplifier working in Hi Eff. mode(D0 = 1) Table 8. DB1 Bit Instruction D7 Thermal warning D6 X D5 X D4 X D3 X D2 Offset (LF) D1 Short circuit protection (CH1) D0 X Table 9. DB2 Bit Instruction D7 Off status D6 X D5 Clip detector output D4 X D3 X D2 Offset (LR) D1 Short circuit protection (CH2) D0 X Doc ID 9800 Rev 4 13/19 Software specifications Table 10. TDA7565 DB3 Bit Instruction D7 Standby status D6 X D5 X D4 X D3 X D2 Offset (RF) D1 Short circuit protection (CH3) D0 X Table 11. DB4 Bit 14/19 Instruction D7 X D6 X D5 X D4 X D3 X D2 Offset (RR) D1 Short circuit protection (CH4) D0 X Doc ID 9800 Rev 4 TDA7565 5 Examples of bytes sequence Examples of bytes sequence 1 - Turn-on of the power amplifier with 26 dB gain, mute on, diagnostic defeat, high eff. mode, voltage converter disabled. Start Address byte with D0 = 0 ACK IB1 ACK XX00X000 IB2 ACK STOP ACK STOP ACK STOP 0XX1XX10 2 - Turn-off of the power amplifier Start Address byte with D0 = 0 ACK IB1 ACK XXXXXXXX IB2 XXX0XXX0 4 - Offset detection procedure start Start Address byte with D0 = 0 ACK IB1 XX1XX11X ACK IB2 XXX1XXX0 5 - Offset detection procedure stop and reading operation. Start Address byte with D0 = 1 ACK DB1 STOP ● The purpose of this test is to check if a D.C. offset (2V typ.) is present on the outputs, produced by input capacitor with anomalous leakage current or humidity between pins. ● The delay from 3 to 4 can be selected by software, starting from 1 ms Doc ID 9800 Rev 4 15/19 Low voltage "start-stop" operation 6 TDA7565 Low voltage "start-stop" operation The most recent OEM specification are requiring automatic stop of car engine at traffic lights in order to reduce emissions of polluting substances. The TDA7565, thanks to its integrated switching voltage converter, allows a continuous operation when battery falls down to 6/7 V during such conditions, without producing pop noise. The maximum system power will be reduced accordingly. The internal converter must be enabled and programmed in order to supply 15 V (D3 (IB2) = 0; D6 (IB2) = 0). The suggested voltage frequency switching is 150 kHz (D6 (IB1) = 1; D7 (IB1) = 0). The following curve is a worst case condition for a start-stop system. The TDA7565, with the switching converter powered on, can sustain this cranking curve without any audio signal interruption. Figure 7. Worst case condition for a start-stop system diagram V Vb1 Vb3 Vb2 tr t1 t2 t3 tf Vb1 = 12 V, Vb2 = 6 V, Vb3 = 7 V Ri ≤ 0.01 Ω (internal resistor of power supply) Recovery time from test start to tr is 1 s tr = 2 ms t1 = 1 ms (the shortest time, at cranking simulation power supply, is 5 ms) t2 = 15 ms t3 = 1 s tf = 0.5 s 16/19 Doc ID 9800 Rev 4 t TDA7565 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 8. DIM. Flexiwatt27 (vertical) mechanical data and package dimensions MIN. 4.45 1.80 A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3 0.75 0.37 0.80 25.75 28.90 22.07 18.57 15.50 7.70 3.70 3.60 mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 MAX. 4.65 2.00 MIN. 0.175 0.070 1.05 0.42 0.57 1.20 26.25 29.30 0.029 0.014 0.031 1.014 1.139 22.87 19.37 15.90 7.95 0.869 0.731 0.610 0.303 4.30 4.40 0.145 0.142 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019 MAX. 0.183 0.079 OUTLINE AND MECHANICAL DATA 0.041 0.016 0.022 0.047 1.033 1.153 0.904 0.762 0.626 0.313 0.169 0.173 5˚ (Typ.) 3˚ (Typ.) 20˚ (Typ.) 45˚ (Typ.) Flexiwatt27 (vertical) (1): dam-bar protusion not included (2): molding protusion included V C B V H H1 V3 A H2 O H3 R3 L4 R4 V1 R2 L2 N R L3 7 Package information L L1 V1 V2 R2 D R1 L5 Pin 1 R1 R1 E G G1 F FLEX27ME M M1 7139011 Doc ID 9800 Rev 4 17/19 Revision history 8 TDA7565 Revision history Table 12. 18/19 Document revision history Date Revision Changes 20-Sep-2003 1 Initial release. 1-Jul-2008 2 Document reformatted. Document status promoted from product preview to datasheet. 25-Jan-2010 3 Updated Features and Description on page 1. Updated Table 4: Electrical characteristics. Added Section 6: Low voltage "start-stop" operation. 03-Feb-2010 4 Minor text changes. Doc ID 9800 Rev 4 TDA7565 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 9800 Rev 4 19/19