TDA7718N 3 band car audio processor Features ■ ■ ■ ■ ■ ■ Input multiplexer – QD1: quasi-differential stereo inputs – SE1: stereo single-ended input – SE2: stereo single-ended input – SE3: stereo single-ended input – FD1 / SE4+SE5: 1 full-differential input or 2 stereo single-ended inputs TSSOP28 ■ Loudness – 2nd order frequency response – Programmable center frequency (400 Hz / 800 Hz / 2400 Hz) – 15 dB with 1 dB steps – Selectable high frequency boost – Selectable flat-mode (constant attenuation) Speaker – 4 independent soft step speaker controls – +15 dB to -79 dB with 1 dB steps – Direct mute ■ Volume – +23 dB to -31 dB with 1 dB step resolution – Soft-step control with programmable blend times Subwoofer – 2nd order low pass filter with programmable cut off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz) – 2 independent soft step level control, +15 dB to –79 dB with 1 dB steps ■ Mute functions – Direct mute – Digitally controlled SoftMute with 4 programmable mute-times (0.48 ms/0.96 ms/8 ms/16 ms) ■ Offset detection – Offset voltage detection circuit for on-board power amplifier failure diagnosis Bass – 2nd order frequency response – Center frequency programmable in 4 steps (60 Hz / 80 Hz / 100 Hz / 200 Hz) – Q programmable 1.0/1.25/1.5/2.0 – DC gain programmable – -15 dB to 15 dB range with 1 dB resolution Middle – 2nd order frequency response – Center frequency programmable in 4 steps (500 Hz / 1 kHz / 1.5 kHz / 2.5 kHz) – Q programmable 0.75/1.0/1.25 – -15 dB to 15 dB range with 1 dB resolution Treble – 2nd order frequency response (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) – Center frequency programmable in 4 steps (10 kHz / 12.5 kHz / 15 kHz / 17.5 kHz) – -15 dB to 15 dB with 1 dB resolution October 2009 Description The TDA7718N is a high performance signal processor specifically designed for car radio applications. The device includes a high performance audioprocessor with fully integrated audio filters and new Soft Step architecture. The digital control allows programming in a wide range of filter characteristics. Table 1. Device summary Order code Package Packing TDA7718N TSSOP28 Tube TDA7718NTR TSSOP28 Tape and reel Doc ID 16502 Rev 1 1/40 www.st.com 1 Contents TDA7718N Contents 1 Block circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin connection and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description of the audioprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.1.1 Quasi-differential stereo input (QD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 Single-ended stereo input (SE1, SE2, SE3) . . . . . . . . . . . . . . . . . . . . . 13 4.1.3 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5) 13 Loudness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Loudness attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 Peak frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.3 High frequency boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.4 Flat mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 SoftMute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 SoftStep volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Bass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 4.7 2/40 Input stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5.1 Bass attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5.2 Bass center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.5.4 DC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Middle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.1 Middle attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.2 Middle center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.3 Quality factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Doc ID 16502 Rev 1 TDA7718N 5 Contents 4.7.1 Treble attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7.2 Center frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.8 Subwoofer filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 Softstep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.10 DC offset detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.11 Audioprocessor testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 I2C bus electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 5.2.1 Receive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.2 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2.3 Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Data byte specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 16502 Rev 1 3/40 List of tables TDA7718N List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/40 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C bus electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Subaddress (receive mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Main selector (0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Soft mute / others (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SoftStep I (5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SoftStep II / DC detector (6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Loudness (7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Volume / output gain (8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Treble filter (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Middle filter (10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Bass filter (11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Subwoofer / middle / bass (12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 1 (19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Testing audio processor 2 (20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Testing audio processor 3 (21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Doc ID 16502 Rev 1 TDA7718N List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Block circuit diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FD / QD / SE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Loudness attenuation @ fP = 400 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness center frequencies @ attn. = 15 dB.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Loudness attenuation, fc = 2.4 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SoftMute timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bass control @ fC = 80 Hz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bass quality factors @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Middle control @ fC = 1 kHz, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle center frequencies @ gain = 14 dB, Q = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Middle quality factors @ gain = 14 dB, fC = 1 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble control @ fC = 17.5 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Treble center frequencies @ gain = 14 dB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Subwoofer cut frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC offset detection circuit (simplified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C bus interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C bus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 TSSOP28 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Doc ID 16502 Rev 1 5/40 SE1L 6/40 Doc ID 16502 Rev 1 FD1R+/QD2R/SE5R FD1R-/QD2G/SE5L FD1L-/QD2G/SE4R FD1L+/QD2L/SE4L QD1R QD1G QD1L SE3R SE3L SE2R SE2L VCC GND SUPPLY CREF VOLUME DIGITAL CONTROL TREBLE BASS SCL SDA I2C BUS SUBWOOFER MIDDLE WIN_IN WIN_TC DC-Offset Detector DC_ERR MONO FADER MONO FADER MONO FADER MONO FADER MONO FADER MONO FADER OUTSWR OUTSWL OUTRR OUTLR OUTRF OUTLF Figure 1. SOFT MUTE 1 SE1R LOUDNESS MUTE Block circuit diagram TDA7718N Block circuit diagram Block circuit diagram MAIN INPUT MULTIPLEXER TDA7718N Pin connection and pin description 2 Pin connection and pin description 2.1 Pin connection Figure 2. Pin connection (top view) SE1L 1 28 Winin SE1R 2 27 DCErr SE2L 3 26 SDA SE2R 4 25 SCL SE3L 5 24 VCC SE3R 6 23 MUTE QD1L 7 22 WINTC QD1G 8 21 OUTLF QD1R 9 20 OUTLR FD1L+/QD2L/SE4L 10 19 OUTRR FD1L-/QD2G/SE4R 11 18 OUTRF FD1R-/QD2G/SE5L 12 17 OUTSWL FD1R+/QD2R/SE5R 13 16 OUTSWR CREF 14 15 GND 2.2 Pin description Table 2. Pin description No. Pin name Description 1 SE1L Single-end input left I 2 SE1R Single-end input right I 3 SE2L Single-end input left I 4 SE2R Single-end input right I 5 SE3L Single-end input left I 6 SE3R Single-end input right I 7 QD1L quasi-differential stereo inputs left I 8 QD1G quasi-differential stereo inputs common I 9 QD1R quasi-differential stereo inputs right I 10 FD1L+/QD2L/SE4L Full differential + input left or quasi-differential left or single-end input left I Doc ID 16502 Rev 1 I/O 7/40 Pin connection and pin description Table 2. TDA7718N Pin description (continued) No. Pin name Description I/O 11 FD1L-/QD2G/SE4R Full differential - input left or quasi-differential ground or single-end input right I 12 FD1R-/QD2G/SE5L Full differential - input right or quasi-differential ground or single-end input left I 13 FD1R+/QD2R/SE5R Full differential + input right or quasi-differential right or single-end input right I 14 CREF Reference capacitor O 15 GND Ground S 16 OUTSWR Subwoofer right output O 17 OUTSWL Subwoofer left output O 18 OUTRF Front right output O 19 OUTRR Rear right output O 20 OUTLR Rear left output O 21 OUTLF Front left output O 22 WinTC DC offset detector filter output O 23 MUTE External mute pin I 24 VCC Supply S SCL 2C I bus clock I 26 SDA I2C bus data I/O 27 DC_ERR 28 WIN_IN 25 8/40 DC offset detector output O DC offset detector input I Doc ID 16502 Rev 1 TDA7718N Electrical specifications 3 Electrical specifications 3.1 Thermal data Table 3. Thermal data Symbol Rth-j amb 3.2 Description Unit 114 °C/W Value Unit 10.5 V 7 V Thermal resistance junction-to-ambient Absolute maximum ratings Table 4. Absolute maximum ratings Symbol Parameter Operating supply voltage VS Vin_max 3.3 Value Maximum voltage for signal input pins Tamb Operating ambient temperature -40 to 85 °C Tstg Storage temperature range -55 to 150 °C Electrical characteristics VS = 8.5 V; Tamb= 25 °C; RL= 10 kΩ; all gains = 0 dB; f = 1 kHz; unless otherwise specified Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply Vs Supply voltage - 7.5 8.5 10 V Is Supply current - 23 29 35 mA Input selector Rin Input resistance All single ended inputs 70 100 130 kΩ VCL Clipping level Input gain = 0 dB 2 - - VRMS SIN Input separation - - 95 - dB Differential stereo inputs Input resistance Differential 70 100 - kΩ CMRR Common mode rejection ratio for main source VCM = 1 VRMS @ 1 kHz 44 60 - dB VCM = 1 VRMS @ 10 kHz 44 60 - dB eNo Output noise @ speaker outputs - 12 22 µV Rin 20 Hz - 20 kHz, A-weighted; all stages 0 dB Doc ID 16502 Rev 1 9/40 Electrical specifications Table 5. TDA7718N Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit Loudness control AMAX Max attenuation - 14 15 16 dB ASTEP Step resolution - 0.5 1 1.5 dB fP1 - 400 - Hz fP2 - 800 - Hz fP3 - 2400 - Hz 22 23 24 dB fPeak Peak frequency Volume control GMAX Max gain AMAX Max attenuation - - -31 -30 dB ASTEP Step resolution - 0.5 1 1.5 dB EA Attenuation set error - -0.75 0 +0.75 dB ET Tracking error - - - 2 dB VDC DC steps - Adjacent attenuation steps -3 0.1 3 mV From 0 dB to GMIN -5 0.5 5 mV - 80 100 - dB Soft mute AMUTE TD Mute attenuation Delay time T1 0.35 0.48 0.65 ms T2 0.7 0.96 1.3 ms T3 5.6 7.6 9.6 ms T4 12.3 15.3 18.3 ms Low threshold for SM pin - - - 1 V VTH High High threshold for SM pin - 2.5 - - V VTH Low RPU Internal pull-up resistor - 32 45 58 kΩ VPU Internal pull-up voltage - 3 3.3 3.6 V fC1 - 60 - Hz fC2 - 80 - Hz fC3 - 100 - Hz Bass control Fc QBASS Center frequency Quality factor fC4 - 200 - Hz Q1 - 1 - - Q2 - 1.25 - - Q3 - 1.5 - - - 2 - - - ±14 ±15 ±16 dB - 0.5 1 1.5 dB DC = off -1 0 +1 dB ±4.3 ±4.7 ±5.1 dB Q4 CRANGE Control range ASTEP Step resolution DCGAIN Bass-DC-gain 10/40 DC = on, gain = ±15 dB Doc ID 16502 Rev 1 TDA7718N Table 5. Electrical specifications Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit - ±14 ±15 ±16 dB - 0.5 1 1.5 dB fC1 - 500 - Hz fC2 - 1 - kHz fC3 - 1.5 - kHz fC4 - 2.5 - kHz Q1 - 0.75 - - Q2 - 1 - - Q3 - 1.25 - - - ±14 ±15 ±16 dB - Middle control CRANGE Control range ASTEP fc Step resolution Center frequency QMIDDLE Quality factor Treble control CRANGE Clipping level ASTEP fc Step resolution Center frequency 0.5 1 1.5 dB fC1 - 10 - kHz fC2 - 12.5 - kHz fC3 - 15 - kHz fC4 - 17.5 - kHz Speaker attenuators GMAX Max gain - 14 15 16 dB AMAX Max attenuation - - -79 -74 dB ASTEP Step resolution - 0.5 1 1.5 dB AMUTE Mute attenuation - 80 90 - dB Attenuation set error - - - 2 dB DC steps Adjacent attenuation steps - 0.1 5 mV d = 0.3 %; byte8_D6=1 2 - - VRMS 2.2 - - VRMS - - 30 100 Ω EE VDC Audio outputs VCL ROUT Clipping level Output impedance d = 1 %; byte8_D6=0 RL Output load resistance - 2 - - kΩ CL Output load capacitor - - - 10 nF DC voltage level - 3.8 4.0 4.2 V fLP1 - 55 - Hz fLP2 - 85 - Hz fLP3 - 120 - Hz fLP4 - 160 - Hz VDC Subwoofer lowpass fLP Lowpass corner frequency Doc ID 16502 Rev 1 11/40 Electrical specifications Table 5. TDA7718N Electrical characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit V1 ±10 ±25 ±40 mV V2 ±30 ±50 ±70 mV V3 ±50 ±75 ±100 mV V4 DC offset detection circuit Vth tsp Zero comp. window size Max rejected spike length ±70 ±100 ±130 mV - 2 11 30 µs - 5 22 50 µs - 10 33 70 µs - 15 44 90 µs ICHDCErr DCErr charge current - 2 5 8 µA IDISDCErr DCErr discharge current - 4 5 9 mA VOutH DCErr high voltage - 3 3.3 3.6 V VOutH DCErr low voltage - - 100 300 mV BW=20 Hz to 20 kHz AWeighted, all gain = 0 dB - 12 22 µV BW=20 Hz - 20 kHz AWeighted, Output muted - 7 12 µV 98 104 - dB General eNO S/N Output noise Signal to noise ratio all gain = 0 dB, A-weighted; Vo = 2 VRMS D Distortion VIN =1 VRMS; all stages 0 dB - 0.01 0.1 % SC Channel separation left/right - - 90 - dB 12/40 Doc ID 16502 Rev 1 TDA7718N Description of the audioprocessor 4 Description of the audioprocessor 4.1 Input stages One quasi-differential stereo input, one full-differential stereo input and maximum five single-ended inputs are available. 4.1.1 Quasi-differential stereo input (QD1) The QD input is implemented as a buffered quasi-differential stereo stage with 100 kΩ inputimpedance at each input. There is -3 dB attenuation at QD input stage. 4.1.2 Single-ended stereo input (SE1, SE2, SE3) The input-impedance at each input is 100 kΩ and the attenuation is fixed to -3 dB for incoming signals. 4.1.3 Full-differential stereo input or single-ended input (FD1/QD2/SE4+SE5) This device provides a full-differential stereo input stage (FD1) or 2nd quasi-differential stereo input stage. The full differential is a buffered full-differential stereo stage with 100 kΩ input-impedance at each input. When using as QD2 application, it needs to connect the two QD2G pins together from external and the input impedance at QDG becomes 50 kΩ. This stage can be also configured as 2 single-ended stereo input stages (SE4 and SE5). The configuration is done with the input selector control bits and the selection of FD1 and QD2 is controlled by a separate bit. There is -3 dB attenuation at the input stage. Figure 3 shows the block diagram of this input stage. Doc ID 16502 Rev 1 13/40 Description of the audioprocessor Figure 3. 14/40 TDA7718N FD / QD / SE block diagram Doc ID 16502 Rev 1 TDA7718N 4.2 Description of the audioprocessor Loudness There are four parameters programmable in the loudness stage. 4.2.1 Loudness attenuation Figure 4 shows the attenuation as a function of frequency at fP = 400 Hz. Figure 4. 4.2.2 Loudness attenuation @ fP = 400 Hz. Peak frequency Figure 5 shows the four possible peak-frequencies at 400, 800 and 2400 Hz. Figure 5. Loudness center frequencies @ attn. = 15 dB. Doc ID 16502 Rev 1 15/40 Description of the audioprocessor 4.2.3 TDA7718N High frequency boost Figure 6 shows the different Loudness shapes in low and high frequency boost. Figure 6. 4.2.4 Loudness attenuation, fc = 2.4 kHz Flat mode In flat mode the loudness stage works as a 0 dB to -15 dB attenuator. 16/40 Doc ID 16502 Rev 1 TDA7718N 4.3 Description of the audioprocessor SoftMute The digitally controlled SoftMute stage allows muting/demuting the signal with a I2C bus programmable slope. The mute process can either be activated by the SoftMute pin or by the I2C bus. This slope is realized in a special S-shaped curve to mute slow in the critical regions (see Figure 7). For timing purposes the bit 0 of the I2C bus output register is set to 1 from the start of muting until the end of demuting. Figure 7. SoftMute timing EXT. MUTE 1 +SIGNAL REF -SIGNAL 1 I2C BUS OUT D97AU634 Time Note: Please notice that a started mute-action is always terminated and could not be interrupted by a change of the mute –signal. 4.4 SoftStep volume When the volume-level is changed audible clicks could appear at the output. The root cause of those clicks could either be a DC-offset before the volume-stage or the sudden change of the envelope of the audio signal. With the SoftStep-feature both kinds of clicks could be reduced to a minimum and are no more audible. The blend-time from one step to the next is programmable as 5 ms or 10 ms. The SoftStep control is described in detail in Chapter 4.9. Doc ID 16502 Rev 1 17/40 Description of the audioprocessor 4.5 TDA7718N Bass There are four parameters programmable in the bass stage: 4.5.1 Bass attenuation Figure 8 shows the attenuation as a function of frequency at a center frequency of 80 Hz. Figure 8. 4.5.2 Bass control @ fC = 80 Hz, Q = 1 Bass center frequency Figure 9 shows the four possible center frequencies 60, 80, 100 and 200 Hz. Figure 9. 18/40 Bass center frequencies @ gain = 14 dB, Q = 1 Doc ID 16502 Rev 1 TDA7718N 4.5.3 Description of the audioprocessor Quality factors Figure 10 shows the four possible quality factors 1, 1.25, 1.5 and 2. Figure 10. Bass quality factors @ gain = 14 dB, fC = 80 Hz 4.5.4 DC mode In this mode the DC-gain is increased by 4.4 dB. In addition the programmed center frequency and quality factor is decreased by 25 % which can be used to reach alternative center frequencies or quality factors. Figure 11. Bass normal and DC mode @ gain = 14 dB, fC = 80 Hz 1. The center frequency, Q and DC-mode can be set fully independently. Doc ID 16502 Rev 1 19/40 Description of the audioprocessor 4.6 TDA7718N Middle There are three parameters programmable in the middle stage: 4.6.1 Middle attenuation Figure 12 shows the attenuation as a function of frequency at a center frequency of 1 kHz. Figure 12. Middle control @ fC = 1 kHz, Q = 1 4.6.2 Middle center frequency Figure 13 shows the four possible center frequencies 500 Hz, 1 kHz, 1.5 kHz and 2.5 kHz. Figure 13. Middle center frequencies @ gain = 14 dB, Q = 1 20/40 Doc ID 16502 Rev 1 TDA7718N 4.6.3 Description of the audioprocessor Quality factors Figure 14 shows the three possible quality factors 0.75, 1 and 1.25. Figure 14. Middle quality factors @ gain = 14 dB, fC = 1 kHz 4.7 Treble There are two parameters programmable in the treble stage: 4.7.1 Treble attenuation Figure 15 shows the attenuation as a function of frequency at a center frequency of 17.5 kHz. Figure 15. Treble control @ fC = 17.5 kHz. Doc ID 16502 Rev 1 21/40 Description of the audioprocessor 4.7.2 TDA7718N Center frequency Figure 16 shows the four possible center frequencies 10 k, 12.5 k, 15 k and 17.5 kHz. Figure 16. Treble center frequencies @ gain = 14 dB 4.8 Subwoofer filter The subwoofer lowpass filter has Butterworth characteristics with programmable cut-off frequency (55 Hz / 85 Hz / 120 Hz / 160 Hz). The output phase can be selected between 0 deg and 180 deg. The input of subwoofer takes signal from bass filter output or output of input mux. Figure 17. Subwoofer cut frequencies 22/40 Doc ID 16502 Rev 1 TDA7718N 4.9 Description of the audioprocessor Softstep control In this device, the softstep function is available for volume, speaker, loudness, treble, middle and bass block. With softstep function, the audible noise of DC offset or the sudden change of signal can be avoided when adjusting gain setting of the block. For each block, the softstep function is controlled by softstep on/off control bit in the control table. The softstep transient time selection (5 ms or 10 ms) is common for all blocks and it is controlled by softstep time control bit. The softstep operation of all blocks has a common centralized control. In this case, a new softstep operation can not be started before the completion previous softstep. There are two different modes to activate the softstep operation. The softstep operation can be started right after I2C data sending, or the softstep can be activated in parallel after data sending of several different blocks. The two modes are controlled by the ‘act bit’ (it is normally bit7 of the byte.) of each byte. When act bit is ‘0’, which means action, the softstep is activated right after the date byte is sent. When the act bit is ‘1’, which means wait, the block goes to wait for softstep status. In this case, the block will wait for some other block to activate the operation. The softstep operation of all blocks in wait status will be done together with the block which activate the softstep. With this mode, all specific blocks can do the softstep in parallel. This avoids waiting when the softstep is operated one by one. Chip Addr Sub Addr 0xxxxxxx |↑ Softstep start here Chip Addr Sub Addr 1xxxxxxx 1xxxxxxx ...... 0xxxxxxx |↑ Softstep start here for all 4.10 DC offset detector Using the DC offset detection circuit (Figure 18) an offset voltage difference between the audio power amplifier and the APR's Front and Rear outputs can be detected, preventing serious damage to the loudspeakers. The circuit compares whether the signal crosses the zero level inside the audio power at the same time as in the speaker cell. The output of the zero-window-comparator of the power amplifier must be connected with the WinIn-input of the APR. The WinIn-input has an internal pull-up resistor connected to 5.5 V. It is recommended to drive this pin with open-collector outputs only. To compensate for errors at low frequencies the WinTC-pin are implemented, with external capacitors introducing the same delay τ = 7.5 kΩ * Cext as the AC-coupling between the APR and the power amplifier introduces. For the zero window comparators, the time constant for spike rejection as well as the threshold are programmable. For electrical characteristics see Chapter 3 on page 9. A low-active DC-offset error signal appears at the DCErr output if the next conditions are both true: a) Front and rear outputs are inside zero crossing windows. b) The Input voltage VWinIn is logic low whenever at least one output of the power amplifier is outside the zero crossing windows. Doc ID 16502 Rev 1 23/40 Description of the audioprocessor TDA7718N After power-on, the external attached capacitor is rapidly charged (fast-charge) to overcome a false indication. Figure 18. DC offset detection circuit (simplified) 24/40 Doc ID 16502 Rev 1 TDA7718N 4.11 Description of the audioprocessor Audioprocessor testing In the test mode, which can be activated by setting bit D7 of the I2C subaddress byte and bit D0 of the testing audioprocessor byte, several internal signals are available at the SE1L pin. In this mode, the input resistance of 100 kΩ is disconnected from the pin. Internal signals available for testing are listed in the data-byte specification. Figure 19. Test circuit 100nF SE1L SE1L WnIn SE1R DCErr SE2L SDA SE2R SCL SE3L VCC SE3R MUTE 100nF SE1R 100nF SE2L 100nF SE2R 100nF SE3L 100nF 100nF SE3R 100nF QD1L QD1L TSSOP28 WINTC 22u QD1G 4.7u QD1G OUTLF QD1R OUTLR 100nF QD1R FD1L+/QD2L/SE4L 4.7u FD1L-/QD2G/SE4R OUTRF FD1R-/QD2G/SE5L OUTSWL FD1R+/QD2R/SE5R OUTSWR OUTRF 4.7u 4.7u FD1R+/QD2R/SE5R OUTRR OUTRR 4.7u FD1R-/QD2G/SE5L OUTLR 4.7u 4.7u FD1L-/QD2G/SE4R OUTLF 4.7u 4.7u FD1L+/QD2L/SE4L 10uF OUTSWL 4.7u CREF OUTSWR GND 10uF Doc ID 16502 Rev 1 25/40 I2C bus specification TDA7718N 5 I2C bus specification 5.1 Interface protocol The interface protocol comprises: ● a start condition (S) ● a chip address byte (the LSB determines read/write transmission) ● a subaddress byte ● a sequence of data (N-bytes + acknowledge) ● a stop condition (P) ● the max. clock speed is 400 kbit/s ● 3.3 V logic compatible Figure 20. I2C bus interface protocol 1. S = Start 2. ACK = Acknowledge 5.2 I2C bus electrical characteristics Table 6. Symbol 26/40 I2C bus electrical characteristics Parameter Min Max Unit - 400 kHz fSCL SCL clock frequency VIH High level input voltage 2.4 - V VIL Low level input voltage - 0.8 V tHD,STA Hold time for START 0.6 - µs tSU,STO Setup time for STOP 0.6 - µs tLOW Low period for SCL clock 1.3 - µs tHIGH High period for SCL clock 0.6 - µs tF Fall time for SCL/SDA - 300 ns tR Rise time for SCL/SDA - 300 ns tHD,DAT Data hold time 0 - ns tSU,DAT Data setup time 100 - ns Doc ID 16502 Rev 1 I2C bus specification TDA7718N Figure 21. I2C bus data 5.2.1 S Receive mode 1 0 0 0 1 0 0 R/W ACK TS X AI A4 A3 A2 A1 A0 ACK DATA ACK P S = Start R/W = "0" -> Receive Mode (Chip can be programmed by µP) "1" -> Transmission Mode (Data could be received by µP) ACK = Acknowledge P = Stop TS = Testing mode AI = Auto increment 5.2.2 S Transmission mode 1 0 0 0 1 0 0 R/W ACK X X X X X X BZ SM ACK P SM = Soft mute activated for main channel BZ = Softstep Busy (‘0’ = Busy) X = Not used The transmitted data is automatic updated after each ACK. Transmission can be repeated without new chip address. 5.2.3 Reset condition A Power-On-Reset is invoked if the supply voltage is below than 3.5 V. After that the registers are initialized to the default data written in following tables. Doc ID 16502 Rev 1 27/40 I2C bus specification Table 7. TDA7718N Subaddress (receive mode) MSB LSB Function I2 I1 I0 A4 A3 A2 A1 A0 0 1 - - - - - - - Testing mode Off On - x - - - - - - Not used - - 0 1 - - - - - Auto increment mode Off On - - - 0 0 0 0 0 Main selector - - - 0 0 0 0 1 Not used - - - 0 0 0 1 0 Not used - - - 0 0 0 1 1 Not used - - - 0 0 1 0 0 Soft mute / others - - - 0 0 1 0 1 Soft step I - - - 0 0 1 1 0 Soft step II / DC-detector - - - 0 0 1 1 1 Loudness - - - 0 1 0 0 0 Volume / output gain - - - 0 1 0 0 1 Treble - - - 0 1 0 1 0 Middle - - - 0 1 0 1 1 Bass - - - 0 1 1 0 0 Subwoofer / middle / bass - - - 0 1 1 0 1 Speaker attenuator left front - - - 0 1 1 1 0 Speaker attenuator right front - - - 0 1 1 1 1 Speaker attenuator left rear - - - 1 0 0 0 0 Speaker attenuator right rear - - - 1 0 0 0 1 Subwoofer attenuator left - - - 1 0 0 1 0 Subwoofer attenuator right - - - 1 0 0 1 1 Testing audio processor 1 - - - 1 0 1 0 0 Testing audio processor 2 - - - 1 0 1 0 1 Testing audio processor 3 28/40 Doc ID 16502 Rev 1 I2C bus specification TDA7718N 5.3 Data byte specification Table 8. Main selector (0) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Main source selector SE1 SE3 QD1 QD2 / FD1 SE2 SE4 SE5 Mute - - - - - - - - - 0 1 - - - FD / QD2 selection FD QD2 - - - 0 1 - - - - Main source input gain select 0 dB 3 dB - - 0 1 - - - - - Subwoofer flat Off On x x - - - - - - Not used Not used (1-3) Doc ID 16502 Rev 1 29/40 I2C bus specification Table 9. TDA7718N Soft mute / others (4) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Pin influence for mute Pin and IIC IIC 0 0 1 1 0 1 0 1 - - Soft mute time 0.48 ms 0.96 ms 7.68 ms 15.36 ms Soft mute On Off - - - - - - - 0 1 - - - - Subwoofer input source Input mux Bass output - - 0 1 - - - - - Subwoofer enable (OUTSWL & OUTSWR) On Off - 0 1 - - - - - - Fast charge On Off 0 1 - - - - - - - Anti-alias filter On Off (bypass) 30/40 Doc ID 16502 Rev 1 I2C bus specification TDA7718N Table 10. SoftStep I (5) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Volume soft step On Off - - - - - 0 1 - - Treble soft step On Off Loudness soft step On Off - - - - 0 1 - - - Middle soft step On Off - - - 0 1 - - - - Bass soft step On Off - - 0 1 - - - - - Speaker LF soft step On Off - 0 1 - - - - - - Speaker RF soft step On Off - Speaker LR soft step On Off 0 1 - - - - - - Doc ID 16502 Rev 1 31/40 I2C bus specification Table 11. TDA7718N SoftStep II / DC detector (6) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 - - - - - - - 0 1 - - - - - - 0 1 - Subwoofer left soft step On Off - - - - - 0 1 - - Subwoofer right soft step On Off - Soft step time 5 ms 10 ms - Zero-comparator window size ±100 mV ±75 mV ±50 mV ±25 mV - Spike rejection time constant 11 µs 22 µs 33 µs 44 µs - - 0 0 1 1 32/40 - - 0 1 0 1 - - 0 0 1 1 0 1 0 1 - - 0 1 - - - - - - - - Doc ID 16502 Rev 1 Speaker RR soft step On Off I2C bus specification TDA7718N Table 12. Loudness (7) MSB LSB Function D7 - - - 0 1 D6 - - 0 1 D4 - - 0 0 1 1 0 1 0 1 - - Table 13. D5 - - - D3 D2 D1 D0 0 0 : 1 1 0 0 : 1 1 0 0 : 1 1 0 1 : 0 1 - - - - - - - - - Attenuation 0 dB -1 dB : -14 dB -15 dB - Center frequency Flat 400 Hz 800 Hz 2400 Hz - High boost On Off - Soft step action Act Wait Volume / output gain (8) MSB LSB Function D7 - - 0 1 D6 - D5 D4 D3 D2 D1 D0 0 0 : 0 0 : 0 0 : 0 1 : 1 : 1 0 0 : 0 1 : 1 1 : 1 0 : 0 : 1 0 0 : 1 0 : 0 1 : 1 0 : 1 : 1 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 0 0 : 1 0 : 1 0 : 1 0 : 1 : 1 0 1 : 1 0 : 1 0 : 1 0 : 1 : 1 Gain/attenuation +0 dB +1 dB : +15 dB +16 dB : +23 dB Not used : Not used -0 dB : -15 dB : -31 dB 0 1 - - - - - - Output gain 1 dB 0 dB - - - - - - - Soft step action Act Wait Doc ID 16502 Rev 1 33/40 I2C bus specification Table 14. TDA7718N Treble filter (9) MSB LSB Function D7 - - 0 1 D6 D5 - - 0 0 1 1 0 1 0 1 - - Table 15. D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB - - - - - Treble center frequency 10.0 kHz 12.5 kHz 15.0 kHz 17.5 kHz - - - - - Soft step action Act Wait Middle filter (10) MSB LSB Function D7 - - 0 1 34/40 D6 - D5 - 0 0 1 1 0 1 0 1 - - D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB - - - - - Middle Q factor 0.75 1 1.25 Reserved - - - - - Soft step action Act Wait Doc ID 16502 Rev 1 I2C bus specification TDA7718N Table 16. Bass filter (11) MSB LSB Function D7 - - 0 1 D6 D5 - - 0 0 1 1 0 1 0 1 - - Table 17. D4 D3 D2 D1 D0 0 0 : 0 0 1 1 : 1 1 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 0 : 1 1 1 1 : 0 0 0 1 : 0 1 1 0 : 1 0 - - - - - - - - - - Gain/attenuation -15 dB -14 dB : -1 dB 0 dB 0 dB +1 dB : +14 dB +15 dB Bass Q factor 1.0 1.25 1.5 2.0 Soft step action Act Wait Subwoofer / middle / bass (12) MSB LSB Function D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 0 1 0 1 - - - - - - - - - - - 0 1 - - - - - 0 0 1 1 0 1 0 1 - - - 0 0 1 1 0 1 0 1 - - - - - - - - - - - - - 0 1 Doc ID 16502 Rev 1 Subwoofer cut-off frequency 55 Hz 85 Hz 120 Hz 160 Hz Subwoofer output phase 180 deg 0 deg Middle center frequency 500 Hz 1000 Hz 1500 Hz 2500 Hz Bass center frequency 60 Hz 80 Hz 100 Hz 200 Hz Bass DC mode On Off 35/40 I2C bus specification Table 18. TDA7718N Speaker attenuation (FL/FR/RL/RR/SWL/SWR) (13-18) MSB LSB Function D7 - 0 1 D6 D5 D4 D3 D2 D1 D0 0 0 : 0 0 0 : 1 1 1 0 0 : 0 0 0 : 0 0 1 0 0 : 0 1 1 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 0 : 1 0 0 : 1 1 x 0 1 : 1 0 1 : 0 1 x - - - - - - - Table 19. Gain/attenuation 0 dB 1 dB : +15 dB -0 dB -1 dB : -78 dB -79 dB mute Soft step action Act Wait Testing audio processor 1 (19) MSB LSB Function D7 - 1. D6 - D5 - D4 D3 D2 D1 - - - - 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 D0 0 1 - - - - - 0 1 - - - - - - 0 1 - - - - - - 0 1 - - - - - - - - The control bit needs both I2C test mode on & sub-address test mode on. 2. The control bit does not depend on test mode. 36/40 Doc ID 16502 Rev 1 Audio processor testing mode Off On Test multiplexer at SE1L (1) SSCLK REQ SMCLK DCDet Vth High DCDet Vth Low IntZeroErr Ref5V5 VGB1.95 Clock200k SDCLK VrefDCO Clock fast mode (2) On Off Clock source (2) External Internal (200 kHz) Attenuator gain clock control (2) On Off I2C bus specification TDA7718N Table 20. Testing audio processor 2 (20) MSB LSB Function D7 - - - - - D6 - D5 - - - - - - - - - D4 - - - 0 0 1 1 0 0 1 1 D3 - - - 0 1 0 1 0 1 0 1 D2 - - 0 1 - - D1 D0 - 0 1 0 1 - - - Test architecture (1) Normal Split - Oscillator clock (2) 400 kHz 800 kHz - Softstep curve (2) S-Curve Linear curve - Manual set busy signal (1) Auto Auto 0 1 - Request for clk generator (1) Allow Allow Stopped Stopped - - 0 1 - - - - - No DCO spike rejection(1) On Off x x - - - - - - Not used 1. The control bit needs sub-address test mode on. 2. The control bit does not depend on test mode. Table 21. Testing audio processor 3 (21) MSB LSB Function D7 - - - D6 - - - D5 - - - D4 - - - D3 - - - D2 - - 0 1 D1 D0 - 0 1 - 0 1 Enable clock for FL/FR/RL/RR/SWL/SWR On Off - Enable clock for volume On Off - Enable clock for treble and bass On Off - - - - 0 1 - - - Enable clock for loudness and middle On Off x x x x - - - - Not used Doc ID 16502 Rev 1 37/40 Package information 6 TDA7718N Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 22. TSSOP28 mechanical data and package dimensions mm inch DIM. MIN. TYP. MAX. A 0.050 A2 0.800 b 0.190 c 0.090 D1 9.600 E E11 k aaa MAX. 0.002 1.050 0.031 0.300 0.007 0.012 0.200 0.004 0.008 9.700 9.800 0.378 0.382 0.386 6.200 6.400 6.600 0.244 0.252 0.260 4.300 4.400 4.500 0.170 0.173 0.177 1.000 0.650 0.450 0.600 OUTLINE AND MECHANICAL DATA 0.047 0.150 e L TYP. 1.200 A1 L1 MIN. 0.006 0.039 0.041 0.026 0.750 1.000 0.018 0.024 0.030 0.039 0˚ (min.), 8˚ (max.) 0.100 0.004 Note: 1. D and E1 does not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch) per side. TSSOP28 Thin Shrink Small Outline Package JEDEC MO-153-AC 0128292 B 38/40 Doc ID 16502 Rev 1 TDA7718N 7 Revision history Revision history Table 22. Document revision history Date Revision 21-Oct-2009 1 Changes Initial release. Doc ID 16502 Rev 1 39/40 TDA7718N Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 40/40 Doc ID 16502 Rev 1