VIPER28 Off-line high voltage converters Datasheet − production data Features ■ 800 V avalanche rugged power section ■ PWM operation with adjustable limiting current ■ 30 mW stand-by power at 265 Vac ■ Operating frequency: – 60 kHz for L type – 115 kHz for H type SDIP10 SO16 narrow Description ■ Frequency jittering for low EMC ■ Output overvoltage protection ■ High primary current protection (2nd OCP) ■ Extra power timer for peak current management ■ On-board soft-start ■ Safe auto-restart after a fault condition ■ Hysteretic thermal shutdown DIP-7 SO 16 The device is an off-line converter with an 800 V rugged power section, a PWM control, two levels of over-current protection, over-voltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. Burst mode operation and device very low consumption help to meet the standby energy saving regulations. Advance frequency jittering reduces EMI filter cost. The extra power timer allows the management of output peak power for a designed time window. Application ■ Auxiliary power supply for consumer and home equipment ■ ATX auxiliary power supply ■ Low / medium power AC-DC adapters ■ SMPS for set-top boxes, DVD players and recorders, white goods The high voltage start-up circuit is embedded in the device. Figure 1. Typical application + + DC input high voltage wide range DC Output voltage DRAIN DRAIN EPT VIPER28 GND Table 1. VDD CONT FB Device summary Order codes Package VIPER28LN / VIPER28HN DIP-7 VIPER28LE / VIPER28HE SDIP10 Packaging Tube VIPER28HD / VIPER28LD SO16 narrow VIPER28HDTR / VIPER28LDTR January 2013 This is information on a product in full production. Tape and reel Doc ID 15028 Rev 5 1/32 www.st.com 32 Contents VIPER28 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 Current mode conversion with adjustable current limit set point . . . . . . . 18 7.8 Overvoltage protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10 Feed-back and overload protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 20 7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 23 7.12 Extra power management function (EPT) . . . . . . . . . . . . . . . . . . . . . . . . 24 7.13 2nd level overcurrent protection and hiccup mode . . . . . . . . . . . . . . . . . . 25 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 Doc ID 15028 Rev 5 VIPER28 Block diagram 1 Block diagram Figure 2. Block diagram VDD DRAIN LEB Internal Supply bus & Ref erence Voltages EPT Tov l BLOCK EPT Tovl SUPPLY & UVLO HV_ON UVLO OSCILLATOR I DDch THERMAL SHUTDOWN OLP SOFT START OCP BLOCK - CONT TURN-ON LOGIC BURST OCP + OVP DETECTION + LOGIC PWM BLOCK LEB R Q S HV_ON R 2nd OCP + + - Q PWM - OVP OTP S Disable 2nd OCP LOGIC OTP OVP OLP Rsense BURST-MODE LOGIC BURST FB GND 2 Typical power Table 2. Typical power 230 VAC Part number VIPER28 85-265 VAC Adapter(1) Open frame(2) Adapter(1) Open frame(2) 18 W 20 W 10 W 12 W 1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient. 2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking. Doc ID 15028 Rev 5 3/32 Pin settings VIPER28 3 Pin settings Figure 3. Connection diagram (top view) Note: The copper area for heat dissipation has to be designed under the DRAIN pins. Table 3. Pin description Pin n. Name Function SDIP10 DIP-7 SO16N 1 1 1...2 GND This pin represents the device ground and the source of the power section. - - 4 N.A. Function: Not available for user. It can be connected to GND (pins 1-2) or left not connected. 2 2 5 VDD Supply voltage of the control section. This pin also provides the charging current of the external capacitor during start-up time. 3 3 6 Control pin. The following functions can be selected: 1. current limit set point adjustment. The internal set default value of the cycleby-cycle current limit can be reduced by connecting to ground an external CONT resistor. 2. output voltage monitoring. A voltage exceeding VOVP threshold (see Table 8 on page 7) shuts the IC down reducing the device consumption. This function is strobed and digitally filtered for high noise immunity. 4 4 7 FB Control input for duty cycle control. Internal current generator provides bias current for loop regulation. A voltage below the threshold VFBbm activates the burst-mode operation. A level close to the threshold VFBlin means that we are approaching the cycle-by-cycle over-current set point. 5 5 8 EPT This pin allows the connection of an external capacitor for the extra power management. If the function is not used, the pin has to be connected to GND. 6...10 7,8 4/32 High voltage drain pin. The built-in high voltage switched start-up bias current 13...16 DRAIN is drawn from this pin too. Pins connected to the metal frame to facilitate heat dissipation. Doc ID 15028 Rev 5 VIPER28 Electrical data 4 Electrical data 4.1 Maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min Max VDRAIN Drain-to-source (ground) voltage V EAV Repetitive avalanche energy (limited by TJ = 150 °C) 3.5 mJ IAR Repetitive avalanche current (limited by TJ = 150 °C) 1 A IDRAIN Pulse drain current (limited by TJ = 150°C) 3 A VCONT Control input pin voltage -0.3 6 V VFB Feed-back voltage -0.3 5.5 V VEPT EPT input pin voltage -0.3 5 V VDD Supply voltage (IDD = 25 mA) -0.3 Self limited V IDD Input current 25 mA Power dissipation at TA < 40 °C (DIP-7) 1 PTOT TJ TSTG 4.2 800 W Power dissipation at TA < 60 °C (SO16N, SDIP-10) 1.5 Operating junction temperature range -40 150 °C Storage temperature -55 150 °C Thermal data Table 5. Thermal data Max value Symbol Parameter Unit SO16N DIP7 SDIP10 RthJP Thermal resistance junction pin (Dissipated power = 1 W) 25 35 35 ° C/W RthJA Thermal resistance junction ambient (Dissipated power = 1 W) 60 100 80 ° C/W RthJA Thermal resistance junction ambient (1) (Dissipated power = 1 W) 50 80 65 ° C/W 1. When mounted on a standard single side FR4 board with 100 mm2 (0.155 sq in) of Cu (35 µm thick) Doc ID 15028 Rev 5 5/32 Electrical data 4.3 VIPER28 Electrical characteristics (TJ = -25 to 125 °C, VDD = 14 V (a); unless otherwise specified) Table 6. Power section Symbol Parameter VBVDSS Break-down voltage IOFF RDS(on) Test condition Min Typ Max Unit IDRAIN = 1 mA, VFB = GND, TJ = 25 °C 800 V OFF state drain current VDRAIN = max rating,VFB = GND, TJ = 25°C 60 μA Drain-source on state resistance IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 25 °C 7 Ω IDRAIN = 0.4 A, VFB = 3 V, VEPT = GND, TJ = 125 °C 14 Ω COSS Effective (energy related) output capacitance Table 7. Supply section Symbol VDRAIN = 0 to 640 V, TJ = 25°C Parameter Test condition 40 pF Min Typ Max Unit 60 80 100 V -2 -3 -4 mA -0.4 -0.6 -0.8 mA 23.5 V Voltage VDRAIN_START Drain-source start voltage VDRAIN = 120 V, VEPT = GND, IDDch Start up charging current VFB = GND, VDD = 4 V VDRAIN = 120 V, VEPT = GND, VFB = GND, VDD = 4 V after fault VDD VDDclamp Operating voltage range After turn-on 8.5 VDD clamp voltage IDD = 20 mA 23.5 VDDon VDD start up threshold VDDoff VDD under voltage shutdown threshold VDD(RESTART) VDD restart voltage threshold VDRAIN = 120 V, VEPT = GND, VFB = GND VDRAIN = 120 V, VEPT = GND, VFB = GND V 13 14 15 V 7.5 8 8.5 V 4 4.5 5 V Current IDD0 Operating supply current, not switching VFB = GND, FSW = 0 kHz VEPT = GND, VDD = 10 V 0.9 mA IDD1 Operating supply current, switching VDRAIN = 120 V, FSW = 60 kHz 2.5 mA VDRAIN = 120 V,FSW = 115 kHz 3.5 mA IDD_FAULT Operating supply current, with protection tripping VDD = 10 V 400 uA IDD_OFF Operating supply current with VDD < VDD_OFF VDD = 7 V 270 uA a. Adjust VDD above VDDon start-up threshold before setting to 14 V 6/32 Doc ID 15028 Rev 5 VIPER28 Table 8. Electrical data Controller section Symbol Parameter Test condition Min Typ Max Unit Feed-back pin VFBolp Over-load shut down threshold 4.5 4.8 5.2 V VFBlin Linear dynamics upper limit 3.2 3.5 3.7 V VFBbm Burst mode threshold Voltage falling 0.6 V VFBbmhys Burst mode hysteresis Voltage rising 100 mV IFB RFB(DYN) HFB Feed-back sourced current VFB = 0.3 V -150 3.3 V < VFB < 4.8 V Dynamic resistance VFB < 3.3 V ΔVFB / ΔID -200 -280 -3 uA uA 14 20 kΩ 2 6 V/A CONT pin VCONT_l Low level clamp voltage ICONT = -100 µA VCONT_h High level clamp voltage ICONT = 1mA 0.5 V 5 5.5 6 V 0.75 0.80 0.85 A Current limitation IDlim Max drain current limitation tSS Soft-start time TON_MIN td tLEB ID_BM VFB = 4 V, ICONT = -10 µA TJ = 25 °C 8.5 Minimum turn ON time 220 400 ms 480 ns Propagation delay 100 ns Leading edge blanking 300 ns Peak drain current during burst mode VFB = 0.6 V 160 mA Oscillator section FOSC FD VIPER28L VIPER28H Modulation depth FM Modulation frequency DMAX Maximum duty cycle VDD = operating voltage range, VFB = 1 V 54 60 66 kHz 103 115 127 kHz VIPER28L ±4 kHz VIPER28H ±8 kHz 250 Hz 70 Doc ID 15028 Rev 5 80 % 7/32 Electrical data Table 8. VIPER28 Controller section (continued) Symbol Parameter Test condition Min Typ Max Unit Over-current protection (2nd OCP) IDMAX Second over-current threshold 1.2 A Over-voltage protection VOVP TSTROBE Over-voltage protection threshold 2.7 Over-voltage protection strobe time 3 3.3 V 2.2 us 85% IDlim A 4 V 0.6 V 5 μA 160 °C 30 °C Extra power management IDLIM_EPT Drain current limit with EPT function VEPT(STOP) EPT shut down threshold VEPT(RESTART) EPT restart threshold IEPT Sourced EPT current ICONT < -10 μA TJ = 25 °C ICONT < -10 μA Thermal shutdown TSD THYST 8/32 Thermal shutdown temperature 150 Thermal shutdown hysteresis Doc ID 15028 Rev 5 VIPER28 Electrical data Figure 4. Minimum turn-on time test circuit VDRAIN 14 V GND DRAIN VDD DRAIN 90 % TONmin 50 Ω CONT 10 % IDRAIN EPT FB 30 V 3.5 V Time IDLIM Time Figure 5. OVP threshold test circuits VCONT 14 V GND DRAIN VDD DRAIN CONT FB VOVP 10 kΩ VDRAIN EPT Time 30 V 2V Time Note: Adjust VDD above VDDon start-up threshold before setting to 14 V Doc ID 15028 Rev 5 9/32 Typical electrical characteristics VIPER28 5 Typical electrical characteristics Figure 6. Current limit vs TJ Figure 7. Switching frequency vs TJ Figure 8. Drain start-up voltage vs TJ Figure 9. HFB vs TJ Figure 10. Operating supply current (no switching) vs TJ 10/32 Figure 11. Operating supply current (switching) vs TJ Doc ID 15028 Rev 5 VIPER28 Typical electrical characteristics Figure 12. Current limit vs RLIM Figure 13. Power MOSFET on-resistance vs TJ Figure 14. Power MOSFET break down voltage vs TJ Doc ID 15028 Rev 5 11/32 Typical electrical characteristics VIPER28 Figure 15. Thermal shutdown VDD VDDon VDDoff VDD(RESTART) time IDRAIN time TJ TSD TSD - THYST Normal operation 12/32 Shut down after over temperature Doc ID 15028 Rev 5 Normal operation time VIPER28 6 Typical circuit Typical circuit Figure 16. Min-features flyback application EPT Figure 17. Full-feature flyback application EPT Doc ID 15028 Rev 5 13/32 Operation descriptions 7 VIPER28 Operation descriptions The device is a high-performance low-voltage PWM controller chip with an 800 V, avalanche rugged Power section. The controller includes: the oscillator with jittering feature, the start up circuits with soft-start feature, the PWM logic, the current limit circuit with adjustable set point, the second overcurrent circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the auto-restart circuit and the thermal protection circuit. The current limit set-point is set by the CONT pin. The burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment. All the fault protections are built in auto restart mode with very low repetition rate to prevent IC's over heating. 7.1 Power section and gate driver The power section is implemented with an avalanche ruggedness N-channel MOSFET, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. The power section has a BVDSS of 800 V min. and a typical RDS(on) of 7 Ω at 25 ° C. The integrated SenseFET structure allows a virtually loss-less current sensing. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 High voltage startup generator The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VDRAIN_START threshold, 80 VDC typically. When the HV current generator is ON, the IDDch current (3 mA typical value) is delivered to the capacitor on the VDD pin. In case of auto restart mode after a fault event, the IDDch current is reduced to 0.6 mA, in order to have a slow duty cycle during the restart phase. 14/32 Doc ID 15028 Rev 5 VIPER28 7.3 Operation descriptions Power-up and soft-start up If the input voltage rises up till the device start threshold, VDRAIN_START, the VDD voltage begins to grow due to the IDDch current (see Table 7 on page 6) coming from the internal high voltage start up circuit. If the VDD voltage reaches VDDon threshold (see Table 7 on page 6) the power MOSFET starts switching and the HV current generator is turned OFF. See Figure 18 on page 15. The IC is powered by the energy stored in the capacitor on the VDD pin, CVDD, until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than VDDoff threshold. In fact, a too low capacitance value could terminate the switching operation before the controller receives any energy from the auxiliary winding. The following formula can be used for the VDD capacitor calculation: Equation 1 I DDch × tSSaux C VDD = ---------------------------------------V DDon – V DDoff The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). During the converter start up time, the drain current limitation is progressively increased to the maximum value. In this way the stress on the secondary diode is considerably reduced. It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the feature is implemented for every attempt of start up converter or after a fault. Figure 18. IDD current during start-up and burst mode VDD VDDon VDDoff t VFB VFBolp VFBlin VFBbmhys VFBbm t VDRAIN t IDD IDD1 IDD0 t IDDch (-3 mA) START- UP NORMAL MODE Doc ID 15028 Rev 5 BURST MODE NORMAL MODE 15/32 Operation descriptions VIPER28 Figure 19. Timing diagram: normal power-up and power-down sequences VIN VIN < VDRAIN_START HV startup is no more activated VDRAIN_START VDD regulation is lost here time VDDon VDDoff VDD(RESTART) VDRAIN time IDD time IDDch (3mA) Power-off Normal operation Power-on Figure 20. Soft-start: timing diagram IDRAIN IDlim tSS (soft start) t VFB TOLP-delay VFBolp VFBlin VOUT t Regulated value t 16/32 Doc ID 15028 Rev 5 time VIPER28 7.4 Operation descriptions Power down operation At converter power down, the system loses regulation as soon as the input voltage is so low that the peak current limitation is reached. The VDD voltage drops and when it falls below the VDDoff threshold (see Table 7 on page 6) the power MOSFET is switched OFF, the energy transfers to the IC interrupted and consequently the VDD voltages decreases, Figure 19 on page 16. Later, if the VIN is lower than VDRAIN_START (see Table 7 on page 6), the start up sequence is inhibited and the power down completed. This feature is useful to prevent converter’s restart attempts and ensures monotonic output voltage decay during the system power down. 7.5 Auto restart operation If after a converter power down, the VIN is higher than VDRAIN_START, the start up sequence is not inhibited and will be activated only when the VDD voltage drops down the VDD(RESTART) threshold (see Table 7 on page 6). This means that the HV start up current generator restarts the VDD capacitor charging only when the VDD voltage drops below VDD(RESTART). The scenario above described is for instance a power down because of a fault condition. After a fault condition, the charging current, IDDch, is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter phase. This feature together with the low VDD(RESTART) threshold ensures that, after a fault, the restart attempts of the IC has a very long repetition rate and the converter works safely with extremely low power throughput. The Figure 21 shows the IC behavioral after a short-circuit event. Figure 21. Timing diagram: behavior after short-circuit V DD Short circuit occurs here VDDon VDDoff V DD(RESTART) V FB time VFBolp V FBlin TREPETITION VDS time = 0.3 x TREPETITION IDD time I DDch (0.6mA) time 7.6 Oscillator The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz (115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of sideband harmonics having the same energy on the whole but smaller amplitudes. Doc ID 15028 Rev 5 17/32 Operation descriptions 7.7 VIPER28 Current mode conversion with adjustable current limit set point The device is a current mode converter: the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. This voltage is compared with the one on the feed-back pin through a voltage divider on cycle by cycle basis. The device has a default current limit value, IDlim, that the designer can adjust according the electrical specification, by the RLIM resistor connected to the CONT, see Figure 12 on page 11. The CONT pin has a minimum current sunk needed to activate the IDlim adjustment: without RLIM or with high RLIM (i.e. 100 kΩ) the current limit is fixed to the default value (see IDlim, Table 8 on page 7). 7.8 Overvoltage protection (OVP) The device has integrated the logic for the monitor of the output voltage using as input signal the voltage VCONT during the OFF time of the power MOSFET. This is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio N AUX -------------N SEC The CONT pin has to be connected to the auxiliary winding through the diode DOVP and the resistors ROVP and RLIM as shows the Figure 23 on page 20 When, during the OFF time, the voltage VCONT exceeds, four consecutive times, the reference voltage VOVP (see Table 8 on page 7) the overvoltage protection will stop the power MOSFET and the converter enters the auto-restart mode. In order to bypass the noise immediately after the turn off of the power MOSFET, the voltage VCONT is sampled inside a short window after the time TSTROBE, see Table 8 on page 7 and the Figure 22 on page 19. The sampled signal, if higher than VOVP, trigger the internal OVP digital signal and increments the internal counter. The same counter is reset every time the signal OVP is not triggered in one oscillator cycle. Referring to the Figure 23, the resistors divider ratio kOVP will be given by: Equation 2 V OVP k OVP = ----------------------------------------------------------------------------------------------------N AUX -------------- ⋅ ( VOUTOVP + V DSEC ) – VDAUX N SEC Equation 3 R LIM k OVP = --------------------------------R LIM + R OVP 18/32 Doc ID 15028 Rev 5 VIPER28 Operation descriptions Where: ● VOVP is the OVP threshold (see Table 8 on page 8) ● VOUT OVP is the converter output voltage value to activate the OVP set by designer ● NAUX is the auxiliary winding turns ● NSEC is the secondary winding turns ● VDSEC is the secondary diode forward voltage ● VDAUX is the auxiliary diode forward voltage ● ROVP together RLIM make the output voltage divider Than, fixed RLIM, according to the desired IDlim, the ROVP can be calculating by: Equation 4 1 – kOVP R OVP = R LIM × ----------------------k OVP The resistor values will be such that the current sourced and sunk by the CONT pin be within the rated capability of the internal clamp. Figure 22. OVP timing diagram VDS t VAUX 0 VCONT t V OVP t TSTROBE STROBE Sampling time t OVP t COUNTER RESET COUNTER STATUS t 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 FAULT 3 →4 t NORMAL OPERATION TEMPORARY DISTURBANCE Doc ID 15028 Rev 5 FEEDBACK LOOP FAILURE t 19/32 Operation descriptions 7.9 VIPER28 About CONT pin Referring to the Figure 23, through the CONT pin, the below features can be implemented: 1. Current limit set point 2. Overvoltage protection on the converter output voltage The Table 9 on page 20 referring to the Figure 23, lists the external components needed to activate one or plus of the CONT pin functions. Figure 23. CONT pin configuration R OV P CONT SOFT START OCP BLOCK - Daux + Auxiliary winding OVP LOGIC R LIM OCP to GATE driver From RSENSE OVP Table 9. CONT pin configurations Function / component RLIM (1) ROVP DAUX IDlim reduction See Figure 12 No No OVP ≥ 80 kΩ See Equation 4 Yes IDlim reduction + OVP See Figure 12 See Equation 4 Yes 1. RLIM has to be fixed before of ROVP 7.10 Feed-back and overload protection (OLP) The device is a current mode converter: the feedback pin controls the PWM operation, controls the burst mode and actives the overload protection. Figure 24 on page 22 and Figure 25 show the internal current mode structure. With the feedback pin voltage between VFBbm and VFBlin, (see Table 8 on page 7) the drain current is sensed and converted in voltage that is applied to the non inverting pin of the PWM comparator. See Figure 2 on page 3. This voltage is compared with the one on the feedback pin through a voltage divider on cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch off of the power MOSFET. The drain current is always limited to IDlim value. In case of overload the feedback pin increases in reaction to this event and when it goes higher than VFBlin, the PWM comparator is disabled and the drain current is limited to IDlim by the OCP comparator, seeFigure 2 on page 3. 20/32 Doc ID 15028 Rev 5 VIPER28 Operation descriptions When the feedback pin voltage reaches the threshold VFBlin an internal current generator starts to charge the feedback capacitor (CFB) and when the feedback voltage reaches the VFBolp threshold, the converter is turned off and the start up phase is activated with reduced value of IDDch to 0.6 mA, see Table 7 on page 6. During the first start up phase of the converter, after the soft-start up time, tSS, the output voltage could force the feedback pin voltage to rise up to the VFBolp threshold that switches off the converter itself. To avoid this event, the appropriate feedback network has to be selected according to the output load. More the network feedback fixes the compensation loop stability. The Figure 24 on page 22 and Figure 25 show the two different feedback networks. The time from the overload detection (VFB = VFBlin) to the device shutdown (VFB = VFBolp) can be set by CFB value (see Figure 24 on page 22 and Figure 25), using the formula: Equation 5 V FBolp – V FBlin T OLP – delay = C FB × ---------------------------------------3μA In the Figure 24, the capacitor connected to FB pin (CFB) is part of the compensation circuit as well as it needs to activate the overload protection (see equation 5). After the start up time, tSS, during which the feedback voltage is fixed at VFBlin, the output capacitor could not be at its nominal value and the controller interprets this situation as an overload condition. In this case, the OLP delay helps to avoid an incorrect device shut down during the start up phase. Owing to the above considerations, the OLP delay time must be long enough to by-pass the initial output voltage transient and check the overload condition only when the output voltage is in steady state. The output transient time depends from the value of the output capacitor and from the load. When the value of the CFB capacitor calculated for the loop stability is too low and cannot ensure enough OLP delay, an alternative compensation network can be used and it is showed in Figure 25 on page 22. Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are introduced by the capacitors CFB and CFB1 and the resistor RFB1. The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole is usually used to compensate the high frequency zero due to the ESR (equivalent series resistor) of the output capacitance of the fly-back converter. The mathematical expressions of these poles and zero frequency, considering the scheme in Figure 25 are reported by the equations below: Equation 6 1 f ZFB = ------------------------------------------------------2 ⋅ π ⋅ C FB1 ⋅ RFB1 Doc ID 15028 Rev 5 21/32 Operation descriptions VIPER28 Equation 7 R FB ( DYN ) + R FB1 fPFB = -----------------------------------------------------------------------------------------2 ⋅ π ⋅ C FB ⋅ ( R FB ( DYN ) ⋅ R FB1 ) Equation 8 1 f PFB = --------------------------------------------------------------------------------------------2 ⋅ π ⋅ C FB1 ⋅ ( R FB1 ⋅ R FB ( DYN ) ) The RFB(DYN) is the dynamic resistance seen by the FB pin. The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The Equation 5 can be still used to calculate the OLP delay time but CFB1 has to be considered instead of CFB. Using the alternative compensation network, the designer can satisfy, in all case, the loop stability and the enough OLP delay time alike. Figure 24. FB pin configuration (option 1) From sense FET PWM To PWM Logic + PWM CONTROL - Cfb BURST BURST-MODE LOGIC BURST-MODE REFERENCES OLP comparator To disable logic + - 4.8V Figure 25. FB pin configuration (option 2) From sense FET PWM To PWM Logic + PWM CONTROL - Rfb1 Cfb BURST Cfb1 BURST-MODE REFERENCES BURST-MODE LOGIC OLP comparator + 4.8V 22/32 Doc ID 15028 Rev 5 - To disable logic VIPER28 7.11 Operation descriptions Burst-mode operation at no load or very light load When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it falls down the burst mode threshold, VFBbm, the power MOSFET is not more allowed to be switched on. After the MOSFET stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding the level, VFBbm + VFBbmhys, the power MOSFET starts switching again. The burst mode thresholds are reported on Table 8 and Figure 26 shows this behavior. Systems alternates period of time where power MOSFET is switching to period of time where power MOSFET is not switching; this device working mode is the burst mode. The power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. The advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode the drain current peak is clamped to the level, ID_BM, reported on Table 8. Figure 26. Burst mode timing diagram, light load management VCOMP VFBbm +VFBbmhys VFBbm time IDD IDD1 IDD0 time IDRAIN ID_BM time Burst Mode Doc ID 15028 Rev 5 23/32 Operation descriptions 7.12 VIPER28 Extra power management function (EPT) Some applications need an extra power for a limited time window during which the converter regulation has to be guaranteed. The extra power management function allows to design a converter that can satisfy this request and is provided by the EPT pin, see Table 8 on page 8. This function requires the use of a capacitor on EPT pin (CEPT) that is charged or discharged by means of a 5 µA current cycle by cycle. When the drain current raises over 85% of Idlim value, see IDLIM_EPT (Table 8 on page 7), the current generator charges CEPT while when the drain current is below IDLIM_EPT discharges the capacitor. If CEPT ‘s voltage reaches the VEPT threshold (typical, 4 V), the converter is shut down. After the converter shut down, the VDD voltage will drop below the VDD(ON) start up threshold (typ. 14.5 V) and according to the auto restart operation (see Section 7.5 on page 17) the VDD pin voltage have to fall below the VDD(RESTART) threshold (typical, 4.5 V) in order to charge again the VDD capacitor. Moreover the PWM operation is enabled again only when the voltage on EPT pin, drop below the VEPT(RESTART) (typical, 0.6 V). The low CEPT discharge current in combination with its low restart threshold, ensures safe operations and avoids overheating in case of repeated overload events. The value of CEPT has to be selected in order to prevent the device overheating. The EPT pin can be connected to GND if the function is not used. 24/32 Doc ID 15028 Rev 5 VIPER28 7.13 Operation descriptions 2nd level overcurrent protection and hiccup mode The device is protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturation of fly-back transformer. Such as anomalous condition is invoked when the drain current exceed the threshold IDMAX, see Table 8 on page 7. To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a “warning state” is entered after the first signal trip. If in the subsequent switching cycle the signal is not tripped, a temporary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the IDMAX threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power MOSFET is turned OFF. The shutdown condition is latched as long as the device is supplied. While it is disabled, no energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor decays till the VDD under voltage threshold (VDDoff), which clears the latch. The start up HV current generator is still off, until VDD voltage goes below its restart voltage, VDD(RESTART). After this condition the VDD capacitor is charged again by 600 µA current, and the converter switching restarts if the VDDon occurs. If the fault condition is not removed the device enters in auto-restart mode. This behavioral results in a low-frequency intermittent operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing diagram of Figure 27. Figure 27. Hiccup-mode OCP: timing diagram Secondary diode short circuit VDD VDDon VDDoff VDD(RESTART) IDRAIN time IDMAX time VDRAIN time Normal operation Hiccup-mode Doc ID 15028 Rev 5 25/32 Package mechanical data 8 VIPER28 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 10. DIP-7 mechanical data mm Dim. Typ Min A 5,33 A1 0,38 A2 3,30 2,92 4,95 b 0,46 0,36 0,56 b2 1,52 1,14 1,78 c 0,25 0,20 0,36 D 9,27 9,02 10,16 E 7,87 7,62 8,26 E1 6,35 6,10 7,11 e 2,54 eA 7,62 eB L M (6)(8) N 10,92 3,30 2,92 3,81 0,40 0,60 2,508 0,50 N1 O (7)(8) 0,60 0,548 1- The leads size is comprehensive of the thickness of the leads finishing material. 2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3- Package outline exclusive of metal burrs dimensions. 4- Datum plane “H” coincident with the bottom of lead, where lead exits body. 5- Ref. POA MOTHER doc. 0037880 6- Creepage distance > 800 V 7- Creepage distance 250 V 8- Creepage distance as shown in the 664-1 CEI / IEC standard. 26/32 Max Doc ID 15028 Rev 5 VIPER28 Package mechanical data Figure 28. Package dimensions Doc ID 15028 Rev 5 27/32 Package mechanical data Table 11. VIPER28 SO16 narrow mechanical data mm Dim. Min. Typ. A 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 0.25 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 28/32 Max. 0.1 Doc ID 15028 Rev 5 VIPER28 Package mechanical data Figure 29. SO16 narrow mechanical data Doc ID 15028 Rev 5 29/32 Package mechanical data Table 12. VIPER28 SDIP10 mechanical data mm Dim. Min. Typ. A 5.33 A1 0.38 A2 2.92 4.95 b 0.36 0.56 b2 0.51 1.15 c 0.2 0.36 D 9.02 10.16 E 7.62 8.26 E1 6.1 7.11 E2 7.62 E3 10.92 e L 1.77 2.92 Figure 30. SDIP10 mechanical drawing 30/32 Max. Doc ID 15028 Rev 5 3.81 VIPER28 9 Revision history Revision history Table 13. Document revision history Date Revision 30-Sep-2008 1 Initial release 22-Jan-2009 2 Updated Figure 3 on page 4 21-Oct-2009 3 Added SO16N and SDIP10 packages 31-Aug-2010 4 Updated Figure 3, Figure 4, Figure 5 on page 9 and Table 3 on page 4 5 Minor text changes to improve readability in Chapter 7.3, Chapter 7.4, Chapter 7.5, Chapter 7.7, Chapter 7.8, Chapter 7.9, Chapter 7.10, Chapter 7.11, Chapter 7.13, in Table 7 on page 6, Table 8 on page 7 and in Figure 22 on page 19 08-Jan-2013 Changes Doc ID 15028 Rev 5 31/32 VIPER28 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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