UNISONIC TECHNOLOGIES CO., LTD PA3332 Preliminary CMOS IC 2.6W STEREO AUDIO AMPLIFIER DESCRIPTION The UTC PA3332 is a stereo audio power amplifier. When the device is idle, it enters SHDN mode for some low current consumption applications. The current dissipation is thus reduced below 5μA. Mute function is included to mute the output. Operating on a 5V power supply, the UTC PA3332 is capable of driving a 4.0 Ω BTL load at a continuous average RMS output of 2.0W per channel with a less than 1% THD.％ There are two input paths, therefore, two different gain loops can be set in the same PCB. We could choose one of the two gain paths through the logic level of IN/IN pin. This increases the flexibility of the hardware design. In order to prevent the speakers from burned-out, the UTC PA3332 also has a function of maximum output power clamping is designed. FEATURES * Including de-pop circuit * Output power at 1% THD+N, VDD=5V 2.0W/CH (TYP.) into a 4Ω Load 1.3W/CH (TYP.) into a 8Ω Load * Output power at 10% THD+N, VDD=5V 2.6W/CH (typical) into a 4Ω Load 1.6W/CH (typical) into a 8Ω Load * BTL mode (Bridge-Tied Load) * Maximum output power clamping circuitry contained * Mute and shutdown control available * Stereo input MUX * Halogen Free ORDERING INFORMATION Ordering Number Lead Free Halogen Free PA3332L-N24-T PA3332G-N24-T PA3332L-N24-R PA3332G-N24-R www.unisonic.com.tw Copyright © 2010 Unisonic Technologies Co., Ltd Package Packing HTSSOP-24 HTSSOP-24 Tube Tape Reel 1 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC PIN CONFIGURATION Note: Recommend connecting the Thermal Pad to the GND for excellent power dissipation. PIN DESCRIPTION PIN NO. 1, 12, 13, 24 2, 9, 11 3 4 5 6 7 PIN NAME 8 SHUTDOWN 10 14 15 LOUTMUTE ROUTIN1/IN2 16 GND/HS Ground connection for circuitry, directly connected to thermal pad. NC LOUT+ LIN1 LIN2 LBPASS LVDD Embedded test mode pin, please keep it floating. Left channel + output in BTL mode Left channel IN1 input, selected when IN1 /IN2 pin is held low. Left channel IN2 input, selected when IN1 /IN2 pin is held high. Connect to voltage divider for left channel internal mid-supply bias. Supply voltage input for left channel and for primary bias circuits. Shutdown mode control signal input, places entire IC in shutdown mode when held high, IDD< 5µA. Left channel - output in BTL mode. Mode control signal input, hold low for activation, hold high for mute. Right channel - output in BTL mode MUX control input, hold high to select in2 inputs (5,20), hold low to select in1 inputs (4,21). Ground connection for circuitry. Supply voltage input for right channel. Connect to voltage divider for right channel internal mid-supply bias. Right channel in2 input, selected when IN1 /IN2 pin is held high. Right channel in1 input, selected when IN1 /IN2 pin is held low. Right channel + output in BTL mode The output power can be clamped by setting a low bound voltage to this pin. The high bound voltage will be generated internally. The output voltage will be clamped between high/low bound voltages. Then the output power is lim-ited. It is weakly pull-low internally, let this pin floating or tied to GND can deactivate this function. 17 18 19 20 21 22 GND RVDD RBYPASS RIN2 RIN1 ROUT+ 23 VOL Thermal Pad DESCRIPTION Recommend connecting the Thermal Pad to the GND for excellent power dissipation. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC BLOCK DIAGRAM 21 20 19 RIN1 RIN2 RIGHT MUX RBYPASS - ROUT+ + ROUT- 15 RVDD 14 MUTE Bias, Mute, Shutdown, and MUX Control 8 SHUTDOWN 23 VOL 22 18 IN1/IN2 16 LVDD 7 6 LBYPASS + 5 4 LIN2 LIN1 LEFT MUX UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw - LOUTLOUT+ 10 3 3 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT Supply Voltage VDD 6 V Input Voltage VIN -0.3~VDD+0.3 V Operating Ambient Temperature TA -40 ~ +85 °C Junction Temperature TJ 150 °C Storage Temperature TSTG -65 ~ +150 °C Reflow Temperature (soldering, 10sec) 260 °C TA ≤ 25°C 2.7 PD Power Dissipation (Note 2) W TA ≤ 70°C 1.7 TA ≤ 85°C 1.4 Electrostatic Discharge VESD -3000 ~ 3000 (Note 3) V Human Body Mode Notes: 1. Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. 2. Recommended PCB Layout 3. Human body model : C = 100pF, R = 1500Ω, 3 positive pulses plus 3 negative pulses UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 4 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL DC Electrical Characteristics (TA=+25°C) TEST CONDITIONS MIN VDD =3.3V Stereo BTL VDD = 5V Stereo BTL DC Differential Output Voltage VO(DIFF) VDD = 5V,Gain = 2 IDD in Shutdown ISD VDD = 5V AC Operation Characteristics (VDD = 5.0V, TA=+25°C, RL = 4Ω, unless otherwise noted) THD = 1%, BTL, RL = 4Ω THD = 1%, BTL, RL = 8Ω Output Power (Note 1) POUT THD = 10%, BTL, RL = 4Ω THD = 10%, BTL, RL = 8Ω PO = 1.6W, BTL, RL = 4Ω Total Harmonic Distortion Plus Noise THD+N PO = 1W, BTL, RL = 8Ω VI = 1V, RL = 10KΩ, G = 1 Max Output Power Bandwidth BOM G = 1, THD = 1% Phase Margin RL = 4Ω, Open Load Power Supply Ripple Rejection PSRR f = 120Hz Mute Attenuation Channel-To-Channel Output f = 1kHz Separation IN1/IN2 Input Separation Input Impedance ZI Signal-To-Noise Ratio PO = 500mW, BTL Output Noise Voltage Vn Output noise voltage AC Operation Characteristics (VDD =3.3V, TA=+25°C, RL = 4Ω, unless otherwise noted) THD = 1%, BTL, RL = 4Ω THD = 1%, BTL, RL = 8Ω Output Power (Note 1) POUT THD = 10%, BTL, RL = 4Ω THD = 10%, BTL, RL = 8Ω PO = 0.7W, BTL, RL = 4Ω Total Harmonic Distortion Plus Noise THD+N PO = 0.45W, BTL, RL = 8Ω VI = 1V, RL = 10KΩ, G = 1 Max Output Power Bandwidth BOM G = 1, THD = 1% Phase Margin RL = 4Ω, Open Load Power Supply Ripple Rejection PSRR f = 120Hz Mute Attenuation Channel-To-Channel Output f = 1kHz Separation IN1/IN2 Input Separation Input Impedance ZI Signal-To-Noise Ratio PO = 500mW, BTL Output Noise Voltage Vn Output noise voltage Note 1: Output power is measured at the output terminals of the IC at 1kHz. Supply Current in Mute Mode IDD(MTE) UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw TYP MAX 7 8 5 2 13 16 50 5 UNIT mA mV μA 2.0 1.3 2.6 1.6 100 60 10 20 60 65 90 m% 80 dB 80 2 90 55 dB MΩ dB μV(rms) W kHz ° dB dB 0.85 0.55 1.1 0.7 270 100 10 20 60 65 90 m% 80 dB 80 2 90 55 dB MΩ dB μV(rms) W kHz ° dB dB 5 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC APPLICATION INFORMATION Input MUX Operation For the UTC PA3332, there exist two input signal paths (IN1 and IN2). Thus, for different input sources, the UTC PA3332 has different gains with this prompt setting. When the IN1 / IN2 pin is in active high, this device operates in IN2 input source; when it is in active low, this device operates in IN1 input source. Bridged-Tied Load Mode Operation The following figure A shows the BTL (Bridged-Tied Load) mode operation. The two linear amplifiers drive both ends of the speaker load. There are several advantages for using the BTL mode: first of all, the differential driving to the speaker load means that when one side is slewing up, the other side is slewing down, and vice versa. The voltage swing on the load is two times that on a ground reference load. In this mode, the peak-to-peak voltage VO(PP) on the load will be double a ground reference configuration. 4 times output power on the load will be generated at the same power supply rail and loading due to the voltage on the load is doubled. Further more, this BTL operation can cancel the dc offsets which save the using of dc coupling capacitor that is needed to cancel dc offsets in the ground reference configuration. Then the input network and speaker responses can only limit the low-frequency performance. Moreover, the saving of dc coupling capacitors can minimize PCB space and the cost. MUTE and SHUTDOWN Mode Operations Circuits with mute and shutdown functions are contained in the UTC PA3332, which is designed to reduce IDD (supply current) to the absolute minimum level during nonuse periods for battery-power conservation. When pulling the shutdown pin (pin 8) high, all linear amplifiers will be deactivated to mute the amplifier outputs. Then the device enters an extremely low current consumption condition, the supply current is less than 5µA. When the mute pin (pin 14) is pulled high, it will force the activated linear amplifier to supply the VDD/2 dc voltage on the output & shutdown the second linear amplifiers to mute the AC performance. The current dissipation will be smaller in the mute mode operation than that in the BTL mode. It is not allowed to leave the shutdown and mute pins floating, or unexpected conditions would occur for the amplifier operations. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC Maximum Power Clampping Function The UTC PA3332 incorporated the maximum power clamping function that effectively reduces damage the speaker due to the larger power through the speaker. The Vol pin (pin 23) is weakly pull-low internally. If a non-zero voltage applies in the Vol pin, the UTC PA3332 will generate a high boundary voltage which the difference between the VDD/2 and the high boundary voltage is the same as the difference between the VDD/2 and the low boundary voltage. (i.e. VOH – VDD/2 = VDD/2 – VOL). Then the outputs of linear amplifiers will be effectively limited between the high/low boundary voltage, the maximum output power is clamped. Thus, the maximum power is controlled perfectively by means of setting the value of Vol, Note that if this function is not used, the Vol pin should be connected to the GND or be floated. Optimizing DEPOP Operation The UTC PA3332 contains a circuit that can reduce poping to minimum during the power-up or shutdown mode. The poping can be generated as long as a voltage step is applied to the speaker and the differential voltage generated at the two ends of the speaker. To get a minimum poping, the bypass capacitor is critical, 1/(CBx100kΩ) ≦ 1/(CI*(RI+RF)). (Where CB is the mid-rail bypass capacitor, 100kΩ is the output impedance of the mid-rail generator, RI is the input impedance, CI is the input coupling capacitor, RF is the gain setting impedance which is on the feedback path. CB is the most important capacitor. It can be applied in reducing the poping together with determining the rate at which the amplifier starts up during startup or recovery from shutdown mode.) The Figure B shows the de-poping circuit for the UTC PA3332. The PNP transistor effectively controls the voltage drop across the 50kΩ by slewing the internal node slowly when power is applied. At start-up, the voltage at BYPASS capacitor is zero. The PNP is ON to pull the mid-point of the bias circuit down. So the capacitor sees a lower effective voltage, and thus the charging is slower. This appears as a linear ramp (while the PNP transistor is conducting), followed by the expected exponential ramp of an RC circuit. VDD 100kΩ Bypass 50kΩ 100kΩ Figure B. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 10 QW-R502-488.A PA3332 Preliminary TEST CIRCUIT TYPICAL APPLICATION CIRCUIT CMOS IC Logical Truth Table Mute X Low Low High High 1IN /IN2 X Low High Low High Shutdown High Low Low Low Low Input X L/R IN1 L/R IN2 L/R IN1 L/R IN2 OUTPUT L/R Out+ L/R OutOutput Output Output Output Output Output - UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw Mode Shutdown (Mute) BTL BTL Mute Mute 8 of 10 QW-R502-488.A PA3332 Preliminary UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw CMOS IC 9 of 10 QW-R502-488.A PA3332 Preliminary CMOS IC UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 10 of 10 QW-R502-488.A