TI MSP430F2131IDGV

SLAS439 − SEPTEMBER 2004
D
D
D
D
D
D Serial Onboard Programming,
− Active Mode: 200 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Ultrafast Wake-Up From Standby Mode in
less than 1 µs
16-Bit RISC Architecture, 65 ns
Instruction Cycle Time
Basic Clock Module Configurations:
− Internal Frequencies up to 16MHz
− 32-kHz Crystal
− High-Frequency Crystal up to 16MHz
− Resonator
− External Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Bootstrap Loader in Flash Devices
Family Members Include:
MSP430F2101: 1KB + 256B Flash Memory
128B RAM
MSP430F2111: 2KB + 256B Flash Memory
128B RAM
MSP430F2121: 4KB + 256B Flash Memory
256B RAM
MSP430F2131: 8KB + 256B Flash Memory
256B RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin Plastic
Small-Outline Thin (TSSOP) Package,
20-Pin TVSOP and 24-Pin QFN
For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.
The MSP430x21x1 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile
analog comparator and sixteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application. The analog comparator provides slope A/D conversion capability.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
−40°C to 85°C
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
PLASTIC
20-PIN TVSOP
(DGV)
PLASTIC
24-PIN QFN
(RGE)
MSP430F2101IDW
MSP430F2111IDW
MSP430F2121IDW
MSP430F2131IDW
MSP430F2101IPW
MSP430F2111IPW
MSP430F2121IPW
MSP430F2131IPW
MSP430F2101IDGV
MSP430F2111IDGV
MSP430F2121IDGV
MSP430F2131IDGV
MSP430F2101IRGE
MSP430F2111IRGE
MSP430F2121IRGE
MSP430F2131IRGE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004 Texas Instruments Incorporated
! ""#$ %&'"!$ !(# !)# &#$* %($# &#)#+%#!, ("!#$!" &! & !(#
$%#""!$ # &#$* *+$, #$ $!'#!$ #$#)#$ !(# *(! !
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1
PRODUCT PREVIEW
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption
SLAS439 − SEPTEMBER 2004
device pinout
19
P1.6/TA1/TDI/TCLK
3
18
P1.5/TA0/TMS
VSS
XOUT/P2.7/CA7
4
17
5
16
P1.4/SMCLK/TCK
P1.3/TA2
XIN/P2.6/CA6
6
15
P1.2/TA1
RST/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
7
14
8
13
9
12
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
10
11
P2.3/TA1/CA0
24 23 22 21 20 19
1
VSS 2
XOUT/P2.7/CA7 3
XIN/P2.6/CA6 4
6
NC
9 10 11 12
P2.4/TA2/CA1
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
7 8
PRODUCT PREVIEW
18 P1.5/TA0/TMS
17 P1.4/SMCLK/TCK
16 P1.3/TA2
15 P1.2/TA1
14 P1.1/TA0
13 P1.0/TACLK
5
P2.3/TA1/CA0
RST/NMI
P2.0/ACLK/CA2
NC
P2.2/CAOUT/TA0/CA4
NC
NC
2
VCC
P2.5/CA5
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
VCC
TEST
20
P2.5/CA5
1
TEST
P1.7/TA2/TDO/TDI
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to VSS recommended
functional block diagram
VCC
XIN
VSS
RST/NMI
P1.x &
JTAG
XIN
XOUT
XOUT
Basic
Clock
MCLK
ACLK
SMCLK
8kB Flash
4kB Flash
2KB Flash
1KB Flash
256B RAM
256B RAM
128B RAM
128B RAM
Watchdog
WDT+
Timer_A3
Brownout
Protection
I/O Port P1
8 I/Os with
Interrupt
Capability
CPU &
Working
Registers
Emulation
15/16−Bit
Comparator_
A+
3 CC
Registers
8 Channel
Input Mux
Note: See port schematics section for detailed I/O information
2
P2.x &
XIN/XOUT
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I/O Port P2
8 I/Os with
Interrupt
Capability
SLAS439 − SEPTEMBER 2004
Terminal Functions
TERMINAL
DW, PW, or DGV
RGE
NO.
NO.
P1.0/TACLK
13
13
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
14
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input,
compare: Out0 output/BSL transmit
P1.2/TA1
15
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input,
compare: Out1 output
P1.3/TA2
16
16
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input,
compare: Out2 output
P1.4/SMCLK/TCK
17
17
I/O
General-purpose digital I/O pin/SMCLK signal output/test clock, input
terminal for device programming and test
P1.5/TA0/TMS
18
18
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output/test
mode select, input terminal for device programming and test
P1.6/TA1/TDI/TCLK
19
20
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/test
data input or test clock input during programming and test
P1.7/TA2/TDO/TDI†
20
21
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/test
data output terminal or test data input during programming and test
P2.0/ACLK/CA2
8
6
I/O
General-purpose digital I/O pin/ACLK output/comparator_A+, CA2
input
P2.1/INCLK/CA3
9
7
I/O
General-purpose digital I/O pin/Timer_A,
INCLK/comparator_A+, CA3 input
P2.2/CAOUT/
TA0/CA4
10
8
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0B input/
comparator_A+, output/comparator_A+, CA4 input/BSL receive
P2.3/CA0/TA1
11
10
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output/
comparator_A+, CA0 input
P2.4/CA1/TA2
12
11
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output/
comparator_A+, CA1 input
P2.5/CA5
3
24
I/O
General-purpose digital I/O pin/ comparator_A+, CA5 input
XIN/P2.6/CA6
6
4
I/O
Input terminal of crystal oscillator/general-purpose digital I/O pin/
comparator_A+, CA6 input
XOUT/P2.7/CA7
5
3
I/O
Output terminal of crystal oscillator/general-purpose digital I/O pin/
comparator_A+, CA7 input
RST/NMI
7
5
I
Reset or nonmaskable interrupt input
TEST
1
22
I
Selects test mode for JTAG pins on Port1. The device protection fuse
is connected to TEST.
VCC
VSS
2
23
4
2
QFN Pad
NA
Package Pad
† TDO or TDI is selected via JTAG instruction.
DESCRIPTION
I/O
clock
signal
PRODUCT PREVIEW
NAME
at
Supply voltage
Ground reference
NA
QFN package pad connection to VSS recommended.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output
driver connection to this pad after reset.
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SLAS439 − SEPTEMBER 2004
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
PRODUCT PREVIEW
Program Counter
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) −−> M(TONI)
Absolute
F F
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
EXAMPLE
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
4
SYNTAX
D = destination
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#45
−−> M(TONI)
SLAS439 − SEPTEMBER 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
−
PRODUCT PREVIEW
D Low-power mode 2 (LPM2);
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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SLAS439 − SEPTEMBER 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
PRODUCT PREVIEW
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will
go into LPM4 immediately.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
15, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
14
0FFFAh
13
0FFF8h
12
Comparator_A+
CAIFG
maskable
0FFF6h
11
Watchdog Timer
WDTIFG
maskable
0FFF4h
10
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
9
Timer_A3
TACCR1 CCIFG.
TACCR2 CCIFG
TAIFG (see Notes 2 & 3)
maskable
0FFF0h
8
0FFEEh
7
0FFECh
6
0FFEAh
5
0FFE8h
4
NOTES: 1.
2.
3.
4.
6
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
maskable
0FFE6h
3
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
maskable
0FFE4h
2
0FFE2h
1
0FFE0h
0, lowest
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
Multiple source flags
Interrupt flags are located in the module
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
6
5
4
3
2
1
0
01h
interrupt flag register 1 and 2
Address
7
02h
4
3
2
1
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
rw-1
rw-(1)
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power−up
Power−On interrupt flag. Set on VCC power−up.
Set via RST/NMI-pin
7
6
5
4
3
2
1
0
03h
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
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PRODUCT PREVIEW
Address
SLAS439 − SEPTEMBER 2004
memory organization
MSP430F2101
MSP430F2111
MSP430F2121
MSP430F2131
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh−0FFE0h
0FFFFh−0FC00h
2KB Flash
0FFFFh−0FFE0h
0FFFFh−0F800h
4KB Flash
0FFFFh−0FFE0h
0FFFFh−0F000h
8KB Flash
0FFFFh−0FFE0h
0FFFFh−0E000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
128 Byte
027Fh − 0200h
128 Byte
027Fh − 0200h
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
PRODUCT PREVIEW
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
DW, PW & DGV Package Pins
RGE Package Pins
Data Transmit
14 - P1.1
14 - P1.1
Data Receive
10 - P2.2
8 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0−n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
8
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
Calibration Register
Size
1 MHz
CALBC1_1MHz
byte
010FFh
CALDCO_1MHz
byte
010FEh
8 MHz
12 MHz
16 MHz
Address
CALBC1_8MHz
byte
010FDh
CALDCO_8MHz
byte
010FCh
CALBC1_12MHz
byte
010FBh
CALDCO_12MHz
byte
010FAh
CALBC1_16MHz
byte
010F9h
CALDCO_16MHz
byte
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull−up/pull−down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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PRODUCT PREVIEW
DCO Frequency
SLAS439 − SEPTEMBER 2004
comparator_A+
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
RGE
13 - P1.0
13 - P1.0
PRODUCT PREVIEW
DW, PW, DGV
Module
Block
Module
Output Signal
Output
Pin Number
DW, PW DGV
RGE
TACLK
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
9 - P2.1
7 - P2.1
INCLK
INCLK
14 - P1.1
14 - P1.1
TA0
CCI0A
14 - P1.1
14 - P1.1
10 - P2.2
8 - P2.2
TA0
CCI0B
18 - P1.5
18 - P1.5
15 - P1.2
16 - P1.3
10
TACLK
Module
Input Name
15 - P1.2
16 - P1.3
GND
CCR0
TA0
VSS
VCC
TA1
VCC
CCI1A
11 - P2.3
10 - P2.3
CAOUT (internal)
CCI1B
15 - P1.2
15 - P1.2
VSS
VCC
GND
19 - P1.6
20 - P1.6
CCR1
TA1
TA2
VCC
CCI2A
12 - P2.4
11 - P2.4
ACLK (internal)
CCI2B
16 - P1.3
16 - P1.3
VSS
VCC
GND
20 - P1.7
21 - P1.7
CCR2
VCC
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TA2
SLAS439 − SEPTEMBER 2004
peripheral file map
Timer_A
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
TACCR2
TACCR1
TACCR0
TAR
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog
Watchdog/timer control
WDTCTL
0120h
PRODUCT PREVIEW
PERIPHERALS WITH WORD ACCESS
PERIPHERALS WITH BYTE ACCESS
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLAS439 − SEPTEMBER 2004
absolute maximum ratings†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J−STD−020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
NOM
MAX
UNITS
Supply voltage during program execution, VCC
MSP430F21x1
1.8
3.6
V
Supply voltage during program/erase flash memory, VCC
MSP430F21x1
2.2
3.6
V
Supply voltage, VSS
0
Operating free-air temperature range, TA
MSP430F21x1
Processor frequency fSYSTEM (Maximum MCLK frequency)
−40
85
dc
6
VCC = 2.2 V,
Duty Cycle = 50% ±10%
dc
8
VCC = 2.7 V,
Duty Cycle = 50% ±10%
dc
12
VCC = 3.0 V,
Duty Cycle = 50% ±10%
dc
TBD,
>12MHz
VCC = 3.3 V,
Duty Cycle = 50% ±10%
dc
TBD,
>12MHz
VCC = 3.6 V,
Duty Cycle = 50% ±10%
dc
TBD,
>12MHz
Supply voltage
range, ’x21x1, during
program execution
12 MHz
6 MHz
1.8 V
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
TBD
Supply voltage range,
’x21x1, during flash
memory programming
2.2 V 2.7 V 3.3 V 3.6 V
Supply Voltage, V
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Frequency vs Supply Voltage, MSP430x21x1
12
POST OFFICE BOX 655303
V
VCC = 1.8 V,
Duty Cycle = 50% ±10%
16 MHz
fSYSTEM , MHz
PRODUCT PREVIEW
MIN
• DALLAS, TEXAS 75265
°C
MHz
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into VCC) excluding external current (see Notes 1 and 2)
TEST CONDITIONS
VCC
MIN
TYP
MAX
Active mode
current
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in flash
CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0
2.2 V
200
250
3V
300
350
Low-power mode
0 current, (LPM0)
see Note 3
fMCLK = 0MHz, fDCO = fSMCLK = 1MHz,
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0
2.2 V
32
45
ILPM0
3V
55
70
Low-power mode
1 current, (LPM2)
see Note 4
fMCLK = fSMCLK = 0MHz, fDCO = 1MHz,
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0
2.2 V
11
14
ILPM2
3V
17
22
0.7
TBD
0.7
TBD
1.0
TBD
0.9
TBD
0.9
TBD
1.5
TBD
0.1
TBD
0.1
TBD
0.8
TBD
IACTIVE
ILPM3
Low-power mode
2 current, (LPM3)
see Note 4
TA = −40°C
TA = 25°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 85°C
ILPM4
NOTES: 1.
2.
3.
4.
5.
Low-power mode
4 current, (LPM4)
see Note 5
TA = −40°C
TA = 25°C
TA = 85°C
fDCO = fMCLK = fSMCLK = 0MHz,
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0MHz,
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
UNIT
µA
2.2 V
3V
2.2 V/3 V
µA
µA
µA
PRODUCT PREVIEW
PARAMETER
µA
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a KDS Daishinku DT−38 (6 pF) crystal and CAPx = 1.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLAS439 − SEPTEMBER 2004
PRODUCT PREVIEW
Active Moode Current − mA
typical supply current (into VCC) characteristics
TBD
VCC − Supply Voltage − V
Active Mode Current − mA
Figure 2. Active mode current vs VCC
TBD
DCO Frequency − MHz
Figure 3. Active mode current vs DCO frequency
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2
VIT+
VIT−
TEST CONDITIONS
Positive-going input threshold voltage
Negative-going input threshold voltage
MIN
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
Vhys
Input voltage hysteresis (VIT+ − VIT−)
RPull
Pull−up/pull−down resistor
For pull−up: VIN = VSS;
For pull−down: VIN = VCC
CI
Input Capacitance
VIN = VSS or VCC
VCC = 3 V
MAX
UNIT
0.45
TYP
0.75
VCC
1.00
1.65
1.35
2.25
0.25
0.55
0.55
1.20
0.75
1.65
0.2
1.0
0.3
1.0
TBD
TBD
TBD
V
VCC
V
V
W
pF
inputs − Ports P1 and P2
PARAMETER
t(int)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External trigger puls
width to set interrupt flag, (see Note 1)
VCC
MIN
2.2 V
50
3V
30
TYP
MAX
UNIT
ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Ilkg(Px.x)
High-impedance leakage current
see Notes 1 and 2
2.2 V/3 V
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull−up/pull−down resistor
is disabled.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PRODUCT PREVIEW
PARAMETER
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2
PARAMETER
VOH
PRODUCT PREVIEW
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
VCC
I(OHmax) = −1.5 mA (see Notes 1 and 3)
I(OHmax) = −6 mA (see Notes 2 and 3)
2.2 V
I(OHmax) = −1.5 mA (see Notes 1 and 3)
I(OHmax) = −6 mA (see Notes 2 and 3)
3V
I(OLmax) = 1.5 mA (see Notes 1 and 3)
I(OLmax) = 6 mA (see Notes 2 and 3)
2.2 V
MIN
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
2.2 V
VSS
VSS
VSS+0.25
VSS+0.6
I(OLmax) = 1.5 mA (see Notes 1 and 3)
3V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2 and 3)
3V
VSS
VSS+0.6
2.2 V
3V
UNIT
V
V
CO
Output capacitance
TBD
pF
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
3. One output loaded at a time.
output frequency − Ports P1 and P2
PARAMETER
fPx.y
fPort_CLK
Port output frequency
(with load)
Clock output
frequency
TEST CONDITIONS
MAX
UNIT
Px.y (TBD), CL = 20 pF, RL = 1 kOhm
(see Note 1 and 2)
2.2 V
VCC
MIN
TYP
10
MHz
3V
12
MHz
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
12
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25
12
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P1.0
20
TA = 85°C
15
10
5
0
0.0
2.5
TA = 25°C
0.5
VOL − Low-Level Output Voltage − V
1.0
Figure 4
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
3.0
3.5
0
VCC = 2.2 V
P1.0
−4
−6
−8
−10
TA = 85°C
−12
TA = 25°C
0.5
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
−14
0.0
2.0
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−2
1.5
VOL − Low-Level Output Voltage − V
1.0
1.5
2.0
2.5
VOH − High-Level Output Voltage − V
VCC = 3 V
P1.0
−5
−10
−15
−20
TA = 85°C
−25
−30
0.0
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH − High-Level Output Voltage − V
Figure 7
Figure 6
NOTE: One output loaded at a time.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
PRODUCT PREVIEW
TA = 25°C
VCC = 2.2 V
P1.0
14
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
16
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
tTA,cap
Timer_A, capture timing
VCC
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
Duty Cycle = 50% ±10%
MIN
TYP
MAX
2.2 V
10
3V
16
UNIT
MHz
2.2 V
50
3V
30
TA0, TA1, TA2
ns
Comparator_A+ (see Note 1)
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
TYP
MAX
2.2 V
VCC
MIN
25
40
3V
45
60
I(DD)
CAON=1, CARSEL=0, CAREF=0
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
2.2 V
30
50
I(Refladder/RefDiode)
3V
45
71
CAON =1
2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, TA = 85°C
2.2 V
390
480
540
3V
400
490
550
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
V
node
CC
Voltage @ 0.5V
V
CC
CC
node
CC
VCC−1
UNIT
µA
µA
V
V(RefVT)
(see Figure 8 and Figure 9)
V(offset)
Vhys
Offset voltage
See Note 2
2.2 V/3 V
−30
30
mV
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
TA = 25
25°C,
C, Overdrive 10 mV,
Without filter: CAF=0
2.2 V
160
210
300
3V
90
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
TA = 25
25°C,
C, Overdrive 10 mV,
Without filter: CAF=0
2.2 V
130
210
300
3V
80
150
240
TA = 25
25°C,
C, Overdrive 10 mV,
With filter: CAF=1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
t(response LH)
t(response HL)
mV
ns
µs
ns
µs
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics
650
650
VCC = 2.2 V
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
95
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
PRODUCT PREVIEW
V(REFVT) − Reference Volts −mV
V(REFVT) − Reference Volts −mV
VCC = 3 V
95
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 8. V(RefVT) vs Temperature, VCC = 3 V
Figure 9. V(RefVT) vs Temperature, VCC = 2.2 V
Short Resistance − Ohms
typical resistance between CA+ and CA− with CASHORT = 1
TBD
VCC − Supply Voltage − V
Figure 10. Short resistance vs VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V VCC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
V+
V−
+
_
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
PRODUCT PREVIEW
Figure 11. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
t(response)
V+
Figure 12. Overdrive Definition
POR/brownout reset (BOR) (see Note 1)
PARAMETER
td(BOR)
VCC(start)
V(B_IT−)
Vhys(B_IT−)
TEST CONDITIONS
MIN
dVCC/dt ≤ 3 V/s (see Figure 13)
Brownout
(see Note 2)
TYP
MAX
UNIT
2000
µs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 13 through Figure 15)
dVCC/dt ≤ 3 V/s (see Figure 13)
70
130
V
1.71
V
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
t(reset)
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
PRODUCT PREVIEW
1
0
t d(BOR)
Figure 13. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(min)− V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(min)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 14. V(CC)min Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC(min)− V
2
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(min)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 15. VCC(min) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average +
MOD
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO)1)
f DCO(RSEL,DCO))(32*MOD) f DCO(RSEL,DCO)1)
DCO frequency
PARAMETER
PRODUCT PREVIEW
MAX
UNIT
fDCO(0,3)
fDCO(1,3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.08
0.12
MHz
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.15
MHz
fDCO(2,3)
fDCO(3,3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.20
MHz
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.21
0.29
MHz
fDCO(4,3)
fDCO(5,3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.29
0.40
MHz
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.41
0.56
MHz
fDCO(6,3)
fDCO(7,3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.58
0.77
MHz
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.81
1.07
MHz
fDCO(8,3)
fDCO(9,3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.14
1.54
MHz
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.67
2.27
MHz
fDCO(10,3)
fDCO(11,3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.35
3.25
MHz
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
2.94
4.07
MHz
fDCO(12,3)
fDCO(13,3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.15
5.67
MHz
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
5.70
7.45
MHz
fDCO(14,3)
fDCO(15,3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.25
11.3
MHz
RSELx = 15, DCOx = 3, MODx = 0
2.2 V/3 V
10.9
16.5
MHz
fDCO(15,7)
SRSEL
RSELx = 15, DCOx = 7, MODx = 0
2.2 V/3 V
16.0
23.0
MHz
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.10
1.12
Duty Cycle
Measured at P1.4/SMCLK
2.2 V/3 V
45
50
55
22
TEST CONDITIONS
POST OFFICE BOX 655303
VCC
• DALLAS, TEXAS 75265
MIN
TYP
1.4
ratio
%
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DT(0,3)
Temperature drift (Box Method),
RSELx = 0, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
2.2 V/3 V
TBD
%
DT(7,3)
Temperature drift (Box Method),
RSELx = 7, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
2.2 V/3 V
TBD
%
DT(15,3)
Temperature drift (Box Method),
RSELx = 15, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
2.2 V/3 V
TBD
%
DV(0,3)
Supply voltage drift (Box Method),
RSELx = 0, DCOx = 3, MODx = 0
TA = 25°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
DT(7,3)
Supply voltage drift (Box Method),
RSELx = 7, DCOx = 3, MODx = 0
TA = 25°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
DT(15,3)
Supply voltage drift (Box Method),
RSELx = 15, DCOx = 3, MODx = 0
TA = 25°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
DT(0,3)
Total drift (Box Method),
RSELx = 0, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
DT(7,3)
Total drift (Box Method),
RSELx = 7, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
DT(15,3)
Total drift (Box Method),
RSELx = 15, DCOx = 3, MODx = 0
TA = −40°C − +85°C
(see Note 1)
1.8 V − 3.6 V
TBD
%
PRODUCT PREVIEW
DCO drift
NOTE 1: These parameters are not production tested.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
DCO clock wake−up time from LPM3/4
tClock,LPM3/4
(see Note 1)
VCC
MIN
TYP
MAX
fDCO = fDCO(3,3), RSELx = 3,
DCOx = 3
2.2 V/3 V
7
fDCO = fDCO(7,3), RSELx = 7,
DCOx = 3
2.2 V/3 V
2
fDCO = fDCO(11,3), RSELx = 11,
DCOx = 3
2.2 V/3 V
1.5
fDCO = fDCO(15,3), RSELx = 15,
2.2 V/3 V
DCOx = 3
1.0
UNIT
µss
1/fMCLK
+
tClock,LPM3/4
NOTES: 1. The DCO clock wake−up time is measured from the edge of an external wake−up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
CPU wake−up time from LPM3/4
(see Note 2)
typical wake−up time characteristics
DCO Wake Time − us
PRODUCT PREVIEW
tCPU,LPM3/4
TBD
DCO Frequency − MHz
Figure 16. Clock wake−up time vs DCO frequency
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0,
1
XTS = 0, LFXT1Sx = 0 or 1
fLFXT1,HF0
LFXT1 oscillator crystal
frequency, HF mode 0
XTS = 1, LFXT1Sx = 0
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal
frequency, HF mode 1
XTS = 1, LFXT1Sx = 1
1
4
MHz
fLFXT1,HF2
LFXT1 oscillator crystal
frequency, HF mode 2
XTS = 1, LFXT1Sx = 2
2
16
MHz
fLFXT1,LF,logic
LFXT1 oscillator logic
level square wave input
frequency, LF mode
XTS = 0, LFXT1Sx = 3
10,000
fLFXT1,HF,logic
LFXT1 oscillator logic
level square wave input
frequency, HF mode
XTS = 1, LFXT1Sx = 3
0.4
16
MHz
ESRLF
Supported ESR for LF
crystals
XTS = 0, LFXT1Sx = 0 or 1
20
100
kW
ESRHF
Supported ESR for HF
crystals (refer to
Figure 17 and
Figure 18)
32,768
CXOUT
Input capacitance
(see Note 1)
Output capacitance
(see Note 1)
LF mode
Duty Cycle
HF mode
50,000
Hz
XTS = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL = 32 pF
500
W
XTS = 0, LFXT1Sx = 1
fLFXT1,HF = 4 MHz, CL = 32 pF
100
W
XTS = 0, LFXT1Sx = 2
fLFXT1,HF = 16 MHz, CL = 32 pF
50
W
2
pF
XTS = 0, XCAPx = 1
11
pF
XTS = 0, XCAPx = 2
17
pF
XTS = 0, XCAPx = 3
22
pF
XTS = 1 (see Note 2)
2
pF
XTS = 0, XCAPx = 0
2
pF
XTS = 0, XCAPx = 1
11
pF
XTS = 0, XCAPx = 2
17
pF
XTS = 0, XCAPx = 3
22
pF
XTS = 1 (see Note 2)
2
pF
XTS = 0, XCAPx = 0
CXIN
32,768
Hz
XTS = 0, Measured at P1.4/ACLK,
fLFXT1,LF = 32,768 Hz
2.2 V/ 3 V
30
50
70
%
XTS = 1, Measured at P1.4/ACLK,
fLFXT1,HF = 10 MHz
2.2 V/ 3 V
35
50
65
%
XTS = 1, Measured at P1.4/ACLK,
fLFXT1,HF = 16 MHz
2.2 V/ 3 V
40
50
60
%
Hz
fFault,LF
Oscillator fault
frequency, LF mode
XTS = 0, LFXT1Sx = 3
(see Note 3)
2.2 V/ 3 V
TBD
10,000
fFault,HF
Oscillator fault
frequency, HF mode
XTS = 1, LFXT1Sx = 3
(see Note 3)
2.2 V/ 3 V
0.05
0.25
PRODUCT PREVIEW
PARAMETER
MHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF).
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PRODUCT PREVIEW
ESR − Ohms
typical operating areas for oscillator LFXT1 in HF mode (XTS = 1)
TBD
Crystal Frequency − kHz
ESR − Ohms
Figure 17. ESR with Safety Factor (SF) = 3 vs Crystal Frequency, CL = 32 pF
TBD
Crystal Frequency − kHz
Figure 18. ESR with Safety Factor (SF) = 3 vs Crystal Frequency, CL = 15 pF
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
TEST
CONDITIONS
VCC(PGM/
ERASE)
VCC
Program and Erase supply voltage
fFTG
IPGM
Flash Timing Generator frequency
IERASE
tCPT
Supply current from VCC during erase
tCMErase
Cumulative mass erase time
257
see Note 1
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
3.6
V
476
kHz
5
mA
2.7 V/ 3.6 V
3
7
mA
4
ms
2.7 V/ 3.6 V
TJ = 25°C
Block program end-sequence wait time
UNIT
3
Program/Erase endurance
Data retention duration
MAX
2.7 V/ 3.6 V
2.7 V/ 3.6 V
tRetention
NOM
2.2
Supply current from VCC during program
Cumulative program time
MIN
20
104
ms
105
cycles
100
years
30
25
18
see Note 2
tFTG
6
10593
Segment erase time
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER
MIN
NOM
MAX
UNIT
V(RAMh)
CPU halted (see Note 1)
1.6
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
VCC
MIN
2.2 V
3V
RInternal
Internal pull-down resistance on TEST
2.2 V/ 3 V
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
NOM
MAX
UNIT
0
5
MHz
0
10
MHz
kΩ
25
60
90
MIN
NOM
MAX
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TEST during fuse blow
TA = 25°C
Voltage level on TEST for fuse-blow
VCC
2.5
6
Time to blow fuse
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
PRODUCT PREVIEW
PARAMETER
SLAS439 − SEPTEMBER 2004
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger
PxSEL.x
CAPD.x
PxDIR.x
0
Direction
Module Direction
1
0: Input
1: Output
PxOUT.x
0
Module Output
1
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
Bus
Keeper
PxIN.x
Module Input
EN
EN
PRODUCT PREVIEW
Set PxIFG.x
Interrupt
Logic
PRIMARY FUNCTION
SECONDARY FUNCTION
GPIO
Control Bits/Signals
Module IO
Analog IO
JTAG
1
N/A
N/A
1
N/A
N/A
DVSS
Timer_A3.TA0
N/A
N/A
Timer_A3.CCI0A
N/A
N/A
P1.2 output
Timer_A3.CCI1A
Timer_A3.TA1
N/A
N/A
P1.3 output
Timer_A3.CCI2A
Timer_A3.TA2
N/A
N/A
input
output
input
output
P1SEL.x
0†
0
1
P1DIR.x
0†
1
0
P1.0/TACLK
P1.0 input†
P1.0 output
Timer_A3.TACLK
P1.1/TA0
P1.1 input†
P1.1 output
P1.2/TA1
P1.2 input†
P1.3/TA2
P1.3 input†
Pin Name (P1.x)
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
APPLICATION INFORMATION
Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
PxREN.x
PxSEL.x
PxDIR.x
0
Module Direction
1
PxOUT.x
0
Module Output
1
PxOUT.x
Direction
0: Input
1: Output
DVSS
0
DVCC
1
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
P1.7/TA2/TDO/TDI
Bus
Keeper
PxIN.x
Module Input
EN
PRODUCT PREVIEW
EN
Set PxIFG.x
Interrupt
Logic
To JTAG
From TEST pad
From JTAG
From JTAG (TDO)
P1.7/TA2/TDO/TDI only
To JTAG pads
TEST
JTAG
Fuse
DVSS
TEST pad
PRIMARY FUNCTION
SECONDARY FUNCTION
GPIO
Control Bits/Signals
Module IO
Analog IO
JTAG
input
output
input
output
P1SEL.x
0†
0
1
1
N/A
X
P1DIR.x
0†
1
0
1
N/A
X
TEST (from pin)
0†
0
0
0
N/A
1
P1.4/SMCLK/TCK
P1.4 input†
P1.4 output
N/A
SMCLK
N/A
TCK
P1.5/TA0/TMS
P1.5 input†
P1.5 output
N/A
Timer_A3.TA0
N/A
TMS
P1.6/TA1/TDI/TCLK
P1.6 input†
P1.6 output
N/A
Timer_A3.TA1
N/A
TDI/TCLK‡
P1.7/TA2/TDO/TDI
P1.7 input†
P1.7 output
† Default after reset (PUC/POR)
† Function controlled by JTAG
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
N/A
Timer_A3.TA2
N/A
TDO/TDI‡
Pin Name (P1.x)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS439 − SEPTEMBER 2004
APPLICATION INFORMATION
Port P2 pin schematic: P2.0 to P2.5, input/output with Schmitt-trigger
P2OUT.x
P2REN.x
CAPD.x
P2SEL.x
P2DIR.x
0
Direction
Module Direction
1
0: Input
1: Output
P2OUT.x
0
Module Output
1
0
DVCC
1
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/TA1/CA0
P2.4/TA2/CA1
P2.5/CA5
Bus
Keeper
P2IN.x
Module Input
PRODUCT PREVIEW
DVSS
EN
EN
Set P2IFG.x
Interrupt
Logic
From Comparator
To Comparator
PRIMARY FUNCTION
SECONDARY FUNCTION
GPIO
Analog IO
JTAG
1
X
N/A
1
X
N/A
0
0
1
N/A
P2.0 output
N/A
ACLK
CA2
N/A
P2.1 input†
P2.1 output
Timer_A3.INCLK
N/A
P2.2 output
Timer_A3.CCI0B
DVSS
Comparator_A.OUT
CA3
P2.2 input†
CA4
N/A
P2.3/TA1/CA0
P2.3 input†
P2.3 output
N/A
Timer_A3.TA1
CA0
N/A
P2.4/TA2/CA1
P2.4 input†
P2.4 output
N/A
Timer_A3.TA2
CA1
N/A
P2.5/CA5
P2.5 input†
P2.5 output
N/A
N/A
CA5
N/A
Control Bits/Signals
Module IO
input
output
input
output
P2SEL.x
0†
0
1
P2DIR.x
0†
1
0
CAPD.x
0†
0
P2.0/ACLK/CA2
P2.0 input†
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
Pin Name (P2.x)
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
APPLICATION INFORMATION
Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input
P2SEL.x
P2DIR.x
DVSS
P2OUT.x
P2REN.x
CAPD.x
0
Direction
1
0: Input
1: Output
DVSS
0
DVCC
1
P2OUT.x
XIN/P2.6/CA6
Bus
Keeper
P2IN.x
EN
EN
Interrupt
Logic
PRODUCT PREVIEW
Set P2IFG.x
From Comparator
To Comparator
LFXT1 Oscillator
1
LFXT1CLK
0
OSCOFF
BCSCTL3.LFXT1S = 11
XOUT
PRIMARY FUNCTION
SECONDARY FUNCTION
GPIO
Control Bits/Signals
Module IO
Analog IO
JTAG
N/A
0
N/A
N/A
X
N/A
X
N/A
1
N/A
XIN†
N/A
CA6
N/A
input
output
input
output
P2SEL.x
0
0
1†
P2DIR.x
0†
1
X
CAPD.x
0†
0
Pin Name (P2.x)
P2.6/XIN/CA6
P2.6 input
P2.6 output
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SLAS439 − SEPTEMBER 2004
APPLICATION INFORMATION
Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output
CAPD.x
P2SEL.x
P2DIR.x
DVSS
P2OUT.x
P2REN.x
0
Direction
1
0: Input
1: Output
DVSS
0
DVCC
1
P2OUT.x
XOUT/P2.7/CA7
Bus
Keeper
P2IN.x
PRODUCT PREVIEW
EN
Set P2IFG.x
EN
Interrupt
Logic
From Comparator
To Comparator
LFXT1CLK
1
From P2.6/XIN/CA6
LFXT1 Oscillator
XIN
0
OSCOFF
BCSCTL3.LFXT1S = 11
PRIMARY FUNCTION
SECONDARY FUNCTION
GPIO
Control Bits/Signals
Module IO
Analog IO
JTAG
1†
0
N/A
N/A
X
X
N/A
N/A
X
1
N/A
input
output
input
output
P2SEL.x
0
0
N/A
P2DIR.x
0†
1
CAPD.x
0†
0
Pin Name (P2.x)
XOUT/P2.7/CA7
P2.7 input
P2.7 output
N/A
XOUT†
CA7
N/A
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 19). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
PRODUCT PREVIEW
Time TMS Goes Low After POR
TMS
ITEST
ITF
Figure 19. Fuse Check Mode Current, MSP430F21x1
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS439 − SEPTEMBER 2004
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
PRODUCT PREVIEW
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°−ā 8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
0.004 (0,10)
PINS **
16
20
24
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
DIM
4040000 / D 02/98
NOTES: A.
B.
C.
D.
34
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
PRODUCT PREVIEW
0°−ā 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLAS439 − SEPTEMBER 2004
MECHANICAL DATA
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
PRODUCT PREVIEW
Gage Plane
0,25
0°−ā 8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
36
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins − MO-153
14/16/20/56 Pins − MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439 − SEPTEMBER 2004
MECHANICAL DATA
RGE (S-PQFP-N24)
PLASTIC QUAD FLATPACK
4,15
3,85
4,15
3,85
PRODUCT PREVIEW
Pin 1 Index Area
Top and Bottom
1,00
0,80
0,20 REF.
Seating Plane
0,05
0,08
0,00
2,55 MAX SQ.
0,50
24X
0,30
1
6
0,50
24
7
19
12
18
2,50
13
Exposed Thermal Die Pad
(See Note D)
0,30
24X
0,18
0,10
4204104/B 11/02
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Quad Flatpack, No-leads, (QFN) package configuration.
The package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane.
Falls within JEDEC M0-220.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
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