CMRDM3575 SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY SILICON MOSFETS w w w. c e n t r a l s e m i . c o m DESCRIPTION: The CENTRAL SEMICONDUCTOR CMRDM3575 consists of complementary N-Channel and P-Channel enhancement-mode silicon MOSFETs designed for high speed pulsed amplifier and driver applications. These MOSFETs offer low rDS(ON) and low threshold voltage. MARKING CODE: CT SOT-963 CASE • Device is Halogen Free by design APPLICATIONS: • Load/Power switches • Power supply converter circuits • Battery powered portable devices MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (Steady State) Continuous Drain Current, tp < 5.0s Power Dissipation Operating and Storage Junction Temperature Thermal Resistance FEATURES: • Power dissipation: 125mW • Low package profile: 0.5mm (MAX) • Low rDS(ON) • Low threshold voltage • Logic level compatible • Small SOT-963 surface mount package SYMBOL VDS VGS ID ID PD TJ, Tstg ΘJA N-CH (Q1) ELECTRICAL CHARACTERISTICS: (TA=25°C) N-CH (Q1) SYMBOL TEST CONDITIONS MIN TYP MAX IGSSF, IGSSR VGS=5.0V, VDS=0 100 IDSS VDS=5.0V, VGS=0 50 IDSS VDS=16V, VGS=0 100 BVDSS VGS=0, ID=250μA 20 VGS(th) VDS=VGS, ID=250μA 0.4 1.0 rDS(ON) VGS=4.5V, ID=100mA 1.5 3.0 rDS(ON) VGS=2.5V, ID=50mA 2.0 4.0 3.0 6.0 rDS(ON) VGS=1.8V, ID=20mA rDS(ON) VGS=1.5V, ID=10mA 4.0 10 rDS(ON) VGS=1.2V, ID=1.0mA 7.0 gFS VDS=5.0V, ID=125mA 1.3 Crss VDS=15V, VGS=0, f=1.0MHz 2.2 Ciss VDS=15V, VGS=0, f=1.0MHz 9.0 Coss VDS=15V, VGS=0, f=1.0MHz 3.0 Qg(tot) VDS=10V, VGS=4.5V, ID=100mA 0.458 Qgs VDS=10V, VGS=4.5V, ID=100mA 0.176 Qgd VDS=10V, VGS=4.5V, ID=100mA 0.138 ton VDD=10V, VGS=4.5V, ID=200mA 25 toff VDD=10V, VGS=4.5V, ID=200mA 85 - P-CH (Q2) 20 8.0 160 140 200 180 125 -65 to +150 1000 P-CH (Q2) MIN TYP MAX 100 50 100 20 0.4 1.0 4.0 5.0 5.5 7.0 8.0 10 11 17 20 0.14 4.0 10 3.7 0.50 0.17 0.11 35 100 - UNITS V V mA mA mW °C °C/W UNITS nA nA nA V V Ω Ω Ω Ω Ω S pF pF pF nC nC nC ns ns R3 (12-December 2012) CMRDM3575 SURFACE MOUNT N-CHANNEL AND P-CHANNEL ENHANCEMENT-MODE COMPLEMENTARY SILICON MOSFETS SOT-963 CASE - MECHANICAL OUTLINE PIN CONFIGURATION LEAD CODE: 1) Source Q1 2) Gate Q1 3) Drain Q2 4) Source Q2 5) Gate Q2 6) Drain Q1 MARKING CODE: CT R3 (12-December 2012) w w w. c e n t r a l s e m i . c o m