www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 FEATURES D Unity Gain Bandwidth: 300 MHz D 0.1 dB Bandwidth: 120 MHz (G=2) D High Slew Rate: 7000 V/µs D HD3 at 10 MHz: –81 dBc (G=2, RL = 150 Ω) D High Output Current: ±145 mA into 50 Ω D Power Supply Voltage Range: ±5 V to ±15 V APPLICATIONS D High-Speed Signal Processing D Test and Measurement Systems D VDSL Line Driver D High-Voltage ADC Preamplifier D Video Line Driver The THS3061 and THS3062 provide well-regulated ac performance characteristics with power supplies ranging from ±5-V operation up to ±15-V supplies. Most notable, the 0.1-dB flat bandwidth is exceedingly high, reaching beyond 100 MHz, and the THS306x has less than 0.3 dB of peaking in the frequency response when configured in unity gain. The unity gain bandwidth of 300 MHz allows for excellent distortion characteristics at 10 MHz. The flexibility of the current feedback design allows for a 220-MHz, –3-dB bandwidth in a gain of 10 indicating excellent performance even at high gains. The THS306x consumes 8.3-mA per channel quiescent current at room temperature and has the capability of producing up to ±145 mA of output current. The THS3061 is packaged in an 8-pin SOIC and an 8-pin MSOP with PowerPAD. The THS3062 is available in an 8-pin SOIC with PowerPAD and an 8-pin MSP with PowerPAD. DESCRIPTION The THS3061 (single) and THS3062 (dual) are high-voltage, high slew-rate current feedback amplifiers utilizing Texas Instruments BICOM-1 process. Designed for low-distortion with a high slew rate of 7000 V/µs, the THS306x amplifiers are ideally suited for applications requiring large, linear output signals such as video line drivers and VDSL line drivers. RELATED DEVICES AND DESCRIPTIONS THS3001 Low Distortion Current Feedback Amplifier THS3112 Dual Current Feedback Amplifier With 175 mA Drive THS3122 Dual Current Feedback Amplifier With 350 mA Drive OPA691 Wideband Current Feedback Amplifier With 350 mA Drive SLEW RATE vs OUTPUT STEP HARMONIC DISTORTION vs FREQUENCY 8000 –20 G=5 VCC = ±15 Rf = 375 Ω TA = 25°C 6000 –30 Harmonic Distortion – dB SR – Slew Rate – V/ µ s 7000 5000 VCC = ±15 4000 3000 2000 –40 –50 G=1 VCC = ±15 V VCC = ±5 V RL = 1 kΩ Rf = 750 Ω VO = 2VPP –60 2nd HD –70 –80 3rd HD 1000 –90 0 0 5 10 15 Output Step – VPP 20 25 –100 100 k 1M 10 M f – Frequency – Hz 100 M Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. !"#$ % &'!!($ #% )'*+&#$ ,#$(- ! ,'&$% & !" $ %)(&&#$ % )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1! ,'&$ )! &(%%2 , (% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- Copyright 2002, Texas Instruments Incorporated www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 16.5 V Supply voltage, VS± ±VS Input voltage, VI 200 mA Output current, IO This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ±3 V Differential input voltage, VID Continuous power dissipation See Dissipation Rating Table PACKAGE DISSIPATION RATINGS 150°C Maximum junction temperature, TJ Operating free-air temperature range, TA –40°C to 85°C Storage temperature range, Tstg –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C θJC (°C/W) θJA (°C/W) D(8 pin)(1) 38.3 95 1.05 W 0.42 W DDA (8 pin) 9.2 45.8 2.18 W 0.87 W DGN (8 pin)(2) 4.7 58.4 1.71 W 0.68 W (1) This data was taken using the JEDEC High-K test PCB. For the JEDEC Low-K test PCB, θJA is 167°C/W with power rating at TA = 25°C of 0.6 W. (2) This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. x 3 in. PCB. (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS306x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. POWER RATING (TJ = 125°C) TA ≤ 25°C TA = 85°C PACKAGE RECOMMENDED OPERATING CONDITIONS Supply voltage MIN MAX Dual supply ±5 ±15 Single supply 10 30 –40 85 Operating free-air temperature, TA UNIT V °C PACKAGE/ORDERING INFORMATION NUMBER OF CHANNELS PLASTIC SOIC-8(1) (D) ORDERABLE PACKAGE AND NUMBER (OPERATING RANGE FROM –40°C TO 85°C) PLASTIC SOIC-8(1) PLASTIC MSOP-8(1) PowerPAD (DDA) PowerPAD (DGN) PACKAGE MARKING 1 THS3061D — THS3061DGN BIB 2 THS3062D THS3062DDA THS3062DGN BIC (1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., THS3062DGNR). PIN ASSIGNMENTS D, DGN TOP VIEW D, DDA, DGN TOP VIEW THS3061 NC VIN– VIN+ VS– 1 8 2 7 3 6 4 5 NC – No internal connection 2 THS3062 NC VS+ VOUT NC 1VOUT 1VIN– 1VIN+ VS– 1 8 2 7 3 6 4 5 VS+ 2VOUT 2VIN– 2VIN+ www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS VS = ±15 V: Rf = 560 Ω, RL = 150 Ω, and G = +2 unless otherwise noted THS3061, THS3062 PARAMETER TEST CONDITIONS TYP 25°C OVER TEMPERATURE 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/TYP/ MAX MHz Typ AC PERFORMANCE Small signal bandwidth Small-signal ((VO = 100 mVPP, Peaking g < 0.3 dB)) G = +1, Rf= 750 Ω 300 G = +2, Rf = 560 Ω 275 G = +5, Rf = 357 Ω 260 G = +10, Rf = 200 Ω 220 Bandwidth for 0.1 dB flatness G = +2, VO = 100mVpp 120 MHz Typ Peaking at a gain of +1 VO = 100 mVpp G = +2, VO = 4 Vpp 0.3 dB Typ 120 MHz Typ G = +5, 20 V Step 7000 G = +2, 10 V Step 5700 V/µs Typ Large-signal bandwidth Slew rate (25% to 75% level) Rise and fall time Settling time to 0.1% 0.01% Harmonic distortion 2nd harmonic G = +2, VO = 10 V Step G = –2, VO = 2 V Step 1 ns Typ 30 ns Typ G = –2, VO = 2 V Step 125 ns Typ G = +2, f = 10 MHz, VO = 2 Vpp RL = 150 Ω –78 dBc Typ dBc Typ –93 dBc Typ RL = 1 kΩ RL = 150 Ω –73 –82 Input voltage noise RL = 1 kΩ G = +2, fc = 10 MHz, VO = 2 Vpp(envelope) ∆f = 200 kHz f > 10 kHz 2.6 nV/√Hz Typ Input current noise (noninverting) f > 10 kHz 20 pA/√Hz Typ Input current noise (inverting) f > 10 kHz 36 pA/√Hz Typ Differential gain (NTSC, PAL) G = +2, RL = 150 Ω 0.02% Typ Differential phase (NTSC, PAL) G = +2, RL = 150 Ω 0.01° Typ VO = 0 V, RL = 1 kΩ VCM = 0 V 1 0.7 0.6 0.6 MΩ Min ±0.7 ±3.5 ±4.4 ±4.5 mV Max VCM = 0 V VCM = 0 V ±10 ±10 µV/°C Typ ±2.0 ±20 ±32 ±35 µA Max VCM = 0 V VCM = 0 V ±25 ±30 nA/°C Typ Input bias current (noninverting) ±6.0 ±25 ±38 ±40 µA Max Average bias current drift (+) VCM = 0 V ±45 ±50 nA/°C Typ 3rd harmonic 3rd order intermodulation distortion –81 DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Average offset voltage drift Input bias current (inverting) Average bias current drift (–) INPUT ±13.9 ±13.1 ±13.1 ±13.1 V Min 72 60 58 58 dB Min 518 kΩ Typ Inverting 71 Ω Typ Noninverting 1 pF Typ Common-mode input range Common-mode rejection ratio Input resistance Input capacitance VCM = ±0.5 V Noninverting 3 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS (continued) VS = ±15 V: Rf = 560 Ω, RL = 150 Ω, and G = +2 unless otherwise noted THS3061, THS3062 PARAMETER TEST CONDITIONS TYP OVER TEMPERATURE 25°C 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/TYP/ MAX ±13.7 ±13.4 ±13.4 ±13.3 ±13 ±12.6 ±12.4 ±12.3 V Min OUTPUT Voltage output swing RL = 1 kΩ RL = 150 Ω Current output, sinking RL = 50 Ω RL = 50 Ω Closed-loop output impedance G = +1, f = 1 MHz Current output, sourcing 145 140 135 130 mA Min –145 –140 –135 –130 mA Min Ω Typ 0.1 POWER SUPPLY ±15 Specified operating voltage V Typ ±16.5 ±16.5 ±16.5 V Max 8.3 10 11.7 12 mA Max 8.3 6.1 6 6 mA Min 76 65 63 63 dB Min 74 65 63 63 dB Min Maximum operating voltage Maximum quiescent current/channel Minimum quiescent current/channel Power supply rejection (+PSRR) Power supply rejection (–PSRR) 4 VS+ = 14.50 V to 15.50 V VS– = –14.50 V to –15.50 V www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS VS = ±5 V: Rf = 560 Ω, RL = 150 Ω, and G = +2 unless otherwise noted THS3061, THS3062 PARAMETER TEST CONDITIONS TYP 25°C OVER TEMPERATURE 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/TYP/ MAX MHz Typ AC PERFORMANCE Small signal bandwidth Small-signal ((VO = 100 mVPP, peaking g < 0.3 dB)) G = +1, Rf= 750 Ω 275 G = +2, Rf = 560 Ω 250 G = +5, Rf = 383 Ω 230 G = +10, Rf = 200 Ω 210 Bandwidth for 0.1 dB flatness G = +2, VO = 100 mVpp 100 MHz Typ Peaking at a gain of +1 VO = 100 mVpp G = +2, VO = 4 Vpp < 0.3 dB Typ 100 MHz Typ G = +1, 5 V Step, Rf= 750 Ω 2700 G = +5, 5 V Step, Rf= 357 Ω 1300 V/µs Typ ns Typ ns Typ dBc Typ dBc Typ –91 dBc Typ Large-signal bandwidth Slew rate (25% to 75% level) Rise and fall time G = +2, VO = 5 V Step 2 Settling time to 0.1% G = –2, VO = 2 V Step 20 G = –2, VO = 2 V Step 160 G = +2, f = 10 MHz, VO = 2 Vpp RL = 150 Ω –76 0.01% Harmonic distortion 2nd harmonic RL = 1 kΩ RL = 150 Ω –70 –77 Input voltage noise RL = 1 kΩ G = +2, fc = 10 MHz, VO = 2 Vpp(envelope) ∆f = 200 kHz f > 10 kHz 2.6 nV/√Hz Typ Input current noise (noninverting) f > 10 kHz 20 pA/√Hz Typ Input current noise (inverting) f > 10 kHz 36 pA/√Hz Typ Differential gain (NTSC, PAL) G = +2, RL = 150 Ω 0.025% Typ Differential phase (NTSC, PAL) G = +2, RL = 150 Ω 0.01° Typ VO = 0 V, RL = 1 kΩ VCM = 0 V 0.8 0.6 0.5 0.5 MΩ Min ±0.3 ±3.5 ±4.4 ±4.5 mV Max VCM = 0 V VCM = 0 V ±9 ±9 µV/°C Typ ±2.0 ±20 ±32 ±35 µA Max VCM = 0 V VCM = 0 V ±20 ±25 nA/°C Typ Input bias current (noninverting) ±6.0 ±25 ±38 ±40 µA Max Average bias current drift (+) VCM = 0 V ±30 ±35 nA/°C Typ 3rd harmonic 3rd order intermodulation distortion –79 DC PERFORMANCE Open-loop transimpedance gain Input offset voltage Average offset voltage drift Input bias current (inverting) Average bias current drift (–) INPUT ±3.9 ±3.1 ±3.1 ±3.1 V Min 70 60 58 58 dB Min 518 kΩ Typ Inverting 71 Ω Typ Noninverting 1 pF Typ Common-mode input range Common-mode rejection ratio Input resistance Input capacitance VCM = ±0.5 V Noninverting 5 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 ELECTRICAL CHARACTERISTICS (continued) VS = ±5 V: Rf = 560 Ω, RL = 150 Ω, and G = +2 unless otherwise noted THS3061, THS3062 PARAMETER TYP TEST CONDITIONS OVER TEMPERATURE 25°C 25°C 0°C to 70°C –40°C to 85°C UNITS MIN/TYP/ MAX ±4.1 ±3.8 ±3.8 ±3.7 ±4.0 ±3.6 ±3.6 ±3.5 V Min OUTPUT RL = 1 kΩ RL = 150 Ω Voltage output swing RL = 50 Ω RL = 50 Ω 63 61 60 59 mA Min Current output, sinking –63 –61 –60 –59 mA Min Closed-loop output impedance G = +1, f = 1 MHz 0.1 Ω Typ V Typ Current output, sourcing POWER SUPPLY ±5 Specified operating voltage Minimum operating voltage ±4.5 ±4.5 ±4.5 V Min Maximum quiescent current 6.3 8.0 9.2 9.5 mA Max Minimum quiescent current 6.3 5.0 4.7 4.6 mA Min 73 65 63 63 dB Min 75 65 63 63 dB Min Power supply rejection (+PSRR) VS+ = 4.50 V to 5.50 V VS– = –4.50 V to –5.50 V Power supply rejection (–PSRR) PARAMETER MEASUREMENT INFORMATION Rg Rf Rg _ VI VO + 50 Ω RL Figure 1. Noninverting Test Circuit 6 Rf VI _ RT VO + RL Figure 2. Inverting Test Circuit www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Small signal frequency response 3 – 14 Large signal frequency response 15, 16 Harmonic distortion vs Frequency 17 – 23 Harmonic distortion vs Output voltage 24 – 29 Output impedance vs Frequency 30 Common-mode rejection ratio vs Frequency 31 Input current noise vs Frequency 32 Voltage noise density vs Frequency 33 Power supply rejection ratio vs Frequency 34 Common-mode rejection ratio (DC) vs Input common-mode range 35 Supply current vs Power supply voltage 36, 37 Slew rate vs Output voltage 38, 39 Slew rate vs Output step Input offset voltage vs Output voltage swing Overdrive recovery time 40 41 42, 43 Differential gain vs Number of 150-Ω loads 44, 45 Differential phase vs Number of 150-Ω loads 46, 47 7 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 TYPICAL CHARACTERISTICS SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE 2 2 1 0 –1 Rf 1 kΩ 1 –1 Rf 1 kΩ Rf 750 Ω –4 1G 100 k 1M 10 M 100 M f – Frequency – Hz Figure 3 1G 9 Rf 357 Ω Rf 500 Ω 7 6 –1 Gain – dB 6 Rf 1 kΩ 4 Rf 1 kΩ 2 0 Rf 750 Ω –3 –2 –4 100 k G=2 VCC = ±15, ±5 V RL = 150 Ω VI = 100 mVPP 2 1 1M 10 M 100 M 1G 1M 10 M 100 M f – Frequency – Hz Figure 9 1M 8 100 M 1G Figure 8 SMALL SIGNAL FREQUENCY RESPONSE Rf 200 Ω 16 14 Rf 560 Ω 10 1G 10 M 18 G=5 VCC = ±15 V RL = 1 kΩ VI = 100 mVPP 12 Rf 383 Ω Rf 560 Ω f – Frequency – Hz Gain – dB Gain – dB 16 Rf 560 Ω 100 k 100 k 18 Rf 200 Ω 14 10 G=2 VCC = ±15, ±5 V RL = 1 kΩ VI = 100 mVPP Figure 7 18 12 Rf 1 kΩ f – Frequency – Hz SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE G=5 VCC = ±5 V RL = 150 Ω VI = 100 mVPP 4 0 100 k 1G 5 3 Rf 560 Ω –4 1M 10 M 100 M f – Frequency – Hz Figure 6 Gain – dB Rf 357 Ω 8 8 –2 8 1G SMALL SIGNAL FREQUENCY RESPONSE 10 0 8 1M 10 M 100 M f – Frequency – Hz Figure 5 SMALL SIGNAL FREQUENCY RESPONSE 2 1 Rf 750 Ω Figure 4 SMALL SIGNAL FREQUENCY RESPONSE G=1 VCC = ±15 V RL = 1 kΩ VI = 100 mVPP Rf 1 kΩ –1 –4 100 k –4 1M 10 M 100M f – Frequency – Hz Rf 500 Ω –3 –3 100 k G=1 VCC = ±15 V RL = 150 Ω VI = 100 mVPP 0 0 –2 –3 Gain – dB Rf 500 Ω –2 Rf 750 Ω –2 G=1 VCC = ±5 V RL = 1 kΩ VI = 100 mVPP Gain – dB Gain – dB 1 Rf 500 Ω Gain – dB G=1 VCC = ±5 V RL = 150 Ω VI = 100 mVPP 2 16 SMALL SIGNAL FREQUENCY RESPONSE 3 Gain – dB 3 1M 10 M 100 M f – Frequency – Hz Figure 10 1G Rf 200 Ω 14 12 Rf 560 Ω 10 Rf 357 Ω 100 k G=5 VCC = ±15 V RL = 150 Ω VI = 100 mVPP Rf 357 Ω 8 100 k 1M 10 M 100 M f – Frequency – Hz Figure 11 1G www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 SMALL SIGNAL FREQUENCY RESPONSE SMALL SIGNAL FREQUENCY RESPONSE 3 20 Gain – dB 1 19 18 G = 10 VCC =±5 V, ±15 V RL = 150 Ω, 1 kΩ VI = 100 mVPP, 17 Rf 332 Ω 1 0 –1 Rf 560 Ω –2 Rf 511 Ω 1M 10 M 100 M –1 Rf 560 Ω Rf 475 Ω –4 100 k 1G 0 –3 –4 100 k Rf 332 Ω –2 –3 16 G = –1 VCC =±15 V RL = 150 Ω VI = 100 mVPP 2 Gain – dB G = –1 VCC =±5 V RL = 150 Ω VI = 100 mVPP 2 Gain – dB SMALL SIGNAL FREQUENCY RESPONSE 3 21 1M 10 M 100 M 1G 100 k 1M f – Frequency – Hz f – Frequency – Hz Figure 12 10 M 100 M 1G f – Frequency – Hz Figure 14 Figure 13 THS3061 LARGE SIGNAL FREQUENCY RESPONSE HARMONIC DISTORTION vs FREQUENCY LARGE SIGNAL FREQUENCY RESPONSE 9 –20 8 Harmonic Distortion – dB RL = 150 Ω 6 Gain – dB 6 Gain – dB Rf = 1 KΩ 3 5 G=2 VCC = ±5 V Rf = 604 Ω RL = 150 Ω RL = 1 kΩ VI = 2 VPP, 4 G=2 VCC = ±15 V Rf = 560 Ω VI = 2 VPP, 0 100 k 3 1M 10 M 100 M –40 –50 –60 2nd HD –70 –80 3rd HD –90 2 1G VCC = ±15 V G=1 RL = 150 Ω VO = 2 VPP Rf = 750 Ω –30 7 –100 100 k f – Frequency – Hz 1M 10 M 100 M 100 k 1G Figure 15 1M 10 M 100 M f – Frequency – Hz f – Frequency – Hz Figure 16 Figure 17 THS3062 HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs FREQUENCY –60 –30 2nd HD –80 –40 –50 VCC = ±5 V G=1 RL = 150 Ω VO = 2 VPP Rf = 750 Ω 2nd HD –60 –70 –80 –90 3rd HD Harmonic Distortion – dB –40 –60 –20 VCC = ±15 V G=1 RL = 150 Ω VO = 2 VPP Rf = 845 Ω Harmonic Distortion – dB Harmonic Distortion – dB –20 HARMONIC DISTORTION vs FREQUENCY 100 k 1M 10 M f – Frequency – Hz Figure 18 100 M –70 –80 2nd HD –90 3rd HD –100 3rd HD –110 –100 –100 VCC = ±5 V, VCC = ±15 V G=2 Rf = 560 Ω RL = 150 Ω VO = 1 VPP 100 k 1M 10 M f – Frequency – Hz Figure 19 100 M 1M 10 M 100 M f – Frequency – Hz Figure 20 9 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 HARMONIC DISTORTION vs FREQUENCY –60 2nd HD –70 –80 3rd HD –90 –60 1M 10 M 2nd HD –70 –80 3rd HD –100 100 M –60 –80 1M 10 M –100 100 k 100 M 1M 10 M f – Frequency – Hz Figure 22 100 M Figure 23 THS3061 THS3061 THS3061 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE –60 –60 2nd HD Harmonic Distortion – dBc –65 –70 –75 3rd HD –80 –85 VCC = ±5 V G=1 RL = 1 kΩ Rf = 750 Ω f = 10 MHz –90 –95 –70 3rd HD –75 –80 –85 VCC = ±15 V G=1 RL = 1 kΩ Rf = 750 Ω f = 10 MHz –90 –95 1 2 3 4 5 0 6 1 2 3 4 –70 –75 3rd HD –80 –85 –90 5 –100 6 0 1 VO – Output Voltage – V VO – Output Voltage – V Figure 24 2 THS3061 3 4 5 6 VO – Output Voltage – V Figure 25 Figure 26 HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE HARMONIC DISTORTION vs OUTPUT VOLTAGE 2nd HD –95 –100 –100 VCC = ±15 V G=1 RL = 150 Ω f= 1 MHz Rf = 750 Ω –65 Harmonic Distortion – dBc 2nd HD 0 2nd HD –70 f – Frequency – Hz –60 –60 –60 3rd HD 8 MHz VCC = ±5 V G=1 RL = 150 Ω f= 1 MHz –65 –70 2nd HD 1 MHz 2nd HD Harmonic Distortion – dBc –60 –75 3rd HD –80 –85 –70 –80 2nd HD 8 MHz –90 3rd HD 1 MHz VCC = ±15 V G=2 Rf = 560 Ω RL = 150 Ω –100 –90 –110 –95 0 0 1 2 3 4 VO – Output Voltage – V Figure 27 5 6 Harmonic Distortion – dBc Harmonic Distortion – dBc –50 3rd HD Figure 21 10 –40 –90 f – Frequency – Hz –65 G=1 VCC = ±15 V VCC = ±5 V RL = 1 kΩ Rf = 750 Ω VO = 2VPP –30 –90 –100 Harmonic Distortion – dBc –20 VCC = ±15 V G=2 Rf = 560 Ω RL = 150 Ω VO = 2VPP –50 Harmonic Distortion – dB –50 Harmonic Distortion – dB –40 VCC = ±5 V G=2 Rf = 560 Ω RL = 150 Ω VO = 2VPP HARMONIC DISTORTION vs FREQUENCY Harmonic Distortion – dB –40 HARMONIC DISTORTION vs FREQUENCY 2 4 6 8 VO – Output Voltage – V Figure 28 10 2nd HD 1 MHz –70 2nd HD f = 8 MHz –80 3rd HD 8 MHz –90 3rd HD f = 1 MHz VCC = ±5 V G=2 Rf = 560 Ω RL = 150 Ω –100 –110 12 0 1 2 3 4 VO – Output Voltage – V Figure 29 5 6 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 COMMON-MODE REJECTION RATIO vs FREQUENCY 100 10 1 0.1 0.01 100 k 1M 10 M 100 M 1G 90 70 THS3062 50 40 THS3061 30 20 10 0 100 k 10 M 100 M 50 In+ 1G 10 40 35 30 VCC = ±5 V 20 15 10 VCC = ±15 V 100 1k 10 k f – Frequency – Hz 100 k 70 VCC = ±15 V, ±5 V G=2 Rf = 560 Ω RL = 150 Ω VO = 35 mVPP 60 50 40 PSRR+ 30 20 10 PSRR– 0 –10 100 k 1M 10 M 100 M f – Frequency – Hz Figure 33 80 RL = 150 Ω 70 60 50 40 30 20 10 0 –15 THS3061 THS3062 SUPPLY CURRENT vs POWER SUPPLY VOLTAGE 21 4 2 18 25°C 15 12 –40°C 9 6.5 8.5 10.5 12.5 14.5 16.5 Power Supply Voltage – V Figure 36 10 15 2500 VCC = ±15 2000 1500 VCC = ±5 1000 6 500 3 4.5 5 G = –1 Rf = 475 Ω RL = 150 Ω TA = 25°C 3000 85°C SR – Slew Rate – V/ µ s 6 ICC – Supply Current – mA I CC – Supply Current – mA –40°C 0 3500 24 8 –5 SLEW RATE vs OUTPUT VOLTAGE 85°C 25°C –10 Input Common-Mode Voltage Range – V Figure 35 SUPPLY CURRENT vs POWER SUPPLY VOLTAGE 10 100 k COMMON-MODE REJECTION RATIO (DC) vs INPUT COMMON-MODE RANGE Figure 34 12 0 2.5 100 1k 10 k f – Frequency – Hz Figure 32 POWER SUPPLY REJECTION RATIO vs FREQUENCY PSRR – Power Supply Rejection Ratio – dBc Hz Vn – Voltage Noise Density – nV/ 100 Figure 31 45 10 In– 150 f – Frequency – Hz VOLTAGE NOISE DENSITY vs FREQUENCY 0 200 0 1M Figure 30 5 VCC = ±15 V, VCC = ±5 V, VCC = ±2.5 V, 250 60 f – Frequency – Hz 25 300 G=2 VCC = ±15 V, ±5 V RL = 150 Ω Rf = 1 kΩ 80 Hz G=2 Rf = 560 Ω VCC = ±15 V CMMR – Common-Mode Rejection Ratio (DC) – dB ZO – Output Impedance – Ω 1000 INPUT CURRENT NOISE vs FREQUENCY I n – Input Current Noise – pA CMRR – Common-Mode Rejection Ratio – dB OUTPUT IMPEDANCE vs FREQUENCY 0 0 4 6 8 10 12 14 Power Supply Voltage – V Figure 37 16 0 2 4 6 VO – Output Voltage – V Figure 38 11 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 SLEW RATE vs OUTPUT VOLTAGE SLEW RATE vs OUTPUT STEP 3000 8000 0 G=5 VCC = ±15 Rf = 375 Ω TA = 25°C SR – Slew Rate – V/ µ s 7000 2000 VCC = ±15 1500 VCC = ±5 1000 6000 VIO– Input Offset Voltage – mV G=1 Rf = 750 Ω RL = 150 Ω TA = 25°C 2500 5000 VCC = ±15 4000 3000 2000 500 1000 1 2 3 4 5 VO – Output Voltage – V 6 0 5 Figure 39 5 4 4 3 3 2 1 1 0 0 –1 –1 –2 G=2 VCC = ±5 Rf = 604 Ω RL = 150 Ω –3 –20 –15 –10 –5 0 5 10 15 VO – Output Voltage Swing – V –5 1.5 15 0.6 10 0.5 0 0 –5 G=5 VCC = ±15 Rf = 560 Ω RL = 150 Ω –3 –4 0.5 0 2 1 t – Time – µs t – Time – µs Figure 42 Figure 43 1.5 –15 0 0.1 DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS 0.05 VCC = ±5 0.04 0.03 0.02 Figure 45 G=2 Rf = 560 Ω PAL Modulation 0.06 VCC = ±5 0.04 0.02 VCC = ±15 VCC = ±15 0 4 4 0.08 0.01 0 2 3 Number of 150-Ω Loads Figure 44 Differential Phase – Degree Differential Phase – Degree VCC = ±15 2 3 Number of 150-Ω Loads VCC = ±15 1 G=2 Rf = 560 Ω NTSC Modulation 0.06 0.3 1 0.2 DIFFERENTIAL PHASE vs NUMBER OF 150-Ω LOADS VCC = ±5 0.2 VCC = ±5 0.3 0.1 2 G=2 Rf = 560 Ω NTSC Modulation 0.4 –10 0.07 0.4 20 DIFFERENTIAL GAIN vs NUMBER OF 150-Ω LOADS 5 –2 G=2 Rf = 560 Ω PAL Modulation 0.5 –1 Figure 41 1 0.6 Differential Gain – % 25 2 DIFFERENTIAL GAIN vs NUMBER OF 150-Ω LOADS 12 20 –1 –4 –3 1 VO – Output Voltage – V VI – Input Voltage – V VI – Input Voltage – V 2 0.5 85°C OVERDRIVE RECOVERY TIME OVERDRIVE RECOVERY TIME 0 25°C –0.5 Figure 40 3 –2 10 15 Output Step – VPP VO – Output Voltage – V 0 –40°C –1.5 0 0 Differential Gain – % SR – Slew Rate – V/ µ s INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE SWING 0 1 2 3 Number of 150-Ω Loads Figure 46 4 1 2 3 Number of 150-Ω Loads Figure 47 4 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 APPLICATION INFORMATION INTRODUCTION The THS306x is a high-speed, operational amplifier configured in a current-feedback architecture. The device is built using Texas Instruments BiCOM–I process, a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing fTs of several GHz. This configuration implements an exceptionally high-performance amplifier that has a wide bandwidth, high slew rate, fast settling time, and low distortion. RECOMMENDED FEEDBACK AND GAIN RESISTOR VALUES As with all current-feedback amplifiers, the bandwidth of the THS306x is an inversely proportional function of the value of the feedback resistor. The recommended resistors for the optimum frequency response are shown in Table 1. These should be used as a starting point and once optimum values are found, 1% tolerance resistors should be used to maintain frequency response characteristics. For most applications, a feedback resistor value of 750 Ω is recommendeda good compromise between bandwidth and phase margin that yields a very stable amplifier. Table 1. Recommended Resistor Values for Optimum Frequency Response 1 RF for VCC = ±15 V 750 Ω RF for VCC = ±5 V 750 Ω 2, –1 560 Ω 560 Ω 5 357 Ω 383 Ω 10 200 Ω 200 Ω GAIN As shown in Table 1, to maintain the highest bandwidth with an increasing gain, the feedback resistor is reduced. The advantage of dropping the feedback resistor (and the gain resistor) is the noise of the system is also reduced compared to no reduction of these resistor values, see noise calculations section. Thus, keeping the bandwidth as high as possible maintains very good distortion performance of the amplifier by keeping the excess loop gain as high as possible. Care must be taken to not drop these values too low. The amplifier’s output must drive the feedback resistance (and gain resistance) and may place a burden on the amplifier. The end result is that distortion may actually increase due to the low impedance load presented to the amplifier. Careful management of the amplifier bandwidth and the associated loading effects needs to be examined by the designer for optimum performance. The THS3061/62 amplifiers exhibit very good distortion performance and bandwidth with the capability of utilizing up to +15 V power supplies. Their excellent current drive capability of up to +145 mA driving into a 50-Ω load allows for many versatile applications. One application is driving a twisted pair line (i.e. telephone line). Figure 48 shows a simple circuit for driving a twisted pair differentially. 13 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 +12 V THS3062(a) 0.1 µF + 10 µF RS + _ VI+ RLine 2n2 499 Ω 1:n 0.1 µF Telephone Line 210 Ω RLine THS3062(b) VI– RS + _ RLine 2n2 499 Ω 0.1 µF 10 µF + –12 V Figure 48. Simple Line Driver With THS3062 Due to the large power supply voltages and the large current drive capability, power dissipation of the amplifier must not be neglected. To have as much power dissipation as possible in a small package, the THS3062 is available only in a MSOP–8 PowerPAD package (DGN) and an even lower thermal impedance SOIC–8 PowerPAD package (DDA). The thermal impedance of a standard SOIC package is too large to allow for useful applications with up to 30 V across the power supply terminals with this dual amplifier. But, the THS3061 – a single amplifier, can be utilized in the standard SOIC package. Again, power dissipation of the amplifier must be carefully examined or else the amplifiers could become too hot and performance can be severely degraded. See the Power Dissipation and Thermal Considerations section for more information on thermal management. 14 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 NOISE CALCULATIONS Noise can cause errors on very small signals. This is especially true for amplifying small signals coming over a transmission line or an antenna. The noise model for current-feedback amplifiers (CFB) is the same as for voltage feedback amplifiers (VFB). The only difference between the two is that CFB amplifiers generally specify different current-noise parameters for each input, while VFB amplifiers usually only specify one noise-current parameter. The noise model is shown in Figure 49. This model includes all of the noise sources as follows: • • • • en = Amplifier internal voltage noise (nV/√Hz) IN+ = Noninverting current noise (pA/√Hz) IN– = Inverting current noise (pA/√Hz) eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx) eRs RS en Noiseless + _ eni IN+ IN– eno eRf Rf eRg Rg Figure 49. Noise Model The total equivalent input noise density (eni) is calculated by using the following equation: e ni + Ǹǒ ǒ 2 e nǓ ) IN ) R Ǔ S 2 ǒ ) IN * ǒR f ø RgǓǓ 2 ǒ Ǔ ) 4 kTR s ) 4 kT R ø R g f where k = Boltzmann’s constant = 1.380658 × 10–23 T = Temperature in degrees Kelvin (273 +°C) Rf || Rg = Parallel resistance of Rf and Rg To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the overall amplifier gain (AV). e no + e ǒ Ǔ R A + e 1) f ni V ni Rg (Noninverting Case) As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing RF and RG), the input noise is reduced considerably because of the parallel resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplify the formula and make noise calculations much easier. 15 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE Achieving optimum performance with high frequency amplifier-like devices in the THS306x family requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: D Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. D Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-µF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 µF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. For driving differential loads with the THS3062, adding a capacitor between the power supply pins improves 2nd order harmonic distortion performance. This also minimizes the current loop formed by the differential drive. D Careful selection and placement of external components preserve the high frequency performance of the THS306x family. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use wirebound type resistors in a high frequency application. Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2.0 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. D Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS since the THS306x family is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS306x is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. D 16 Socketing a high speed part like the THS306x family is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS306x family parts directly onto the board. www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 PowerPAD DESIGN CONSIDERATIONS The THS306x family is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure 50(a) and Figure 50(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 50(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device. The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking. DIE Side View (a) Thermal Pad DIE End View (b) Bottom View (c) Figure 50. Views of Thermally Enhanced Package Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach. ÓÓÓ ÓÓ ÓÓ ÓÓÓ ÓÓ ÓÓ ÓÓÓ ÓÓ ÓÓ ÓÓÓ ÓÓ 68 Mils x 70 Mils (Via diameter = 10 mils) Figure 51. DGN PowerPAD PCB Etch and Via Pattern 17 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 PowerPAD PCB LAYOUT CONSIDERATIONS 1. Prepare the PCB with a top side etch pattern as shown in Figure 51. There should be etch for the leads as well as etch for the thermal pad. 2. Place five holes in the area of the thermal pad. These holes should be 10 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow. 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS306x family IC. These additional vias may be larger than the 10-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. 4. Connect all holes to the internal ground plane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS306x family PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process. 7. Apply solder paste to the exposed thermal pad area and all of the IC terminals. 8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. POWER DISSIPATION AND THERMAL CONSIDERATIONS To maintain maximum output capabilities, the THS360x does not incorporate automatic thermal shutoff protection. The designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150°C is exceeded. For best performance, design for a maximum junction temperature of 125°C. Between 125°C and 150°C, damage does not occur, but the performance of the amplifier begins to degrade. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula. P Dmax + Tmax * T A q JA where PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (°C). TA is the ambient temperature (°C). θJA = θJC + θCA θJC is the thermal coefficient from the silicon junctions to the case (°C/W). θCA is the thermal coefficient from the case to ambient air (°C/W). 18 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 For systems where heat dissipation is more critical, the THS306x family of devices is offered in an 8-pin MSOP with PowerPAD and the THS3062 is available in the SOIC–8 PowerPAD package offering even better thermal performance. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note number SLMA002. The following graph also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance. PD – Maximum Power Dissipation – W 4 TJ = 125°C 3.5 θJA = 45.8°C/W 3 θJA = 58.4°C/W 2.5 θJA = 98°C/W 2 1.5 1 0.5 θJA = 158°C/W 0 –40 –20 0 20 40 60 80 TA – Free-Air Temperature – °C 100 Results are With No Air Flow and PCB Size = 3”x3” θJA = 45.8°C/W for 8-Pin SOIC w/PowerPad (DDA) θJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN) θJA = 98°C/W for 8-Pin SOIC High Test PCB (D) θJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder Figure 52. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. DRIVING A CAPACITIVE LOAD Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS306x has been internally compensated to maximize its bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device’s phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 53. A minimum value of 10 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loading and provides the proper line impedance matching at the source end. Rf Rg Input _ 10 Ω Output THS306x + CLOAD Figure 53. Driving a Capacitive Load 19 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 GENERAL CONFIGURATIONS A common error for the first-time CFB user is creating a unity gain buffer amplifier by shorting the output directly to the inverting input. A CFB amplifier in this configuration oscillates and is not recommended. The THS306x, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing capacitors directly from the output to the inverting input is not recommended. This is because, at high frequencies, a capacitor has a very low impedance. This results in an unstable amplifier and should not be considered when using a current-feedback amplifier. Because of this, integrators and simple low-pass filters, which are easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required, simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 54). Rg Rf f V – VO + VI R1 –3dB O + V I ǒ + 1) 1 2pR1C1 Ǔǒ R f Rg Ǔ 1 1 ) sR1C1 C1 Figure 54. Single-Pole Low-Pass Filter If a multiple-pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is because the filtering elements are not in the negative feedback loop and stability is not compromised. Because of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize distortion. An example is shown in Figure 55. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 Rg Rf –3dB Rg = ( Figure 55. 2-Pole Low-Pass Sallen-Key Filter 20 + 1 2pRC Rf 1 2– Q ) www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 There are two simple ways to create an integrator with a CFB amplifier. The first, shown in Figure 56, adds a resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant and the feedback impedance never drops below the resistor value. The second, shown in Figure 57, uses positive feedback to create the integration. Caution is advised because oscillations can occur due to the positive feedback. C1 Rf V Rg – VI VO + O + VI THS306x S) 1 ȣ ȡ ǒRgf Ǔȧ SRfC1ȧ Ȣ Ȥ R Figure 56. Inverting CFB Integrator Rg Rf For Stable Operation: R2 – THS306x VO + R1 || RA VO ≅ VI R1 R2 ( ≥ Rf Rg Rf Rg sR1C1 1+ ) VI RA C1 Figure 57. Noninverting CFB Integrator The THS306x may also be employed as a very good video distribution amplifier. One characteristic of distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG) are compromised as the number of lines increases and the closed-loop gain increases. Be sure to use termination resistors throughout the distribution system to minimize reflections and capacitive loading. Rg Rf – 75 Ω 75-Ω Transmission Line VO1 + VI 75 Ω 75 Ω THS306x N Lines 75 Ω VON 75 Ω Figure 58. Video Distribution Amplifier Application 21 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN PINS ** 0.050 (1,27) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.157 (4,00) 0.150 (3,81) 1 Gage Plane 7 A 0.010 (0,25) 0°–ā8° 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) 4040047/D 10/96 NOTES:A. B. C. D. 22 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 MECHANICAL INFORMATION DDA (S–PDSO–G8) Power PADt PLASTIC SMALL-OUTLINE 0,49 0,35 1,27 8 0,10 M 5 Thermal Pad (See Note D) 0,20 NOM 3,99 3,81 6,20 5,84 Gage Plane 1 0,25 4 4,98 4,80 0°–8° 0,89 0,41 1,68 MAX Seating Plane 1,55 1,40 0,13 0,03 0,10 4202561/A 02/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. PowerPAD is a trademark of Texas Instruments. 23 www.ti.com SLOS394A – JULY 2002 – OCTOBER 2002 MECHANICAL INFORMATION DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 Thermal Pad (See Note D) 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°–ā6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073271/A 01/98 NOTES:A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions include mold flash or protrusions. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically and thermally connected to the backside of the die and possibly selected leads. E. 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