SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 D D D D D D D Meets or Exceeds the Requirements of ANSI TIA/EIA-644 Standard Operates With a Single 3.3-V Supply Designed for Signaling Rate of up to 155 Mbps Differential Input Thresholds ± 100 mV Max Low-Voltage TTL (LVTTL) Logic Output Levels Open-Circuit Fail Safe Characterized For Operation From 0°C to 70°C SN75LVDS32D (Marked as 75LVDS32) SN75LVDS32PW (Marked as DS32) (TOP VIEW) 1B 1A 1Y G 2Y 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4B 4A 4Y G 3Y 3A 3B SN75LVDS9637D (Marked as DF637 or 7L9637) SN75LVDS9637DGK (Marked as AXI) (TOP VIEW) description The SN75LVDS32 and SN75LVDS9637 are differential line receivers that implement the VCC 1A 1 8 electrical characteristics of low-voltage differential 1Y 7 2 1B signaling (LVDS). This signaling technique lowers 2Y 3 6 2A the output voltage levels of 5-V differential GND 4 5 2B standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100 mV allow operation with a differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN75LVDS32 and SN75LVDS9637 are characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 logic diagram ’LVDS32 logic diagram (positive logic) G G 1A 1B ’LVDS9637D logic diagram (positive logic) 4 1A 12 2 1B 6 2A 2 1Y 7 6 3 3 2A 1Y 1 8 2Y 5 2B 5 2Y 7 2B 3A 3B 4A 4B 10 11 9 14 15 13 3Y 4Y Function Tables SN75LVDS32 DIFFERENTIAL INPUT ENABLES G G Y VID ≥ 100 mV H X X L H H –100 mV < VID < 100 mV H X X L ? ? VID ≤ –100 mV H X X L L L X L H Z Open H X X L H H H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate 2 OUTPUT A, B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 logic symbol† SN75LVDS32 G G 1A 1B 2A 2B 3A 3B 4A 4B 4 ≥1 EN 12 2 3 1Y 1 5 6 2Y 7 10 11 3Y 9 14 13 15 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Function Table logic symbol† SN75LVDS9637 SN75LVDS9637 DIFFERENTIAL INPUT OUTPUT A, B Y VID ≥ 100 mV –100 mV < VID < 100 mV H 1A 1B 2A ? VID ≤ –100 mV L Open H H = high level, L = low level, ? = indeterminate POST OFFICE BOX 655303 2B 8 7 6 5 2 3 1Y 2Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. • DALLAS, TEXAS 75265 3 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 equivalent input and output schematic diagrams EQUIVALENT OF EACH A OR B INPUT EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS VCC VCC 300 kΩ TYPICAL OF ALL OUTPUTS VCC 300 kΩ 50 Ω 5Ω Input Y Output A Input 7V B Input 7V 7V 7V absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input voltage range, VI (A or B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65_C to 150_C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260_C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR‡ ABOVE TA = 25°C TA = 70°C POWER RATING D (8) 725 mW 5.8 mW/°C 464 mW D (16) 950 mW 7.6 mW/°C 608 mW PW 774 mW 6.2 mW/°C 496 mW DGK 425 mW 3.4 mW/°C 272 mW ‡ This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 recommended operating conditions MIN Supply voltage, VCC 3 High-level input voltage, VIH G, G Low-level input voltage, VIL G, G NOM MAX 3.3 3.6 2 Magnitude of differential input voltage, |VID| |V ID 2 Operating free-air temperature, TA | 2.4 0 V V 0.1 Common-mode input voltage, VIC (see Figure 1) UNIT 0.8 V 0.6 V * | V2ID| V VCC – 0.8 70 V °C VIC – Common Mode Input Voltage Range – V COMMON-MODE INPUT VOLTAGE RANGE vs DIFFERENTIAL INPUT VOLTAGE 2.5 2 Max at VCC >3.15 V Max at VCC = 3 V 1.5 1 ÁÁ ÁÁ 0.5 Min 0 0 0.1 0.2 0.3 0.4 0.5 VID – Differential Input Voltage – V 0.6 Figure 1. VIC Versus VID and VCC POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 SN75LVDSxxxx electrical characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS VITH+ VITH– Positive-going differential input voltage threshold VOH VOL High-level output voltage ICC See Figure 2 and Table 1 Negative-going differential input voltage threshold‡ IOH = –8 mA IOL = 8 mA Low-level output voltage SN75LVDS32 Supply current SN75LVDS9637 II Input current (A or B inputs) II(OFF) IIH Power-off input current (A or B inputs) Enabled, 100 –100 10 18 Disabled 0.25 0.5 No load 5.5 10 –2 –10 – 20 – 1.2 –3 VCC = 0, VIH = 2 V VI = 3.6 V mV V 0.4 No load UNIT mV 2.4 VI = 0 VI = 2.4 V High-level input current (G, or G inputs) SN75LVDS32, SN75LVDS9637 MIN TYP† MAX 6 V mA µA 20 µA 10 µA IIL Low-level input current (G, or G inputs) VIL = 0.8 V 10 µA IOZ High-impedance output current VO = 0 or VCC ± 10 µA † All typical values are at TA = 25°C and with VCC = 3.3 V. ‡ The algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for the negative-going differential input voltage threshold only. SN75LVDSxxxx switching characteristics over recommended operating conditions (unless otherwise noted) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ Á ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ PARAMETER TEST CONDITIONS SN75LVDS32, SN75LVDS9637 MIN TYP† MAX UNIT tpLH tpHL Propagation delay time, low-to-high-level output 2.1 6 ns Propagation delay time, high-to-low-level output 2.1 6 ns tsk(p) tsk(o) Pulse skew (|tPHL – tPLH|) 0.6 1.5 ns 0.7 1.5 ns 0.6 ns 0.6 ns 1 ns 25 ns 25 ns 25 ns tsk(pp) tr Channel-to-channel output skew† Part-to-part skew‡ CL = 100 pF, See Figure 3 Output signal rise time, 20% to 80% tf tpHZ Output signal fall time, 80% to 20% tpLZ tpZH Propagation delay time, low-level-to-high-impedance output Propagation delay time, high-level-to-high-impedance output Propagation delay time, high-impedance-to-high-level output See Figure 4 tpZL Propagation delay time, high-impedance-to-low-level output 25 ns † All typical values are at 25°C and with a 3.3-V supply. ‡ tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output § tsk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together. ¶ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, same temperature, and have identical packages and test circuits. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION A Y VID B (VIA + VIB)/2 VIA VIC VO VIB Figure 2. Voltage Definitions ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMONMODE INPUT VOLTAGE VIA 1.25 V VIB 1.15 V VID 100 mV VIC 1.2 V 1.15 V 1.25 V –100 mV 1.2 V 2.4 V 2.3 V 100 mV 2.35 V 2.3 V 2.4 V –100 mV 2.35 V 0.1 V 0V 100 mV 0.05 V 0V 0.1 V –100 mV 0.05 V 1.5 V 0.9 V 600 mV 1.2 V 0.9 V 1.5 V –600 mV 1.2 V 2.4 V 1.8 V 600 mV 2.1 V 1.8 V 2.4 V –600 mV 2.1 V 0.6 V 0V 600 mV 0.3 V 0V 0.6 V –600 mV 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION VID VIA CL 10 pF VIB VO VIA 1.4 V VIB 1V 0.4 V 0 –0.4 V VID tPHL tPLH 80% VO 20% 80% 20% VOH 1.4 V VOL tf tr NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 3. Timing Test Circuit and Wave Forms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 PARAMETER MEASUREMENT INFORMATION B 1.2 V 500 Ω A G Inputs (see Note A) 10 pF (see Note B) ± VO VTEST G 2.5 V VTEST A G 1V 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPLZ tPLZ tPZL tPZL Y VTEST 2.5 V 1.4 V VOL +0.5 V VOL 0 1.4 V A 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPHZ G tPHZ tPZH tPZH VOH VOH –0.5 V Y 1.4 V 0 NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 4. Enable/Disable Time Test Circuit and Wave Forms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 APPLICATION INFORMATION using an LVDS receiver with RS-422 data Receipt of data from a TIA/EIA-422 line driver may be accomplished using a TIA/EIA-644 line receiver with the addition of an attenuator circuit. This technique gives the user a very high-speed and low-power 422 receiver. If the ground noise between the transmitter and receiver is not a concern (less than ±1 V), the answer can be as simple as shown below in Figure 5. The use of a resistor divider circuit in front of the LVDS receiver attenuates the 422 differential signal to LVDS levels. The resistors present a total differential load of 100 Ω to match the characteristic impedance of the transmission line and to reduce the signal 10:1. The maximum 422 differential output signal or 6 V is reduced to 600 mV. The high input impedance of the LVDS receiver prevents input bias offsets and maintains a better than 200-mV differential input voltage threshold at the inputs to the divider. This circuit is used in front of each LVDS channel that also receives 422 signals. R1 45.3 Ω ’LVDS32 R3 5.11 Ω A R4 5.11 Ω B Y R2 45.3 Ω NOTE A: The components used were standard values. R1, R2 = NRC12F45R3TR, NIC Components, 45.3 Ohm, 1/8W, 1%, 1206 Package R3, R4 = NRC12F5R11TR, NIC Components, 5.11 Ohm, 1/8W, 1%, 1206 Package The resistor values do not need to be 1% tolerance. However, it can be difficult locating a supplier of resistors having values less than 100 Ω in stock and readily available. The user may find other suppliers with comparable parts having tolerances of 5% or even 10%. These parts are adequate for use in this circuit. Figure 5. RS-422 Data Input to an LVDS Receiver Under Low Ground Noise Conditions If ground noise between the RS-422 driver and LVDS receiver is a concern, then the common-mode voltage must be attenuated. The circuit must then be modified to connect the node between R3 and R4 to the LVDS receiver ground. This modification to the circuit increases the common-mode voltage from ±1 V to greater than ±4.5 V. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 APPLICATIONS INFORMATION The devices are generally used as building blocks for high-speed point-to-point data transmission where ground differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers approach ECL speeds without the power and dual supply requirements. TRANSMISSION DISTANCE vs SIGNALING RATE Transmission Distance – m 100 30% Jitter (see Note A) 10 5% Jitter (see Note A) 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 10 100 1000 Signaling Rate – Mbps NOTE A: This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure 6. Typical Transmission Distance vs Signaling Rate 1 1B VCC 16 0.1 µF (see Note A) 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 0.001 µF (see Note A) 15 1Y G 3.3 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 NOTES: A. Place a 0.1 µF and a 0.001 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitors should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 7. Typical Application Circuit Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 APPLICATION INFORMATION 1/4 ’LVDS31 Strb/Data_TX TpBias on Twisted-Pair A Strb/Data_Enable TP 55 Ω ’LVDS32 5 kΩ Data/Strobe 55 Ω 3.3 V TP 20 kΩ 500 Ω VG on Twisted-Pair B 1 Arb_RX 500 Ω 20 kΩ 3.3 V 20 kΩ 500 Ω 2 Arb_RX 500 Ω 20 kΩ 3.3 V 7 kΩ Twisted-Pair B Only 7 kΩ 10 kΩ Port_Status 3.3 kΩ NOTES: A. B. C. D. Resistors are leadless thick-film (0603) 5% tolerance. Decoupling capacitance is not shown but recommended. VCC is 3 V to 3.6 V. The differential output voltage of the ’LVDS31 can exceed that allowed by IEEE1394. Figure 8. 100-Mbps IEEE 1394 Transceiver 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 APPLICATION INFORMATION fail safe One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV if it is within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 9. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high level, regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt Y B VIT ≈ 2.3 V Figure 9. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 APPLICATION INFORMATION 0.01 µF 1 VCC 16 0.1 µF (see Note A) 1B 100 Ω 2 3 VCC 4 5 6 1A 4B 2Y 4Y G 2A 100 Ω 7 4A 2B 3Y 3A 5V 1N645 (2 places) 15 1Y G ≈3.6 V 14 100 Ω (see Note B) 13 12 11 See Note C 10 100 Ω 8 GND 3B 9 NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%. C. Unused enable inputs should be tied to VCC or GND as appropriate. Figure 10. Operation With 5-V Supply related information IBIS modeling is available for this device. Please contact the local TI sales office or the TI Web site at www.ti.com for more information. For more application guidelines, please see the following documents: D D D D D D 14 Low-Voltage Differential Signalling Design Notes (TI literature SLLA014) Interface Circuits for TIA/EIA-644 (LVDS) (TI literature SLLA038) Reducing EMI with LVDS (TI literature SLLA030) Slew Rate Control of LVDS Circuits (TI literature SLLA034) Using an LVDS Receiver with RS-422 Data (TI literature SLLA031) Evaluating the LVDS EVM (TI literature SLLA033) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 MECHANICAL INFORMATION D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 MECHANICAL INFORMATION DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN75LVDS32, SN75LVDS9637 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS SLLS360B – JUNE 1999 – REVISED JUNE 2001 MECHANICAL INFORMATION PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN75LVDS32D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS32DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS32DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS9637D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS9637DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS9637DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75LVDS9637DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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