TI SN74AVCH8T245RHLR

SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
FEATURES
•
•
•
DGV OR PW PACKAGE
(TOP VIEW)
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
RHL PACKAGE
(TOP VIEW)
VCCB
VCCB
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCCB
•
•
Max Data Rates:
– 320 Mbps (VCCA ≥ 1.8 V and VCCB ≥ 1.8 V)
– 170 Mbps (VCCA ≤ 1.8 V or VCCB ≤ 1.8 V)
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1
24
3
4
23 VCCB
22 OE
21 B1
5
6
20 B2
19 B3
7
8
18 B4
17 B5
9
10
16 B6
15 B7
2
14 B8
11
12
13
GND
•
•
VCCA
•
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
VCC Isolation Feature – If Either VCC Input Is at
GND, All I/O Ports Are in the High-Impedance
State
Ioff Supports Partial-Power-Down Mode
Operation
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
GND
•
DESCRIPTION/ORDERING INFORMATION
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The
SN74AVCH8T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB
as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The
B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal
low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
ORDERING INFORMATION
PACKAGE (1)
TA
QFN – RHL
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
(1)
ORDERABLE PART NUMBER
Reel of 1000
SN74AVCH8T245RHLR
Tube of 60
SN74AVCH8T245PW
Reel of 2000
SN74AVCH8T245PWR
Reel of 2000
SN74AVCH8T245DGVR
TOP-SIDE MARKING
WP245
WP245
WP245
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN74AVCH8T245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are
effectively isolated.
The SN74AVCH8T245 is designed so the control pins (DIR and OE) are supplied by VCCA.
The SN74AVCH8T245 solution is compatible with a single-supply system and can be replaced later with a '245
function, with minimal printed circuit board redesign.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both outputs are in the high-impedance
state. The bus-hold circuitry on the powered-up side always stays active.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
All output Hi-Z
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
2
22
OE
A1
3
21
To Seven Other Channels
2
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B1
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
VI
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5 VCCA + 0.5
B port
–0.5 VCCB + 0.5
Supply voltage range
Input voltage range (2)
UNIT
V
V
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DGV package
86
PW package
88
RHL package
(1)
(2)
(3)
(4)
V
V
°C/W
43
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Recommended Operating Conditions (1) (2) (3)
VCCI
MIN
MAX
UNIT
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
High-level
input voltage
VIH
Low-level
input voltage
VIL
High-level
input voltage
VIH
VIL
Low-level
input voltage
VI
Input voltage
VO
Output voltage
IOH
Data inputs
Data inputs
DIR
(referenced to VCCA)
DIR
(referenced to VCCA)
VCCI × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
V
1.2 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
1.2 V to 1.95 V
VCCA × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
1.2 V to 1.95 V
VCCA × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
3.6
VCCO
3-state
0
3.6
Input transition rise or fall rate
TA
Operating free-air temperature
V
0.8
0
Low-level output current
V
V
Active state
∆t/∆v
(1)
(2)
(3)
1.2 V to 1.95 V
0
High-level output current
IOL
4
VCCO
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
mA
mA
5
ns/V
85
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Electrical Characteristics
(1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.2 V to 3.6 V
1.2 V to 3.6 V
IOH = –3 mA
1.2 V
1.2 V
IOH = –6 mA
1.4 V
1.4 V
1.05
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
IOL = 100 µA
1.2 V to 3.6 V
1.2 V to 3.6 V
IOL = 3 mA
1.2 V
1.2 V
IOL = 6 mA
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
0.7
1.2 V to 3.6 V
1.2 V to 3.6 V
VI = 0.42 V
1.2 V
1.2 V
VI = 0.49 V
1.4 V
1.4 V
15
VI = 0.58 V
1.65 V
1.65 V
25
VI = 0.7 V
2.3 V
2.3 V
45
VI = 0.8 V
3.3 V
3.3 V
VI = 0.78 V
1.2 V
1.2 V
VI = 0.91 V
1.4 V
1.4 V
–15
VI = 1.07 V
1.65 V
1.65 V
–25
VI = 1.6 V
2.3 V
2.3 V
–45
VI = 2 V
3.3 V
3.3 V
–100
1.2 V
1.2 V
1.6 V
1.6 V
125
1.95 V
1.95 V
200
2.7 V
2.7 V
300
3.6 V
3.6 V
1.2 V
1.2 V
1.6 V
1.6 V
–125
1.95 V
1.95 V
–200
2.7 V
2.7 V
–300
3.6 V
3.6 V
–500
IOH = –8 mA
VOL
IOL = 8 mA
Control
inputs
II
IBHL (3)
IBHH
(4)
IBHLO (5)
IBHHO
(1)
(2)
(3)
(4)
(5)
(6)
(6)
–40°C to 85°C
VCCB
IOH = –100 µA
VOH
TA = 25°C
VCCA
VI = VIH
VI = VIL
VI = VCCA or GND
VI = 0 to VCC
VI = 0 to VCC
MIN
TYP
MAX
MIN MAX
UNIT
VCCO – 0.2
0.95
V
0.2
0.15
±0.025
±0.25
±1
V
µA
25
µA
100
–25
µA
50
µA
500
–50
µA
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
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SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Electrical Characteristics (continued) (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
A port
Ioff
B port
A or B port
IOZ (3)
B port
A port
ICCA
TEST CONDITIONS
VI or VO = 0 to 3.6 V
ICCB
ICCA + ICCB
0V
0 V to 3.6 V
±0.1
±1
±5
0 V to 3.6 V
0V
±0.1
±1
±5
3.6 V
3.6 V
±0.5
±2.5
±5
0V
3.6 V
±5
3.6 V
0V
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
8
0V
3.6 V
–2
3.6 V
0V
8
1.2 V to 3.6 V
1.2 V to 3.6 V
8
0V
3.6 V
8
3.6 V
0V
–2
1.2 V to 3.6 V
1.2 V to 3.6 V
16
µA
VO = VCCO or GND,
VI = VCCI or GND,
OE = don't care
VI = VCCI or GND,
VI = VCCI or GND,
IO = 0
IO = 0
IO = 0
–40°C to 85°C
VCCB
VO = VCCO or GND,
VI = VCCI or GND,
OE = VIH
VI = VCCI or GND,
TA = 25°C
VCCA
MIN
TYP MAX
MIN
MAX
UNIT
µA
µA
µA
µA
Ci
Control
inputs
VI = 3.3 V or GND
3.3 V
3.3 V
3.5
4.5
pF
Cio
A or B port
VO = 3.3 V or GND
3.3 V
3.3 V
6
7
pF
(1)
(2)
(3)
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
For I/O ports, the parameter IOZ includes the input leakage current.
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 10)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
6
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3.1
2.6
2.5
3
3.5
3.1
2.6
2.5
3
3.5
3.1
2.7
2.5
2.4
2.3
3.1
2.7
2.5
2.4
2.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.1
4
3.5
3.2
3.1
5.1
4
3.5
3.2
3.1
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.8
4.7
4
4.1
4.3
5.1
4.7
4
4.1
4.3
5.1
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UNIT
ns
ns
ns
ns
ns
ns
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 10)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.7
0.5
5.4
0.5
4.6
0.5
4.9
0.5
6.8
2.7
0.5
5.4
0.5
4.6
0.5
4.9
0.5
6.8
2.6
0.5
5.4
0.5
5.1
0.5
4.7
0.5
4.5
2.6
0.5
5.4
0.5
5.1
0.5
4.7
0.5
4.5
3.7
1.1
8.7
1.1
8.7
1.1
8.7
1.1
8.7
3.7
1.1
8.7
1.1
8.7
1.1
8.7
1.1
8.7
4.8
1.1
7.6
1.1
7.1
1
5.6
1
5.2
4.8
1.1
7.6
1.1
7.1
1
5.6
1
5.2
3.1
0.5
8.6
0.5
8.6
0.5
8.6
0.5
8.6
3.1
0.5
8.6
0.5
8.6
0.5
8.6
0.5
8.6
4.1
0.5
8.4
0.5
7.6
0.5
7.2
0.5
7.8
4.1
0.5
8.4
0.5
7.6
0.5
7.2
0.5
7.8
UNIT
ns
ns
ns
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 10)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
0.5
5.1
0.5
4.4
0.5
4
0.5
3.9
2.5
0.5
5.1
0.5
4.4
0.5
4
0.5
3.9
2.5
0.5
4.6
0.5
4.4
0.5
3.9
0.5
3.7
2.5
0.5
4.6
0.5
4.4
0.5
3.9
0.5
3.7
3
1
6.8
1
6.8
1
6.8
1
6.8
3
1
6.8
1
6.8
1
6.8
1
6.8
4.6
1.1
8.2
1
6.7
0.5
5.1
0.5
4.5
4.6
1.1
8.2
1
6.7
0.5
5.1
0.5
4.5
2.8
0.5
7.1
0.5
7.1
0.5
7.1
0.5
7.1
2.8
0.5
7.1
0.5
7.1
0.5
7.1
0.5
7.1
3.9
0.5
7.8
0.5
6.9
0.5
6
0.5
5.8
3.9
0.5
7.8
0.5
6.9
0.5
6
0.5
5.8
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UNIT
ns
ns
ns
ns
ns
ns
7
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 10)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.4
0.5
4.7
0.5
3.9
0.5
3.1
0.5
2.8
2.4
0.5
4.7
0.5
3.9
0.5
3.1
0.5
2.8
3
0.5
4.9
0.5
4
0.5
3.1
0.5
2.9
3
0.5
4.9
0.5
4
0.5
3.1
0.5
2.9
2.2
0.5
4.8
0.5
4.8
0.5
4.8
0.5
4.8
2.2
0.5
4.8
0.5
4.8
0.5
4.8
0.5
4.8
4.5
1.1
7.9
0.5
6.4
0.5
4.6
0.5
4
4.5
1.1
7.9
0.5
6.4
0.5
4.6
0.5
4
1.8
0.5
5.1
0.5
5.1
0.5
5.1
0.5
5.1
1.8
0.5
5.1
0.5
5.1
0.5
5.1
0.5
5.1
3.6
0.5
7.1
0.5
6.3
0.5
5.1
0.5
3.9
3.6
0.5
7.1
0.5
6.3
0.5
5.1
0.5
3.9
UNIT
ns
ns
ns
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 10)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
8
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.3
0.5
4.5
0.5
3.7
0.5
2.9
0.5
2.5
2.3
0.5
4.5
0.5
3.3
0.5
2.9
0.5
2.5
3.5
0.5
6.8
0.5
3.9
0.5
2.8
0.5
2.5
3.5
0.5
6.8
0.5
3.9
0.5
2.8
0.5
2.5
2
0.5
4
0.5
4
0.5
4
0.5
4
2
0.5
4
0.5
4
0.5
4
0.5
4
4.5
1.1
7.8
0.5
6.2
0.5
4.5
0.5
3.9
4.5
1.1
7.8
0.5
6.2
0.5
4.5
0.5
3.9
1.7
0.5
4
0.5
4
0.5
4
0.5
4
1.7
0.5
4
0.5
4
0.5
4
0.5
4
3.4
0.5
6.9
0.5
6
0.5
4.8
0.5
4.2
3.4
0.5
6.9
0.5
6
0.5
4.8
0.5
4.2
Submit Documentation Feedback
UNIT
ns
ns
ns
ns
ns
ns
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
Operating Characteristics
TA = 25°C
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
1
1
1
1
1
1
1
1
1
1
12
12
12
13
14
Outputs
disabled
1
1
1
1
1
Outputs
enabled
12
12
12
13
14
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TEST
CONDITIONS
PARAMETER
A to B
CpdA
(1)
B to A
A to B
CpdB (1)
B to A
(1)
Outputs
enabled
Outputs
disabled
Outputs
enabled
Outputs
disabled
Outputs
enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
UNIT
pF
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
pF
Outputs
disabled
Power dissipation capacitance per transceiver
Table 1. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
Submit Documentation Feedback
UNIT
µA
9
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS
Typical Propagation Delay (A to B) vs Load Capacitance
TA = 25°C, VCCA = 1.2 V
6
5
tPD − ns
4
3
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
60
CL − pF
Figure 1.
6
6
5
5
4
4
tPHL − ns
tPLH − ns
Typical Propagation Delay (A to B) vs Load Capacitance
TA = 25°C, VCCA = 1.5 V
3
2
3
VCCB = 1.2 V
2
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 1.8 V
1
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
0
10
10
20
30
40
50
60
0
10
20
30
CL − pF
CL − pF
Figure 2.
Figure 3.
Submit Documentation Feedback
40
50
60
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Typical Propagation Delay (A to B) vs Load Capacitance
TA = 25°C, VCCA = 1.8 V
6
6
5
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
5
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
4
tPHL − ns
4
tPLH − ns
VCCB = 1.2 V
3
3
2
2
1
1
0
0
0
10
20
30
40
50
60
0
10
20
CL − pF
30
40
50
60
CL − pF
Figure 4.
Figure 5.
Typical Propagation Delay (A to B) vs Load Capacitance
TA = 25°C, VCCA = 2.5 V
6
6
5
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
5
VCCB = 1.8 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
4
VCCB = 3.3 V
tPHL − ns
tPLH − ns
4
3
3
2
2
1
1
0
0
0
10
20
30
40
50
60
0
CL − pF
10
20
30
40
50
60
CL − pF
Figure 6.
Figure 7.
Submit Documentation Feedback
11
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
TYPICAL CHARACTERISTICS (continued)
Typical Propagation Delay (A to B) vs Load Capacitance
TA = 25°C, VCCA = 3.3 V
6
6
5
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
5
VCCB = 1.8 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
3
3
2
2
1
1
0
0
0
12
VCCB = 3.3 V
4
tPHL − ns
tPLH − ns
4
10
20
30
40
50
60
0
10
20
30
CL − pF
CL − pF
Figure 8.
Figure 9.
Submit Documentation Feedback
40
50
60
SN74AVCH8T245
8-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
www.ti.com
SCES565G – APRIL 2004 – REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
CL
RL
VTP
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPZL
VCCO
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
tPLZ
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOL + VTP
VOL
tPZH
tPHZ
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 10. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74AVCH8T245DGVRE4
ACTIVE
TVSOP
DGV
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AVCH8T245PWRE4
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74AVCH8T245RHLRG4
ACTIVE
QFN
RHL
24
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74AVCH8T245DGVR
ACTIVE
TVSOP
DGV
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH8T245PW
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH8T245PWE4
ACTIVE
TSSOP
PW
24
60
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH8T245PWR
ACTIVE
TSSOP
PW
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AVCH8T245RHLR
ACTIVE
QFN
RHL
24
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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