93LC46A/B 1K 2.5V Microwire® Serial EEPROM FEATURES BLOCK DIAGRAM • Single supply with operation down to 2.5V • Low power CMOS technology - 1 mA active current (typical) - 1 µA standby current (maximum) • 128 x 8 bit organization (93LC46A) • 64 x 16 bit organization (93LC46B) • Self-timed ERASE and WRITE cycles (including auto-erase) • Automatic ERAL before WRAL • Power on/off data protection circuitry • Industry standard 3-wire serial interface • Device status signal during ERASE/WRITE cycles • Sequential READ function • 1,000,000 E/W cycles guaranteed • Data retention > 200 years • 8-pin PDIP/SOIC and 8-pin TSSOP packages • Available for the following temperature ranges: - Commercial (C): 0°C to +70°C - Industrial (I): -40°C to +85°C ADDRESS DECODER MEMORY ARRAY ADDRESS COUNTER DATA REGISTER OUTPUT BUFFER DO DI MODE DECODE LOGIC CS CLK Vcc Vss CLOCK GENERATOR DESCRIPTION The Microchip Technology Inc. 93LC46AX/BX are 1Kbit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP, 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package. PACKAGE TYPE DIP 8 1 3 DO 4 7 NC 6 NC 5 Vss CLK 1 2 DI 3 DO 4 8 VCC NC 1 7 NC Vcc 2 NC CS 3 Vss CLK 4 6 5 93LC46AX/BX DI CS 93LC46A/B 2 93LC46A/B CLK Vcc SOIC TSSOP 8 NC 7 Vss 6 DO 5 DI CS CLK DI DO 1 2 3 4 93LC46A/B CS SOIC 8 7 6 5 Vcc NC NC Vss Microwire is a registered trademark of National Semiconductor Incorporated. 2000 Microchip Technology Inc. DS21173E-page 1 93LC46A/B 1.0 1.1 ELECTRICAL CHARACTERISTICS TABLE 1-1 Name Maximum Ratings* Vcc ...................................................................................7.0V All inputs and outputs w.r.t. Vss ............... -0.6V to Vcc +1.0V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2 PIN FUNCTION TABLE Function CS Chip Select CLK Serial Data Clock DI Serial Data Input DO Serial Data Output VSS Ground NC No Connect VCC Power Supply DC AND AC ELECTRICAL CHARACTERISTICS All parameters apply over the specified operating ranges unless otherwise noted Parameter High level input voltage Low level input voltage Low level output voltage Commercial (C): Industrial (I): VCC = +2.5V to +6.0V VCC = +2.5V to +6.0V Tamb = 0°C to +70°C Tamb = -40°C to +85°C Symbol Min. Max. Units VIH1 2.0 Vcc +1 V 2.7V < VCC ≤ 6.0V (Note 2) Conditions VIH2 0.7 VCC Vcc +1 V VCC < 2.7V VIL1 -0.3 0.8 V VCC > 2.7V (Note 2) VIL2 -0.3 0.2 Vcc V VCC < 2.7V VOL1 — 0.4 V IOL = 2.1 mA; Vcc = 4.5V VOL2 — 0.2 V IOL =100 µA; Vcc = Vcc Min. VOH1 2.4 — V IOH = -400 µA; Vcc = 4.5V VOH2 VCC-0.2 — V IOH = -100 µA; Vcc = Vcc Min. Input leakage current ILI -10 10 µA VIN = VSS to Vcc Output leakage current ILO -10 10 µA VOUT = VSS to Vcc pF VIN/VOUT = 0 V (Notes 1 & 2) Tamb = +25°C, FCLK = 1 MHz High level output voltage Pin capacitance (all inputs/outputs) CIN, COUT ICC write Operating current Standby current ICC read ICCS — 7 — 1.5 mA — 1 500 mA µA FCLK = 2 MHz; Vcc = 6.0V FCLK = 1 MHz; Vcc = 3.0V — 1 µA CS = Vss; DI = VSS MHz MHz ns VCC > 4.5V VCC < 4.5V Clock frequency FCLK — 2 1 Clock high time TCKH 250 — Clock low time TCKL 250 — ns Chip select setup time TCSS 50 — ns Relative to CLK Chip select hold time TCSH 0 — ns Relative to CLK Chip select low time TCSL 250 — ns Data input setup time TDIS 100 — ns Relative to CLK Data input hold time TDIH 100 — ns Relative to CLK Data output delay time TPD — 400 ns CL = 100 pF Data output disable time TCZ — 100 ns CL = 100 pF (Note 2) Status valid time TSV — 500 ns CL = 100 pF TWC — 6 ms ERASE/WRITE mode ERAL mode Program cycle time Endurance TEC — 6 ms TWL — 15 ms — 1M — cycles WRAL mode 25°C, VCC = 5.0V, Block Mode (Note 3) Note 1: This parameter is tested at Tamb = 25°C and Fclk = 1 MHz. 2: This parameter is periodically sampled and not 100% tested. 3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on our website. DS21173E-page 2 2000 Microchip Technology Inc. 93LC46A/B 2.0 PIN DESCRIPTION CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle. 2.1 Chip Select (CS) After detection of a START condition the specified number of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (Table 2-1 and Table 2-2). CLK and DI then become don't care inputs waiting for a new START condition to be detected. A high level selects the device; a low level deselects the device and forces it into standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the programming cycle is completed. 2.3 CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a RESET status. 2.2 Data In (DI) Data In (DI) is used to clock in a START bit, opcode, address, and data synchronously with the CLK input. Serial Clock (CLK) 2.4 The Serial Clock is used to synchronize the communication between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. Data Out (DO) Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address, and data. This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY status information is available on the DO pin if CS is brought high after being low for minimum chip select low time (TCSL) and an ERASE or WRITE operation has been initiated. CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a START condition). The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready. TABLE 2-1 INSTRUCTION SET FOR 93LC46A Instruction SB Opcode Address Data In Data Out Req. CLK Cycles ERASE 1 11 A6 A5 A4 A3 A2 A1 ERAL 1 00 1 0 X X X X A0 — (RDY/BSY) 10 X — (RDY/BSY) 10 EWDS 1 00 0 0 X X X EWEN 1 00 1 1 X X X X X — HIGH-Z 10 X X — HIGH-Z 10 READ 1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18 WRITE 1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY) 18 WRAL 1 00 0 1 X X X X X D7 - D0 (RDY/BSY) 18 TABLE 2-2 INSTRUCTION SET FOR 93LC46B Instruction SB Opcode Address ERASE 1 11 A5 A4 A3 A2 A1 Data In Data Out Req. CLK Cycles A0 — (RDY/BSY) 9 ERAL 1 00 1 0 X X X X — (RDY/BSY) 9 EWDS 1 00 0 0 X X X X — HIGH-Z 9 EWEN 1 00 1 1 X X X X — HIGH-Z 9 READ 1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY) 25 WRAL 1 00 0 1 X X X X D15 - D0 (RDY/BSY) 25 2000 Microchip Technology Inc. DS21173E-page 3 93LC46A/B 3.0 FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS. 3.1 START Condition The START bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a START condition is detected, CS, CLK, and DI may change in any combination (except to that of a START condition), without resulting in any device operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode. An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in. FIGURE 3-1: CS After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don’t care bits until a new START condition is detected. 3.2 Data In (DI) and Data Out (DO) It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin. 3.3 Data Protection During power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions. The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional protection against accidentally programming during normal operation. SYNCHRONOUS DATA TIMING VIH TCSS VIL TCKH TCKL TCSH VIH CLK VIL TDIS TDIH VIH DI VIL TPD TPD VOH DO (READ) VOL TCZ TSV DO VOH (PROGRAM) VOL Note: TCZ STATUS VALID AC Test Conditions: VIL = 0.4V, VIH = 2.4V DS21173E-page 4 2000 Microchip Technology Inc. 93LC46A/B 3.4 ERASE 3.5 The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle. The Erase All (ERAL) instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction. FIGURE 3-2: Erase All (ERAL) The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire ERAL cycle is complete. ERASE TIMING TCSL CS CHECK STATUS CLK 1 DI 1 1 AN AN-1 AN-2 ••• A0 TCZ TSV DO HIGH-Z BUSY READY HIGH-Z TWC FIGURE 3-3: ERAL TIMING TCSL CS CHECK STATUS CLK 1 DI 0 0 1 0 X ••• X TSV DO HIGH-Z BUSY TCZ READY HIGH-Z TEC Guaranteed at Vcc = 4.5V to +6.0V. 2000 Microchip Technology Inc. DS21173E-page 5 93LC46A/B 3.6 ERASE/WRITE Disable and Enable (EWDS/EWEN) 3.7 The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93LC46A) or 16-bit (93LC46B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. The 93LC46A/B powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. FIGURE 3-4: READ EWDS TIMING TCSL CS CLK 1 DI FIGURE 3-5: 0 0 0 0 ••• X X EWEN TIMING TCSL CS CLK 0 1 DI FIGURE 3-6: 0 1 1 ••• X X READ TIMING CS CLK DI DO 1 HIGH-Z DS21173E-page 6 1 0 An ••• A0 0 Dx ••• D0 Dx ••• D0 Dx ••• D0 2000 Microchip Technology Inc. 93LC46A/B 3.8 WRITE 3.9 The WRITE instruction is followed by 8 bits (93LC46A) or 16 bits (93LC46B) of data which are written into the specified address. After the last data bit is put on the DI pin, the falling edge of CS initiates the self-timed autoerase and programming cycle. The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. FIGURE 3-7: Write All (WRAL) The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (TCSL). WRITE TIMING TCSL CS CLK DI 1 0 1 An ••• A0 Dx ••• D0 TSV HIGH-Z DO TCZ READY BUSY HIGH-Z Twc FIGURE 3-8: WRAL TIMING TCSL CS CLK DI 1 0 0 0 1 X ••• X Dx ••• D0 TSV DO HIGH-Z BUSY TCZ READY HIGH-Z TWL Guaranteed at Vcc = 4.5V to +6.0V. 2000 Microchip Technology Inc. DS21173E-page 7 93LC46A/B NOTES: DS21173E-page 8 2000 Microchip Technology Inc. 93LC46A/B NOTES: 2000 Microchip Technology Inc. DS21173E-page 9 93LC46A/B NOTES: DS21173E-page 10 2000 Microchip Technology Inc. 93LC46A/B 93LC46A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 93LC46A/B — /P Package: Temperature Range: P SN SM ST Plastic DIP (300 mil Body), 8-lead Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (208 mil Body), 8-lead TSSOP, 8-lead Blank = 0 °C to +70°C I = -40°C to +85°C 93LC46A 93LC46AT 93LC46AX 93LC46AXT Device: = = = = 93LC46B 93LC46BT 93LC46BX 93LC46BXT 1K Microwire Serial EEPROM (x8) 1K Microwire Serial EEPROM (x8) Tape and Reel 1K Microwire Serial EEPROM (x8) in alternate pinout (SN only) 1K Microwire Serial EEPROM (x8) in alternate pinout, Tape and Reel (SN only) 1K Microwire Serial EEPROM (x16) 1K Microwire Serial EEPROM (x16) Tape and Reel 1K Microwire Serial EEPROM (x16) in alternate pinout (SN only) 1K Microwire Serial EEPROM (x16) in alternate pinout, Tape and Reel (SN only) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. DS21173E-page 11 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office China - Beijing Singapore 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. 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Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 2/01 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/01/00 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS21173E-page 12 2000 Microchip Technology Inc.