EMIF07-LCD02F3 7-line IPAD™, EMI filter and ESD protection for LCD and cameras Features ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency in EMI filtering ■ Lead-free package ■ Very low PCB space occupation: 1.94 mm x 1.54 mm Flip Chip (18 bumps) ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging Figure 1. Pin layout (bump side) 5 4 3 2 1 O1 O2 GND I1 I2 A I3 B Complies with the following standards ■ ■ GND IEC 61000-4-2 level 4 on inputs and outputs: – 15 kV (air discharge) – 8 kV (contact discharge) O3 O4 O5 GND I4 I5 C MIL STD 883G - Method 3015-7 Class 3 O6 O7 GND I6 I7 D Applications Where EMI filtering in ESD sensitive equipment is required: ■ LCD for mobile phones ■ Computers and printers ■ Communication systems ■ MCU boards Figure 2. Device configuration Low-pass Filter Output Input GND Description GND GND Ri/o = 70 Ω Cline = 30 pF The EMIF07-LCD02F3 is a 7-line highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. The EMIF07 Flip Chip package means the package size is equal to the die size. This filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. February 2010 TM: IPAD is a trademark of STMicroelectronics. Doc ID 11639 Rev 3 1/8 www.st.com 8 Characteristics 1 EMIF07-LCD02F3 Characteristics Table 1. Symbol Tj Absolute maximum ratings (Tamb = 25 °C) Parameter and test conditions Unit 125 °C Maximum junction temperature Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameters I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage IPP Peak pulse current RI/O Series resistance between input and output Cline Input capacitance per line Symbol IF VF VCL VBR VRM V IRM IR Test conditions IPP Min Typ Max Unit 6 8 10 V 200 nA VBR IR = 1 mA IRM VRM = 3 V 50 R2 Tolerance ± 20% 70 Cline 2/8 Value Vline = 0 V, VOSC = 30 mV, F =1 MHz Doc ID 11639 Rev 3 Ω 30 pF EMIF07-LCD02F3 Figure 3. Characteristics Attenuation measurement and Aplac simulation Figure 4. dB 0.00 0.00 Analog cross talk measurement dB -10.00 -20.00 -10.00 -30.00 -20.00 -40.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 F (Hz) -50.00 100.0k -90.00 1.0M 10.0M 100.0M Line 1 Line 3 Line 5 Line 7 Figure 5. F (Hz) 1.0G -100.00 100.0k Line 2 Line 4 Line 6 1.0M 10.0M 100.0M 1.0G Xtalk 1/2 Voltages when IEC 61000-4-2 (+15 kV air discharge) applied to input pin Figure 6. Voltages when IEC 61000-4-2 (-15 kV air discharge) applied to input pin 10 V/div 10 V/div Input Input 10 V/div 10 V/div Output Output 100 ns/div Figure 7. 100 ns/div Line capacitance versus applied voltage Cline (pF) 30 25 20 15 10 5 Vline (V) 0 0 1 2 3 4 Doc ID 11639 Rev 3 5 6 3/8 Application information 2 EMIF07-LCD02F3 Application information Figure 8. Aplac model Lbump Rbump Rline Rbump Lbump O1 I1 MODEL = D1 MODEL = D2 bulk bulk MODEL = D3 Cbump Figure 9. Rbump Rbump Rbump Rbump Cbump Lbump Cbump Lbump Cbump Lbump Lbump Rgnd Rgnd Rgnd Rgnd Lgnd Lgnd Lgnd Lgnd Aplac parameters aplacvar Rline 70 aplacvar C_d1 15p aplacvar C_d2 15p aplacvar C_d3 600p aplacvar Ls 950pH aplacvar Rs 150m aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Cbump 150f aplacvar Lgnd 50pH aplacvar Rgnd 100m aplacvar Rsub 10m 4/8 Diode D1 BV=7 IBV=1m CJO=C_d1 M=0.28 RS=0.1 VJ=0.6 TT=100n Doc ID 11639 Rev 3 Diode D2 BV=7 IBV=1m CJO=C_d2 M=0.28 RS=0.1 VJ=0.6 TT=100n Diode D3 BV=7 IBV=1m CJO=C_d3 M=0.28 RS=0.01 VJ=0.6 TT=100n EMIF07-LCD02F3 3 Ordering information scheme Ordering information scheme Figure 10. Ordering information scheme EMIF yy - xxx zz F3 EMI filter Number of lines Information x = resistance value (ohm) z = capacitance value / 10 (pF) or 3 letters = application 2 digits = version Package F = Flip Chip 3 = Lead-free, pitch = 400 µm, bump = 255 µm Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 11. Package dimensions 400 µm ± 40 255 µm± 40 605 µm ± 55 1.54 mm ± 30 µm 400 µm ± 40 170 µm 1.94 mm ± 30µm 170 µm 4 Doc ID 11639 Rev 3 5/8 Ordering information EMIF07-LCD02F3 Figure 12. Footprint Figure 13. Marking Dot, ST logo ECOPACK status xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 220 µm recommended 260 µm maximum Solder mask opening: 300 µm minimum x x z y ww Solder stencil opening: 220 µm recommended Dot identifying Pin A1 location Ø 1.55 ± 0.1 4.0 ± 0.1 2.0 ± 0.05 3.5 ± 0.1 2.08 xxz yww ST xxz yww ST xxz yww ST 8.0 ± 0.3 0.20 ± 0.02 1.75 ± 0.1 Figure 14. Flip Chip tape and reel specification 4.0 ± 0.1 1.71 0.69 ± 0.05 User direction of unreeling All dimensions in mm Note: More information is available in the application notes: AN2348: “STMicroelectronics 400 micro-metre Flip Chip : Package description and recommendation for use” AN1751: “EMI filters: Recommendations and measurements” 5 Ordering information Table 3. 6/8 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF07-LCD02F3 GX Flip Chip 3.9 mg 5000 Tape and reel 7” Doc ID 11639 Rev 3 EMIF07-LCD02F3 6 Revision history Revision history Table 4. Document revision history Date Revision Changes 12-Sep-2005 1 First issue. 28-Apr-2008 2 Updated ECOPACK statement. Updated Figure 10, Figure 11 and Figure 14. Reformatted to current standards. 19-Feb-2010 3 Updated die size in Figure 11. Doc ID 11639 Rev 3 7/8 EMIF07-LCD02F3 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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