ESDA6V1W5 ® QUAL TRANSIL ARRAY FOR ESD PROTECTION Application Specific Discretes A.S.D. MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : Computers Printers Communication systems GSM handsets and accessories Other telephone sets Set top boxes FEATURES 4 unidirectional TRANSIL functions. Breakdown voltage : VBR = 6.1 V min. Low leakage current : < 1µA. Very low PCB space consuming : 4.2 mm2 typically. DESCRIPTION The ESDA6V1W5 is a 4-bit wide monolithic suppressor which is designed to protect component connected to data and transmission lines against ESD. It clamps the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transients. SOT323-5L FUNCTIONAL DIAGRAM 1 5 2 3 4 BENEFITS High ESD protection level : up to 25 kV. High integration. Suitable for high density boards. ESD RESPONSE TO IEC1000-4-2 (air discharge 16 kV, positive surge) COMPLIES WITH THE FOLLOWING STANDARDS : IEC 1000-4-2 level 4 MIL STD 883C-Method 3015-6 : class 3. (human body model) September 1999 - Ed: 1A 1/7 ESDA6V1W5 ABSOLUTE MAXIMUM RATINGS (Tamb = 25°C) Symbol Parameter VPP ESD discharge PPP Peak pulse power (8/20 µs) Top Operating temperature range Tj Test conditions Value Unit MIL STD 883C - Method 3015-6 IEC1000-4-2, air discharge IEC1000-4-2, contact discharge 25 16 9 kV 150 W - 40 to + 85 °C 150 °C - 55 to + 150 °C 260 °C Junction temperature Tstg Storage temperature range TL Lead solder temperature (10 secondes duration) ELECTRICAL CHARACTERISTICS (Tamb = 25°C) Symbol Parameter Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current αT Voltage temperature coefficient C Capacitance per line Rd Dynamic resistance VF Forward voltage drop Types VBR min. ESDA6V1W5 @ VCL VBR VRM V IRM IR slope : 1 / R d IR max. IRM @ VRM max. IPP Rd αT C typ. max. typ. note 1 note 2 0V bias -4 VF @ IF max. V V mA µA V mΩ 10 /°C pF V mA 6.1 7.2 1 1 3 350 6 90 1.25 200 note 1 : Square pulse Ipp = 15A, tp=2.5µs. note 2 : ∆ VBR = αT* (Tamb -25°C) * VBR (25°C) 2/7 I VRM ESDA6V1W5 CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula: VCL = VBR + Rd IPP Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20µs and 10/1000µs surges. I Ipp 2µs t tp = 2.5µs 2.5µs duration measurement wave. As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd. 3/7 ESDA6V1W5 Fig. 1 : Peak power dissipation versus initial junction temperature Fig. 2 : Peak pulse power versus exponential pulse duration (Tj initial = 25 °C) Ppp[Tj initial]/Ppp[Tj initial=25°C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Ppp(W) 1000 100 tp(µs) Tj initial(°C) 0 25 50 75 100 10 125 150 175 Fig. 3 : Clamping voltage versus peak pulse current (Tj initial = 25 °C). Rectangular waveform tp = 2.5 µs. 1 10 100 Fig. 4 : Capacitance versus reverse applied voltage (typical values). Ipp(A) 90 50.0 C(pF) 80 tp=2.5µs F=1MHz Vosc=30mV 70 10.0 60 50 40 1.0 30 20 Vcl(V) 0.1 0 5 10 15 20 25 30 VR(V) 10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Fig. 6 : Peak forward voltage drop versus peak forward current (typical values). Fig. 5 : Relative variation of leakage current versus junction temperature (typical values). IR[Tj] / IR[Tj=25°C] IFM(A) 1E+0 5 4 Tj=25°C 3 1E-1 2 1E-2 Tj(°C) 1 25 4/7 50 75 100 VFM(V) 125 150 1E-3 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 ESDA6V1W5 1. ESD protection by the ESDA6V1W5 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system. Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. A Keyboard terminal printer etc B I/O C FUNCTIONAL DECODER D The ESDA6V1W5 array is the ideal product for use as board level protection of ESD sensitive semiconductor components. The tiny SOT323-5L package makes the ESDA6V1W5 device some of the smallest ESD protection devices available. It also allows design flexibility in the design of "crowded" boards where the space saving is at a premium. This enables to shorten the routing and can contribute to improved ESD performance. 2. Circuit Board Layout Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : The ESDA6V1W5 should be placed as near as possible to the input terminals or connectors. Minimise the path length between the ESD suppressor and the protected device Minimise all conductive loops, including power and ground loops The ESD transient return path to ground should be kept as short as possible. Use ground planes whenever possible. 5/7 ESDA6V1W5 ORDER CODE ESDA 6V1 W5 ESD ARRAY PACKAGE : SOT323-5L VBR min Ordering type Marking Package Weight Base qty Delivery mode ESDA6V1W5 E61 SOT323-5L 5.4 mg. 3000 Tape & reel PACKAGE MECHANICAL DATA SOT323-5L DIMENSIONS REF. A A2 A1 D e H c Inches Min. Max. Min. Max. A 0.8 1.1 0.031 0.043 A1 0 0.1 0 0.004 A2 0.8 1 0.031 0.039 b 0.15 0.3 0.006 0.012 c 0.1 0.18 0.004 0.007 D 1.8 2.2 0.071 0.086 E 1.15 1.35 0.045 0.053 e E Q1 Millimeters e 0.65 Typ. 0.026 Typ. H 1.8 2.4 0.071 0.094 Q1 0.1 0.4 0.004 0.016 b FOOT PRINT (in millimeters) Mechanical specifications 0.3mm 1mm 29mm 1mm 0.35mm 6/7 Lead plating Tin-lead Lead plating thickness 5µm min. 25 µm max. Lead material Sn / Pb (70% to 90% Sn) Lead coplanarity 10µm max. Body material Molded epoxy Epoxy meets UL94,V0 ESDA6V1W5 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - Printed in Italy - All rights reserved. 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