TI MSP430F2112IPW

MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultra-Low Power Consumption:
-- Active Mode: 200 µA at 1 MHz, 2.2 V
-- Standby Mode: 0.7 µA
-- Off Mode (RAM Retention): 0.1 µA
D Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
D 16-Bit RISC Architecture,
62.5-ns Instruction Cycle Time
D Basic Clock Module Configurations:
-- Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very Low-Power Low-Frequency
Oscillator
-- 32-kHz Crystal
-- High-Frequency Crystal up to 16 MHz
-- Resonator
-- External Digital Clock Source
-- External Resistor
D 16-Bit Timer0_A3 With Three
D
D
D
Capture/Compare Registers
16-Bit Timer1_A2 With Two
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope
Analog-to-Digital (A/D) Conversion
10-Bit, 200-ksps A/D Converter With
Internal Reference, Sample-and-Hold,
Autoscan, and Data Transfer Controller
D Universal Serial Communication Interface
-- Enhanced UART Supporting Auto
Baudrate Detection (LIN)
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- I2Ct
D Brownout Detector
D Serial Onboard Programming,
No External Programming Voltage Needed,
Programmable Code Protection by
Security Fuse
Bootstrap Loader in Flash Devices
On-Chip Emulation Module
D
D
D Family Members Include:
MSP430F2132
-- 8KB + 256B Flash Memory
-- 512B RAM
MSP430F2122
-- 4KB + 256B Flash Memory
-- 512B RAM
MSP430F2112
-- 2kB + 256B Flash Memory
-- 256B RAM
D Available in 28-Pin TSSOP and 32-Pin QFN
(See Available Options)
D For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide,
Literature Number SLAU144
description
The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 µs.
The MSP430F21x2 series is an ultra-low-power microcontroller with two built-in 16-bit timers, a fast 10-bit A/D
converter with integrated reference and a data transfer controller (DTC), a comparator, built-in communication
capability using the universal serial communication interface, and up to 24 I/O pins.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
Copyright  2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
AVAILABLE OPTIONS
TA
--40°C
40 C to 85°C
85 C
--40°C
40 C to 105°C
105 C
2
PACKAGED DEVICES
PLASTIC 28-PIN TSSOP (PW)
PLASTIC 32-PIN QFN (RHB)
MSP430F2112IPW
MSP430F2112IRHB
MSP430F2122IPW
MSP430F2122IRHB
MSP430F2132IPW
MSP430F2132IRHB
MSP430F2112TPW
MSP430F2112TRHB
MSP430F2122TPW
MSP430F2122TRHB
MSP430F2132TPW
MSP430F2132TRHB
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
pin designation, PW package
TEST/SBWTCK
DVCC
1
2
28
27
P1.7/TA2_0/TDO/TDI
P1.6/TA1_0/TDI/TCLK
P2.5/ROSC/CA5
DVSS
3
4
26
25
P1.5/TA0_0/TMS
P1.4/SMCLK/TCK
XOUT/P2.7/CA7
XIN/P2.6/CA6
RST/NMI/SBWTDIO
5
6
7
24
23
22
P1.3/TA2_0
P1.2/TA1_0
P1.1/TA0_0/TA0_1
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/SMCLK/A1/CA3
8
9
21
20
P1.0/TACLK/ADC10CLK/CAOUT
P2.4/TA2_0/A4/VREF+/VeREF+/CA1
P2.2/TA0_0/A2/CA4/CAOUT
P3.0/UCB0STE/UCA0CLK/A5
10
11
19
18
P2.3/TA1_0/A3/VREF-/VeREF-/CA0
P3.7/TA1_1/A7
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
12
13
14
17
16
15
P3.6/TA0_1/A6
P3.5/UCA0RXD/UCA0SOMI
P3.4/UCA0TXD/UCA0SIMO
P2.5/ROSC/CA5
NC
DVCC
TEST/SBWTCK
P1.7/TA2_0/TDO/TDI
P1.6/TA1_0/TDI/TCLK
P1.5/TA0_0/TMS
P1.4/SMCLK/TCK
pin designation, RHB package
32 31 30 29 28 27 26 25
1
24
2
23
P1.3/TA2_0
P1.2/TA1_0
XIN/P2.6/CA6
3
22
P1.1/TA0_0/TA0_1
NC
4
21
P1.0/TACLK/ADC10CLK/CAOUT
RST/NMI/SBWTDIO
P2.0/ACLK/A0/CA2
5
6
20
19
NC
P2.4/TA2_0/A4/VREF+/VeREF+/CA1
P2.1/TAINCLK/SMCLK/A1/CA3
7
18
P2.3/TA1_0/A3/VREF-/VeREF-/CA0
P2.2/TA0_0/A2/CA4/CAOUT
8
17
9 10 11 12 13 14 15 16
NC
P3.0/UCB0STE/UCA0CLK/A5
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3.6/TA0_1/A6
P3.7/TA1_1/A7
DVSS
XOUT/P2.7/CA7
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
functional block diagram
XIN
XOUT
DVCC
D/AVSS
AVCC
P1.x
P3.x
P2.x
8
8
8
ADC10
Port P1
Port P2
Port P3
10-bit
8
Channels
Autoscan
DTC
8 I/O
Interrupt
capability
pull-up/down
resistors
8 I/O
Interrupt
capability
pull-up/down
resistors
8 I/O
Watchdog
WDT+
Timer0_A3
Timer1_A2
3 CC
Registers
2 CC
Registers
ACLK
Basic Clock
System+ SMCLK
Flash
RAM
8kB
4kB
2kB
512B
512B
256B
MCLK
16MHz
CPU
incl. 16
Registers
MAB
MDB
Emulation
2BP
JTAG
Interface
Brownout
Protection
Comp_A+
15-Bit
Spy-Bi
Wire
RST/NMI
4
pull-up
pull-down
resistors
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USCI A0
UART/
LIN,
IrDA, SPI
USCI B0
SPI, I2C
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Terminal Functions
TERMINAL
28-Pin
PW
32-Pin
RHB
I/O
P1.0/TACLK/
ADC10CLK/CAOUT
21
21
I/O
General-purpose digital I/O pin
Timer0_A3, clock signal TACLK input
Timer1_A2, clock signal TACLK input
ADC10, conversion clock
Comparator_A+ output
P1.1/TA0_0/TA0_1
22
22
I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI0A input, compare: Out0_0 Output
Timer1_A2, capture: CCI0A input
P1.2/TA1_0
23
23
I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI1A input, compare: Out1_0 Output
P1.3/TA2_0
24
24
I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI2A input, compare: Out2_0 Output
P1.4/SMCLK/TCK
25
25
I/O
General-purpose digital I/O pin
SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0_0/TMS
26
26
I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out0_0 Output
JTAG test mode select, input terminal for device programming and test
P1.6/TA1_0/TDI/TCLK
27
27
I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out1_0 Output
JTAG test data input or test clock input in programming an test
P1.7/TA2_0/TDO/TDI
28
28
I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out2_0 Output
JTAG test data output terminal or test data input in programming an test
P2.0/ACLK/A0/CA2
8
6
I/O
General-purpose digital I/O pin
ACLK signal output
ADC10 analog input A0
Comparator_A+ input
P2.1/TAINCLK/
SMCLK/A1/CA3
9
7
I/O
General-purpose digital I/O pin
SMCLK signal output
Timer0_A3, clock signal TACLK input
Timer1_A2, clock signal TACLK input
ADC10 analog input A1
Comparator_A+ input
P2.2/TA0_0/A2/CA4/
CAOUT
10
8
I/O
General-purpose digital I/O pin
Timer0_A3, capture: CCI0B input, compare: Out0_0 Output
ADC10 analog input A2
Comparator_A+ input
Comparator_A+ output
P2.3/TA1_0/A3/
VREF-- /VeREF-- /CA0
19
18
I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out1_0 Output
ADC10 analog input A3 / negative reference
Comparator_A+ input
P2.4/TA2_0/A4/
VREF+/VeREF+/CA1
20
19
I/O
General-purpose digital I/O pin
Timer0_A3, compare: Out2_0 Output
ADC10 analog input A4 / positive reference
Comparator_A+ input
NAME
DESCRIPTION
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Terminal Functions
TERMINAL
28-Pin
PW
32-Pin
RHB
I/O
XIN/P2.6/CA6
6
3
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Comparator_A+ input
XOUT/P2.7/CA7
5
2
I/O
Output terminal of crystal oscillator
General-purpose digital I/O pin
Comparator_A+ input
P3.0/UCB0STE/
UCA0CLK/A5
11
9
I/O
General-purpose digital I/O pin
USCI_B0 slave transmit enable/USCI_A0 clock input/output
ADC10 analog input A5
P3.1/UCB0SIMO/
UCB0SDA
12
10
I/O
General-purpose digital I/O pin
USCI_B0 slave in/master out in SPI mode, SDA I2C data in I2C mode
P3.2/UCB0SOMI/
UCB0SCL
13
11
I/O
General-purpose digital I/O pin
USCI_B0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.3/UCB0CLK/
UCA0STE
14
12
I/O
General-purpose digital I/O
USCI_B0 clock input/output, USCI_A0 slave transmit enable
P3.4/UCA0TXD/
UCA0SIMO
15
13
I/O
General-purpose digital I/O pin
USCI_A0 transmit data output in UART mode, slave data in/master out in SPI mode
P3.5/UCA0RXD/
UCA0SOMI
16
14
I/O
General-purpose digital I/O pin
USCI_A0 receive data input in UART mode, slave data out/master in in SPI mode
P3.6/TA0_1/A6
17
15
I/O
General-purpose digital I/O pin
Timer1_A2, capture: CCI0B input, compare: Out0_1 Output
ADC10 analog input A6
P3.7/TA1_1/A7
18
16
I/O
General-purpose digital I/O pin
Timer1_A2, capture: CCI1A input, compare: Out1_1 Output
ADC10 analog input A7
RST/NMI/SBWTDIO
7
5
I
Reset or nonmaskable interrupt input
Spy--bi--Wire test data input/output during programming and test
TEST/SBWTCK
1
29
I
Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST.
P2.5/ROSC/CA5
3
32
I/O
DVCC
2
30
Digital supply voltage
4
1
Digital supply voltage
NA
4, 17,
20, 31
NAME
DVSS
NC
6
DESCRIPTION
General-purpose digital I/O pin
Input for external resistor defining the DCO nominal frequency
Comparator_A+ input
Not connected internally. Recommended connection to VSS.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining
registers
are
general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g., ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g., CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g., JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
Absolute
F F
MOV &MEM,&TCDAT
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ----> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ----> R11
R10 + 2----> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
SYNTAX
EXAMPLE
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
#45
----> M(TONI)
D = destination
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
--
All clocks are active.
D Low-power mode 0 (LPM0)
--
CPU is disabled.
--
ACLK and SMCLK remain active, MCLK is disabled.
D Low-power mode 1 (LPM1)
--
CPU is disabled.
--
ACLK and SMCLK remain active, MCLK is disabled.
--
DCO’s dc generator is disabled if DCO not used in active mode.
D Low-power mode 2 (LPM2)
--
CPU is disabled.
--
MCLK and SMCLK are disabled.
--
DCO’s dc generator remains enabled.
--
ACLK remains active.
D Low-power mode 3 (LPM3)
--
CPU is disabled.
--
MCLK and SMCLK are disabled.
--
DCO’s dc-generator is disabled.
--
ACLK remains active.
D Low-power mode 4 (LPM4)
8
--
CPU is disabled.
--
ACLK is disabled.
--
MCLK and SMCLK are disabled.
--
DCO’s dc generator is disabled.
--
Crystal oscillator is stopped.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. If the reset
vector (0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU enters LPM4 after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out of range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0xFFFE
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 6)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC
30
Maskable
0xFFFA
29
TA1CCR1 CCIFG,
TA1CTL TAIFG
(see Notes 2 and 3)
Maskable
0xFFF8
28
Comparator_A+
CAIFG
Maskable
0xFFF6
27
Watchdog timer
WDTIFG
Maskable
0xFFF4
26
Timer0_A3
TA0CCR0 CCIFG
(see Note 3)
Maskable
0xFFF2
25
Maskable
0xFFF0
24
Timer1_A2
Timer1_A2
TA1CCR0 CCIFG
(see Note 3)
Timer0_A3
TA0CCR1 CCIFG,
TA0CCR2 CCIFG,
TA0CTL TAIFG
(see Notes 2 and 3)
USCI_A0/USCI_B0 receive
USCI_B0 I2C status
UCA0RXIFG, UCB0RXIFG
(see Note 2 and 4)
Maskable
0xFFEE
23
USCI_A0/USCI_B0 transmit
USCI_B0 I2C receive/transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 5)
Maskable
0xFFEC
22
ADC10
ADC10IFG (see Note 3)
Maskable
0xFFEA
21
0xFFE8
20
Maskable
0xFFE6
19
Maskable
0xFFE4
18
0xFFE2
17
0xFFE0
16
(See Note 7)
0xFFDE
15
(See Note 8)
0xFFDC to 0xFFC0
14 to 0, lowest
I/O port P2 (eight flags)
I/O port P1 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 and 3)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
NOTES: 1.
2.
3.
4.
5.
6.
7.
A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000 to 0x01FF).
Multiple source flags.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
7
6
00h
5
4
ACCVIE
rw--0
2
1
0
NMIIE
OFIE
WDTIE
rw--0
rw--0
rw--0
WDTIE
Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog
timer is configured in interval timer mode.
OFIE
Oscillator fault enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
Flash access violation interrupt enable
Address
7
6
5
01h
10
3
UCA0RXIE
USCI_A0 receive interrupt enable
UCA0TXIE
USCI_A0 transmit interrupt enable
UCB0RXIE
USCI_B0 receive interrupt enable
UCB0TXIE
USCI_B0 transmit interrupt enable
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4
3
2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw--0
rw--0
rw--0
rw--0
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw--0
rw--(0)
rw--(1)
rw--1
rw--(0)
WDTIFG
Set on watchdog timer overflow or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on
VCC power up
PORIFG
Power-on interrupt flag. Set on VCC power-up.
NMIIFG
Set via RST/NMI pin
Address
7
6
5
4
03h
3
2
1
0
UCB0TX
IFG
UCB0RX
IFG
UCA0TX
IFG
UCA0RX
IFG
rw--1
rw--0
rw--1
rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is reset or set by PUC.
Bit can be read and written. It is reset or set by POR.
SFR bit is not present in device
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
memory organization
MSP430F2112
MSP430F2122
MSP430F2132
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
2 KB
0xFFFF to 0xFFC0
0xFFFF to 0xF800
4 KB
0xFFFF to 0xFFC0
0xFFFF to 0xF000
8 KB
0xFFFF to 0xFFC0
0xFFFF to 0xE000
Information memory
Size
Flash
256 Byte
0x10FFh to 0x1000
256 Byte
0x10FFh to 0x1000
256 Byte
0x10FFh to 0x1000
Boot memory
Size
ROM
1 KB
0x0FFF to 0x0C00
1 KB
0x0FFF to 0x0C00
1 KB
0x0FFF to 0x0C00
Size
256 B
0x02FF to 0x0200
512 Byte
0x03FF to 0x0200
512 Byte
0x03FF to 0x0200
16-bit
8-bit
8-bit SFR
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
0x01FF to 0x0100
0x00FF to 0x0010
0x000F to 0x0000
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.
BSL FUNCTION
28-PIN PW PACKAGE PINS
32-PIN RHB PACKAGE PINS
Data transmit
22 -- P1.1
22 -- P1.1
Data receive
10 -- P2.2
8 -- P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low-frequency oscillator, an internal digitally controlled oscillator (DCO),
and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 µs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal or the internal very
low power LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
D
D Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
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13
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
calibration data stored in information memory segment A
Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.
TAGS USED BY THE ADC CALIBRATION TAGS
NAME
ADDRESS
VALUE
DESCRIPTION
TAG_DCO_30
0x10F6
0x01
DCO frequency calibration at VCC = 3 V and TA = 30°C at calibration
TAG_ADC10_1
0x10DA
0x10
ADC10_1 calibration tag
--
0xFE
Identifier for empty memory areas
TAG_EMPTY
LABELS USED BY THE ADC CALIBRATION TAGS
CONDITION AT CALIBRATION / DESCRIPTION
LABEL
SIZE
ADDRESS
OFFSET
CAL_ADC_25T85
INCHx = 0x1010, REF2_5 = 1, TA = 85°C
word
0x000E
CAL_ADC_25T30
INCHx = 0x1010, REF2_5 = 1, TA = 30°C
word
0x000C
REF2_5 = 1, TA = 30°C, IVREF+ = 1 mA
word
0x000A
CAL_ADC_15T85
INCHx = 0x1010, REF2_5 = 0, TA = 85°C
word
0x0008
CAL_ADC_15T30
INCHx = 0x1010, REF2_5 = 0, TA = 30°C
word
0x0006
CAL_ADC_15VREF_FACTOR
CAL_ADC_25VREF_FACTOR
REF2_5 = 0, TA = 30°C, IVREF+ = 0.5 mA
word
0x0004
CAL_ADC_OFFSET
External VREF = 1.5 V, fADC10CLK = 5 MHz
word
0x0002
CAL_ADC_GAIN_FACTOR
External VREF = 1.5 V, fADC10CLK = 5 MHz
word
0x0000
CAL_BC1_1MHz
--
byte
0x0007
CAL_DCO_1MHz
--
byte
0x0006
CAL_BC1_8MHz
--
byte
0x0005
CAL_DCO_8MHz
--
byte
0x0004
CAL_BC1_12MHz
--
byte
0x0003
CAL_DCO_12MHz
--
byte
0x0002
CAL_BC1_16MHz
--
byte
0x0001
CAL_DCO_16MHz
--
byte
0x0000
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are three 8-bit I/O ports implemented—ports P1 through P3:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pullup/pulldown resistor.
The MSP430F21x2 devices provides up to 24 total port I/O pins available externally. See the device pinout for
more information.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
watchdog timer + (WDT+)
The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
ADC10
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and data transfer controller (DTC), for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
Comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
Timer0_A3
Timer0_A3 is a 16-bit timer/counter with three capture/compare registers. Timer0_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer0_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER0_A3 SIGNAL CONNECTIONS
INPUT PIN NUMBER
28-PIN PW
32-PIN RHB
DEVICE
INPUT SIGNAL
21 -- P1.0
21 -- P1.0
TACLK
MODULE
INPUT
NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
28-PIN PW
32-PIN RHB
9 -- P2.1
7 -- P2.1
TAINCLK
INCLK
22 -- P1.1
22 -- P1.1
TA0
CCI0A
22 -- P1.1
22 -- P1.1
10 -- P2.2
8 -- P2.2
TA0
CCI0B
26 -- P1.5
26 -- P1.5
23 -- P1.2
24 -- P1.3
23 -- P1.2
24 -- P1.3
CCR0
TA0
DVSS
GND
10 -- P2.2
8 -- P2.2
DVCC
VCC
ADC10 (internal)
ADC10 (internal)
TA1
CCI1A
23 -- P1.2
23 -- P1.2
CAOUT (internal)
CCI1B
27 -- P1.6
27 -- P1.6
DVSS
GND
19 - P2.3
18 -- P2.3
CCR1
TA1
DVCC
VCC
ADC10 (internal)
ADC10 (internal)
TA2
CCI2A
24 -- P1.3
24 -- P1.3
ACLK (internal)
CCI2B
28 -- P1.7
28 -- P1.7
DVSS
GND
DVCC
VCC
POST OFFICE BOX 655303
CCR2
• DALLAS, TEXAS 75265
TA2
20 - P2.4
19 -- P2.4
ADC10 (internal)
ADC10 (internal)
15
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Timer1_A2
Timer1_A2 is a 16-bit timer/counter with two capture/compare registers. Timer1_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer1_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
TIMER1_A2 SIGNAL CONNECTIONS
INPUT PIN NUMBER
28-PIN PW
32-PIN RHB
DEVICE INPUT
SIGNAL
21 -- P1.0
21 -- P1.0
TACLK
MODULE
INPUT NAME
TACLK
ACLK
ACLK
SMCLK
SMCLK
9 -- P2.1
7 -- P2.1
TAINCLK
INCLK
22 -- P1.1
22 -- P1.1
TA0
CCI0A
17 -- P3.6
15 -- P3.6
TA0
CCI0B
DVSS
GND
18 -- P3.7
16 -- P3.7
DVCC
VCC
TA1
CCI1A
CAOUT (internal)
CCI1B
DVSS
GND
DVCC
VCC
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
CCR1
OUTPUT PIN NUMBER
28-PIN PW
32-PIN RHB
17 -- P3.6
15 -- P3.6
18 -- P3.7
16 -- P3.7
TA0
TA1
universal serial communications interface (USCI)
The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the
USCI functionality.
USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.
USCI_B0 provides support for SPI (3 or 4 pin) and I2C.
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
peripheral file map
PERIPHERALS WITH WORD ACCESS
ADC10
ADC data transfer start address
ADC memory
ADC control register 1
ADC control register 0
ADC analog enable 0
ADC analog enable 1
ADC data transfer control register 1
ADC data transfer control register 0
ADC10SA
ADC10MEM
ADC10CTL1
ADC10CTL0
ADC10AE0
ADC10AE1
ADC10DTC1
ADC10DTC0
0x01BC
0x01B4
0x01B2
0x01B0
0x004A
0x004B
0x0049
0x0048
Timer0_A3
Capture/compare register
Capture/compare register
Capture/compare register
Timer0_A3 register
Capture/compare control
Capture/compare control
Capture/compare control
Timer0_A3 control
Timer0_A3 interrupt vector
TA0CCR2
TA0CCR1
TA0CCR0
TA0R
TA0CCTL2
TA0CCTL1
TA0CCTL0
TA0CTL
TA0IV
0x0176
0x0174
0x0172
0x0170
0x0166
0x0164
0x0162
0x0160
0x012E
Timer1_A2
Capture/compare register
Capture/compare register
Timer1_A2 register
Capture/compare control
Capture/compare control
Timer1_A2 control
Timer1_A2 interrupt vector
TA1CCR1
TA1CCR0
TA1R
TA1CCTL1
TA1CCTL0
TA1CTL
TA1IV
0x0194
0x0192
0x0190
0x0184
0x0182
0x0180
0x011E
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
0x012C
0x012A
0x0128
Watchdog Timer+
Watchdog/timer control
WDTCTL
0x0120
PERIPHERALS WITH BYTE ACCESS
USCI_B0
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI B0 I2C Interrupt enable
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0CIE
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
0x06F
0x06E
0x06D
0x06C
0x06B
0x06A
0x069
0x068
0x011A
0x0118
USCI_A0
(28--pin and 32--pin version
only)
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x005D
Comparator_A+
Comparator_A port disable
Comparator_A control2
Comparator_A control1
CAPD
CACTL2
CACTL1
0x005B
0x005A
0x0059
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17
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
PERIPHERALS WITH BYTE ACCESS (continued)
18
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
0x0053
0x0058
0x0057
0x0056
Port P3
Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3REN
P3SEL
P3DIR
P3OUT
P3IN
0x0010
0x001B
0x001A
0x0019
0x0018
Port P2
Port P2 selection 2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2SEL2
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
0x0042
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
Port P1
Port P1 selection 2 register
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1SEL2
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
0x0041
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
0x0003
0x0002
0x0001
0x0000
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to + 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Storage temperature (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution, VCC
AVCC = DVCC = VCC (see Note 1)
1.8
3.6
V
Supply voltage during flash memory programming, VCC
AVCC = DVCC = VCC (see Note 1)
2.2
3.6
V
Supply voltage, VSS
AVSS = DVSS = VSS
0.0
0.0
V
I version
--40
85
T version
--40
105
VCC = 1.8 V,
Duty cycle = 50% ±10%
dc
6
VCC = 2.7 V,
Duty cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V,
Duty cycle = 50% ±10%
dc
16
Operating free-air
free air temperature range,
range TA
Processor frequency fSYSYTEM (Maximum MCLK frequency)
(see Notes 1, 2 and Figure 1)
°C
MHz
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Legend:
System Frequency --MHz
16 MHz
Supply voltage range,
during flash memory
programming
12 MHz
Supply voltage range,
during program execution
6 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage --V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
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• DALLAS, TEXAS 75265
19
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
IAM,100kHz
Active mode (AM)
current (1MHz)
Active mode (AM)
current (1MHz)
Active mode (AM)
current (4kHz)
Active mode (AM)
current (100kHz)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes from flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
2.2 V
MIN
TYP
MAX
200
250
µA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
300
2.2 V
160
3V
fMCLK = fSMCLK =
fACLK = 32,768Hz/8 = 4,096Hz,
fDCO = 0Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
--40°C to 85°C
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz
0Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0
0, SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
--40°C to 85°C
POST OFFICE BOX 655303
350
µA
260
2
5
22V
2.2
105_C
6
µA
--40°C to 85°C
3
7
3V
105_C
105_C
--40°C to 85°C
105_C
9
22V
2.2
3V
60
• DALLAS, TEXAS 75265
85
90
72
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
20
UNIT
95
100
µA
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
typical characteristics -- active mode supply current (into DVCC + AVCC)
8.0
5.0
fDCO = 16 MHz
6.0
fDCO = 12 MHz
5.0
4.0
fDCO = 8 MHz
3.0
2.0
4.0
TA = 25 °C
3.0
VCC = 3 V
TA = 85 °C
2.0
TA = 25 °C
1.0
1.0
0.0
1.5
TA = 85 °C
Active Mode Current -- mA
Active Mode Current -- mA
7.0
VCC = 2.2 V
fDCO = 1 MHz
2.0
2.5
3.0
3.5
4.0
0.0
0.0
VCC -- Supply Voltage -- V
Figure 2. Active Mode Current vs VCC, TA = 25°C
POST OFFICE BOX 655303
4.0
8.0
12.0
16.0
fDCO -- DCO Frequency -- MHz
Figure 3. Active Mode Current vs DCO Frequency
• DALLAS, TEXAS 75265
21
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low-power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0, 1MHz
ILPM0, 100kHz
ILPM2
Low-power mode 0
(LPM0) current,
current
see Note 3
Low-power mode 0
(LPM0) current,
current
see Note 3
Low-power mode 2
(LPM2) current,
current
see Note 4
TEST CONDITIONS
TA
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
MHz
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 1
1, SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 0
--40°C to 85°C
fMCLK = 0 MHz,
fSMCLK = fDCO(0, 0) ≈ 100 kHz,
kHz
fACLK = 0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1
1, SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz,
fACLK = 32
32,768
768 Hz,
Hz
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1
1, SCG0 = 0
0, SCG1 = 1,
1
OSCOFF = 0
--40°C to 85°C
105_C
--40°C to 85°C
105_C
105_C
--40°C to 85°C
105_C
--40°C to 85°C
105_C
--40°C to 85°C
105_C
VCC
22V
2.2
3V
22V
2.2
3V
22V
2.2
3V
--40°C to 85°C
ILPM3,LFXT1
ILPM3,VLO
Low-power mode 3
(LPM3) current,
current
see Note 4
Low-power mode 3
current, (LPM3)
see Note 4
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 32,768 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
fDCO = fMCLK = fSMCLK = 0 MHz,
fACLK from
f
internal
i
l LF oscillator
ill
(VLO),
(VLO)
CPUOFF = 1,
1 SCG0 = 1,
1 SCG1 = 1,
1
OSCOFF = 0
85°C
105°C
--40°C to 85°C
85°C
ILPM4
fDCO = fMCLK = fSMCLK = 0 MHz,
MHz
fACLK = 0 Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
TYP
MAX
32
45
55
20
POST OFFICE BOX 655303
27
31
31
42
13
16
20
20
25
0.7
1.2
1.6
2.3
3
6
0.9
1.2
7
--40°C
0.25
0.7
25°C
0.3
0.7
1.2
1.9
85°C
--40°C to 85°C
3V
2
5
0.7
0.8
1.4
2.1
105°C
2.5
6
--40°C
0.1
0.5
0.1
0.5
0.8
1.5
2
4
25°C
85°C
105°C
2.2 V/
3V
• DALLAS, TEXAS 75265
µA
31
2.8
105°C
µA
46
3
22V
2.2
µA
74
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9 pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
22
70
1.6
3V
UNIT
49
105°C
85°C
Low-power mode 4
(LPM4) current,
current
see Note 5
2.2 V
MIN
µA
µA
µ
µA
A
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
typical characteristics -- LPM4 current
ILPM4 -- Low-Power Mode Current -- µA
2.4
VCC = 3.6 V
2.2
VCC = 3 V
2.0
VCC = 2.2 V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
--40.0 --20.0
VCC = 1.8 V
0.0
20.0
40.0
60.0
80.0 100.0
TA -- Temperature -- °C
Figure 4. ILPM4 -- LPM4 Current vs Temperature
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs -- Ports P1, P2, P3, JTAG, RST/NMI, and XIN (see Note 1)
PARAMETER
VIT+
VIT--
TEST CONDITIONS
Positive-going
P
iti
i input
i
t threshold
th h ld
voltage
Negative-going
N
ti
i input
i
t threshold
th h ld
voltage
Vhys
Input voltage hysteresis
(VIT+ -- VIT--)
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS;
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
MAX
UNIT
0.45
0.75
VCC
2.2 V
1.00
1.65
3V
1.35
2.25
0.25
0.55
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
TYP
35
50
5
V
VCC
V
V
kΩ
pF
NOTE 1: XIN only in bypass mode
inputs -- Ports P1, P2
PARAMETER
t(int)
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger pulse width to set interrupt
flag (see Note 2)
External interrupt timing
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
NOTE 2: An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1, P2 and P3
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
High-impedance leakage current
See Notes 1 and 2
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1, P2 and P3
PARAMETER
VOH
VOL
High level output
High-level
voltage
Low level output
Low-level
voltage
NOTES: 1. The maximum total current,
voltage drop specified.
2. The maximum total current,
voltage drop specified.
VCC
MIN
I(OHmax) = --1.5 mA (see Notes 1)
TEST CONDITIONS
2.2 V
VCC --0.25
TYP
MAX
VCC
I(OHmax) = --6 mA (see Notes 2)
2.2 V
VCC --0.6
VCC
I(OHmax) = --1.5 mA (see Notes 1)
3V
VCC --0.25
VCC
I(OHmax) = --6 mA (see Notes 2)
3V
VCC --0.6
VCC
I(OLmax) = 1.5 mA (see Notes 1)
2.2 V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
2.2 V
VSS
VSS+0.6
I(OLmax) = 1.5 mA (see Notes 1)
3V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
3V
VSS
VSS+0.6
UNIT
V
V
IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
output frequency -- Ports P1, P2 and P3
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
7.5
MHz
fPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ
(see Note 1 and 2)
2.2 V
3V
12
MHz
fPort_CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
7.5
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
I OL -- Typical Low-Level Output Current -- mA
I OL -- Typical Low-Level Output Current -- mA
25.0
TA = 25°C
VCC = 2.2 V
P2.4
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.4
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
TA = 25°C
0.5
VOL -- Low-Level Output Voltage -- V
1.0
Figure 5
I OH -- Typical High-Level Output Current -- mA
I OH -- Typical High-Level Output Current -- mA
--10.0
--15.0
--25.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
VOH -- High-Level Output Voltage -- V
3.0
3.5
VCC = 3 V
P2.4
--10.0
--20.0
--30.0
--40.0
TA = 85°C
--50.0
0.0
TA = 25°C
0.5
1.0
1.5
Figure 8
NOTE: One output loaded at a time.
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH -- High-Level Output Voltage -- V
Figure 7
26
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
VCC = 2.2 V
P2.4
--5.0
--20.0
2.0
Figure 6
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
1.5
VOL -- Low-Level Output Voltage -- V
• DALLAS, TEXAS 75265
3.5
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC(start)
See Figure 9
dVCC/dt ≤ 3 V/s
V(B_IT--)
See Figure 9 through Figure 11
dVCC/dt ≤ 3 V/s
Vhys(B_IT--)
See Figure 9
dVCC/dt ≤ 3 V/s
td(BOR)
See Figure 9
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
VCC
MIN
TYP
MAX
0.7 × V(B_IT--)
70
2.2 V/3 V
2
130
UNIT
V
1.71
V
210
mV
2000
µs
µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data.
The voltage level V(B_IT--) + Vhys(B_IT--) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
1
0
t d(BOR)
Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- µs
1 ns
tpw -- Pulse Width -- µs
Figure 10. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw -- Pulse Width -- µs
tpw -- Pulse Width -- µs
Figure 11. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1; e.g., RSELx = 0 overlaps RSELx = 1,
and RSELx = 14 overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1)
MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1)
DCO frequency
PARAMETER
VCC
Supply voltage range
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3.0
3.6
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
Duty Cycle
1.55
ratio
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
%
29
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
--1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time = 5 ms
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time = 5 ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time = 5 ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
Gating time = 2 ms
25°C
3V
15.84
16
16.16
MHz
MIN
MAX
UNIT
calibrated DCO frequencies -- tolerance over temperature 0°C -- +85°C
TA
VCC
1-MHz tolerance over temperature
PARAMETER
0°C to 85°C
3V
--2.5
±0.5
+2.5
%
8-MHz tolerance over temperature
0°C to 85°C
3V
--2.5
±1
+2.5
%
12-MHz tolerance over temperature
0°C to 85°C
3V
--2.5
±1
+2.5
%
16-MHz tolerance over temperature
0°C to 85°C
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
30
1-MHz
1
MHz calibration value
8-MHz
8
MHz calibration value
12-MHz
12
MHz calibration value
16 MHz calibration value
16-MHz
TEST CONDITIONS
BCSCTL1 = CALBC1_1MHZ;
CALBC1 1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
BCSCTL1 = CALBC1_8MHZ;
CALBC1 8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time = 5 ms
0°C
0
C to 85°C
85 C
0°C
0
C to 85°C
85 C
BCSCTL1 = CALBC1_12MHZ;
CALBC1 12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time = 5 ms
0°C
0
C to 85°C
85 C
BCSCTL1 = CALBC1_16MHZ;
DCOCTL = CALDCO
CALDCO_16MHZ
16MHZ
Gating time = 2 ms
0°C to 85°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3V
TYP
--3
±2
+3
2.2 V
0.970
1
1.030
MHz
%
3V
0.975
1
1.025
MHz
3.6 V
0.970
1
1.030
MHz
2.2 V
7.760
8
8.400
MHz
3V
7.800
8
8.200
MHz
3.6 V
7.600
8
8.240
MHz
2.2 V
11.64
12
12.36
MHz
3V
11.64
12
12.36
MHz
3.6 V
11.64
12
12.36
MHz
3V
15.52
16
16.48
MHz
3.6 V
15.00
16
16.48
MHz
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance over supply voltage VCC
TA
VCC
1-MHz tolerance over VCC
25°C
1.8 V to 3.6 V
--3
±2
+3
%
8-MHz tolerance over VCC
25°C
1.8 V to 3.6 V
--3
±2
+3
%
12-MHz tolerance over VCC
25°C
2.2 V to 3.6 V
--3
±2
+3
%
16-MHz tolerance over VCC
25°C
3 V to 3.6 V
--6
±2
+3
%
25°C
1.8 V to 3.6 V
0.970
1
1.030
MHz
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fCAL(1MHz)
1-MHz calibration
value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time = 5 ms
fCAL(8MHz)
8-MHz calibration
value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time = 5 ms
25°C
1.8 V to 3.6 V
7.760
8
8.240
MHz
fCAL(12MHz)
12-MHz calibration
value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time = 5 ms
25°C
2.2 V to 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16-MHz calibration
value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time = 2 ms
25°C
3 V to 3.6 V
15.00
16
16.48
MHz
TA
VCC
MIN
MAX
UNIT
1-MHz tolerance overall
--40°C to
105°C
1.8 V to 3.6 V
--5
±2
+5
%
8-MHz tolerance overall
--40°C to
105°C
1.8 V to 3.6 V
--5
±2
+5
%
12-MHz tolerance overall
--40°C to
105°C
2.2 V to 3.6 V
--5
±2
+5
%
16-MHz tolerance overall
--40°C to
105°C
3 V to 3.6 V
--6
±3
+6
%
calibrated DCO frequencies -- overall tolerance
PARAMETER
TEST CONDITIONS
TYP
fCAL(1MHz)
1-MHz calibration value
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
Gating time = 5 ms
--40°C to
105°C
1.8 V to 3.6 V
0.950
1
1.050
MHz
fCAL(8MHz)
8-MHz calibration value
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ,
Gating time = 5 ms
--40°C to
105°C
1.8 V to 3.6 V
7.600
8
8.400
MHz
fCAL(12MHz)
12-MHz calibration value
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ,
Gating time = 5 ms
--40°C to
105°C
2.2 V to 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
16-MHz calibration value
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ,
Gating time = 2 ms
--40°C to
105°C
3 V to 3.6 V
15.00
16
17.00
MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- calibrated DCO frequency
1.03
TA = 85 °C
1.02
Frequency -- MHz
TA = 25 °C
1.01
TA = 105 °C
1.00
TA = --40 °C
0.99
0.98
0.97
1.5
2.0
2.5
3.0
VCC -- Supply Voltage -- V
3.5
4.0
Figure 12. Calibrated 1 MHz Frequency vs VCC
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
,electrical
characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
tDCO,LPM3/4
tCPU,LPM3/4
TEST CONDITIONS
DCO clock wake
wake-up
up time from
LPM3/4 (see Note 1)
VCC
MIN
TYP
MAX
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1 = CALBC1_8MHZ,
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
1.5
BCSCTL1 = CALBC1_12MHZ,
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1
BCSCTL1 = CALBC1_16MHZ,
DCOCTL = CALDCO_16MHZ
3V
1
UNIT
µs
s
CPU wake-up time from LPM3/4
(see Note 2)
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake-up time from LPM3/4
DCO Wake Time -- us
10.00
RSELx = 0...11
1.00
0.10
0.10
RSELx = 12...15
1.00
10.00
DCO Frequency -- MHz
Figure 13. Clock Wake-Up Time From LPM3 vs DCO Frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO with external resistor ROSC (see Note)
PARAMETER
TEST CONDITIONS
VCC
fDCO,ROSC
DCO output frequency
with ROSC
DCOR = 1,
RSELx = 4,
4 DCOx = 3
3, MODx = 0
0,
TA = 25°C
Dt
Temperature drift
DV
Drift with VCC
MIN
TYP
MAX
UNIT
2.2 V
1.8
3V
1.95
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
MHz
NOTE: ROSC = 100 kΩ. Metal film resistor, type 0257. 0.6 W with 1% tolerance and TK = ±50 ppm/°C.
typical characteristics -- DCO with external resistor ROSC
10.00
DCO Frequency -- MHz
DCO Frequency -- MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
1.00
0.10
RSELx = 4
0.01
10.00
10000.00
ROSC -- External Resistor -- kΩ
Figure 14. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
2.25
DCO Frequency -- MHz
ROSC = 100k
2.00
1.75
DCO Frequency -- MHz
10000.00
2.50
2.25
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
--25
0
25
50
75
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
ROSC = 1M
0.25
ROSC = 100k
2.00
ROSC = 1M
0.25
100
0.00
2.0
TA -- Temperature -- °C
Figure 16. DCO Frequency vs Temperature,
VCC = 3 V
34
1000.00
Figure 15. DCO Frequency vs ROSC,
VCC = 3 V, TA = 25°C
2.50
0.00
--50
100.00
ROSC -- External Resistor -- kΩ
POST OFFICE BOX 655303
2.5
3.0
3.5
VCC -- Supply Voltage -- V
Figure 17. DCO Frequency vs VCC,
TA = 25°C
• DALLAS, TEXAS 75265
4.0
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency,
LF mode
XTS = 0, XCAPx = 0,
LFXT1Sx = 3
1.8 V to 3.6 V
OALF
CL,eff
Oscillation allowance for
LF crystals
Integrated effective load
capacitance LF mode
capacitance,
(see Note 1)
MIN
TYP
32,768
10,000
32,768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
1
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle
LF mode
fFault,LF
Oscillator fault frequency,
LF mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
UNIT
Hz
50,000
Hz
kΩ
XTS = 0, XCAPx = 0
XTS = 0,
Measured at P2.0/ACLK,
fLFXT1,LF = 32,768Hz
MAX
2.2 V/3 V
30
2.2 V/3 V
10
pF
50
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
VCC
TA = --40°C to 85°C
2.2 V/3 V
fVLO
VLO frequency
TA = 105°C
2.2 V/3 V
dfVLO/dT
VLO frequency temperature drift
See Note 1
2.2 V/3 V
dfVLO/dVCC
VLO frequency supply voltage drift
See Note 2
1.8V to 3.6V
MIN
TYP
MAX
4
12
20
22
UNIT
kHz
kHz
0.5
%/°C
4
%/V
NOTES: 1. Calculated using the box method:
I Version: (MAX(--40_C to 85_C) -- MIN(--40_C to 85_C))/MIN(--40_C to 85_C)/(85_C -- (--40_C))
T Version: (MAX(--40_C to 105_C) -- MIN(--40_C to 105_C))/MIN(--40_C to 105_C)/(105_C -- (--40_C))
2. Calculated using the box method: (MAX(1.8 V to 3.6 V) -- MIN(1.8 V to 3.6 V))/MIN(1.8 V to 3.6 V)/(3.6 V -- 1.8 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
XTS = 1, XCAPx = 0, LFXT1Sx = 0
1.8 V to 3.6 V
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, XCAPx = 0, LFXT1Sx = 1
1.8 V to 3.6 V
1
4
MHz
LFXT1 oscillator
ill t crystal
t l frequency,
f
HF mode 2
1.8 V to 3.6 V
2
10
MHz
fLFXT1,HF2
XTS = 1, XCAPx = 0, LFXT1Sx = 2
2.2 V to 3.6 V
2
12
MHz
3 V to 3.6 V
2
16
MHz
LFXT1 oscillator
ill t logic
l i level
l
l square
wave input frequency,
frequency HF mode
1.8 V to 3.6 V
0.4
10
MHz
XTS = 1, XCAPx = 0, LFXT1Sx = 3
2.2 V to 3.6 V
0.4
12
MHz
3 V to 3.6 V
0.4
16
MHz
fLFXT1,HF,logic
OAHF
CL,eff
Duty cycle
fFault,HF
Oscillation allowance for HF
crystals
(see Figure 18 and Figure 19)
Integrated effective load
capacitance, HF mode
(see Note 1)
HF mode
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
2700
Ω
XTS = 1, XCAPx = 0, LFXT1Sx = 1,
fLFXT1,HF = 4 MHz, CL,eff = 15 pF
800
Ω
XTS = 1, XCAPx = 0, LFXT1Sx = 2,
fLFXT1,HF = 16 MHz, CL,eff = 15 pF
300
Ω
1
pF
XTS = 1, XCAPx = 0 (see Note 2)
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 10 MHz
2.2 V/3 V
40
50
60
%
XTS = 1, XCAPx = 0,
Measured at P2.0/ACLK,
fLFXT1,HF = 16 MHz
2.2 V/3 V
40
50
60
%
2.2 V/3 V
30
300
kHz
Oscillator fault frequency, HF mode XTS = 1, XCAPx = 0, LFXT1Sx = 3
(see Note 4)
(see Notes 3)
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1)
Oscillation Allowance -- Ohms
100000.00
10000.00
1000.00
LFXT1Sx = 2
100.00
LFXT1Sx = 1
LFXT1Sx = 0
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
Figure 18. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
XT Oscillator Supply Current -- uA
1800.0
LFXT1Sx = 2
1600.0
1400.0
1200.0
1000.0
800.0
600.0
400.0
LFXT1Sx = 1
200.0
0.0
0.0
LFXT1Sx = 0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 19. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer0_A3
PARAMETER
TEST CONDITIONS
fTA
Timer0 A3 clock frequency
Timer0_A3
Internal: SMCLK, ACLK,
External: TACLK,
TACLK INCLK
INCLK,
Duty cycle = 50% ± 10%
tTA,cap
Timer0_A3, capture timing
TA0_0, TA1_0, TA2_0
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer1_A2
PARAMETER
TEST CONDITIONS
fTB
Timer1 A2 clock frequency
Timer1_A2
Internal: SMCLK, ACLK;
External: TACLK,
TACLK INCLK;
Duty cycle = 50% ± 10%
tTB,cap
Timer1_A2, capture timing
TA0_1, TA1_1
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK,
External: UCLK,
Duty cycle = 50% ± 10%
fUSCI
USCI input clock frequency
fmax,BITCLK
Maximum BITCLK clock frequency
(equals baudrate in MBaud) (see
Note 1)
tτ
UART receive deglitch time
(see Note 2)
MAX
UNIT
fSYSTEM
MHz
2.2V /3 V
2
MHz
2.2 V
50
150
600
ns
3V
50
100
600
ns
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 20 and Figure 21)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time
NOTE:
f UCxCLK =
TEST CONDITIONS
VCC
MIN
TYP
SMCLK, ACLK,
Duty cycle = 50% ± 10%
UCLK edge to SIMO valid,
CL = 20 pF
MAX
UNIT
fSYSTEM
MHz
2.2 V
110
ns
3V
75
ns
2.2 V
0
ns
3V
0
ns
2.2 V
30
ns
3V
20
ns
1 with t
LO∕HI ≥ max(t VALID,MO(USCI) + t SU,SI(Slave), t SU,MI(USCI) + t VALID,SO(Slave)).
2t LO∕HI
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
USCI (SPI slave mode) (see Figure 22 and Figure 23)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time,
STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time,
Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time,
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time,
STE high to SOMI high impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
NOTE:
f UCxCLK =
UCLK edge to SOMI valid,
CL = 20 pF
50
ns
10
ns
2.2 V
20
ns
3V
15
ns
2.2 V
10
ns
3V
10
ns
2.2 V
75
110
ns
3V
50
75
ns
1 with t
LO∕HI ≥ max(t VALID,MO(Master) + t SU,SI(USCI), t SU,MI(Master) + t VALID,SO(USCI)) .
2t LO∕HI
For the master’s parameters tSU,MI(Master) and tVALID,MO(Master) refer to the SPI parameters of the attached master.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 21. SPI Master Mode, CKPH = 1
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
tHD,MI
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)3
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 22. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLO/HI
tLO/HI
tSU,SI
tHD,SI
SIMO
tSTE,ACC
tVALID,SO
tSTE,DIS
SOMI
Figure 23. SPI Slave Mode, CKPH = 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C mode) (see Figure 24)
PARAMETER
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK,
External: UCLK,
Duty Cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
2.2 V/3 V
0
fSCL ≤ 100kHz
2.2 V/3 V
4.0
us
fSCL > 100kHz
2.2 V/3 V
0.6
us
fSCL ≤ 100kHz
2.2 V/3 V
4.7
us
fSCL > 100kHz
2.2 V/3 V
0.6
us
tHD,STA
Hold time (repeated) start
tSU,STA
Setup time for a repeated start
tHD,DAT
Data hold time
2.2 V/3 V
0
ns
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for stop
2.2 V/3 V
4.0
us
tSP
Pulse width of spikes suppressed by
input filter
2.2 V
50
150
600
ns
3V
50
100
600
ns
tHD,STA
tSU,STA tHD,STA
SDA
1/fSCL
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 24. I2C Mode Timing
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
I(DD)
CAON = 1
1, CARSEL = 0
0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0,
CAREF = 1/2/3
1/2/3,
No load at P1.0/CA0 and P1.1/CA1
V(IC)
V(Ref025)
V(Ref050)
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
Common-mode input voltage
CAON = 1
2.2 V/3 V
0
Voltage @ 0.25 V
node
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.23
0.24
0.25
node
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
V
CC
Voltage @ 0.5V
V
CC
CC
CC
VCC --1
UNIT
µA
µA
V
V(RefVT)
See Figure 28 and Figure 29
PCA0 = 1, CARSEL = 1, CAREF = 3,
P1 0/CA0 and P1.1/CA1,
P1 1/CA1
No load at P1.0/CA0
TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
--30
30
mV
Vhys
Input hysteresis
CAON = 1
2.2 V/3 V
0
0.7
1.4
mV
2.2 V
80
165
300
3V
70
120
240
t(response)
Response time
(low to high and high to low)
(see Note 3)
TA = 25°C, Overdrive 10 mV,
Without filter: CAF = 0
(see Note 3, Figure 25 and Figure 26)
mV
ns
TA = 25°C, Overdrive 10 mV,
2.2 V
1.4
1.9
2.8
µs
With filter: CAF = 1
3V
0.9
1.5
2.2
(see Note 3, Figure 25 and Figure 26)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P2.2/TA0_0/A2/CA4/CAOUT. If the Comparator_A+ is enabled a settling time of 60 ns (typical) is added
to the response time.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0V
VCC
0
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 25. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V-400 mV
t(response)
V+
Figure 26. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
--
IOUT = 10µA
Comparator_A+
CASHORT = 1
Figure 27. Comparator_A+ Short Resistance Test Condition
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator_A+
650.0
650.0
VCC = 2.2 V
V(REFVT) -- Reference Volts -- mV
V(REFVT) -- Reference Volts -- mV
VCC = 3 V
600.0
600.0
Typical
Typical
550.0
550.0
500.0
500.0
450.0
450.0
400.0
--45.0 --25.0 --5.0 15.0 35.0 55.0 75.0 95.0 115.0
400.0
--45.0 --25.0 --5.0 15.0 35.0 55.0 75.0 95.0 115.0
TA -- Free-Air Temperature -- °C
TA -- Free-Air Temperature -- °C
Figure 29. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 28. V(RefVT) vs Temperature, VCC = 3 V
Short Resistance -- kOhms
100.00
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
10.00
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC -- Normalized Input Voltage -- V/V
Figure 30. Short Resistance vs VIN/VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions (see Note 1)
PARAMETER
TEST CONDITIONS
TA
VCC
VCC
Analog supply voltage
range
VSS = 0 V
VAx
Analog input voltage
range (see Note 2)
All Ax terminals,
Analog inputs selected in ADC10AE
register
IADC10
ADC10 supply current
(see Note 3)
fADC10CLK = 5 MHz,
ADC10ON = 1, REFON = 0
ADC10SHT0 = 1, ADC10SHT1 = 0,
ADC10DIV = 0
I: --40°C
40 C to 85°C
85 C
T: --40°C to105°C
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 0,
REFON = 1, REFOUT = 0
I: --40°C to 85°C
T: --40°C to105°C
fADC10CLK = 5 MHz,
ADC10ON = 0, REF2_5V = 1,
REFON = 1, REFOUT = 0
I: --40°C to 85°C
T: --40°C to105°C
3V
--40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
--40°C to 85°C
2.2 V/3 V
105°C
2.2 V/3 V
IREF+
Reference supply
current reference buffer
current,
disabled (see Note 4)
fADC10CLK = 5 MHz,
ADC10ON = 0,
1 REF2
5V = 0
0,
REFON = 1,
REF2_5V
REFOUT = 1,
ADC10SR = 0
Reference buffer supply
current with
ADC10SR = 1
(see Note 4)
fADC10CLK = 5 MHz,
ADC10ON = 0,
REFON = 1,
REF2_5V = 0,
REFOUT = 1,
ADC10SR = 1
CI
Input capacitance
Only one terminal Ax selected at a
time
I: --40°C to 85°C
T: --40°C to105°C
RI
Input MUX ON
resistance
0V ≤ VAx ≤ VCC
I: --40°C to 85°C
T: --40°C to105°C
IREFB,1
NOTES: 1.
2.
3.
4.
46
TYP
MAX
UNIT
2.2
3.6
V
0
VCC
V
2.2 V
0.52
1.05
3V
0.6
1.2
mA
2.2 V/3 V
mA
0 25
0.25
Reference buffer supply
current with
ADC10SR = 0
(see Note 4)
IREFB,0
MIN
2.2 V/3 V
0.4
04
mA
1.1
0.5
1.4
mA
1.8
mA
0.7
mA
0.8
mA
27
pF
2000
Ω
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, built-in voltage reference
PARAMETER
VCC,REF+
VREF+
ILD,VREF+
Positive built-in
reference analog supply
voltage range
Positive built-in
reference voltage
TCREF+
tREFON
tREFBURST
TA
2.2
2.8
IVREF+ ≤ 1 mA, REF2_5V = 1
2.9
IVREF+ ≤ IVREF+max, REF2_5V = 0
IVREF+ ≤ IVREF+max, REF2_5V = 1
TYP
MAX
UNIT
V
2.2 V/
3V
1.41
1.5
1.59
V
3V
2.35
2.5
2.65
V
2.2 V
±0.5
mA
3V
±1
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 0.75 V,
REF2_5V = 0
2.2 V/
3V
±2
LSB
IVREF+ = 500 µA ± 100 µA,
Analog input voltage VAx ≈ 1.25 V,
REF2_5V = 1
3V
±2
LSB
ADC10SR = 0
3V
400
ADC10SR = 1
3V
2000
2.2 V/
3V
100
IVREF+ = 100 µA→900 µA,
0 5 x VREF+, Error of
VAx ≈ 0.5
conversion result ≤ 1 LSB
Max. capacitance at pin
VREF+ (see Note 1)
IVREF+ ≤ ±1 mA,
REFON = 1, REFOUT = 1
Temperature coefficient
IVREF+ = const. with 0 mA ≤ IVREF+ ≤ 1 mA
(see Note 3)
Settling time of
reference buffer
(see Note 2)
MIN
IVREF+ ≤ 1 mA, REF2_5V = 0
VREF+ load regulation
response time
Settling time of internal
reference voltage
(see Note 2)
VCC
IVREF+ ≤ 0.5 mA, REF2_5V = 1
Maximum VREF+ load
current
VREF+ load regulation
CVREF+
TEST CONDITIONS
ns
pF
--40°C
to 85°C
2.2 V/
3V
±100 ppm/°C
85°C to
105°C
2.2 V/
3V
±110 ppm/°C
IVREF+ = 0.5 mA, REF2_5V = 0,
REFON = 0 → 1
3.6 V
30
IVREF+ = 0.5 mA,
REF2 5V = 0,
REF2_5V
REFON = 1,
REFBURST = 1
ADC10SR = 0
2.2 V
1
ADC10SR = 1
2.2 V
2.5
IVREF+ = 0.5 mA,
REF2 5V = 1,
REF2_5V
REFON = 1,
REFBURST = 1
ADC10SR = 0
3V
2
ADC10SR = 1
3V
4.5
µs
µs
s
µs
s
NOTES: 1. The capacitance applied to the internal buffer operational amplifier, if switched to terminal P2.4/TA2/A4/VREF+/VeREF+
(REFOUT = 1), must be limited; the reference buffer may become unstable, otherwise.
2. The condition is that the error in a conversion started after tREFON or tRefBuf is less than ±0.5 LSB.
3. Calculated using the box method: ((MAX(VREF(T)) -- MIN(VREF(T))) / MIN(VREF(T)) / (TMAX -- TMIN)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, external reference (see Note 1)
PARAMETER
VeREF+
Positive external reference input
voltage range (see Note 2)
TEST CONDITIONS
UNIT
VeREF-- ≤ VeREF+ ≤ (VCC -- 0.15 V)
SREF1 = 1, SREF0 = 1 (see Note 3)
1.4
3.0
0
1.2
V
1.4
VCC
V
∆VeREF
Differential external reference input
voltage range
∆VeREF = VeREF+ -- VeREF--
VeREF+ > VeREF-- (see Note 5)
Static input current into VeREF--
MAX
VCC
VeREF+ > VeREF--
IVeREF--
TYP
1.4
Negative external reference input
voltage range (see Note 4)
Static input current into VeREF+
MIN
VeREF+ > VeREF-- ,
SREF1 = 1, SREF0 = 0
VeREF--
IVeREF+
VCC
V
0V ≤ VeREF+ ≤ VCC,
SREF1 = 1, SREF0 = 0
2.2 V/3 V
±1
0V ≤ VeREF+ ≤ (VCC -- 0.15 V) ≤ 3 V,
SREF1 = 1, SREF0 = 1 (see Note 3)
2.2 V/3 V
0
0V ≤ VeREF-- ≤ VCC
2.2 V/3 V
±1
µA
A
µA
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters
PARAMETER
fADC10CLK
fADC10OSC
tCONVERT
tADC10ON
TEST CONDITIONS
ADC10 built-in oscillator frequency
Conversion time
MIN
MAX
UNIT
2.2 V/3 V
0.45
6.3
ADC10SR =
1
2.2 V/3 V
0.45
1.5
ADC10DIVx = 0, ADC10SSELx = 0
fADC10CLK = fADC10OSC
2.2 V/3 V
3.7
6.3
MHz
ADC10 built-in oscillator,
ADC10SSELx = 0
fADC10CLK = fADC10OSC
2.2 V/3 V
2.06
3.51
µs
MHz
13×
ADC10DIV×
1/fADC10CLK
fADC10CLK from ACLK, MCLK or
SMCLK: ADC10SSELx ≠ 0
Turn on settling time of the ADC
TYP
ADC10SR =
0
For specified
performance of
ADC10 linearity
parameters
ADC10 input clock frequency
VCC
See Note 1
µs
100
ns
NOTE 1: The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signals are already
settled.
10-bit ADC, linearity parameters
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
Integral linearity error
2.2 V/3 V
±1
LSB
ED
Differential linearity error
2.2 V/3 V
±1
LSB
2.2 V/3 V
±1
LSB
EO
EG
ET
Offset error
Gain error
Total unadjusted error
Source impedance RS < 100 Ω
SREFx = 010, Unbuffered external reference; VeREF+ = 1.5 V
2.2 V
±1.1
±2
LSB
SREFx = 010, Unbuffered external reference; VeREF+ = 2.5 V
3V
±1.1
±2
LSB
SREFx = 011, Buffered external reference (see Note 2),
VeREF+ = 1.5 V
2.2 V
±1.1
±4
LSB
SREFx = 011, Buffered external reference (see Note 2),
VeREF+ = 2.5 V
3V
±1.1
±3
LSB
SREFx = 010, Unbuffered external reference; VeREF+ = 1.5 V
2.2 V
±2
±5
LSB
SREFx = 010, Unbuffered external reference; VeREF+ = 2.5 V
3V
±2
±5
LSB
SREFx = 011, Buffered external reference (see Note 2),
VeREF+ = 1.5 V
2.2 V
±2
±7
LSB
SREFx = 011, Buffered external reference (see Note 2),
VeREF+ = 2.5 V
3V
±2
±6
LSB
NOTE 2: The reference buffer’s offset adds to the gain and total unadjusted error.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in VMID
PARAMETER
ISENSOR
Temperature sensor supply
current (see Note 1)
VSensor
REFON = 0, INCHx = 0Ah,
ADC10ON = 1, TA = 25_C
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
TCSENSOR
VOffset,Sensor
TEST CONDITIONS
Sensor offset voltage
Sensor output voltage
(see Note 3)
VCC
MIN
TYP
MAX
2.2 V
40
120
3V
60
160
2.2 V/3 V
ADC10ON = 1, INCHx = 0Ah
(see Note 2)
3.55
--100
UNIT
µA
A
mV/°C
100
mV
Temperature sensor voltage
at TA = 105°C (T version only)
2.2 V/3 V
1265
1365
1465
mV
Temperature sensor voltage
at TA = 85°C
2.2 V/3 V
1195
1295
1395
mV
Temperature sensor voltage
at TA = 25°C
2.2 V/3 V
985
1085
1185
Temperature sensor voltage
at TA = 0°C
2.2 V/3 V
895
995
1095
2.2 V/3 V
30
mV
tSensor(sample)
Sample time required if
channel 10 is selected (see
Note 4)
ADC10ON = 1, INCHx = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel11 (see Note 5)
ADC10ON = 1,
1 INCHx = 0Bh
0Bh,
VMID
VCC divider at channel 11
ADC10ON = 1, INCHx = 0Bh,
VMID is ≈0.5 x VCC
2.2 V
1.06
1.1
1.14
3V
1.46
1.5
1.54
tVMID(sample)
Sample time required if
channel 11 is selected
(see Note 6)
ADC10ON = 1, INCHx = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
3V
1220
µs
2.2 V
NA
3V
NA
µA
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON = 1 and INCH = 0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [°C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [°C] + VSensor(TA = 0°C) [mV]
3. Results based on characterization and/or production test, not TCSensor or VOffset,sensor.
4. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).
5. No additional current is needed. The VMID is used during sampling.
6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
Program and erase supply voltage
MIN
TYP
2.2
fFTG
Flash timing generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
257
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
tCPT
Cumulative program time (see Note 1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
TJ = 25°C
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
20
104
Program/erase endurance
MAX
ms
105
cycles
tRetention
Data retention duration
100
tWord
Word or byte program time
30
tFTG
tBlock, 0
Block program time for first byte or word
25
tFTG
tBlock, 1-63
Block program time for each additional byte or word
18
tFTG
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
tSeg Erase
Segment erase time
See Note 2
years
6
tFTG
10593
tFTG
4819
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER
V(RAMh)
TEST CONDITIONS
RAM retention supply voltage (see Note)
CPU halted
MIN
1.6
TYP
MAX
UNIT
V
NOTE: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen
during this supply voltage condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
JTAG and Spy-Bi-Wire interface
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V/3 V
0
20
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse length
2.2 V/3 V
0.025
15
us
tSBW,En
Spy-Bi-Wire enable time,
TEST high to acceptance of first clock edge
(see Note 1)
2.2 V/3 V
1
us
tSBW,Ret
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
15
100
2.2 V
0
5
MHz
3V
0
10
MHz
2.2 V/3 V
25
90
kΩ
fTCK
TCK input frequency (see Note 2)
RInternal
Internal pulldown resistance on TEST
60
us
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high
before applying the first SBWCLK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG fuse (see Note)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TEST for fuse-blow (F versions)
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
TA = 25°C
VCC
MIN
NOM
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTE: Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
APPLICATION INFORMATION
Port P1 pin schematic: P1.0, input/output with Schmitt trigger
Pad Logic
P1REN.0
P1DIR.0
P1SEL2.0
0
0
from
Comparator
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
ADC10CLK
DVSS
1
P1OUT.0
0
P1.0/TACLK/
ADC10CLK/CAOUT
Bus
Keeper
EN
P1SEL.0
P1IN.0
EN
Module X IN
D
P1IE.x
EN
P1IRQ.0
Q
Set
P1IFG.x
P1SEL.0
P1IES.0
Interrupt
Edge Select
Port P1 (P1.0) pin functions
PIN NAME (P1.x)
(P1 x)
x
P1.0/TACLK/
/
/
ADC10CLK/CAOUT
0
CONTROL BITS / SIGNALS
FUNCTION
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0, O: 1
0
0
Timer0_A3.TACLK, Timer1_A2.TACLK
0
1
0
ADC10CLK
1
1
0
CAOUT
1
1
1
P1.0 (I/O)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P1 pin schematic: P1.1 to P1.3, input/output with Schmitt trigger
Pad Logic
P1REN.x
0
P1DIR.x
0
P1OUT.x
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
Timer0_A3
output
DVSS
P1.1/TA0_0/TA0_1
P1.2/TA1_0
P1.3/TA2_0
Bus
Keeper
EN
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
Port P1 (P1.1 to P1.3) pin functions
PIN NAME (P1.x)
(P1 x)
x
P1.1/TA0_0/TA0_1
/
_ /
_
1
CONTROL BITS / SIGNALS
FUNCTION
P1.1 (I/O)
Timer0_A3.CCI0A, Timer1_A2.CCI0A
Timer0_A3.TA0
P1.2/TA1_0
/
_
P1.3/TA2_0
/
_
54
2
3
P1DIR.x
P1SEL.x
P1SEL2.x
I: 0; O: 1
0
0
0
1
0
1
1
0
I: 0; O: 1
0
0
Timer0_A3.CCI0A
0
1
0
Timer0_A3.TA0
1
1
0
0
0
P1.2 (I/O)
P1.3 (I/O)
I: 0; O: 1
Timer0_A3.CCI0A
0
1
0
Timer0_A3.TA0
1
1
0
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P1 pin schematic: P1.4
P1REN.4
Pad Logic
P1DIR.4
0
0
P1OUT.4
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
SMCLK
DVSS
Bus
Keeper
EN
P1SEL.4
P1IN.4
P1.4/SMCLK/TCK
EN
Module X IN
D
P1IE.x
P1IRQ.4
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
To JTAG
From JTAG
Port P1 (P1.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.4/SMCLK/TCK
/
/
x
4
FUNCTION
P1.4 (I/O)
P1DIR.x
P1SEL.x
P1SEL2.x = 0
JTAG Mode
I: 0; O: 1
0
0
SMCLK
1
1
0
TCK (see Note 1)
X
X
1
NOTES: 1. In JTAG Mode the internal pullup/pulldown resistors are disabled.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P1 pin schematic: P1.5 to P1.7
P1REN.x
Pad Logic
P1DIR.x
0
0
P1OUT.x
1
0
DVCC
1
Bus
Keeper
EN
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
Set
P1IFG.x
P1SEL.x
P1IES.x
Interrupt
Edge Select
To JTAG
From JTAG
56
1
Direction
0: Input
1: Output
1
Module X Out
DVSS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P1.5/TA0_0/TMS
P1.6/TA1_0/TDI/TCLK
P1.7/TA2_0/TDO/TDI
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P1 (P1.5 to P1.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P1.x)
P1.5/TA0_0/TMS
/
_ /
P1.6/TA1_0/
/
_ /
TDI/TCLK
P1.7/TA2_0/TDO/TDI
/
_ /
/
x
5
6
FUNCTION
P1.5 (I/O)
P1SEL.x
P1SEL2.x = 0
JTAG Mode
I: 0; O: 1
0
0
Timer0_A3.TA0
1
1
0
TMS (see Note 1)
X
X
1
I: 0; O: 1
0
0
1
1
0
P1.6 (I/O)
Timer0_A3.TA1
7
P1DIR.x
Timer0_A3.CCI0B
0
1
0
TDI/TCLK (see Note 1)
X
X
1
I: 0; O: 1
0
0
P1.6 (I/O)
Timer0_A3.TA2
1
1
0
TDO/TDI (see Note 1)
X
X
1
NOTES: 1. In JTAG Mode the internal pullup/pulldown resistors are disabled.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.0 and P2.1, input/output with Schmitt trigger
Pad Logic
To ADC10
INCHx = y
To
Comparator_A
From
Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
0
Module X OUT
1
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
58
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.0/ACLK/A0/CA2
P2.1/TAINCLK/
SMCLK/A1/CA3
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 (P2.0 and P2.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
x
P2.0/ACLK/A0/CA2
/
/ /
0
P2.1/TAINCLK/
/
/
SMCLK/A1/CA3
1
FUNCTION
ADC10AE0.y
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x = 0
P2.0 (I/O)
0
0
I: 0; O: 1
0
ACLK
0
0
1
1
A0
1
0
X
X
CA2
0
1
X
X
P2.1 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TAINCLK, Timer1_A2.TAINCLK
0
0
0
1
SMCLK
0
0
1
1
A1
1
0
X
X
CA3
0
1
X
X
NOTE: X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.2, input/output with Schmitt trigger
Pad Logic
To ADC10
INCHx = y
To
Comparator_A
From
Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
0
P2DIR.2
P2SEL2.2
Direction
0: Input
1: Output
1
Module Output
0
from
Comparator
1
1
P2OUT.2
0
Bus
Keeper
EN
P2SEL.2
P2IN.2
EN
Module X IN
D
P2IE.x
P2IRQ.2
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
60
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.2/TA0_0/A2/CA4/
CAOUT
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 (P2.2) pin functions
PIN NAME (P2.x)
(P2 x)
x
P2.2/TA0_0/A2/CA4/
/
_ / /
/
CAOUT
2
FUNCTION
CONTROL BITS / SIGNALS
ADC10AE0.x
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x
P2.0 (I/O)
0
0
I: 0; O: 1
0
0
Timer0_A3.TA0
0
0
1
1
0
Timer0_A3.CCI0B
0
0
0
1
0
A2
1
0
X
X
X
CA4
0
1
X
X
X
CAOUT
0
0
1
1
1
NOTE: X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
61
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.3 and P2.4, input/output with Schmitt trigger
Pad Logic
To/from ADC10
reference
To ADC10
INCHx = y
To
Comparator_A
From
Comparator_A
CAPD.x
ADC10AE0.y
P2REN.x
DVSS
0
DVCC
1
1
P2DIR.x
0
Direction
0: Input
1: Output
1
P2OUT.x
0
Module X OUT
1
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
62
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.3/TA1_0/A3/VRef-/
Ve Ref-/CA0
P2.4/TA2_0/A4/VRef-+/
Ve Ref+/CA1
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 (P2.3 and P2.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
P2.3/TA1_0/A3/
/
_ / /
VRef-- /VeRef-- /CA0
P2.4/TA2_0/A4/
/
_ / /
VRef+/VeRef+/CA1
x
3
4
FUNCTION
ADC10AE0.y
CAPD.x
P2DIR.x
P2SEL.x
P2SEL2.x = 0
P2.3 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TA1
0
0
1
1
A3/VRef-- /VeRef--
1
0
X
X
CA0
0
1
X
X
P2.4 (I/O)
0
0
I: 0; O: 1
0
Timer0_A3.TA2
0
0
1
1
A4/VRef+/VeRef+
1
0
X
X
CA1
0
1
X
X
NOTE: X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
63
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.5, input/output with Schmitt trigger
Pad Logic
To Comparator
From Comparator
CAPD.x
To DCO
in DCO
DCOR
P2REN.x
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2IFG.5
P2SEL.5
P2IES.5
Interrupt
Edge Select
Port P2 (P2.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
P2.5/R
/ OSC//CA5
x
5
FUNCTION
CAPD.5
DCOR
P2DIR.5
P2SEL.5
P2SEL2.x = 0
P2.5 (I/O)
0
0
I: 0, O: 1
0
ROSC
0
1
X
X
DVSS
0
0
1
1
CA5 (see Note 2)
1
0
X
X
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
64
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.6, input/output with Schmitt trigger
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
Pad Logic
To Comparator
From
Comparator
P2SEL.7
CAPD.6
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/CA6
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
Set
P2IFG.6
P2SEL.6
P2IES.6
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
65
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2.6 pin functions
CONTROL BITS / SIGNALS
Pin Name (P2.x)
P2.6/XIN/CA6
/
/
x
6
FUNCTION
CAPD.6
P2DIR.6
P2SEL.6
P2SEL2.x = 0
P2.6 (I/O)
0
I: 0; O: 1
0
XIN (default)
X
1
1
CA6 (see Note 2)
1
X
0
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
66
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2 pin schematic: P2.7, input/output with Schmitt trigger
BCSCTL3.LFXT1Sx = 11
P2.6/XIN/CA6
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
Pad Logic
To Comparator
From
Comparator
P2SEL.6
CAPD.7
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT/CA7
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
P2SEL.7
P2IES.7
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
67
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P2.7 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P2.x)
P2.7/XOUT/CA7
/
/
x
7
FUNCTION
CAPD.7
P2DIR.7
P2SEL.7
P2SEL2.x = 0
P2.7 (I/O)
0
I: 0, O: 1
0
XOUT (default)
X
1
1
CA7 (see Note 2)
1
X
0
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.x bit.
68
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P3 pin schematic: P3.0, input/output with Schmitt trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
DVSS
0
DVCC
1
1
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
1
Direction
0: Input
1: Output
Bus
Keeper
EN
P3SEL.x
P3IN.x
P3.0/UCB0STE/
UCA0CLK/A5
Port P3.0 pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.x)
P3.0/UCB0STE/
/
/
UCA0CLK/A5
x
0
FUNCTION
ADC10AE0.y
P3DIR.x
P3SEL.x
P3SEL2.x = 0
P3.0 (I/O)
0
I: 0; O: 1
0
UCB0STE/UCA0CLK (see Notes 1 and 2)
0
X
1
A5 (see Notes 1 and 2)
1
X
X
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. If the I2C functionality is selected, the output drives only the logical 0 to VSS level.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
69
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P3 pin schematic: P3.1 to P3.5, input/output with Schmitt trigger
Pad Logic
P3REN.x
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3 (P3.1 to P3.5) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P3.x)
x
P3.1/UCB0SIMO/
/
/
UCB0SDA
1
P3.2/UCB0SOMI/
/
/
UCB0SCL
2
P3.3/UCB0CLK/
/
/
UCA0STE
3
P3.4/UCA0TXD/
/
/
UCA0SIMO
4
P3.5/UCA0RXD/
/
/
UCA0SOMI
5
FUNCTION
P3.1 (I/O)
UCB0SIMO/UCB0SDA (see Notes 1, 2 and 3)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (see Notes 1, 2 and 3)
P3.3 (I/O)
UCB0CLK/UCA0STE (see Notes 1 and 2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (see Notes 1 and 2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (see Notes 1 and 2)
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
70
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P3DIR.x
P3SEL.x
P3SEL2.x = 0
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt trigger
Pad Logic
To ADC10
INCHx = y
ADC10AE0.y
P3REN.x
DVSS
0
DVCC
1
1
P3DIR.x
0
Direction
0: Input
1: Output
1
P3OUT.x
0
Module X OUT
1
P3.6/TA0_1/A6
P3.7/TA1_1/A7
Bus
Keeper
EN
P3SEL.x
P3IN.x
Port P3 (P3.6 and P3.7) pin functions
PIN NAME (P3.x)
P3.6/TA0_1/A6
/
_ /
P3.7/TA1_1/A7
/
_ /
ADC10AE0.y
P3DIR.x
P3SEL.x
P3SEL2 = 0
P3.6 (I/O)
0
I: 0; O: 1
0
Timer1_A2.TA0
0
1
1
Timer1_A2.CCI0B
0
0
1
A6
1
X
X
P3.7 (I/O)
0
I: 0; O: 1
0
Timer1_A2.TA1
0
1
1
Timer1_A2.CCI1A
0
0
1
A7
1
X
X
x
6
7
FUNCTION
NOTES: 1. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
71
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
APPLICATION INFORMATION
JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
&
Emulation
Module
DVCC
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
72
POST OFFICE BOX 655303
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MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
APPLICATION INFORMATION
JTAG fuse check mode
MSP430F21x2 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated,
a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse
is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall
system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current flows only when the fuse check mode is active and the TMS pin is in a low state (see
Figure 31). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 31. Fuse Check Mode Current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
73
MSP430F21x2
MIXED SIGNAL MICROCONTROLLER
SLAS578A -- NOVEMBER 2007 -- REVISED APRIL 2008
Data Sheet Revision History
LITERATURE
NUMBER
SUMMARY
SLAS578
PRODUCT PREVIEW data sheet release
SLAS578A
PRODUCTION DATA data sheet release
74
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2112IPW
ACTIVE
TSSOP
PW
28
MSP430F2112IPWR
ACTIVE
TSSOP
PW
MSP430F2112IRHBR
ACTIVE
QFN
MSP430F2112IRHBT
ACTIVE
MSP430F2112TPW
50
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2112TPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2112TRHB
PREVIEW
QFN
RHB
32
250
MSP430F2112TRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
TBD
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2112TRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2122IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2122IPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2122IRHB
PREVIEW
QFN
RHB
32
250
MSP430F2122IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2122IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2122TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2122TPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Call TI
Call TI
MSP430F2122TRHB
PREVIEW
QFN
RHB
32
250
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2122TRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2132IPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2132IPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2132IRHB
PREVIEW
QFN
RHB
32
250
MSP430F2132IRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2132IRHBT
ACTIVE
QFN
RHB
32
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2132TPW
ACTIVE
TSSOP
PW
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2132TPWR
ACTIVE
TSSOP
PW
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2132TRHB
PREVIEW
QFN
RHB
32
250
TBD
TBD
Call TI
Call TI
MSP430F2122TRHBR
Addendum-Page 1
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
21-Apr-2008
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2132TRHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2132TRHBT
ACTIVE
QFN
RHB
32
250
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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