TI TPS7A8001DRBR

TPS7A80xx
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
Low-Noise, High-Bandwidth PSRR,
Low-Dropout 1A Linear Regulator
Check for Samples: TPS7A80xx
FEATURES
DESCRIPTION
•
•
The TPS7A80xx family of low-dropout linear
regulators (LDOs) offer very high power-supply ripple
rejection (PSRR) at the output. This series of LDOs
uses an advanced BiCMOS process and a
PMOSFET pass device to achieve very low noise,
excellent transient response, and excellent PSRR
performance.
1
2
•
•
•
•
•
•
•
•
Low-Dropout 1A Regulator with Enable
Available in Multiple Output Versions:
– Fixed Output Voltages: 0.8V to 5.0V Using
Innovative Factory EEPROM Programming
– Adjustable Output Voltages: 0.8V to 6.0V
Ultra-High PSRR:
– 63dB at 1kHz
– 57dB at 100kHz
– 38dB at 1MHz
Low Noise: 15.6 × VOUT mVRMS typical (100Hz to
100kHz)
Stable with a 4.7mF Ceramic Capacitor
Excellent Load/Line Transient Response
3% Overall Accuracy (over Load/Line/Temp)
Over-Current and Over-Temperature
Protection
Very Low Dropout: 170mV Typical at 1A
3mm × 3mm SON-8 DRB Package
The TPS7A80xx is stable with a 4.7mF ceramic output
capacitor, and uses a precision voltage reference and
feedback loop to achieve a worst-case accuracy of
3% over all load, line, process, and temperature
variations.
This device is fully specified over the temperature
range of TJ = –40°C to +125°C and is offered in a
3mm × 3mm, SON-8 package with a thermal pad.
Typical Application Circuit for Fixed Voltage Versions
Optional 1.0mF input capacitor.
May improve source impedance,
noise, or PSRR.
VIN
IN
R1
TPS7A8001
EN
APPLICATIONS
•
•
•
VEN
OUT
1
8
IN
2
7
IN
FB/SNS
3
6
NR
GND
4
5
EN
NR
R2
To avoid inrush current,
it is recommended to
always connect a
1nF to 10nF capacitor
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
OUT
4.7mF
Ceramic
FB
GND
Telecom Infrastructure
Audio
High-Speed I/F (PLL/VCO)
VOUT
OUT
TYPICAL POWER-SUPPLY RIPPLE REJECTION
90
80
PSRR (dB)
70
60
50
40
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
IOUT = 1A
30
20
VDO = 1.0V
No CIN
10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS7A80xx
SBVS135A – JUNE 2010 – REVISED JUNE 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS7A80xxyyyz
(1)
(2)
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Voltage
Current
MIN
MAX
UNIT
IN
–0.3
+7.0
V
FB, NR
–0.3
+3.6
V
EN
–0.3
VIN +
0.3 (2)
V
OUT
–0.3
+7.0
V
OUT
Temperature
Internally Limited
–55
+150
Storage, Tstg
–55
+150
°C
2
kV
500
V
Human body model (HBM) QSS 009-105 (JESD22-A114A)
Electrostatic Discharge Rating (3)
(1)
(2)
(3)
2
A
Operating virtual junction, TJ
Charged device model (CDM) QSS 009-147
(JESD22-C101B.01)
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods my affect device reliability.
VEN absolute maximum rating is VIN + 0.3V or +7.0V, whichever is smaller.
ESD testing is performed according to the respective JESD22 JEDEC standard.
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TPS7A80xx
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
THERMAL INFORMATION
TPS7A80xx
THERMAL METRIC (1)
DRB (2)
UNITS
8 PINS
qJA
Junction-to-ambient thermal resistance (3)
47.8
qJCtop
Junction-to-case (top) thermal resistance (4)
83.0
qJB
Junction-to-board thermal resistance (5)
N/A
(6)
yJT
Junction-to-top characterization parameter
yJB
Junction-to-board characterization parameter (7)
17.8
qJCbot
Junction-to-case (bottom) thermal resistance (8)
12.1
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
2.1
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) The exposed pad is connected to the PCB ground layer through a 2×2 thermal via array.
(b) The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction
Temperature sections.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
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ELECTRICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater),
IOUT = 1mA, VEN = 2.2V, COUT = 4.7mF, and CNR = 0.01mF, unless otherwise noted. TPS7A8001 is tested at
VOUT = 0.8V and VOUT = 6.0V. Typical values are at TJ = +25°C.
TPS7A80xx
PARAMETER
VIN
Input voltage range (1)
VNR
Internal reference
Output voltage range
VOUT
Output accuracy (2)
0.790
V
V
0.8
6.0
V
VOUT + 0.5V ≤ VIN ≤ 6.0V, VIN ≥ 2.5V,
100mA ≤ IOUT ≤ 500mA, 0°C ≤ TJ ≤ 85°C
-2.0
+2.0
%
VOUT + 0.5V ≤ VIN ≤ 6.5V, VIN ≥ 2.2V,
100mA ≤ IOUT ≤ 1A
–3.0
+3.0
%
100mA ≤ IOUT ≤ 1A
±0.3
150
mV/V
2
mV/mA
VOUT + 0.5V ≤ VIN ≤ 6.5V, VIN ≥ 2.2V,
IOUT = 500mA, VFB = GND or VSNS = GND
250
mV
VOUT + 0.5V ≤ VIN ≤ 6.5V, VIN ≥ 2.5V,
IOUT = 750mA, VFB = GND or VSNS = GND
350
mV
VOUT + 0.5V ≤ VIN ≤ 6.5V, VIN ≥ 2.5V,
IOUT = 1A, VFB = GND or VSNS = GND
500
mV
1400
2000
mA
60
100
mA
VOUT = 0.85 × VOUT(NOM), VIN ≥ 3.3V
1100
IOUT = 1mA
IGND
Ground pin current
350
mA
ISHDN
Shutdown current (IGND)
VEN ≤ 0.4V, VIN ≥ 2.2V, RL = 1kΩ, 0°C ≤ TJ ≤ 85°C
0.20
2
mA
IFB
Feedback pin current
TPS7A8001 (adjustable), VIN = 6.5V, VFB = 0.8V
0.02
1.0
mA
ISNS
Sense pin current
TPS7A80xx (fixed), VIN = 6.5V, VSNS = VOUT(NOM)
0.02
1.0
mA
PSRR
VN
Power-supply rejection ratio
Output noise voltage
IOUT = 1A
VIN = 4.3V, VOUT = 3.3V,
IOUT = 750mA
BW = 100Hz to 100kHz,
VIN = 4.3V, VOUT = 3.3V,
IOUT = 100mA
RL = 1kΩ
Enable pin current, enabled
VIN = VEN = 6.5V
Startup time
VOUT(NOM) = 3.3V,
VOUT = 0% to 90% VOUT(NOM),
RL = 3.3kΩ, COUT = 4.7mF
Undervoltage lockout
VIN rising, RL = 1kΩ
Hysteresis
VIN falling, RL = 1kΩ
Thermal shutdown temperature
TJ
Operating junction temperature
63
dB
f = 10kHz
63
dB
f = 100kHz
57
dB
f = 1MHz
38
dB
CNR = 0.001mF
15.6 × VOUT
mVRMS
CNR = 0.01mF
15.6 × VOUT
mVRMS
CNR = 0.1mF
15.1 × VOUT
mVRMS
1.35
Enable low (shutdown)
TSD
dB
f = 1kHz
3.6V < VIN ≤ 6.5V, RL = 1kΩ
VEN(LO)
UVLO
48
1.2
Enable high (enabled)
tSTR
f = 100Hz
2.2V ≤ VIN ≤ 3.6V, RL = 1kΩ
VEN(HI)
IEN(HI)
(3)
V
0.810
TPS7A8001 (adjustable version)
Load regulation
(1)
(2)
UNIT
6.5
5.0
ΔVOUT/ΔIOUT
Output current limit
0.800
MAX
0.8
VOUT(NOM) + 0.5V ≤ VIN ≤ 6.5V, VIN ≥ 2.2V,
IOUT = 100mA
ICL
TYP
TPS7A80xx (fixed versions)
Line regulation
Dropout voltage (3)
MIN
2.2
ΔVOUT/ΔVIN
VDO
4
TEST CONDITIONS
V
V
0
0.02
CNR = 1nF
0.4
V
1.0
mA
0.1
CNR = 10nF
ms
1.6
1.86
Shutdown, temperature increasing
Reset, temperature decreasing
2
ms
2.10
mV
+160
°C
+140
–40
V
75
°C
+125
°C
Minimum VIN = VOUT + VDO or 2.2V, whichever is greater.
As for TPS7A8001 (adjustable); it does not include external resistor tolerances and it is not tested at this condition: VOUT = 0.8V, 4.5V ≤
VIN ≤ 6.5V, and 750mA ≤ IOUT ≤ 1A because of power dissipation higher than maximum rating of the package.
VDO is not measured for fixed output voltage devices with VOUT < 1.7V because minimum VIN = 2.2V.
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TPS7A80xx
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAMS
OUT
IN
SNS
Current
Limit
EN
Thermal
Shutdown
2.5mA
UVLO
1.20V
Bandgap
VOUT > 1.6V
Quick-Start
33kW
NR
33kW
225kW
0.8V
15pF
VOUT £ 1.6V
58.7kW
TPS7A80xx
GND
Figure 1. Fixed Voltage Versions
OUT
IN
Current
Limit
EN
Thermal
Shutdown
UVLO
1.20V
Bandgap
33kW
FB
Quick-Start
NR
33kW
225kW
0.8V
15pF
Adjustable
58.7kW
TPS7A8001
GND
Figure 2. Adjustable Voltage Version
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PIN CONFIGURATION
DRB PACKAGE
3mm x 3mm SON-8
(TOP VIEW)
OUT
1
8
IN
OUT
2
7
IN
FB/SNS
3
6
NR
GND
4
5
EN
Table 1. PIN DESCRIPTIONS
6
NAME
PIN NO.
IN
7, 8
DESCRIPTION
GND
4, pad
EN
5
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. Refer to Shutdown in the Application Information section for more details. EN must not be left floating
and can be connected to IN if not used.
NR
6
Connect an external capacitor between this pin and ground to reduce output noise to very low levels. Also,
the capacitor slows down the VOUT ramp (RC softstart).
FB
3
Adjustable voltage version only. This pin is the input to the control loop error amplifier and is used to set
the output voltage of the device.
SNS
3
Fixed voltage versions only. This pin is the input to the control loop error amplifier and is used to set the
output voltage of the device. This pin is to be shorted to OUT at load devices.
OUT
1, 2
Unregulated input supply.
Ground.
Regulator output. A 4.7mF or larger capacitor of any type is required for stability.
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TPS7A80xx
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
TYPICAL CHARACTERISTICS: TPS7A8001
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, all temperature values refer to TJ, unless otherwise noted.
LOAD REGULATION
LOAD REGULATION UNDER LIGHT LOADS
3.399
3.399
+125°C
+85°C
+25°C
0°C
-40°C
3.366
3.333
VOUT (V)
VOUT (V)
3.333
+125°C
+85°C
+25°C
0°C
-40°C
3.366
3.3
3.3
3.267
3.267
3.234
3.234
NOTE: Y axis shows 1% VOUT per division
NOTE: Y axis shows 1% VOUT per division
3.201
3.201
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
5
10
Figure 3.
0.816
25
LINE REGULATION UNDER LIGHT LOADS
0.824
VOUT = 0.8V
IOUT = 750mA
+125°C
+85°C
+25°C
0°C
-40°C
0.816
VOUT = 0.8V
IOUT = 5mA
+125°C
+85°C
+25°C
0°C
-40°C
0.808
VOUT (V)
0.818
VOUT (V)
20
Figure 4.
LINE REGULATION
0.824
15
IOUT (mA)
0.8
0.792
0.8
0.792
0.784
0.784
NOTE: Y axis shows 1% VOUT per division
NOTE: Y axis shows 1% VOUT per division
0.776
0.776
2.2
2.6
3
3.4
3.8
4.2 4.6
VIN (V)
Figure 5.
Copyright © 2010, Texas Instruments Incorporated
5
5.4
5.8
6.2
6.6
2.2
2.6
3
3.4
3.8
4.2 4.6
VIN (V)
5
5.4
5.8
6.2
6.6
Figure 6.
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TYPICAL CHARACTERISTICS: TPS7A8001 (continued)
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, all temperature values refer to TJ, unless otherwise noted.
DROPOUT VOLTAGE vs INPUT VOLTAGE
DROPOUT VOLTAGE vs INPUT VOLTAGE
500
500
IOUT = 1A
450
+125°C
+85°C
+25°C
0°C
-40°C
400
300
+125°C
+85°C
+25°C
0°C
-40°C
400
350
300
VDO (V)
VDO (V)
350
IOUT = 750mA
450
250
200
250
200
150
150
100
100
50
50
0
0
2
2.5
3
3.5
4
4.5
VIN (V)
5
5.5
6
2
6.5
2.5
3
3.5
Figure 7.
+125°C
+85°C
+25°C
0°C
-40°C
400
350
300
VIN = 3.6V
450
6
6.5
+125°C
+85°C
+25°C
0°C
-40°C
400
350
VDO (V)
VDO (V)
5.5
DROPOUT VOLTAGE vs LOAD CURRENT
500
IOUT = 500mA
450
5
Figure 8.
DROPOUT VOLTAGE vs INPUT VOLTAGE
500
4
4.5
VIN (V)
250
200
300
250
200
150
150
100
100
50
50
0
0
2
2.5
3
3.5
4
4.5
VIN (V)
5
5.5
6
0
6.5
100 200 300 400 500 600 700 800 900 1000
VIN (V)
Figure 9.
Figure 10.
DROPOUT VOLTAGE vs TEMPERATURE
500
450
VIN = 3.6V
IOUT = 1000mA
IOUT = 750mA
IOUT = 5mA
400
VDO (V)
350
300
250
200
150
100
50
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 11.
8
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TYPICAL CHARACTERISTICS: TPS7A8001 (continued)
300
300
250
250
200
200
IGND (mA)
IGND (mA)
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, all temperature values refer to TJ, unless otherwise noted.
GROUND PIN CURRENT vs INPUT VOLTAGE
GROUND PIN CURRENT vs LOAD CURRENT
150
+125°C
+85°C
+25°C
0°C
-40°C
100
50
0
VOUT = 0.8V
IOUT = 750mA
2.2
2.6
3
3.4
150
+125°C
+85°C
+25°C
0°C
-40°C
100
50
0
3.8
4.2 4.6
VIN (V)
5
5.4
5.8
6.2
0
6.6
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
Figure 12.
Figure 13.
SHUTDOWN CURRENT vs TEMPERATURE
CURRENT LIMIT vs TEMPERATURE
1800
2
1.8
1.6
VIN = 5V
VIN = 5.5V
VIN = 6V
VIN = 6.6V
1600
1400
1200
1.2
ICL (mA)
ISHDN (mA)
1.4
VIN = 2.2V
VIN = 2.5V
VIN = 3V
VIN = 3.3V
1
0.8
1000
800
600
0.6
VIN = 2.2V
VIN = 3.8V
VIN = 5.5V
VIN = 6.5V
400
0.4
200
0.2
VEN = 0.4V
0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
Figure 14.
Copyright © 2010, Texas Instruments Incorporated
80
95
110 125
0
VOUT = VIN - 0.5V
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 15.
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TYPICAL CHARACTERISTICS: TPS7A8001 (continued)
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, TJ = 25°C, unless otherwise noted.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
90
90
VDO = 1.0V
VDO = 0.5V
VDO = 0.3V
80
70
60
PSRR (dB)
PSRR (dB)
70
80
50
40
10
50
40
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
IOUT = 1A
30
30
20
60
IOUT = 100mA
No CIN
10
100
20
VDO = 1.0V
No CIN
10
1k
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Figure 16.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
80
70
70
60
60
PSRR (dB)
PSRR (dB)
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
90
VDO = 0.5V
No CIN
80
50
40
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
IOUT = 1A
20
50
40
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
IOUT = 1A
30
20
10
VDO = 1.0V
COUT = 22mF
No CIN
10
10
100
1k
10M
Figure 17.
90
30
1M
10k
100k
Frequency (Hz)
1M
10M
10
100
1k
10k
100k
Frequency (Hz)
Figure 18.
1M
10M
Figure 19.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
90
80
PSRR (dB)
70
60
50
40
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
IOUT = 1A
30
20
VDO = 0.5V
COUT = 22mF
No CIN
10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
Figure 20.
10
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
TYPICAL CHARACTERISTICS: TPS7A8001 (continued)
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, TJ = 25°C, unless otherwise noted.
POWER-SUPPLY RIPPLE REJECTION
POWER-SUPPLY RIPPLE REJECTION
vs DROPOUT VOLTAGE
vs DROPOUT VOLTAGE
90
80
70
70
60
60
50
40
50
40
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
30
20
f = 1kHz
f = 10kHz
f = 100kHz
f = 1MHz
30
20
10
10
0.5
1
1.5
2
VDO (V)
2.5
3
1
1.5
2
VDO (V)
2.5
3
Figure 22.
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
RMS Noise (100Hz to 100kHz)
47.95VRMS (COUT = 4.7mF)
47.33VRMS (COUT = 22mF)
47.42VRMS (COUT = 47mF)
VDO = 0.5V
IOUT = 100mA
10
1
COUT = 4.7mF
COUT = 22mF
COUT = 47mF
0.01
10
0.5
Figure 21.
100
0.1
0
3.5
100
1k
Frequency (Hz)
10k
Output Spectral Noise Density (mV/ÖHz)
0
Output Spectral Noise Density (mV/ÖHz)
IOUT = 750mA
No CIN
80
PSRR (dB)
PSRR (dB)
90
IOUT = 100mA
No CIN
100
3.5
RMS Noise (100Hz to 100kHz)
48.14VRMS (CNR = 1nF)
47.33VRMS (CNR = 10nF)
45.90VRMS (CNR = 100nF)
VDO = 0.5V
IOUT = 100mA
10
1
0.1
CNR = 1nF
CNR = 10nF
CNR = 100nF
0.01
100k
10
100
1k
Frequency (Hz)
Figure 23.
10k
100k
Figure 24.
Output Spectral Noise Density (mV/ÖHz)
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
100
RMS Noise (100Hz to 100kHz)
92.07VRMS (IOUT = 10mA)
47.95VRMS (IOUT = 100mA)
46.87VRMS (IOUT = 750mA)
VDO = 0.5V
10
1
0.1
IOUT = 10mA
IOUT = 100mA
IOUT = 750mA
0.01
10
100
1k
Frequency (Hz)
10k
100k
Figure 25.
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TPS7A80xx
SBVS135A – JUNE 2010 – REVISED JUNE 2010
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TYPICAL CHARACTERISTICS: TPS7A8001 (continued)
At VOUT(TYP) = 3.3V, VIN = VOUT(TYP) + 0.5V or 2.2V (whichever is greater), IOUT = 100mA, VEN = VIN, CIN = 1mF, COUT = 4.7mF, and
CNR = 0.01mF, TJ = 25°C, unless otherwise noted.
STARTUP TIME
vs NOISE REDUCTION CAPACITANCE
LINE TRANSIENT RESPONSE
1000
7
RLOAD = 1kW
3.333
3.32475
VOUT
6
VIN (V), 0.5V/div
100
10
3.3165
5.5
3.30825
VIN = 3.8V ® 4.8V ® 3.8V (1V/div)
5
3.3
3.29175
4.5
3.2835
4
1
VOUT (V), 0.25% of 3.3V/div
EN to 90% VOUT (ms)
6.5
3.27525
3.5
IOUT = 500mA
3.267
3
50ms/div
0.1
1
10
100
1000
CNR (nF)
Figure 26.
Figure 27.
LOAD TRANSIENT RESPONSE
3.8
4.5
4.5
VIN (for reference)
3.75
3.5
3.5
2
3.3
IOUT = 100mA ® 1A ® 100mA (1A/ms)
3.25
VEN, VOUT (V)
2.5
2.5
1.5
1.5
3.15
0.5
3.15
0
OUT
2
1
1
3.2
EN
3
IOUT (A)
VOUT
3.35
RLOAD = 33W
4
4
3.7
VIN, VOUT (V)
ENABLE PULSE RESPONSE
5
3.85
0.5
0
-0.5
50ms/div
1ms/div
Figure 28.
Figure 29.
POWER-UP/POWER-DOWN RESPONSE(1)
7
RLOAD = 33W
6
VIN, VOUT (V)
5
4
VIN = VEN
VOUT
3
2
1
0
-1
1ms/div
Figure 30.
(1)
12
The internal reference requires approximately 2ms of rampup time (see Startup); therefore, VOUT fully reaches the
target output voltage of 3.3V in 2ms from starup.
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TPS7A80xx
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SBVS135A – JUNE 2010 – REVISED JUNE 2010
APPLICATION INFORMATION
The TPS7A80xx belongs to a family of new
generation LDO regulators that use innovative
circuitry to achieve ultra-wide bandwidth and high
loop gain, resulting in extremely high PSRR (over a
1MHz range) at very low headroom (VIN – VOUT). A
noise reduction capacitor (CNR) at the NR pin
bypasses noise generated by the bandgap reference
in order to improve PSRR, while a quick-start circuit
fast-charges this capacitor. This family of regulators
offers sub-bandgap output voltages, current limit, and
thermal protection, and is fully specified from –40°C
to +125°C.
Figure 31 shows the basic circuit connections for the
fixed voltage options. Figure 32 gives the connections
for the adjustable output version (TPS7A8001).
IN
VOUT
OUT
TPS7A80xx SNS
EN
GND
4.7mF
Ceramic
NR
VEN
To avoid inrush current,
it is recommended to
always connect a
1nF to 10nF capacitor
Figure 31. Typical Application Circuit
(Fixed Voltage Versions)
IN
VOUT
OUT
R1
TPS7A8001
EN
FB
GND
NR
4.7mF
Ceramic
R2
VEN
To avoid inrush current,
it is recommended to
always connect a
1nF to 10nF capacitor
Figure 32. Typical Application Circuit
(Adjustable Voltage Version)
VOUT
R1
R2
0.8V
0Ω (Short)
10.0kΩ
1.0V
2.49kΩ
10.0kΩ
1.2V
4.99kΩ
10.0kΩ
1.5V
8.87kΩ
10.0kΩ
1.8V
12.5kΩ
10.0kΩ
2.5V
21.0kΩ
10.0kΩ
3.3V
30.9kΩ
10.0kΩ
5.0V
52.3kΩ
10.0kΩ
Input and Output Capacitor Requirements
Optional 1.0mF input capacitor.
May improve source impedance,
noise, or PSRR.
VIN
Sample resistor values for common output voltages
are shown in Table 2. In Table 2, E96 series resistors
are used, and all values meet 1% of the target VOUT,
assuming resistors with zero error. For the actual
design, pay attention to any resistor error factors.
Using lower values for R1 and R2 reduces the noise
injected from the FB pin.
Table 2. Sample 1% Resistor Values for Common
Output Voltages
Optional 1.0mF input capacitor.
May improve source impedance,
noise, or PSRR.
VIN
For the adjustable version (TPS7A8001), the voltage
on the FB pin sets the output voltage and is
determined by the values of R1 and R2. The values of
R1 and R2 can be calculated for any voltage using the
formula given in Equation 1:
(R + R2 )
VOUT = 1
x 0.800
R2
(1)
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1mF to 1.0mF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or if the device is
located several inches from the power source. If
source impedance is not sufficiently low, a 0.1mF
input capacitor may be necessary to ensure stability.
The TPS7A80xx is designed to be stable with
standard ceramic capacitors of capacitance values
4.7mF or larger. This device is evaluated using a
4.7mF ceramic capacitor of 10V rating, 10%
tolerance, X5R type, and 0805 size (2.0mm x
1.25mm).
X5R- and X7R-type capacitors are highly
recommended because they have minimal variation
in value and ESR over temperature. Maximum ESR
should be <1.0Ω.
Copyright © 2010, Texas Instruments Incorporated
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TPS7A80xx
SBVS135A – JUNE 2010 – REVISED JUNE 2010
The TPS7A80xx implements an innovative internal
compensation circuit that does not require a feedback
capacitor across R2 for stability. A feedback capacitor
should not be used for this device.
Output Noise
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS7A80xx, the bandgap does not
contribute significantly to noise. Instead, noise is
dominated by the output resistor divider and the error
amplifier input. To minimize noise in a given
application, use a 0.01mF (minimum) noise-reduction
capacitor.
Equation 2 approximates the total noise when
CNR = 0.01mF:
VN = 15.6 (VRMS/V) ´ VOUT
(2)
Board Layout Recommendations to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Internal Current Limit
The TPS7A80xx internal current limit helps protect
the regulator during fault conditions. During current
limit, the output sources a fixed amount of current
that is largely independent of output voltage. For
reliable operation, the device should not be operated
in a current limit state for extended periods of time.
The PMOS pass element in the TPS7A80xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting may be
appropriate.
Shutdown
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
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Dropout Voltage
The TPS7A80xx uses a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element.
VDO scales approximately with output current
because the PMOS device in dropout behaves the
same way as a resistor.
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 21 and
Figure 22 in the Typical Characteristics section.
Startup
Through a lower resistance, the bandgap reference
can quickly charge the noise reduction capacitor
(CNR). The TPS7A80xx has a quick-start circuit to
quickly charge CNR, if present; see the Functional
Block Diagrams. At startup, this quick-start switch is
closed, with only 33kΩ of resistance between the
bandgap reference and the NR pin. The quick-start
switch opens approximately 2ms after any device
enabling event, and the resistance between the
bandgap reference and the NR pin becomes higher in
value (approximately 250kΩ) to form a very good
low-pass (RC) filter. This low-pass filter achieves very
good noise reduction for the reference voltage.
Inrush current can be a problem in many applications.
The 33kΩ resistance during the startup period is
intentionally put there to slow down the reference
voltage ramp up, thus reducing the inrush current.
For example, the capacitance of connecting the
recommended CNR value of 0.01mF along with the
33kΩ resistance causes approximately 1ms RC
delay. Startup time with the other CNR values can be
calculated as:
tSTR (s) = 76,000 x CNR (F)
(3)
Although the noise reduction effect is nearly saturated
at 0.01mF, connecting a CNR value greater than
0.01mF can help reduce noise slightly more; however,
startup time will be extremely long because the
quick-start switch opens after approximately 2ms.
That is, if CNR is not fully charged during this 2ms
period, CNR finishes charging through a higher
resistance of 250kΩ, and takes much longer to fully
charge.
Note that a low leakage CNR should be used; most
ceramic capacitors are suitable.
Transient Response
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
14
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TPS7A80xx
www.ti.com
The TPS7A80xx utilizes an undervoltage lock-out
circuit to keep the output shut off until the internal
circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
than 50ms duration.
Minimum Load
The TPS7A80xx is stable and well-behaved with no
output load. Traditional PMOS LDO regulators suffer
from lower loop gain at very light output loads. The
TPS7A80xx employs an innovative low-current mode
circuit to increase loop gain under very light or
no-load conditions, resulting in improved output
voltage regulation performance down to zero output
current.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage because of
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces a worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS7A80xx
has been designed to protect against overload
conditions. It was not intended to replace proper
heatsinking. Continuously running the TPS7A80xx
into thermal shutdown degrades device reliability.
Power Dissipation
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
Copyright © 2010, Texas Instruments Incorporated
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 4:
P D + ǒVIN * VOUTǓ
I OUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On the SON (DRB) package, the primary conduction
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be
connected to ground or be left floating; however, it
should be attached to an appropriate amount of
copper PCB area to ensure the device does not
overheat. The maximum junction-to-ambient thermal
resistance depends on the maximum ambient
temperature, maximum device junction temperature,
and power dissipation of the device and can be
calculated using Equation 5:
()125OC * T A)
R qJA +
PD
(5)
Knowing the maximum RqJA, the minimum amount of
PCB copper area needed for appropriate heatsinking
can be estimated using Figure 33.
160
140
120
qJA (°C/W)
Undervoltage Lock-Out (UVLO)
SBVS135A – JUNE 2010 – REVISED JUNE 2010
100
80
60
40
20
0
0
Note:
1
2
4
5
7
3
6
Board Copper Area (in2)
8
9
10
qJA value at board size of 9in2 (that is, 3in ×
3in) is a JEDEC standard.
Figure 33. qJA vs Board Size
Figure 33 shows the variation of qJA as a function of
ground plane Copper area in the board. It is intended
only as a guideline to demonstrate the effect of heat
spreading in the ground plane and should not be
used in a estimating the thermal performance in real
application environment.
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
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TPS7A80xx
SBVS135A – JUNE 2010 – REVISED JUNE 2010
www.ti.com
ESTIMATING JUNCTION TEMPERATURE
20
YJB: TJ = TB + YJB · PD
18
14
12
10
8
6
(6)
4
Where PD is the power dissipation shown by
Equation 5, TT is the temperature at the center-top of
the IC package, and TB is the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 35 shows).
2
NOTE: Both TT and TB can be measured on actual
application boards using a thermo-gun (an infrared
thermometer).
For more information about measuring TT and TB, see
the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 34, the new thermal metrics (ΨJT
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 6 is a good
way to estimate TJ by simply measuring TT or TB,
regardless of the application board size.
YJB
16
YJT and YJB (°C/W)
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older qJC,Top parameter is listed as
well.
YJT: TJ = TT + YJT · PD
YJT
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 34. ΨJT and ΨJB vs Board Size
For a more detailed discussion of why TI does not
recommend using qJC(top) to determine thermal
characteristics, refer to application report SBVA025,
Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
application report SPRA953, IC Package Thermal
Metrics, also available on the TI website.
Figure 35. Measuring Point for TT and TB
16
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Copyright © 2010, Texas Instruments Incorporated
TPS7A80xx
www.ti.com
SBVS135A – JUNE 2010 – REVISED JUNE 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June, 2010) to Revision A
Page
•
Increased output current limit maximum specification from 1900mA to 2000mA ................................................................. 4
•
Changed ground pin current typical specification for IOUT = 1mA from 45mA to 60mA ......................................................... 4
•
Corrected typical hysteresis value from 150mV to 75mV ..................................................................................................... 4
Copyright © 2010, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
29-Jun-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
TPS7A8001DRBR
PREVIEW
SON
TPS7A8001DRBT
PREVIEW
SON
Pins
Package Qty
DRB
8
3000
TBD
Call TI
Call TI
Samples Not Available
DRB
8
250
TBD
Call TI
Call TI
Samples Not Available
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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