TI PCI1410GHK

 Data Manual
2000
PCIBus Solutions
Printed in U.S.A.
03/00
SCPS045C
PCI1410
PC Card Controllers
Data Manual
Literature Number: SCPS045C
March 2000
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
Contents
Section
1
2
3
Title
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Feature/Protocol Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Power Supply Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Clamping Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Peripheral Component Interconnect (PCI) Interface . . . . . . . . . . . . . .
3.4.1
PCI Bus Lock (LOCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2
Loading Subsystem Identification . . . . . . . . . . . . . . . . . . . . .
3.5
PC Card Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1
PC Card Insertion/Removal and Recognition . . . . . . . . . . .
3.5.2
P2C Power-Switch Interface (TPS2211) . . . . . . . . . . . . . . .
3.5.3
Zoomed Video Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4
Ultra Zoomed Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5
Internal Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6
Integrated Pullup Resistors For PC Card Interface . . . . . .
3.5.7
SPKROUT and CAUDPWM Usage . . . . . . . . . . . . . . . . . . .
3.5.8
LED Socket Activity Indicators . . . . . . . . . . . . . . . . . . . . . . . .
3.5.9
PC Card-16 Distributed DMA Support . . . . . . . . . . . . . . . . .
3.5.10
PC Card-16 PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.11
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Serial Bus Interface Implementation . . . . . . . . . . . . . . . . . . .
3.6.2
Serial Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
Serial Bus EEPROM Application . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Accessing Serial Bus Devices Through Software . . . . . . . .
3.7
Programmable Interrupt Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
PC Card Functional and Card Status Change Interrupts .
3.7.2
Interrupt Masks and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
Using Parallel IRQ Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4
Using Parallel PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .
Page
1–1
1–1
1–1
1–2
1–2
2–1
3–1
3–1
3–2
3–2
3–2
3–2
3–3
3–3
3–3
3–4
3–5
3–6
3–6
3–7
3–7
3–8
3–8
3–10
3–10
3–11
3–11
3–11
3–13
3–14
3–15
3–15
3–17
3–17
3–18
iii
4
iv
3.7.5
Using Serialized IRQSER Interrupts . . . . . . . . . . . . . . . . . . .
3.7.6
SMI Support in the PCI1410 . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8
Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Clock Run Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
CardBus PC Card Power Management . . . . . . . . . . . . . . . .
3.8.3
16-Bit PC Card Power Management . . . . . . . . . . . . . . . . . . .
3.8.4
Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.5
Requirements for Suspend Mode . . . . . . . . . . . . . . . . . . . . .
3.8.6
Ring Indicate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.7
PCI Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8
CardBus Bridge Power Management . . . . . . . . . . . . . . . . . .
3.8.9
ACPI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.10
Master List of PME Context Bits and
Global Reset Only Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC Card Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
PCI Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register . . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 I/O Limit Registers 0, 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-bit I/F Legacy-Mode Base-Address Register . . . . . . . . .
4.29 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18
3–18
3–19
3–19
3–19
3–19
3–20
3–21
3–21
3–22
3–23
3–23
3–24
4–1
4–1
4–2
4–2
4–3
4–4
4–5
4–5
4–5
4–6
4–6
4–6
4–7
4–7
4–8
4–9
4–9
4–9
4–10
4–10
4–11
4–11
4–12
4–12
4–13
4–14
4–15
4–15
4–15
4–16
4.30
4.31
4.32
4.33
4.34
4.35
4.36
4.37
4.38
4.39
4.40
4.41
5
Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Next-Item Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Bridge Support Extensions
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.42 Power Management Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.43 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . .
4.44 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . .
4.45 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.49 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.50 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . .
ExCA Compatibility Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . .
5.2
ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
ExCA Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4
ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . .
5.5
ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6
ExCA Card Status-Change-Interrupt Configuration Register . . . . . . .
5.7
ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . .
5.8
ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9
ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers . . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers . . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers . . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers . . . .
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers . . .
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers . . .
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers . . . .
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers . . .
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers . .
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers .
5.19 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers . . .
4–19
4–20
4–21
4–22
4–23
4–24
4–25
4–26
4–26
4–27
4–28
4–29
4–29
4–30
4–31
4–32
4–33
4–33
4–34
4–34
4–35
5–1
5–4
5–5
5–6
5–8
5–9
5–10
5–11
5–12
5–13
5–13
5–14
5–14
5–15
5–16
5–17
5–18
5–19
5–20
5–21
5–22
5–23
v
6
7
8
9
vi
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers . . . 5–23
5.23 ExCA Memory Windows 0–4 Page Register . . . . . . . . . . . . . . . . . . . . 5–24
CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–1
6.1
Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–2
6.2
Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–3
6.3
Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–4
6.4
Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–6
6.5
Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8
6.6
Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–9
Distributed DMA (DDMA) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–1
7.1
DDMA Current Address/Base-Address Register . . . . . . . . . . . . . . . . . 7–1
7.2
DDMA Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–2
7.3
DDMA Current Count/Base Count Register . . . . . . . . . . . . . . . . . . . . . 7–2
7.4
DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7.5
DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–3
7.6
DDMA Request Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7.7
DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–4
7.8
DDMA Master Clear Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
7.9
DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–5
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.1
Absolute Maximum Ratings Over Operating
Temperature Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–1
8.2
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 8–2
8.3
Electrical Characteristics Over Recommended
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–3
8.4
PCI Clock/Reset Timing Requirements Over Recommended
Ranges of Supply Voltage and Operating Free-Air Temperature . . . 8–4
8.5
PCI Timing Requirements Over Recommended Ranges
of Supply Voltage and Operating Free-Air Temperature . . . . . . . . . . . 8–4
8.6
PC Card Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4
Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–1
List of Illustrations
Figure
Title
2–1 PCI-to-CardBus Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 PCI-to-PC Card (16-Bit) Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 GGU Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 GHK Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI1410 Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 3-State Bidirectional Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 TPS2211 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 TPS2211 Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Zoomed Video Implementation Using PCI1410 . . . . . . . . . . . . . . . . . . . . . . .
3–6 Zoomed Video Switching Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–7 Sample Application of SPKROUT and CAUDPWM . . . . . . . . . . . . . . . . . . . .
3–8 Two Sample LED Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 Serial EEPROM Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 Serial Bus Start/Stop Conditions and Bit Transfers . . . . . . . . . . . . . . . . . . .
3–11 Serial Bus Protocol Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–12 Serial Bus Protocol – Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–13 Serial Bus Protocol – Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–14 EEPROM Interface Doubleword Data Collection . . . . . . . . . . . . . . . . . . . . .
3–15 EEPROM Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–16 IRQ Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–17 Suspend Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–18 Signal Diagram of Suspend Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–19 RI_OUT Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–20 Block Diagram of a Status/Enable Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 ExCA Register Access Through I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Register Access Through Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Accessing CardBus Socket Registers Through PCI Memory . . . . . . . . . . . .
Page
2–1
2–2
2–3
2–3
3–1
3–2
3–4
3–5
3–5
3–6
3–8
3–8
3–11
3–12
3–12
3–13
3–13
3–13
3–14
3–18
3–20
3–21
3–22
3–24
5–1
5–1
6–1
vii
List of Tables
Table
Title
2–1 CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number . .
2–2 CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number . . .
2–3 CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number . . .
2–4 CardBus PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 16-Bit PC Card Signal Names Sorted Alphabetically to
GGU/PGE/GHK Terminal Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 PC Card Power Switch Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 PCI Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 PCI Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 Multifunction and Miscellaneous Terminals . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 16-Bit PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . . . .
2–13 16-Bit PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . . . . .
2–14 CardBus PC Card Interface System Terminals . . . . . . . . . . . . . . . . . . . . . . .
2–15 CardBus PC Card Address and Data Terminals . . . . . . . . . . . . . . . . . . . . . .
2–16 CardBus PC Card Interface Control Terminals . . . . . . . . . . . . . . . . . . . . . . .
3–1 PC Card Card-Detect and Voltage-Sense Connections . . . . . . . . . . . . . . . .
3–2 Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 PC/PCI Channel Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 I/O Addresses Used for PC/PCI DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Registers and Bits Loadable Through Serial EEPROM . . . . . . . . . . . . . . . . .
3–7 PCI1410 Registers Used to Program Serial Bus Devices . . . . . . . . . . . . . . .
3–8 Interrupt Mask and Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–9 PC Card Interrupt Events and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–10 SMI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–11 Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 PCI Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Bit Field Access Tag Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Secondary Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 Bridge Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 System Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 Multifunction Routing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 Retry Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
Page
2–4
2–5
2–6
2–8
2–10
2–12
2–12
2–12
2–13
2–14
2–15
2–16
2–17
2–18
2–19
2–20
3–4
3–9
3–10
3–10
3–11
3–13
3–14
3–16
3–16
3–18
3–23
4–1
4–2
4–3
4–4
4–8
4–14
4–17
4–19
4–20
4–10
4–11
4–12
4–13
4–14
4–15
4–16
4–17
Card Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket DMA Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Socket DMA Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Control/Status Bridge Support
Extensions Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–18 General-Purpose Event Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–19 General-Purpose Event Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–20 General-Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–21 General-Purpose Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–22 Serial Bus Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–23 Serial Bus Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–24 Serial Bus Slave Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–25 Serial Bus Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 ExCA Registers and Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 ExCA Identification and Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 ExCA Interface Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 ExCA Power Control Register 82365SL Support . . . . . . . . . . . . . . . . . . . . . .
5–5 ExCA Power Control Register 82365SL-DF Support . . . . . . . . . . . . . . . . . . .
5–6 ExCA Interrupt and General Control Register . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 ExCA Card Status-Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 ExCA Card Status-Change-Interrupt Configuration Register . . . . . . . . . . . .
5–9 ExCA Address Window Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 ExCA I/O Window Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 ExCA Memory Windows 0–4 Start-Address High-Byte Registers . . . . . . .
5–12 ExCA Memory Windows 0–4 End-Address High-Byte Registers . . . . . . . .
5–13 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers . . . . . .
5–14 ExCA Card Detect and General Control Register . . . . . . . . . . . . . . . . . . . . .
5–15 ExCA Global Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 CardBus Socket Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 Socket Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 Socket Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Socket Present State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–5 Socket Force Event Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–6 Socket Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–7 Socket Power Management Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–21
4–22
4–23
4–24
4–25
4–27
4–28
4–29
4–30
4–31
4–32
4–33
4–33
4–34
4–34
4–35
5–2
5–4
5–5
5–6
5–7
5–8
5–9
5–10
5–11
5–12
5–16
5–18
5–20
5–21
5–22
6–1
6–2
6–3
6–4
6–7
6–8
6–9
ix
7–1
7–2
7–3
7–4
7–5
x
Distributed DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDMA Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDMA Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDMA Multichannel/Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7–1
7–3
7–3
7–4
7–5
1 Introduction
1.1 Description
The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant
with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between
PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card
specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full
32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V,
as required.
The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus
PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface
Specification and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges.
All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is
register compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1410, such as socket activity light-emitting diode (LED)
outputs, are discussed in detail throughout the design specification.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.
1.2 Features
The PCI1410 supports the following features:
•
Ability to wake from D3hot and D3cold
•
Fully compatible with the Intel 430TX (Mobile Triton II) chipset
•
A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball grid array (GGU) package, or
209-terminal MicroStar BGA (GHK) package
•
3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
•
Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards
•
Single PC Card or CardBus slot with hot insertion and removal
•
Burst transfers to maximize data throughput on the PCI bus and the CardBus bus
•
Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI
interrupts, and serial ISA IRQ and PCI interrupts
TI is a trademark of Texas Instruments.
MicroStar BGA is a trademark of Texas Instruments.
Intel is a trademark of Intel Corporation.
Other trademarks are the property of their respective owners.
1–1
•
Serial EEPROM interface for loading subsystem ID and subsystem vendor ID
•
Pipelined architecture allows greater than 130-Mbps sustained throughput from CardBus to PCI and from
PCI to CardBus
•
Interface to parallel single-slot PC Card power interface switches like the TI TPS2211
•
Up to five general-purpose I/Os
•
Programmable output select for CLKRUN
•
Five PCI memory windows and two I/O windows available to the 16-bit PC Card socket
•
Two I/O windows and two memory windows available to the CardBus socket
•
Exchangeable card architecture (ExCA) compatible registers are mapped in memory and I/O space
•
Intel 82365SL-DF and 82365SL register compatible
•
Distributed DMA (DDMA) and PC/PCI DMA
•
16-Bit DMA on the PC Card socket
•
Ring indicate, SUSPEND, PCI CLKRUN, and CardBus CCLKRUN
•
Socket activity LED pins
•
PCI bus lock (LOCK)
•
Advanced submicron, low-power CMOS technology
•
Internal ring oscillator
1.3 Related Documents
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0)
•
PCI Bus Power Management Interface Specification (Revision 1.1)
•
PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (Revision 0.6)
•
PCI Local Bus Specification (Revision 2.2)
•
PCI Mobile Design Guide (Revision 1.0)
•
PCI14xx Implementation Guide for D3 Wake-Up
•
1997 PC Card Standard
•
PC 98
•
PC 99
•
Serialized IRQ Support for PCI Systems (Revision 6)
1.4 Ordering Information
ORDERING NUMBER
PCI1410
NAME
PC Card Controller
VOLTAGE
3.3-V, 5-V tolerant I/Os
PACKAGE
144-terminal LQFP
144-terminal PBGA
209-terminal PBGA
1–2
2 Terminal Descriptions
The PCI1410 is packaged in either a 144-terminal GGU MicroStar BGA or a 144-terminal PGE package. It is also
packaged in a 209-terminal GHK MicroStar BGA that is pin compatible with the TI PCI4410. The PCI4410 is a
single-socket CardBus bridge with integrated OHCI link. Figure 2–1 is a PGE-package terminal diagram showing
PCI-to-CardBus signal names, and Figure 2–2 is a PGE-package terminal diagram showing PCI-to-PC Card signal
names. Figure 2–3 and Figure 2–4 are terminal diagrams for the GGU and GHK packages, respectively.
108
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73
CCLK
CDEVSEL
CGNT
CSTOP
CPERR
CBLOCK
V CC
CPAR
CRSVD
CC/BE1
CAD16
CAD14
CAD15
CAD12
GND
CAD13
CAD11
CAD10
VCCCB
CAD9
CC/BE0
CAD8
V CC
CAD7
CRSVD
CAD5
CAD6
CAD3
CAD4
CAD1
GND
CAD2
CAD0
CCD1
VCCD1
VCCD0
PGE LOW-PROFILE QUAD FLAT PACKAGE
(TOP VIEW)
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142
1
2
3
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23
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29
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34
35
36
143
144
VPPD1
VPPD0
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
MFUNC3
MFUNC2
VCCI
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VCC
AD7
C/BE0
AD8
AD9
AD10
VCCP
AD11
GND
AD12
AD13
AD14
AD15
C/BE1
REQ
GNT
AD31
AD30
AD29
GND
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
VCC
AD23
AD22
AD21
VCCP
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
VCC
TRDY
DEVSEL
STOP
PERR
SERR
PAR
CTRDY
CIRDY
CFRAME
CC/BE2
CAD17
GND
CAD18
CAD19
CVS2
CAD20
CRST
CAD21
CAD22
VCC
CREQ
CAD23
CC/BE3
VCCCB
CAD24
CAD25
CAD26
GND
CVS1
CINT
CSERR
CAUDIO
CSTSCHG
CCLKRUN
CCD2
VCC
CAD27
CAD28
CAD29
CAD30
CRSVD
CAD31
Figure 2–1. PCI-to-CardBus Terminal Diagram
2–1
108
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ADDR16
ADDR21
WE
ADDR20
ADDR14
ADDR19
V CC
ADDR13
ADDR18
ADDR8
ADDR17
ADDR9
IOWR
ADDR11
GND
IORD
OE
CE2
VCCCB
ADDR10
CE1
DATA15
V CC
DATA7
DATA14
DATA6
DATA13
DATA5
DATA12
DATA4
GND
DATA11
DATA3
CD1
VCCD1
VCCD0
PGE LOW-PROFILE QUAD FLAT PACKAGE
(TOP VIEW)
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REQ
GNT
AD31
AD30
AD29
GND
AD28
AD27
AD26
AD25
AD24
C/BE3
IDSEL
VCC
AD23
AD22
AD21
VCCP
AD20
PRST
PCLK
GND
AD19
AD18
AD17
AD16
C/BE2
FRAME
IRDY
VCC
TRDY
DEVSEL
STOP
PERR
SERR
PAR
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34
35
36
ADDR22
ADDR15
ADDR23
ADDR12
ADDR24
GND
ADDR7
ADDR25
VS2
ADDR6
RESET
ADDR5
ADDR4
VCC
INPACK
ADDR3
REG
VCCCB
ADDR2
ADDR1
ADDR0
GND
VS1
READY(IREQ)
WAIT
BVD2(SPKR)
BVD1(STSCHG/RI)
WP(IOIS16)
CD2
VCC
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
Figure 2–2. PCI-to-PC Card (16-Bit) Terminal Diagram
2–2
VPPD1
VPPD0
SUSPEND
MFUNC6
MFUNC5
MFUNC4
GRST
MFUNC3
MFUNC2
VCCI
SPKROUT
MFUNC1
MFUNC0
RI_OUT/PME
GND
AD0
AD1
AD2
AD3
AD4
AD5
AD6
VCC
AD7
C/BE0
AD8
AD9
AD10
VCCP
AD11
GND
AD12
AD13
AD14
AD15
C/BE1
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 2–3. GGU Package Terminal Diagram
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
Figure 2–4. GHK Package Terminal Diagram
Table 2–1 shows the terminal assignments for the 144-terminal GGU CardBus and 16-bit PC Card signal names.
Table 2–2 shows the terminal assignments for the 144-terminal PGE CardBus and 16-bit PC Card signal names.
Table 2–3 shows the terminal assignments for the 209-terminal GHK CardBus and 16-bit PC Card signal names.
Table 2–4 shows the CardBus PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers.
Table 2–5 shows the 16-bit PC Card signal names sorted alphabetically to the GGU/PGE/GHK terminal numbers.
2–3
Table 2–1. CardBus and 16-Bit PC Card Signal Names by GGU Terminal Number
SIGNAL NAME
TERM.
TERM
NO.
2–4
CARD
BUS
16-BIT
SIGNAL NAME
TERM.
TERM
NO.
CARD
BUS
16-BIT
SIGNAL NAME
TERM.
TERM
NO.
CARD
BUS
16-BIT
SIGNAL NAME
TERM.
TERM
NO.
CARD
BUS
16-BIT
A1
REQ
REQ
C11
CGNT
WE
G10
CAD11
OE
L4
GND
GND
A2
CRSVD
DATA2
C12
CSTOP
ADDR20
G11
CAD10
CE2
L5
AD9
AD9
A3
CAD28
DATA8
C13
CPERR
ADDR14
G12
CAD9
ADDR10
L6
A4
CCD2
CD2
D1
AD27
AD27
G13
VCC
AD2
VCC
AD2
CSERR
WAIT
D2
AD28
AD28
H1
VCCCB
PCLK
L7
A5
VCCCB
PCLK
L8
RI_OUT/
PME
RI_OUT/
PME
A6
CAD26
ADDR0
D3
GND
GND
H2
GND
GND
L9
A7
VCCCB
ADDR3
D4
AD29
AD29
H3
AD19
AD19
L10
VCCI
MFUNC4
VCCI
MFUNC4
A8
VCCCB
CAD23
D5
CCLKRUN
WP
(IOIS16)
H4
AD18
AD18
L11
SUSPEND
SUSPEND
A9
CAD21
ADDR5
D6
CINT
READY
(IREQ)
H10
CAD7
DATA7
L12
CCD1
CD1
A10
CAD19
ADDR25
D7
CAD25
ADDR1
H11
DATA3
CC/BE2
D8
CAD22
ADDR4
H12
VCC
DATA15
CAD0
A11
VCC
CAD8
L13
ADDR12
M1
SERR
SERR
A12
CIRDY
ADDR15
D9
CVS2
VS2
H13
CC/BE0
CE1
M2
PAR
PAR
A13
CTRDY
ADDR22
D10
CAD17
ADDR24
J1
AD17
AD17
M3
AD14
AD14
B1
GNT
GNT
D11
CBLOCK
ADDR19
J2
AD16
AD16
M4
AD11
AD11
B2
CAD31
DATA10
D12
C/BE2
M5
AD8
AD8
DATA1
D13
VCC
ADDR13
C/BE2
CAD29
VCC
CPAR
J3
B3
J4
FRAME
FRAME
M6
AD6
AD6
B4
VCC
BVD2
(SPKR)
E1
C/BE3
C/BE3
J10
CAD3
DATA5
M7
AD4
AD4
B5
VCC
CAUDIO
E2
AD24
AD24
J11
CAD6
DATA13
M8
GND
GND
B6
GND
GND
E3
AD25
AD25
J12
CAD5
DATA6
M9
SPKROUT
SPKROUT
B7
CC/BE3
REG
E4
AD26
AD26
J13
CRSVD
DATA14
M10
GRST
GRST
B8
CREQ
INPACK
E10
CRSVD
ADDR18
K1
IRDY
IRDY
M11
MFUNC6
MFUNC6
B9
CRST
RESET
E11
CC/BE1
ADDR8
K2
VPPD1
VPPD1
CAD18
ADDR7
E12
CAD16
ADDR17
K3
VCC
TRDY
M12
B10
VCC
TRDY
M13
VCCD1
VCCD1
B11
CFRAME
ADDR23
E13
CAD14
ADDR9
K4
AD12
AD12
N1
C/BE1
C/BE1
B12
CCLK
ADDR16
F1
AD22
AD22
K5
AD10
AD10
N2
AD15
AD15
B13
CDEVSEL
ADDR21
F2
AD23
AD23
K6
AD7
AD7
N3
AD13
AD13
C1
AD30
AD30
F3
AD1
N4
AD31
F4
VCC
IDSEL
AD1
AD31
VCC
IDSEL
K7
C2
K8
MFUNC0
MFUNC0
N5
VCCP
C/BE0
VCCP
C/BE0
C3
CAD30
DATA9
F10
CAD15
IOWR
K9
MFUNC2
MFUNC2
N6
AD5
AD5
C4
CAD27
DATA0
F11
CAD12
ADDR11
K10
CAD2
DATA11
N7
AD3
AD3
C5
CSTSCHG
BVD1
(STSCHG/RI)
F12
GND
GND
K11
GND
GND
N8
AD0
AD0
C6
CVS1
VS1
F13
CAD13
IORD
K12
CAD1
DATA4
N9
MFUNC1
MFUNC1
C7
CAD24
ADDR2
G1
CAD4
DATA12
N10
MFUNC3
MFUNC3
VCC
ADDR6
G2
L1
DEVSEL
DEVSEL
N11
MFUNC5
MFUNC5
C9
VCC
CAD20
VCCP
AD21
K13
C8
VCCP
AD21
G3
AD20
AD20
L2
STOP
STOP
N12
VPPD0
VPPD0
C10
GND
GND
G4
PRST
PRST
L3
PERR
PERR
N13
VCCD0
VCCD0
Table 2–2. CardBus and 16-Bit PC Card Signal Names by PGE Terminal Number
SIGNAL NAME
TERM
TERM.
NO.
CARD
BUS
16-BIT
SIGNAL NAME
TERM
TERM.
NO.
CARD
BUS
16-BIT
SIGNAL NAME
TERM
TERM.
NO.
CARD
BUS
16-BIT
SIGNAL NAME
TERM
TERM.
NO.
CARD
BUS
16-BIT
1
REQ
REQ
37
C/BE1
C/BE1
73
VCCD0
VCCD0
109
CTRDY
ADDR22
2
GNT
GNT
38
AD15
AD15
74
VCCD1
VCCD1
110
CIRDY
ADDR15
3
AD31
AD31
39
AD14
AD14
75
CCD1
CD1
111
CFRAME
ADDR23
4
AD30
AD30
40
AD13
AD13
76
CAD0
DATA3
112
CC/BE2
ADDR12
5
AD29
AD29
41
AD12
AD12
77
CAD2
DATA11
113
CAD17
ADDR24
6
GND
GND
42
GND
GND
78
GND
GND
114
GND
GND
7
AD28
AD28
43
AD11
AD11
79
CAD1
DATA4
115
CAD18
ADDR7
8
AD27
AD27
44
VCCP
AD10
80
CAD4
DATA12
116
CAD19
ADDR25
9
AD26
AD26
45
VCCP
AD10
81
CAD3
DATA5
117
CVS2
VS2
10
AD25
AD25
46
AD9
AD9
82
CAD6
DATA13
118
CAD20
ADDR6
11
AD24
AD24
47
AD8
AD8
83
CAD5
DATA6
119
CRST
RESET
12
C/BE3
C/BE3
48
C/BE0
C/BE0
84
CRSVD
DATA14
120
CAD21
ADDR5
13
IDSEL
IDSEL
49
AD7
AD7
85
CAD7
DATA7
121
CAD22
ADDR4
14
VCC
AD23
VCC
AD23
50
VCC
AD6
87
VCC
CAD8
VCC
DATA15
122
51
VCC
AD6
86
15
123
VCC
CREQ
VCC
INPACK
16
AD22
AD22
52
AD5
AD5
88
CC/BE0
CE1
124
CAD23
ADDR3
17
AD21
AD21
53
AD4
AD4
89
CAD9
ADDR10
125
CC/BE3
REG
18
VCCP
AD20
54
AD3
AD3
90
55
AD2
AD2
91
VCCCB
CAD10
VCCCB
CE2
126
19
VCCP
AD20
127
VCCCB
CAD24
VCCCB
ADDR2
20
PRST
PRST
56
AD1
AD1
92
CAD11
OE
128
CAD25
ADDR1
21
PCLK
PCLK
57
AD0
AD0
93
CAD13
IORD
129
CAD26
ADDR0
22
GND
GND
58
GND
GND
94
GND
GND
130
GND
GND
23
AD19
AD19
59
RI_OUT/
PME
RI_OUT/
PME
95
CAD12
ADDR11
131
CVS1
VS1
24
AD18
AD18
60
MFUNC0
MFUNC0
96
CAD15
IOWR
132
CINT
READY
(IREQ)
25
AD17
AD17
61
MFUNC1
MFUNC1
97
CAD14
ADDR9
133
CSERR
WAIT
26
AD16
AD16
62
SPKROUT
SPKROUT
98
CAD16
ADDR17
134
CAUDIO
BVD2
(SPKR)
27
C/BE2
C/BE2
63
VCCI
VCCI
99
CC/BE1
ADDR8
135
CSTSCHG
BVD1
(STSCHG/RI)
28
FRAME
FRAME
64
MFUNC2
MFUNC2
100
CRSVD
ADDR18
136
CCLKRUN
WP (IOIS16)
29
IRDY
IRDY
65
MFUNC3
MFUNC3
101
CPAR
ADDR13
137
CCD2
CD2
30
VCC
TRDY
VCC
TRDY
66
GRST
GRST
102
67
MFUNC4
MFUNC4
103
VCC
CBLOCK
VCC
ADDR19
138
31
139
VCC
CAD27
VCC
DATA0
32
DEVSEL
DEVSEL
68
MFUNC5
MFUNC5
104
CPERR
ADDR14
140
CAD28
DATA8
33
STOP
STOP
69
MFUNC6
MFUNC6
105
CSTOP
ADDR20
141
CAD29
DATA1
34
PERR
PERR
70
SUSPEND
SUSPEND
106
CGNT
WE
142
CAD30
DATA9
35
SERR
SERR
71
VPPD0
VPPD0
107
CDEVSEL
ADDR21
143
CRSVD
DATA2
36
PAR
PAR
72
VPPD1
VPPD1
108
CCLK
ADDR16
144
CAD31
DATA10
2–5
Table 2–3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number
TERM.
NO.
2–6
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
SIGNAL NAME
CARDBUS
16-BIT
A4
NC
NC
E9
CAD29
DATA1
H17
CAD11
OE
A5
NC
NC
E10
CSTSCHG
BVD1(STSCHG/RI)
H18
CAD10
CE2
A6
NC
NC
E11
GND
GND
H19
A7
NC
NC
E12
CREQ
INPACK
J1
VCCCB
AD31
VCCCB
AD31
A8
CAD30
DATA9
E13
CVS2
VS2
J2
AD30
AD30
A9
CCD2
CD2
E14
CFRAME
ADDR23
J3
AD29
AD29
A10
CINT
READY(IREQ)
E17
CDEVSEL
ADDR21
J5
GND
GND
A11
CAD24
ADDR2
E18
CSTOP
ADDR20
J6
AD28
AD28
A12
VCCCB
VCC
VCCCB
VCC
E19
CBLOCK
ADDR19
J14
CC/BE0
CE1
A13
F1
NC
NC
J15
CAD9
ADDR10
A14
CAD20
ADDR6
F2
NC
NC
J17
CAD8
DATA15
A15
GND
GND
F3
NC
NC
J18
A16
CTRDY
ADDR22
F5
NC
NC
J19
VCC
CAD7
VCC
DATA7
B5
NC
NC
F6
NC
NC
K1
AD27
AD27
B6
NC
NC
F7
NC
NC
K2
AD26
AD26
B7
NC
NC
F8
NC
NC
K3
AD25
AD25
B8
CRSVD
DATA2
F9
CAD28
DATA8
K5
AD24
AD24
B9
VCC
CSERR
VCC
WAIT
F10
CCLKRUN
WP(IOIS16)
K6
C/BE3
C/BE3
B10
F11
CVS1
VS1
K14
CRSVD
DATA14
B11
CAD25
ADDR1
F12
CRST
RESET
K15
CAD5
DATA6
B12
CC/BE3
REG
F13
CC/BE2
ADDR12
K17
CAD6
DATA13
B13
CAD22
ADDR4
F14
CPERR
ADDR14
K18
CAD3
DATA5
B14
CAD19
ADDR25
F15
CGNT
WE
K19
CAD4
DATA12
B15
CAD17
ADDR24
F17
IDSEL
IDSEL
NC
NC
F18
VCC
ADDR18
L1
C5
VCC
CRSVD
L2
C6
NC
NC
F19
CC/BE1
ADDR8
L3
VCC
AD23
VCC
AD23
C7
NC
NC
G1
NC
NC
L5
AD21
AD21
C8
CAD31
DATA10
G2
NC
NC
L6
AD22
AD22
C9
CAD27
DATA0
G3
NC
NC
L14
CAD1
DATA4
C10
CAUDIO
BVD2(SPKR)
G5
NC
NC
L15
GND
GND
C11
CAD26
ADDR0
G6
NC
NC
L17
CAD2
DATA11
C12
CAD23
ADDR3
G14
CAD16
ADDR17
L18
CAD0
DATA3
C13
CAD21
ADDR5
G15
CPAR
ADDR13
L19
CCD1
CD1
C14
CAD18
ADDR7
G17
CAD14
ADDR9
M1
C15
CIRDY
ADDR15
G18
CAD15
IOWR
M2
VCCP
AD20
VCCP
AD20
D1
NC
NC
G19
CAD12
ADDR11
M3
PRST
PRST
D19
CCLK
ADDR16
H1
GNT
GNT
M5
GND
GND
E1
NC
NC
H2
REQ
REQ
M6
PCLK
PCLK
E2
NC
NC
H3
NC
NC
M14
NC
NC
E3
NC
NC
H5
NC
NC
M15
NC
NC
E6
NC
NC
H6
NC
NC
M17
NC
NC
E7
NC
NC
H14
CAD13
IORD
M18
VCCD0
VCCD0
E8
NC
NC
H15
GND
GND
M19
VCCD1
VCCD1
Table 2–3. CardBus and 16-Bit PC Card Signal Names by GHK Terminal Number (Continued)
TERM.
NO.
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
SIGNAL NAME
CARDBUS
16-BIT
TERM.
NO.
N1
AD19
AD19
R1
TRDY
TRDY
U15
N2
AD18
AD18
R2
STOP
STOP
N3
AD17
AD17
R3
SERR
N5
IRDY
IRDY
R6
AD14
SIGNAL NAME
CARDBUS
16-BIT
NC
NC
V5
AD12
AD12
SERR
V6
AD14
V7
VCCP
AD7
VCCP
AD7
N6
AD16
AD16
R7
AD10
AD10
V8
AD4
AD4
N14
NC
NC
R8
AD6
AD6
V9
AD1
AD1
N15
NC
NC
R9
GND
GND
V10
MFUNC1
MFUNC1
N17
NC
NC
R10
GRST
NC
R11
VCCI
MFUNC6
GRST
NC
VCCI
MFUNC6
V11
N18
V12
VPPD0
VPPD0
N19
NC
NC
R12
NC
NC
V13
NC
NC
P1
C/BE2
C/BE2
R13
NC
NC
V14
NC
NC
P2
FRAME
FRAME
R14
NC
NC
V15
NC
NC
P3
VCC
PERR
VCC
PERR
R17
NC
NC
W4
C/BE1
C/BE1
P5
R18
NC
NC
W5
GND
GND
P6
DEVSEL
DEVSEL
R19
NC
NC
W6
AD9
AD9
P7
AD13
AD13
T1
PAR
PAR
W7
P8
AD8
AD8
T19
NC
NC
W8
VCC
AD3
VCC
AD3
P9
RI_OUT/PME
RI_OUT/PME
U5
AD15
AD15
W9
AD2
AD2
P10
MFUNC2
MFUNC2
U6
AD11
AD11
W10
MFUNC0
MFUNC0
P11
MFUNC5
MFUNC5
U7
C/BE0
C/BE0
W11
MFUNC3
MFUNC3
P12
NC
NC
U8
AD5
AD5
W12
SUSPEND
SUSPEND
P13
NC
NC
U9
AD0
AD0
W13
NC
NC
P14
NC
NC
U10
SPKROUT
SPKROUT
W14
NC
NC
P15
NC
NC
U11
MFUNC4
MFUNC4
W15
NC
NC
P17
NC
NC
U12
VPPD1
VPPD1
W16
NC
NC
P18
NC
NC
U13
NC
NC
P19
NC
NC
U14
NC
NC
2–7
Table 2–4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO.
SIGNAL NAME
TERM. NO.
SIGNAL NAME
GGU
PGE
GHK
AD0
N8
57
U9
CAD11
AD1
K7
56
V9
AD2
L7
55
W9
AD3
N7
54
AD4
M7
AD5
N6
AD6
AD7
TERM. NO.
SIGNAL NAME
GGU
PGE
GHK
G10
92
H17
CRST
GGU
PGE
GHK
B9
119
F12
CAD12
F11
95
G19
CAD13
F13
93
H14
CRSVD
A2
143
B8
CRSVD
E10
100
F18
W8
CAD14
E13
97
G17
CRSVD
J13
84
K14
53
V8
CAD15
F10
52
U8
CAD16
E12
96
G18
CSERR
A5
133
B10
98
G14
CSTOP
C12
105
E18
M6
51
R8
CAD17
D10
K6
49
V7
CAD18
B10
113
B15
CSTSCHG
C5
135
E10
115
C14
CTRDY
A13
109
A16
AD8
M5
47
P8
CAD19
AD9
L5
46
W6
CAD20
A10
116
B14
CVS1
C6
131
F11
C9
118
A14
CVS2
D9
117
E13
AD10
K5
45
R7
AD11
M4
43
U6
CAD21
A9
120
C13
DEVSEL
L1
32
P6
CAD22
D8
121
B13
FRAME
J4
28
AD12
K4
41
P2
V5
CAD23
A8
124
C12
GND
D3
6
A15
AD13
N3
AD14
M3
40
P7
CAD24
C7
127
A11
GND
H2
22
E11
39
R6
CAD25
D7
128
B11
GND
L4
42
H15
AD15
AD16
N2
38
U5
CAD26
A6
129
C11
GND
M8
58
J5
J2
26
N6
CAD27
C4
139
C9
GND
K11
78
L15
AD17
J1
25
N3
CAD28
A3
140
F9
GND
F12
94
M5
AD18
H4
24
N2
CAD29
B3
141
E9
GND
C10
114
R9
AD19
H3
23
N1
CAD30
C3
142
A8
GND
B6
130
W5
AD20
G3
19
M2
CAD31
B2
144
C8
GNT
B1
2
H1
AD21
G2
17
L5
CAUDIO
B5
134
C10
GRST
M10
66
V11
AD22
F1
16
L6
C/BE0
N5
48
U7
IDSEL
F4
13
L1
AD23
F2
15
L3
C/BE1
N1
37
W4
IRDY
K1
29
N5
AD24
E2
11
K5
C/BE2
J3
27
P1
MFUNC0
K8
60
W10
AD25
E3
10
K3
C/BE3
E1
12
K6
MFUNC1
N9
61
V10
AD26
E4
9
K2
CBLOCK
D11
103
E19
MFUNC2
K9
64
P10
AD27
D1
8
K1
CC/BE0
H13
88
J14
MFUNC3
N10
65
W11
AD28
D2
7
J6
CC/BE1
E11
99
F19
MFUNC4
L10
67
U11
AD29
D4
5
J3
CC/BE2
A11
112
F13
MFUNC5
N11
68
P11
AD30
C1
4
J2
CC/BE3
B7
125
B12
MFUNC6
M11
69
R11
AD31
C2
3
J1
CCD1
L12
75
L19
PAR
M2
36
T1
CAD0
L13
76
L18
CCD2
A4
137
A9
PCLK
H1
21
M6
CAD1
K12
79
L14
CCLK
B12
108
D19
PERR
L3
34
P5
CAD2
K10
77
L17
CCLKRUN
D5
136
F10
PRST
G4
20
M3
CAD3
J10
81
K18
CDEVSEL
B13
107
E17
REQ
A1
1
H2
CAD4
K13
80
K19
CFRAME
B11
111
E14
RI_OUT/PME
L8
59
P9
CAD5
J12
83
K15
CGNT
C11
106
F15
SERR
M1
35
R3
CAD6
J11
82
K17
CINT
D6
132
A10
SPKROUT
M9
62
U10
CAD7
H10
85
J19
CIRDY
A12
110
C15
STOP
L2
33
R2
CAD8
H12
87
J17
CPAR
D13
101
G15
SUSPEND
L11
70
W12
CAD9
G12
89
J15
CPERR
C13
104
F14
TRDY
K3
31
R1
CAD10
G11
91
H18
CREQ
B8
123
E12
VCC
F3
14
A13
2–8
Table 2–4. CardBus PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK
Terminal Number (Continued)
TERM. NO.
SIGNAL NAME
TERM. NO.
GGU
PGE
GHK
VCC
VCC
K2
30
B9
L6
50
F17
VCC
VCC
H11
86
J18
D12
102
VCC
C8
122
SIGNAL NAME
VCC
VCCCB
GGU
PGE
TERM. NO.
GHK
B4
138
W7
G13
90
A12
A7
126
H19
L2
VCCCB
VCCD0
N13
73
P3
VCCD1
M13
74
SIGNAL NAME
VCCI
VCCP
GGU
PGE
GHK
L9
63
R10
G1
18
M1
V6
N4
44
M18
VCCP
VPPD0
N12
71
V12
M19
VPPD1
M12
72
U12
2–9
Table 2–5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK Terminal Number
TERM. NO.
SIGNAL NAME
TERM. NO.
SIGNAL NAME
GGU
PGE
GHK
AD0
N8
57
U9
ADDR11
AD1
K7
56
V9
ADDR12
A11
AD2
L7
55
W9
ADDR13
D13
AD3
N7
54
W8
ADDR14
C13
AD4
M7
53
V8
ADDR15
AD5
N6
52
U8
ADDR16
AD6
M6
51
R8
ADDR17
AD7
K6
49
V7
ADDR18
AD8
M5
47
P8
AD9
L5
46
W6
AD10
K5
45
AD11
M4
43
AD12
K4
41
AD13
N3
AD14
M3
AD15
AD16
TERM. NO.
SIGNAL NAME
GGU
PGE
GHK
GGU
PGE
GHK
F11
95
G19
GND
D3
6
A15
112
F13
GND
H2
22
E11
101
G15
GND
L4
42
H15
104
F14
GND
M8
58
J5
A12
110
C15
GND
K11
78
L15
B12
108
D19
GND
F12
94
M5
E12
98
G14
GND
C10
114
R9
E10
100
F18
GND
B6
130
W5
ADDR19
D11
103
E19
GNT
ADDR20
C12
105
E18
GRST
R7
ADDR21
B13
107
E17
IDSEL
F4
13
L1
U6
ADDR22
A13
109
A16
INPACK
B8
123
E12
V5
ADDR23
B11
111
E14
IORD
F13
93
H14
40
P7
ADDR24
D10
113
B15
IOWR
F10
96
G18
39
R6
ADDR25
A10
116
B14
IRDY
K1
29
N5
N2
38
U5
BVD1(STSCHG/RI)
C5
135
E10
MFUNC0
K8
60
W10
J2
26
N6
BVD2(SPKR)
B5
134
C10
MFUNC1
N9
61
V10
AD17
J1
25
N3
C/BE0
N5
48
U7
MFUNC2
K9
64
P10
AD18
H4
24
N2
C/BE1
N1
37
W4
MFUNC3
N10
65
W11
AD19
H3
23
N1
C/BE2
J3
27
P1
MFUNC4
L10
67
U11
AD20
G3
19
M2
C/BE3
E1
12
K6
MFUNC5
N11
68
P11
AD21
G2
17
L5
CD1
L12
75
L19
MFUNC6
M11
69
R11
AD22
F1
16
L6
CD2
A4
137
A9
OE
G10
92
H17
AD23
F2
15
L3
CE1
H13
88
J14
PAR
M2
36
T1
AD24
E2
11
K5
CE2
G11
91
H18
PCLK
H1
21
M6
AD25
E3
10
K3
DATA0
C4
139
C9
PERR
L3
34
P5
AD26
E4
9
K2
DATA1
B3
141
E9
PRST
G4
20
M3
AD27
D1
8
K1
DATA2
A2
143
B8
READY(IREQ)
D6
132
A10
AD28
D2
7
J6
DATA3
L13
76
L18
REG
B7
125
B12
AD29
D4
5
J3
DATA4
K12
79
L14
REQ
A1
1
H2
AD30
C1
4
J2
DATA5
J10
81
K18
RESET
B9
119
F12
AD31
C2
3
J1
DATA6
J12
83
K15
RI_OUT/PME
L8
59
P9
ADDR0
A6
129
C11
DATA7
H10
85
J19
SERR
M1
35
R3
ADDR1
D7
128
B11
DATA8
A3
140
F9
SPKROUT
M9
62
U10
ADDR2
C7
127
A11
DATA9
C3
142
A8
STOP
L2
33
R2
ADDR3
A8
124
C12
DATA10
B2
144
C8
SUSPEND
L11
70
W12
ADDR4
D8
121
B13
DATA11
K10
77
L17
TRDY
K3
31
R1
ADDR5
A9
120
C13
DATA12
K13
80
K19
14
A13
C9
118
A14
DATA13
J11
82
K17
VCC
VCC
F3
ADDR6
K2
30
B9
ADDR7
B10
115
C14
DATA14
J13
84
K14
L6
50
F17
ADDR8
E11
99
F19
DATA15
H12
87
J17
ADDR9
E13
97
G17
DEVSEL
L1
32
P6
ADDR10
G12
89
J15
FRAME
J4
28
P2
2–10
VCC
VCC
VCC
VCC
B1
2
H1
M10
66
V11
H11
86
J18
D12
102
L2
C8
122
P3
Table 2–5. 16-Bit PC Card Signal Names Sorted Alphabetically to GGU/PGE/GHK
Terminal Number (Continued)
TERM. NO.
SIGNAL NAME
VCC
VCCCB
GGU
PGE
TERM. NO.
GHK
B4
138
W7
G13
90
A12
VCCCB
VCCD0
A7
126
H19
N13
73
VCCD1
M13
74
SIGNAL NAME
VCCI
VCCP
TERM. NO.
GGU
PGE
GHK
SIGNAL NAME
GGU
PGE
GHK
L9
63
R10
VS1
C6
131
F11
G1
18
M1
VS2
D9
117
E13
V6
WAIT
A5
133
B10
N4
44
M18
VCCP
VPPD0
N12
71
V12
WE
C11
106
F15
M19
VPPD1
M12
72
U12
WP(IOIS16)
D5
136
F10
2–11
The terminals are grouped in tables by functionality (see Table 2–6 through Table 2–16), such as PCI system function
and power-supply function. The terminal numbers are also listed for convenient reference.
Table 2–6. Power Supply Terminals
TERMINAL
NUMBER
NAME
DESCRIPTION
GGU
PGE
GHK
GND
B6, C10,
D3, F12,
H2, K11,
L4, M8
6, 22, 42,
58, 78,
94, 114,
130
A15, E11,
H15, J5,
L15, M5,
R9, W5
Device ground terminals
VCC
B4, C8,
D12, F3,
H11, K2,
L6
14, 30,
50, 86,
102, 122,
138
A13, B9,
F17, J18,
L2, P3,
W7
Power supply terminal for core logic (3.3 V)
VCCCB
A7, G13
90, 126
A12, H19
Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V.
VCCI
L9
63
R10
VCCP
G1, N4
18, 44
M1, V6
Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V
Clamp voltage for PCI signaling, 5 V or 3.3 V
Table 2–7. PC Card Power Switch Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
GGU
PGE
GHK
VCCD0
VCCD1
N13
M13
73
74
M18
M19
O
Logic controls to the TPS2211 PC Card power interface switch to control AVCC.
VPPD0
VPPD1
N12
M12
71
72
V12
U12
O
Logic controls to the TPS2211 PC Card power interface switch to control AVPP.
Table 2–8. PCI System Terminals
TERMINAL
NAME
GRST
NUMBER
GGU
M10
PGE
66
I/O
DESCRIPTION
GHK
V11
I
Global reset. When the global reset is asserted, the GRST signal causes the PCI1410 to place all
output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the
device is completely in its default state. For systems that require wake-up from D3, GRST will
normally be asserted only during initial boot. PRST should be used following initial boot so that PME
context is retained when transitioning from D3 to D0. For systems that do not require wake-up from
D3, GRST should be tied to PRST.
When the SUSPEND mode is enabled, the device is protected from the GRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
PCLK
PRST
H1
G4
21
20
M6
M3
I
I
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled
at the rising edge of PCLK.
PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1410 to place all output buffers
in a high-impedance state and reset internal registers. When PRST is asserted, the device is
completely nonfunctional. After PRST is deasserted, the PCI1410 is in a default state.
When the SUSPEND mode is enabled, the device is protected from the PRST, and the internal
registers are preserved. All outputs are placed in a high-impedance state.
2–12
Table 2–9. PCI Address and Data Terminals
TERMINAL
NUMBER
NAME
GGU
PGE
GHK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
J2
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
K7
N8
3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57
J1
J2
J3
J6
K1
K2
K3
K5
L3
L6
L5
M2
N1
N2
N3
N6
U5
R6
P7
V5
U6
R7
W6
P8
V7
R8
U8
V8
W8
W9
V9
U9
C/BE3
C/BE2
C/BE1
C/BE0
E1
J3
N1
N5
12
27
37
48
K6
P1
W4
U7
PAR
M2
36
T1
I/O
DESCRIPTION
I/O
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, AD31–AD0 contain a 32-bit
address or other destination information. During the data phase, AD31–AD0 contain data.
I/O
PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, C/BE3–C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which
byte paths of the full 32-bit data bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0),
C/BE1 applies to byte 1 (AD15–AD8), C/BE2 applies to byte 2 (AD23–AD16), and C/BE3 applies
to byte 3 (AD31–AD24).
I/O
PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates even parity across the
AD31–AD0 and C/BE3–C/BE0 buses. As an initiator during PCI cycles, the PCI1410 outputs this
parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is
compared to the initiator parity indicator. A compare error results in the assertion of a parity error
(PERR).
2–13
Table 2–10. PCI Interface Control Terminals
TERMINAL
NUMBER
I/O
DESCRIPTION
P6
I/O
PCI device select. The PCI1410 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the bus, the PCI1410 monitors DEVSEL until a target responds. If no target responds
before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort.
28
P2
I/O
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that
a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
is deasserted, the PCI bus transaction is in the final data phase.
B1
2
H1
I
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after
the current data transaction has completed. GNT may or may not follow a PCI bus request, depending
on the PCI bus parking algorithm.
IDSEL
F4
13
L1
I
Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL
can be connected to one of the upper 24 PCI address lines on the PCI bus.
IRDY
K1
29
N5
I/O
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase
of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY and TRDY
are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted.
PERR
L3
34
P5
I/O
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not
match PAR when PERR is enabled through bit 6 of the command register (offset 04h, see
Section 4.4).
REQ
A1
1
H2
O
PCI bus request. REQ is asserted by the PCI1410 to request access to the PCI bus as an initiator.
NAME
GGU
PGE
GHK
DEVSEL
L1
32
FRAME
J4
GNT
2–14
SERR
M1
35
R3
O
PCI system error. SERR is an output that is pulsed from the PCI1410 when enabled through bit 8 of
the command register (offset 04h, see Section 4.4) indicating a system error has occurred. The
PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the
command register, this signal also pulses, indicating that an address parity error has occurred on a
CardBus interface.
STOP
L2
33
R2
I/O
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI
bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that
do not support burst data transfers.
TRDY
K3
31
R1
I/O
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY and
TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted.
Table 2–11. Multifunction and Miscellaneous Terminals
TERMINAL
NUMBER
NAME
MFUNC0
GGU
PGE
GHK
K8
60
W10
I/O
DESCRIPTION
I/O
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0,
GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a
parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED
output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30,
Multifunction Routing Register, for configuration details.
MFUNC1
N9
61
V10
I/O
MFUNC2
K9
64
P10
I/O
Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2,
socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a
parallel IRQ. See Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC3
N10
65
W11
I/O
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt
signal IRQSER. See Section 4.30, Multifunction Routing Register, for configuration details.
Serial data (SDA). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC1 terminal
provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity
LED output, ZV switching outputs, CardBus audio PWM, GPE, RI_OUT, or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC4
L10
67
U11
I/O
MFUNC5
N11
68
P11
I/O
Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4,
socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE, or a parallel IRQ.
See Section 4.30, Multifunction Routing Register, for configuration details.
MFUNC6
M11
69
R11
I/O
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.
RI_OUT/PME
L8
59
P9
O
Ring indicate out and power management event output. Terminal provides an output for
ring-indicate or PME signals.
SPKROUT
M9
62
U10
O
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO
through the PCI1410 from the PC Card interface. SPKROUT is driven as the exclusive-OR
combination of card SPKR//CAUDIO inputs.
SUSPEND
L11
70
W12
I
Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST
signal is asserted. See Section 3.8.4, Suspend Mode, for details.
Serial clock (SCL). When VCCD0 and VCCD1 are high after a PCI reset, the MFUNC4 terminal
provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
2–15
Table 2–12. 16-Bit PC Card Address and Data Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
GGU
PGE
GHK
ADDR25
ADDR24
ADDR23
ADDR22
ADDR21
ADDR20
ADDR19
ADDR18
ADDR17
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
A10
D10
B11
A13
B13
C12
D11
E10
E12
B12
A12
C13
D13
A11
F11
G12
E13
E11
B10
C9
A9
D8
A8
C7
D7
A6
116
113
111
109
107
105
103
100
98
108
110
104
101
112
95
89
97
99
115
118
120
121
124
127
128
129
B14
B15
E14
A16
E17
E18
E19
F18
G14
D19
C15
F14
G15
F13
G19
J15
G17
F19
C14
A14
C13
B13
C12
A11
B11
C11
O
PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit.
DATA15
DATA14
DATA13
DATA12
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
H12
J13
J11
K13
K10
B2
C3
A3
H10
J12
J10
K12
L13
A2
B3
C4
87
84
82
80
77
144
142
140
85
83
81
79
76
143
141
139
J17
K14
K17
K19
L17
C8
A8
F9
J19
K15
K18
L14
L18
B8
E9
C9
I/O
PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.
2–16
Table 2–13. 16-Bit PC Card Interface Control Terminals
TERMINAL
NUMBER
NAME
BVD1
(STSCHG/RI)
GGU
C5
PGE
135
I/O
DESCRIPTION
GHK
E10
I
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include
batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2
is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low,
the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits.
See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
Status change. STSCHG is used to alert the system to a change in the READY, write protect,
or battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.
BVD2
(SPKR)
B5
134
C10
I
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include
batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a
memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2
is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low,
the battery is no longer serviceable and the data in the memory PC Card is lost. See
Section 5.6, ExCA Card Status-Change-Interrupt Configuration Register, for enable bits.
See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
Speaker. SPKR is an optional binary audio signal available only when the card and socket
have been configured for the 16-bit I/O interface. The audio signals from cards A and B are
combined by the PCI1410 and are output on SPKROUT.
DMA request. BVD2 can be used as the DMA request signal during DMA operations to a
16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a
DMA operation.
CD1
CD2
L12
A4
75
137
L19
A9
I
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the
PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are pulled low. For signal
status, see Section 5.2, ExCA Interface Status Register.
CE1
CE2
H13
G11
88
91
J14
H18
O
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address
bytes. CE1 enables even-numbered address bytes, and CE2 enables odd-numbered
address bytes.
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read
cycle at the current address.
INPACK
B8
123
E12
I
DMA request. INPACK can be used as the DMA request signal during DMA operations from
a 16-bit PC Card that supports DMA. If it is used as a strobe, then the PC Card asserts this
signal to indicate a request for a DMA operation.
I/O read. IORD is asserted by the PCI1410 to enable 16-bit I/O PC Card data output during
host I/O read cycles.
IORD
F13
93
H14
O
DMA write. IORD is used as the DMA write strobe during DMA operations from a 16-bit PC
Card that supports DMA. The PCI1410 asserts IORD during DMA transfers from the PC
Card to host memory.
I/O write. IOWR is driven low by the PCI1410 to strobe write data into 16-bit I/O PC Cards
during host I/O write cycles.
IOWR
F10
96
G18
O
DMA read. IOWR is used as the DMA write strobe during DMA operations from a 16-bit PC
Card that supports DMA. The PCI1410 asserts IOWR during transfers from host memory
to the PC Card.
Output enable. OE is driven low by the PCI1410 to enable 16-bit memory PC Card data
output during host memory read cycles.
OE
G10
92
H17
O
DMA terminal count. OE is used as terminal count (TC) during DMA operations to a 16-bit
PC Card that supports DMA. The PCI1410 asserts OE to indicate TC for a DMA write
operation.
2–17
Table 2–13. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NAME
READY
(IREQ)
NUMBER
GGU
D6
PGE
132
I/O
DESCRIPTION
I
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket
are configured for the memory-only interface. READY is driven low by the 16-bit memory PC
Cards to indicate that the memory card circuits are busy processing a previous write command.
READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer
command.
GHK
A10
Interrupt request. IREQ is asserted by a 16-bit I/O PC Card to indicate to the host that a device
on the 16-bit I/O PC Card requires service by the host software. IREQ is high (deasserted) when
no interrupt is requested.
REG
B7
125
B12
O
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE or WE active) and to the I/O space (IORD or
IOWR active). Attribute memory is a separately accessed section of card memory and is generally
used to record card capacity and other configuration and attribute information.
DMA acknowledge. REG is used as a DMA acknowledge (DACK) during DMA operations to a
16-bit PC Card that supports DMA. The PCI1410 asserts REG to indicate a DMA operation. REG
is used in conjunction with the DMA read (IOWR) or DMA write (IORD) strobes to transfer data.
RESET
B9
119
F12
O
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
VS1
VS2
C6
D9
131
117
F11
E13
I/O
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
WAIT
A5
133
B10
I
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or
I/O cycle in progress.
WE
C11
106
F15
O
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also
used for memory PC Cards that employ programmable memory technologies.
DMA terminal count. WE is used as TC during DMA operations to a 16-bit PC Card that supports
DMA. The PCI1410 asserts WE to indicate TC for a DMA read operation.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect
switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16)
function.
WP
(IOIS16)
D5
136
F10
I
I/O is 16 bits. IOIS16 applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card
when the address on the bus corresponds to an address to which the 16-bit PC Card responds,
and the I/O port that is addressed is capable of 16-bit accesses.
DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit
PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA
operation.
Table 2–14. CardBus PC Card Interface System Terminals
TERMINAL
NUMBER
NAME
GGU
PGE
I/O
DESCRIPTION
GHK
CCLK
B12
108
D19
O
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface.
All signals except CRST, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and
CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the
rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped
in the low state or slowed down for power savings.
CCLKRUN
D5
136
F10
I/O
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the PCI1410 to indicate that the CCLK frequency is going to be decreased.
O
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a
known state. When CRST is asserted, all CardBus PC Card signals are placed in a
high-impedance state, and the PCI1410 drives these signals to a valid logic level. Assertion can
be asynchronous to CCLK, but deassertion must be synchronous to CCLK.
CRST
2–18
B9
119
F12
Table 2–15. CardBus PC Card Address and Data Terminals
TERMINAL
NUMBER
NAME
GGU
PGE
GHK
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76
C8
A8
E9
F9
C9
C11
B11
A11
C12
B13
C13
A14
B14
C14
B15
G14
G18
G17
H14
G19
H17
H18
J15
J17
J19
K17
K15
K19
K18
L17
L14
L18
CC/BE3
CC/BE2
CC/BE1
CC/BE0
B7
A11
E11
H13
125
112
99
88
B12
F13
F19
J14
CPAR
D13
101
G15
I/O
DESCRIPTION
I/O
CardBus address and data. These signals make up the multiplexed CardBus address and data
bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0
contain a 32-bit address. During the data phase of a CardBus cycle, CAD31–CAD0 contain data.
CAD31 is the most significant bit.
I/O
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same
CardBus terminals. During the address phase of a CardBus cycle, CC/BE3–CC/BE0 define the
bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables
determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to
byte 0 (CAD7–CAD0), CC/BE1 applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2
(CAD23–CAD16), and CC/BE3 applies to byte 3 (CAD31–CAD24).
I/O
CardBus parity. In all CardBus read and write cycles, the PCI1410 calculates even parity across
the CAD and CC/BE buses. As an initiator during CardBus cycles, the PCI1410 outputs CPAR
with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to
the initiator’s parity indicator; a compare error results in a parity error assertion.
2–19
Table 2–16. CardBus PC Card Interface Control Terminals
TERMINAL
NUMBER
NAME
I/O
DESCRIPTION
C10
I
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The
PCI1410 supports the binary audio mode and outputs a binary signal from the card to
SPKROUT.
103
E19
I/O
75
137
L19
A9
I
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1
and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
I/O
CardBus device select. The PCI1410 asserts CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL until a target
responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle
with an initiator abort.
GGU
PGE
GHK
CAUDIO
B5
134
CBLOCK
D11
CCD1
CCD2
L12
A4
CDEVSEL
B13
107
E17
CardBus lock. CBLOCK is used to gain exclusive access to a target.
CFRAME
B11
111
E14
I/O
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is
asserted to indicate that a bus transaction is beginning, and data transfers continue while this
signal is asserted. When CFRAME is deasserted, the CardBus bus transaction is in the final
data phase.
CGNT
C11
106
F15
O
CardBus bus grant. CGNT is driven by the PCI1410 to grant a CardBus PC Card access to the
CardBus bus after the current data transaction has been completed.
CINT
D6
132
A10
I
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing
from the host.
CIRDY
A12
110
C15
I/O
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK when
both CIRDY and CTRDY are asserted. Until CIRDY and CTRDY are both sampled asserted,
wait states are inserted.
CPERR
C13
104
F14
I/O
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during
special cycles. It is driven low by a target two clocks following that data when a parity error is
detected.
CREQ
B8
123
E12
I
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the
CardBus bus as an initiator.
CSERR
A5
133
B10
I
CardBus system error. CSERR reports address parity errors and other system errors that could
lead to catastrophic results. CSERR is driven by the card synchronous to CCLK. The PCI1410
can report CSERR to the system by assertion of SERR on the PCI interface.
CSTOP
C12
105
E18
I/O
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current
CardBus transaction. CSTOP is used for target disconnects, and is commonly asserted by
target devices that do not support burst data transfers.
CSTSCHG
C5
135
E10
I
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is
used as a wake-up mechanism.
CTRDY
A13
109
A16
I/O
CardBus target ready. CTRDY indicates the ability of the CardBus target ability to complete the
current data phase of the transaction. A data phase is completed on a rising edge of CCLK,
when both CIRDY and CTRDY are asserted; until this time, wait states are inserted.
CVS1
CVS2
C6
D9
131
117
F11
E13
I/O
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in
conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine
the operating voltage and card type.
2–20
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI1410. Figure 3–1 shows a simplified block diagram of the PCI1410.
The PCI interface includes all address/data and control signals for PCI protocol. The interrupt interface includes
terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling. Miscellaneous system interface
terminals include multifunction terminals: SUSPEND, RI_OUT/PME (power management control signal), and
SPKROUT.
PCI Bus
INTA
Interrupt
Controller
Activity LED
TPS2211
Power
Switch
IRQSER
PCI1410
4
PCI950
IRQSER
Deserializer
IRQ2–15
3
PC Card
Socket
Zoomed Video
68
23
19
VGA
Controller
PCI930
ZV Switch
Zoomed Video
External ZV Port
4
Audio
Subsystem
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode 23 terminals are used for routing the ZV signals
to the VGA controller and audio subsystem.
Figure 3–1. PCI1410 Simplified Block Diagram
3.1 Power Supply Sequencing
The PCI1410 contains 3.3-V I/O buffers with 5-V tolerance requiring a core power supply and clamp voltages. The
core power supply is always 3.3 V. The clamp voltages can be either 3.3 V or 5 V, depending on the interface. The
following power-up and power-down sequences are recommended.
The power-up sequence is:
1. Apply 3.3-V power to the core.
2. Assert GRST to the device to disable the outputs during power up. Output drivers must be powered up in
the high-impedance state to prevent high current levels through the clamp diodes to the 5-V supply.
3. Apply the clamp voltage.
The power-down sequence is:
1. Use GRST to switch outputs to a high-impedance state.
2. Remove the clamp voltage.
3. Remove the 3.3-V power from the core.
3–1
3.2 I/O Characteristics
Figure 3–2 shows a 3-state bidirectional buffer. Section 8.2, Recommended Operating Conditions, provides the
electrical characteristics of the inputs and outputs.
NOTE:The PCI1410 meets the ac specifications of the 1997 PC Card Standard and PCI Local
Bus Specification.
VCCP
Tied for Open Drain
OE
Pad
Figure 3–2. 3-State Bidirectional Buffer
NOTE: Unused pins (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the PCI1410 will be interfaced with: 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example, PCI
signaling can be either 3.3 V or 5 V, and the PCI1410 must reliably accommodate both voltage levels. This is
accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage applied. If a system
designer desires a 5-V PCI bus, then VCCP can be connected to a 5-V power supply.
The PCI1410 requires three separate clamping voltages because it supports a wide range of features. The three
voltages are listed and defined in Section 8.2, Recommended Operating Conditions.
3.4 Peripheral Component Interconnect (PCI) Interface
The PCI1410 is fully compliant with the PCI Local Bus Specification. The PCI1410 provides all required signals for
PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by connecting the VCCP
terminals to the desired voltage level. In addition to the mandatory PCI signals, the PCI1410 provides the optional
interrupt signal INTA.
3.4.1
PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is provided on
the PCI1410 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal via
the multifunction routing register. See Section 4.30, Multifunction Routing Register, for details. Note that the use of
LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is asserted,
nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a transaction on
the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own protocol. It is possible
for different initiators to use the PCI bus while a single master retains ownership of LOCK. Note that the CardBus
signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into several
transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock is defined by
PCI to be 16 bytes, aligned. The LOCK protocol defined by the PCI Local Bus Specification allows a resource lock
without interfering with nonexclusive real-time data transfer, such as video.
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this scenario,
the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is asserted. A complete
3–2
bus lock may have a significant impact on the performance of the video. The arbiter that supports complete bus lock
must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation
is in progress.
The PCI1410 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for PCI-to-CardBus
bridges. This includes disabling write posting while a locked operation is in progress, which can solve a potential
deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur if a CardBus target
supports delayed transactions and blocks access to the target until it completes a delayed read. This target
characteristic is prohibited by the PCI Local Bus Specification, and the issue is resolved by the PCI master using
LOCK.
3.4.2
Loading Subsystem Identification
The subsystem vendor ID register (see Section 4.26) and subsystem ID register (see Section 4.27) make up a
doubleword of PCI configuration space located at offset 40h for functions 0 and 1. This doubleword register is used
for system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a PC 99 requirement.
The PCI1410 offers two mechanisms to load a read-only value into the subsystem registers. The first mechanism
relies upon the system BIOS providing the subsystem ID value. The default access mode to the subsystem registers
is read-only, but can be made read/write by setting bit 5 (SUBSYSRW) in the system control register (see
Section 4.29) at PCI offset 80h. Once this bit is set, the BIOS can write a subsystem identification value into the
registers at PCI offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register and
subsystem ID register are limited to read-only access. This approach saves the added cost of implementing the serial
electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI1410 loads the data from the serial EEPROM
after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI1410 core,
including the serial bus state machine (see Section 3.8.4, Suspend Mode, for details on using SUSPEND).
The PCI1410 provides a two-line serial bus host controller that can interface to a serial EEPROM. See Section 3.6,
Serial Bus Interface, for details on the two-wire serial bus controller and applications.
3.5 PC Card Applications
This section describes the PC Card interfaces of the PCI1410:
•
•
•
•
•
•
•
•
3.5.1
Card insertion/removal and recognition
P2C power-switch interface
Zoomed video support
Speaker and audio applications
LED socket activity indicators
PC Card-16 DMA support
PC Card controller programming model
CardBus socket registers
PC Card Insertion/Removal and Recognition
The 1997 PC Card Standard addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card detect and voltage sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface. The encoding scheme is defined in the 1997 PC Card
Standard and in Table 3–1.
3–3
Table 3–1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2
CD1//CCD1
VS2//CVS2
VS1//CVS1
KEY
INTERFACE
VOLTAGE
Ground
Ground
Open
Open
5V
16-bit PC Card
5V
Ground
Ground
Open
Ground
5V
16-bit PC Card
5 V and 3.3 V
Ground
Ground
Ground
Ground
5V
16-bit PC Card
5 V, 3.3 V, and X.X V
Ground
Ground
Open
Ground
LV
16-bit PC Card
3.3 V
Ground
Connect to CVS1
Open
Connect to CCD1
LV
CardBus PC Card
3.3 V
Ground
Ground
Ground
Ground
LV
16-bit PC Card
3.3 V and X.X V
Connect to CVS2
Ground
Connect to CCD2
Ground
LV
CardBus PC Card
3.3 V and X.X V
Connect to CVS1
Ground
Ground
Connect to CCD2
LV
CardBus PC Card
3.3 V, X.X V, and Y.Y V
Ground
Ground
Ground
Open
LV
16-bit PC Card
Y.Y V
Connect to CVS2
Ground
Connect to CCD2
Open
LV
CardBus PC Card
Y.Y V
Ground
Connect to CVS2
Connect to CCD1
Open
LV
CardBus PC Card
X.X V and Y.Y V
Connect to CVS1
Ground
Open
Connect to CCD2
LV
CardBus PC Card
Y.Y V
Ground
Connect to CVS1
Ground
Connect to CCD1
Reserved
Ground
Connect to CVS2
Connect to CCD1
Ground
Reserved
3.5.2
P2C Power-Switch Interface (TPS2211)
The PCI1410 provides a P2C (PCMCIA peripheral control) interface for control of the PC Card power switch. The
VCCD and VPPD terminals are used with the TI TPS2211 single slot PC Card power interface switch to provide power
switch support. Figure 3–3 shows terminal assignments for the TPS2211. Figure 3–4 illustrates a typical application,
where the PCI1410 represents the PC Card controller.
VCCD0
VCCD1
3.3V
3.3V
5V
5V
GND
OC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN
VPPD0
VPPD1
AVCC
AVCC
AVCC
AVPP
12V
Figure 3–3. TPS2211 Terminal Assignments
The PCI1410 also includes support for the Maxim 1602 single-channel CardBus and PCMCIA power-switching
network. Application of this power switch would be similar to the TPS2211.
Maxim is a trademark of Maxim Integrated Products, Inc.
3–4
Power Supply
12 V
5V
3.3 V
12V
5V
3.3V
TPS2211
AVPP
SHDN
SHDN
Supervisor
VPP1
VPP2
VCC
VCC
AVCC
VCCD0
VCCD1
VPPD0
VPPD1
PCI1410
(PC Card
Controller)
PC Card
OC
Figure 3–4. TPS2211 Typical Application
3.5.3
Zoomed Video Support
The PCI1410 allows for the implementation of zoomed video for PC Cards. Zoomed video is supported by setting
bit 6 (ZVENABLE) in the card control register (see Section 4.32) on a per-socket function basis. Setting this bit puts
PC Card 16 address lines ADDR25–ADDR4 of the PC Card interface in the high-impedance state. These lines can
then transfer video and audio data directly to the appropriate controller. Card address lines ADDR3–ADDR0 can still
access PC Card CIS registers for PC Card configuration. Figure 3–5 illustrates a PCI1410 ZV implementation.
Speakers
CRT
Motherboard
PCI Bus
VGA
Controller
Audio
Codec
Zoomed
Video Port
PCM
Audio
Input
19
PCI1410
4
PC Card
19
PC Card
Interface
Video
Audio
4
Figure 3–5. Zoomed Video Implementation Using PCI1410
Not shown in Figure 3–5 is the multiplexing scheme used to route a socket ZV source or an external ZV source to
the graphics controller. A typical external source might be provided from a high-speed serial bus like IEEE 1394. The
PCI1410 provides ZVSTAT and ZVSEL0 signals on the multifunction terminals to switch external bus drivers.
Figure 3–6 shows an implementation for switching between two ZV streams using external logic.
3–5
PCI1410
ZVSTAT
ZVSEL0
Figure 3–6. Zoomed Video Switching Application
Figure 3–6 illustrates an implementation using standard three-state bus drivers with active-low output enables.
ZVSEL0 is an active-low output indicating that the socket ZV mode is enabled. ZVSTAT is an active-high output
indicating that the PCI1410 socket is enabled for ZV mode. The implementation shown in Figure 3–6 can be used
if PC Card ZV is prioritized over other sources.
3.5.4
Ultra Zoomed Video
Ultra zoomed video is an enhancement to the PCI1410 DMA engine and is intended to improve the 16-bit bandwidth
for MPEG I and MPEG II decoder PC Cards. This enhancement allows the PCI1410 to fetch 32 bits of data from
memory versus the 11XX/12XX 16-bit fetch capability. This enhancement allows a higher sustained throughput to
the 16-bit PC Card because the PCI1410 prefetches an extra 16 bits (32 bits total) during each PCI read transaction.
If the PCI bus becomes busy, then the PCI1410 has an extra 16 bits of data to perform back-to-back 16-bit
transactions to the PC Card before having to fetch more data. This feature is built into the DMA engine and software
is not required to enable this enhancement.
NOTE: The 11XX and 12XX series CardBus controllers have enough 16-bit bandwidth to
support MPEG II PC Card decoders, but it was decided to improve the bandwidth even more
in the 14XX series CardBus controllers.
3.5.5
Internal Ring Oscillator
The internal ring oscillator provides an internal clock option for the PCI1410 so that the PCI clock is not required in
order for the PCI1410 to power down a socket or interrogate a PC Card. This internal oscillator operates nominally
at 16 kHz and can be enabled by setting bit 27 (P2CCLK) of the system control register (offset 80h, see Section 4.29)
to 1. This function is disabled by default.
3–6
3.5.6
Integrated Pullup Resistors For PC Card Interface
The 1997 PC Card Standard requires pullup resistors on various terminals to support both CardBus and 16-bit card
configurations. Unlike the PCI1210/1211 which required external pullup resistors, the PCI1410 has integrated all of
these pullup resistors.
PIN NUMBER
SIGNAL NAME
ADDR14/CPERR
3.5.7
GGU
PGE
GHK
C13
104
F14
READY/CINT
D6
132
A10
ADDR15/CIRDY
A12
110
C15
CD1/CCD1
L12
75
L19
VS1/CVS1
C6
131
F11
ADDR19/CBLOCK
D11
103
E19
ADDR20/CSTOP
C12
105
E18
ADDR21/CDEVSEL
B13
107
E17
ADDR22/CTRDY
A13
109
A16
VS2/CVS2
D9
117
E13
RESET/CRST
B9
119
F12
WAIT/CSERR
A5
133
B10
INPACK/CREQ
B8
123
E12
BVD2(SPKR)/CAUDIO
B5
134
C10
BVD1(STSCHG)/CSTSCHG
C5
135
E10
CD2/CCD2
A4
137
A9
SPKROUT and CAUDPWM Usage
SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured for
I/O mode, the BVD2 terminal becomes SPKR. This terminal is also used in CardBus binary audio applications, and
is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1410. The CardBus CAUDIO signal
also can pass a single-amplitude binary waveform. The binary audio signal from the PC Card socket is used in the
PCI1410 to produce SPKROUT. This output is enabled by bit 1 (SPKROUTEN) in the card control register (see
Section 4.32).
Older controllers support CAUDIO in binary or PWM mode but use the same terminal (SPKROUT). Some audio chips
may not support both modes on one terminal and may have a separate terminal for binary and PWM. The PCI1410
implementation includes a signal for PWM, CAUDPWM, which can be routed to an MFUNC terminal. Bit 2
(AUD2MUX) located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to
CAUDPWM. See Section 4.30, Multifunction Routing Register, for details on configuring the MFUNC terminals.
Figure 3–7 illustrates a sample application using SPKROUT and CAUDPWM.
3–7
System
Core Logic
BINARY_SPKR
SPKROUT
Speaker
Subsystem
PCI1410
PWM_SPKR
CAUDPWM
Figure 3–7. Sample Application of SPKROUT and CAUDPWM
3.5.8
LED Socket Activity Indicators
The socket activity LEDs are provided to indicate when a PC Card is being accessed. The LED_SKT signal can be
routed to the multifunction terminals. When configured for LED output, this terminal outputs an active high signal to
indicate socket activity. See Section 4.30, Multifunction Routing Register, for details on configuring the multifunction
terminals.
The LED signal is active high and is driven in pulses of 64-ms duration. When the LED is not being driven high, it is
driven to a low state. Either of the two circuits shown in Figure 3–8 can be implemented to provide LED signaling and
it is left for the board designer to implement the circuit that best fits the application.
The LED activity signals are valid when a card is inserted, powered, and not in reset. For PC Card-16, the LED activity
signal is pulsed when READY/IREQ is low. For CardBus cards, the LED activity signal is pulsed if CFRAME, CIRDY,
or CREQ is active.
Current Limiting
R ≈ 500 Ω
LED
PCI1410
ApplicationSpecific Delay
Current Limiting
R ≈ 500 Ω
PCI1410
LED
Figure 3–8. Two Sample LED Circuits
As indicated, the LED signals are driven for a period of 64 ms by a counter circuit. To avoid the possibility of the LED
appearing to be stuck when the PCI clock is stopped, the LED signaling is cut off when the SUSPEND signal is
asserted, when the PCI clock is to be stopped during the clock run protocol, or when in the D2 or D1 power state.
If any additional socket activity occurs during this counter cycle, then the counter is reset and the LED signal remains
driven. If socket activity is frequent (at least once every 64 ms), then the LED signal remains driven.
3.5.9
PC Card-16 Distributed DMA Support
The PCI1410 supports a distributed DMA slave engine for 16-bit PC Card DMA support. The distributed DMA (DDMA)
slave register set provides the programmability necessary for the slave DDMA engine. Table 3–2 provides the DDMA
register configuration.
3–8
Two socket-function-dependent PCI configuration header registers that are critical for DDMA are the socket DMA
register 0 (offset 94h, see Section 4.35) and the socket DMA register 1 (offset 98h, see Section 4.36). Distributed
DMA is enabled through socket DMA register 0 and the contents of this register configure the PC Card-16 terminal
(SPKR, IOIS16, or INPACK) which is used for the DMA request signal, DREQ. The base address of the DDMA slave
registers and the transfer size (bytes or words) are programmed through the socket DMA register 1. Refer to the
programming model and register descriptions (see Section 7 for details).
Table 3–2. Distributed DMA Registers
TYPE
DDMA
BASE ADDRESS
OFFSET
REGISTER NAME
R
W
Current address
Reserved
Page
Reserved
Reserved
R
W
R
Current count
N/A
W
Mode
R
Multichannel
W
00h
Base address
Mask
Reserved
04h
Base count
N/A
Status
Request
Command
08h
N/A
Reserved
Master clear
Reserved
0Ch
The DDMA registers contain control and status information consistent with the 8237 DMA controller; however, the
register locations are reordered and expanded in some cases. While the DDMA register definitions are identical to
those in the 8237 DMA controller, some register bits defined in the 8237 DMA controller do not apply to distributed
DMA in a PCI environment. In such cases, the PCI1410 implements these obsolete register bits as read-only,
nonfunctional bits. The reserved registers shown in Table 3–2 are implemented as read-only and return 0s when read.
Write transactions to reserved registers have no effect.
The DDMA transfer is prefaced by several configuration steps that are specific to the PC Card and must be completed
after the PC Card is inserted and interrogated. These steps include setting the proper DREQ signal assignment,
setting the data transfer width, and mapping and enabling the DDMA register set. As discussed above, this is done
through socket DMA register 0 and socket DMA register 1. The DMA register set is then programmed similarly to an
8237 controller, and the PCI1410 awaits a DREQ assertion from the PC Card requesting a DMA transfer.
DMA writes transfer data from the PC Card-to-PCI memory addresses. The PCI1410 accepts data 8 or 16 bits at a
time, depending on the programmed data width, and then requests access to the PCI bus by asserting its REQ signal.
Once the PCI bus is granted in an idle state, the PCI1410 initiates a PCI memory write command to the current
memory address and transfers the data in a single data phase. After terminating the PCI cycle, the PCI1410 accepts
the next byte(s) from the PC Card until the transfer count expires.
DMA reads transfer data from PCI memory addresses to the PC Card application. Upon the assertion of DREQ, the
PCI1410 asserts REQ to acquire the PCI bus. Once the bus is granted in an idle state, the PCI1410 initiates a PCI
memory read operation to the current memory address and accepts 8 or 16 bits of data, depending on the
programmed data width. After terminating the PCI cycle, the data is passed onto the PC Card. After terminating the
PC Card cycle, the PCI1410 requests access to the PCI bus again until the transfer count has expired.
The PCI1410 target interface acts normally during this procedure and accepts I/O reads and writes to the DDMA
registers. While a DDMA transfer is in progress and the host resets the DMA channel, the PCI1410 asserts TC and
ends the PC Card cycle(s). TC is indicated in the DDMA status register (DDMA offset 08h, see Section 7.5). At the
PC Card interface, the PCI1410 supports demand mode transfers. The PCI1410 asserts DACK during the transfer
unless DREQ is deasserted before TC. TC is mapped to the OE PC Card terminal for DMA write operations and is
mapped to the WE PC Card terminal for DMA read operations. The DACK signal is mapped to the PC Card REG signal
in all transfers, and the DREQ terminal is routed to one of three options which is programmed through socket DMA
register 0.
3–9
3.5.10 PC Card-16 PC/PCI DMA
Some chip sets provide a way for legacy I/O devices to do DMA transfers on the PCI bus. In the PC/PCI DMA protocol,
the PCI1410 acts as a PCI target device to certain DMA related I/O addresses. The PCI1410 PCREQ and PCGNT
signals are provided as a point-to-point connection to a chipset supporting PC/PCI DMA. The PCREQ and PCGNT
signals may be routed to the MFUNC2 and MFUNC5 terminals, respectively. See Section 4.30, Multifunction Routing
Register, for details on configuring the multifunction terminals.
Under the PC/PCI protocol, a PCI DMA slave device (such as the PCI1410) requests a DMA transfer on a particular
channel using a serialized protocol on PCREQ. The I/O DMA bus master arbitrates for the PCI bus and grants the
channel through a serialized protocol on PCGNT when it is ready for the transfer. The I/O cycle and memory cycles
are then presented on the PCI bus, which performs the DMA transfers similarly to legacy DMA master devices.
PC/PCI DMA is enabled for each PC Card-16 slot by setting bit 19 (CDREQEN) in the respective system control
register (see Section 4.29). On power up this bit is reset and the card PC/PCI DMA is disabled. Bit 3 (CDMA_EN)
of the system control register is a global enable for PC/PCI DMA, and is set at power up and never cleared if the
PC/PCI DMA mechanism is implemented. The desired DMA channel for each PC Card-16 slot must be configured
through bits 18–16 (CDMACHAN field) in the system control register. The channels are configured as indicated in
Table 3–3.
Table 3–3. PC/PCI Channel Assignments
SYSTEM CONTROL
REGISTER
DMA CHANNEL
CHANNEL TRANSFER
DATA WIDTH
BIT 18
BIT 17
BIT16
0
0
0
Channel 0
8-bit DMA transfers
0
0
1
Channel 1
8-bit DMA transfers
0
1
0
Channel 2
8-bit DMA transfers
0
1
1
Channel 3
8-bit DMA transfers
1
0
0
Channel 4
Not used
1
0
1
Channel 5
16-bit DMA transfers
1
1
0
Channel 6
16-bit DMA transfers
1
1
1
Channel 7
16-bit DMA transfers
As in distributed DMA, the PC Card terminal mapped to DREQ must be configured through socket DMA register 0
(offset 94h, see Section 4.35). The data transfer width is a function of channel number and the DDMA slave registers
are not used. When a DREQ is received from a PC Card and the channel has been granted, the PCI1410 decodes
the I/O addresses listed in Table 3–4 and performs actions dependent upon the address.
Table 3–4. I/O Addresses Used for PC/PCI DMA
DMA I/O ADDRESS
DMA CYCLE TYPE
TERMINAL COUNT
PCI CYCLE TYPE
00h
Normal
0
I/O read/write
04h
Normal TC
1
I/O read/write
C0h
Verify
0
I/O read
C4h
Verify TC
1
I/O read
When the PC/PCI DMA is used as a PC Card-16 DMA mechanism, it may not provide the performance levels of
DDMA; however, the design of a PCI target implementing PC/PCI DMA is considerably less complex. No bus master
state machine is required to support PC/PCI DMA, since the DMA control is centralized in the chipset. This DMA
scheme is often referred to as centralized DMA for this reason.
3.5.11 CardBus Socket Registers
The PCI1410 contains all registers for compatibility with the latest 1997 PC Card Standard. These registers exist as
the CardBus socket registers and are listed in Table 3–5.
3–10
Table 3–5. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
Socket power management
20h
3.6 Serial Bus Interface
The PCI1410 provides a serial bus interface to load subsystem identification and select register defaults through a
serial EEPROM and to provide a PC Card power switch interface alternative to P2C. See Section 3.5.2, P 2C
Power-Switch Interface (TPS2211), for details. The PCI1410 serial bus interface is compatible with various I2C and
SMBus components.
3.6.1
Serial Bus Interface Implementation
To enable the serial interface, a pullup resistor must be implemented on the VCCD0 and VCCD1 terminals and the
appropriate pullup resistors must be implemented on the SDA and SCL signals, that is, the MFUNC1 and MFUNC4
terminals. When the interface is detected, bit 3 (SBDETECT) in the serial bus control and status register (offset B3h,
see Section 4.50) is set. The SBDETECT bit is cleared by a writeback of 1.
The PCI1410 implements a two-pin serial interface with one clock signal (SCL) and one data signal (SDA). When
pullup resistors are provided on the VCCD0 and VCCD1 terminals, the SCL signal is mapped to the MFUNC4 terminal
and the SDA signal is mapped to the MFUNC1 terminal. The PCI1410 drives SCL at nearly 100 kHz during data
transfers, which is the maximum specified frequency for standard mode I2C. The serial EEPROM must be located
at address A0h. Figure 3–9 illustrates an example application implementing the two-wire serial bus.
VCC
Serial
EEPROM
5V
PCI1410
A2
VCCD0
A1
VCCD1
A0
SCL
MFUNC4
SDA
MFUNC1
Figure 3–9. Serial EEPROM Application
Some serial device applications may include PC Card power switches, ZV source switches, card ejectors, or other
devices that may enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches
are discussed in the sections that follow.
3.6.2
Serial Bus Interface Protocol
The SCL and SDA signals are bidirectional, open-drain signals and require pullup resistors as shown in Figure 3–9.
The PCI1410 supports up to 100 Kb/s data transfer rate and is compatible with standard mode I2C using 7-bit
addressing.
3–11
All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start
condition, which is signalled when the SDA line transitions to a low state while SCL is in the high state, as illustrated
in Figure 3–10. The end of a requested data transfer is indicated by a stop condition, which is signalled by a
low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3–10. Data on SDA must remain stable
during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are interpreted
as control signals, that is, a start or a stop condition.
SDA
SCL
Start
Condition
Stop
Condition
Data Line Stable,
Data Valid
Change of
Data Allowed
Figure 3–10. Serial Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer is
unlimited; however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is indicated by
the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal. Figure 3–11
illustrates the acknowledge protocol.
SCL From
Master
1
2
3
7
8
9
SDA Output
By Transmitter
SDA Output
By Receiver
Figure 3–11. Serial Bus Protocol Acknowledge
The PCI1410 is a serial bus master; all other devices connected to the serial bus external to the PCI1410 are slave
devices. As the bus master, the PCI1410 drives the SCL clock at nearly 100 kHz during bus cycles and places SCL
in a high-impedance state (zero frequency) during idle states.
Typically, the PCI1410 masters byte reads and byte writes under software control. Doubleword reads are performed
by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control. See
Section 3.6.3, Serial Bus EEPROM Application, for details on how the PCI1410 automatically loads the subsystem
identification and other register defaults through a serial bus EEPROM.
Figure 3–12 illustrates a byte write. The PCI1410 issues a start condition and sends the 7-bit slave device address
and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The slave device
acknowledges if it recognizes the address. If there is no acknowledgment received by the PCI1410, then bit 6 is set
in the serial bus control and status register (offset B3h, see Section 4.50). The word address byte is then sent by the
PCI1410 and another slave acknowledgment is expected. Then the PCI1410 delivers the data byte MSB first and
expects a final acknowledgment before issuing the stop condition.
3–12
Slave Address
S
Word Address
b6 b5 b4 b3 b2 b1 b0
0
A
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
A b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3–12. Serial Bus Protocol – Byte Write
Figure 3–13 illustrates a byte read. The read protocol is very similar to the write protocol except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI1410 master must acknowledge reception
of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data transfers.
The SCL signal remains driven by the PCI1410 master.
Slave Address
S
Word Address
b6 b5 b4 b3 b2 b1 b0
1
A
b7 b6 b5 b4 b3 b2 b1 b0
A
R/W
Data Byte
Slave Address
b6 b5 b4 b3 b2 b1 b0
A b7 b6 b5 b4 b3 b2 b1 b0 M
A = Slave Acknowledgement
P
S/P = Start/Stop Condition
Figure 3–13. Serial Bus Protocol – Byte Read
Figure 3–14 illustrates EEPROM interface doubleword data collection protocol.
Slave Address
S
1
0
1
0
0
Word Address
0
0
Start
0
A
Slave Address
b7 b6 b5 b4 b3 b2 b1 b0
R/W
Data Byte 3
M
A = Slave Acknowledgement
A
S
1
0
1
0
0
M
Data Byte 1
M = Master Acknowledgement
M
0
1
A
R/W
Restart
Data Byte 2
0
Data Byte 0
M
P
S/P = Start/Stop Condition
Figure 3–14. EEPROM Interface Doubleword Data Collection
3.6.3
Serial Bus EEPROM Application
When the PCI bus is reset and the serial bus interface is detected, the PCI1410 attempts to read the subsystem
identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may be
loaded with defaults through the EEPROM are provided in Table 3–6.
Table 3–6. Registers and Bits Loadable Through Serial EEPROM
OFFSET
REFERENCE
PCI OFFSET
01h
40h
Subsystem vendor ID, subsystem ID
31–0
02h
80h
System control
31–30, 27, 26, 24, 15, 14, 6–3, 1
03h
8Ch
Multifunction routing
27–0
04h
90h
Retry status, card control, device control, diagnostic
31, 28–24, 22, 19–16, 15, 7, 6
REGISTER
BITS LOADED FROM EEPROM
3–13
Figure 3–15 details the EEPROM data format. This format must be followed for the PCI1410 to properly load
initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the ROM_ERR
bit (bit 0) in the serial bus control and status register (offset B3h, see Section 4.50).
Slave Address = 1010 000
Reference(0)
Word Address 00h
Byte 3 (0)
Word Address 01h
Reference(n)
Byte 2 (0)
Word Address 02h
Byte 3 (n)
Word Address 8 × (n–1) + 1
Byte 1 (0)
Word Address 03h
Byte 2 (n)
Word Address 8 × (n–1) + 2
Byte 0 (0)
Word Address 04h
Byte 1 (n)
Word Address 8 × (n–1) + 3
RSVD
Byte 0 (n)
Word Address 8 × (n–1) + 4
RSVD
RSVD
RSVD
Reference(1)
Word Address 8 × (n–1)
RSVD
Word Address 08h
RSVD
EOL
Word Address 8 × (n)
Figure 3–15. EEPROM Data Format
The byte at the EEPROM word address 00h must either contain a valid offset reference, as listed in Table 3–6, or
an end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load from
the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be considered when
programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the PCI1410. All hardware address bits for the
EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the sample
application circuit (Figure 3–9) assumes the 1010b high address nibble. The lower three address bits are terminal
inputs to the chip, and the sample application shows these terminal inputs tied to GND.
When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in Figure 3–14.
The address autoincrements after every byte transfer according to the doubleword read protocol. Note that the word
addresses align with the data format illustrated in Figure 3–15. The PCI1410 continues to load data from the serial
EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain eight-byte data structures.
Note, the eight-byte data structure is important to provide correct addressing per the doubleword read format shown
in Figure 3–14. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that is 01h, 02h,
03h, 04h. If the offsets are not sequential, then the registers will be loaded incorrectly.
3.6.4
Accessing Serial Bus Devices Through Software
The PCI1410 provides a programming mechanism to control serial bus devices through software. The programming
is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3–7 lists the registers used
to program a serial bus device through software.
Table 3–7. PCI1410 Registers Used to Program Serial Bus Devices
PCI OFFSET
3–14
REGISTER NAME
DESCRIPTION
B0h
Serial bus data
Contains the data byte to send on write commands or the received data byte on read commands
B1h
Serial bus index
The content of this register is sent as the word address on byte writes or reads. This register is not used
in the quick command protocol.
B2h
Serial bus slave
address
Write transactions to this register initiate a serial bus transaction. The slave device address and the R/W
command selector are programmed through this register.
B3h
Serial bus control
and status
Read data valid, general busy, and general error status are communicated through this register. In
addition, the protocol select bit is programmed through this register.
To write a byte, the serial bus data register must be programmed with the data, the serial bus index register must be
programmed with the byte address, and the serial bus slave address register must be programmed with the 7-bit slave
address (SLAVADDR field) and bit 0 (RWCMD) must be reset.
On byte reads, the byte address is programmed into the serial bus index register, the serial bus slave address register
must be programmed with the 7-bit slave address (SLAVADDR field) and bit 0 (RWCMD) must be set, and bit 5
(REQBUSY) in the serial bus control and status register (see Section 4.50) must be polled until clear. Then the
contents of the serial bus data register are valid read data from the serial bus interface.
3.7 Programmable Interrupt Subsystem
Interrupts provide a way for I/O devices to let the microprocessor know that they require servicing. The dynamic
nature of PC Cards and the abundance of PC Card I/O applications require substantial interrupt support from the
PCI1410. The PCI1410 provides several interrupt signaling schemes to accommodate the needs of a variety of
platforms. The different mechanisms for dealing with interrupts in this device are based on various specifications and
industry standards. The ExCA register set provides interrupt control for some 16-bit PC Card functions, and the
CardBus socket register set provides interrupt control for the CardBus PC Card functions. The PCI1410 is, therefore,
backward compatible with existing interrupt control register definitions, and new registers have been defined where
required.
The PCI1410 detects PC Card interrupts and events at the PC Card interface and notifies the host controller using
one of several interrupt signaling protocols. To simplify the discussion of interrupts in the PCI1410, PC Card interrupts
are classified as either card status change (CSC) or as functional interrupts.
The method by which any type of PCI1410 interrupt is communicated to the host interrupt controller varies from
system to system. The PCI1410 offers system designers the choice of using parallel PCI interrupt signaling, parallel
ISA-type IRQ interrupt signaling, or the IRQSER serialized ISA and/or PCI interrupt protocol. It is possible to use the
parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs, as detailed in the sections that
follow. All interrupt signalling is provided through the seven multifunction terminals, MFUNC0–MFUNC6.
3.7.1
PC Card Functional and Card Status Change Interrupts
PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are
indicated by asserting specially-defined signals on the PC Card interface. Functional interrupts are generated by
16-bit I/O PC Cards and by CardBus PC Cards.
Card status change (CSC)-type interrupts are defined as events at the PC Card interface that are detected by the
PCI1410 and may warrant notification of host card and socket services software for service. CSC events include both
card insertion and removal from PC Card sockets, as well as transitions of certain PC Card signals.
Table 3–8 summarizes the sources of PC Card interrupts and the type of card associated with them. CSC and
functional interrupt sources are dependent on the type of card inserted in the PC Card socket. The three types of cards
that can be inserted into any PC Card socket are:
•
•
•
16-bit memory card
16-bit I/O card
CardBus cards
3–15
Table 3–8. Interrupt Mask and Flag Registers
CARD TYPE
EVENT
MASK
FLAG
Battery conditions
(BVD1, BVD2)
ExCA offset 05h/805h
bits 1 and 0
ExCA offset 04h/804h
bits 1 and 0
Wait states
(READY)
ExCA offset 05h/805h
bit 2
ExCA offset 04h/804h
bit 2
Change in card status
(STSCHG)
ExCA offset 05h/805h
bit 0
ExCA offset 04h/804h
bit 0
Interrupt request
(IREQ)
Always enabled
PCI configuration offset 91h
bit 0
Power cycle complete
ExCA offset 05h/805h
bit 3
ExCA offset 04h/804h
bit 3
Change in card status
(CSTSCHG)
Socket mask
bit 0
Socket event
bit 0
Interrupt request
(CINT)
Always enabled
PCI configuration offset 91h
bit 0
Power cycle complete
Socket mask
bit 3
Socket event
bit 3
Card insertion or
removal
Socket mask
bits 2 and 1
Socket event
bits 2 and 1
16
bit
16-bit
memory
16 bit I/O
16-bit
All 16-bit
PC Cards
CardBus
Functional interrupt events are valid only for 16-bit I/O and CardBus cards; that is, the functional interrupts are not
valid for 16-bit memory cards. Furthermore, card insertion and removal-type CSC interrupts are independent of the
card type. Table 3–9 describes the PC Card interrupt events.
Table 3–9. PC Card Interrupt Events and Description
CARD TYPE
16-bit
memory
16 bit I/O
16-bit
CardBus
All PC Cards
EVENT
TYPE
SIGNAL
DESCRIPTION
BVD1(STSCHG)//CSTSCHG
A transition on BVD1 indicates a change in the
PC Card battery conditions.
BVD2(SPKR)//CAUDIO
A transition on BVD2 indicates a change in the
PC Card battery conditions.
Battery conditions
(BVD1, BVD2)
CSC
Wait states
(READY)
CSC
READY(IREQ)//CINT
A transition on READY indicates a change in the ability
of the memory PC Card to accept or provide data.
Change in card
status (STSCHG)
CSC
BVD1(STSCHG)//CSTSCHG
The assertion of STSCHG indicates a status change
on the PC Card.
Interrupt request
(IREQ)
Functional
READY(IREQ)//CINT
The assertion of IREQ indicates an interrupt request
from the PC Card.
Change in card
status (CSTSCHG)
CSC
BVD1(STSCHG)//CSTSCHG
The assertion of CSTSCHG indicates a status change
on the PC Card.
Interrupt request
(CINT)
Functional
READY(IREQ)//CINT
The assertion of CINT indicates an interrupt request
from the PC Card.
Card insertion
or removal
CSC
CD1//CCD1,
CD2//CCD2
A transition on either CD1//CCD1 or CD2//CCD2
indicates an insertion or removal of a 16-bit or CardBus
PC Card.
Power cycle
complete
CSC
N/A
An interrupt is generated when a PC Card power-up
cycle has completed.
The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus. For
example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and CINT for
CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second, enclosed in
parentheses. The CardBus signal name follows after a double slash (//).
3–16
The 1997 PC Card Standard describes the power-up sequence that must be followed by the PCI1410 when an
insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this
power-up sequence, the PCI1410 interrupt scheme can be used to notify the host system (see Table 3–9), denoted
by the power cycle complete event. This interrupt source is considered a PCI1410 internal event because it depends
on the completion of applying power to the socket rather than on a signal change at the PC Card interface.
3.7.2
Interrupt Masks and Flags
Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 3–9 by setting
the appropriate bits in the PCI1410. By individually masking the interrupt sources listed, software can control those
events that cause a PCI1410 interrupt. Host software has some control over the system interrupt the PCI1410 asserts
by programming the appropriate routing registers. The PCI1410 allows host software to route PC Card CSC and PC
Card functional interrupts to separate system interrupts. Interrupt routing somewhat specific to the interrupt signaling
method used is discussed in more detail in the following sections.
When an interrupt is signaled by the PCI1410, the interrupt service routine must determine which of the events listed
in Table 3–8 caused the interrupt. Internal registers in the PCI1410 provide flags that report the source of an interrupt.
By reading these status bits, the interrupt service routine can determine the action to be taken.
Table 3–8 details the registers and bits associated with masking and reporting potential interrupts. All interrupts can
be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types of interrupts.
Notice that there is not a mask bit to stop the PCI1410 from passing PC Card functional interrupts through to the
appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there should never
be a card interrupt that does not require service after proper initialization.
Table 3–8 lists the various methods of clearing the interrupt flag bits. The flag bits in the ExCA registers (16-bit PC
Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of 1 to the
flag bit to clear and the other is by reading the flag bit register. The selection of flag bit clearing is made by bit 2
(IFCMODE) in the ExCA global control register (see Section 5.20), located at ExCA offset 1Eh/81Eh, and defaults
to the flag cleared on read method.
The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket force event
register (see Section 6.4). Although some of the functionality is shared between the CardBus registers and the ExCA
registers, software should not program the chip through both register sets when a CardBus card is functioning.
3.7.3
Using Parallel IRQ Interrupts
The seven multifunction terminals, MFUNC6–MFUNC0, implemented in the PCI1410 may be routed to obtain a
subset of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel
ISA type IRQ interrupt signaling, software must program the device control register (offset 92h, see Section 4.33),
located at PCI offset 92h, to select the parallel IRQ signaling scheme. See Section 4.30, Multifunction Routing
Register, for details on configuring the multifunction terminals.
A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This requirement
is dictated by certain card and socket services software. The INTA requirement calls for routing the MFUNC0 terminal
for INTA signaling. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.
As an example, suppose the six IRQs used by legacy PC Card applications are IRQ3, IRQ4, IRQ5, IRQ10, IRQ11,
and IRQ15. The multifunction routing register must be programmed to a value of 0FBA 5432h. This value routes the
MFUNC0 terminal to INTA signaling and routes the remaining terminals as illustrated in Figure 3–16. Not shown is
that INTA must also be routed to the programmable interrupt controller (PIC), or to some circuitry that provides parallel
PCI interrupts to the host.
3–17
PCI1410
MFUNC1
IRQ3
PIC
MFUNC2
IRQ4
MFUNC3
IRQ5
MFUNC4
IRQ10
MFUNC5
IRQ11
MFUNC6
IRQ15
Figure 3–16. IRQ Implementation
Power-on software is responsible for programming the multifunction routing register to reflect the IRQ configuration
of a system implementing the PCI1410. See Section 4.30, Multifunction Routing Register, for details on configuring
the multifunction terminals.
The parallel ISA type IRQ signaling from the MFUNC6–MFUNC0 terminals is compatible with those input directly into
the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs. Design constraints
may demand more MFUNC6–MFUNC0 IRQ terminals than the PCI1410 makes available.
3.7.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt mode, parallel ISA IRQ signaling mode,
and when only IRQs are serialized with the IRQSER protocol. The socket function interrupts are routed to INTA
(MFUNC0).
3.7.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI1410 uses a single terminal to communicate all interrupt
status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple
interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet data
describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For details on
the IRQSER protocol refer to the document Serialized IRQ Support for PCI Systems.
3.7.6
SMI Support in the PCI1410
The PCI1410 provides a mechanism for interrupting the system when power changes have been made to the PC
Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI) scheme.
SMI interrupts are generated by the PCI1410, when enabled, after a write cycle to either the socket control register
(see Section 6.5) of the CardBus register set or the ExCA power control register (ExCA offset 02h, see Section 5.3)
causes a power cycle change sequence sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (offset 80h, see Section 4.29). These
bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 3–10 describes the SMI control bits
function.
Table 3–10. SMI Control
BIT NAME
FUNCTION
SMIROUTE
This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.
SMISTATUS
This socket-dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.
SMIENB
When set, SMI interrupt generation is enabled.
If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC. The CSC interrupt can be either level
or edge mode, depending upon the CSCMODE bit (bit 1) in the ExCA global control register (ExCA offset 1Eh, see
Section 5.20).
If IRQ2 is selected by SMIROUTE, then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data
slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either
MFUNC1, MFUNC3, or MFUNC6 through the multifunction routing register (offset 8Ch, see Section 4.30).
3–18
3.8 Power Management Overview
In addition to the low-power CMOS technology process used for the PCI1410, various features are designed into the
device to allow implementation of popular power-saving techniques. These features and techniques are discussed
in this section.
3.8.1
Clock Run Protocol
The PCI CLKRUN feature is the primary method of power management on the PCI interface of the PCI1410. CLKRUN
signalling is provided through the MFUNC6 terminal. Since some chip sets do not implement CLKRUN, this is not
always available to the system designer, and alternate power-saving features are provided. For details on the
CLKRUN protocol see the PCI Mobile Design Guide.
The PCI1410 does not permit the central resource to stop the PCI clock under any of the following conditions:
•
Bit 1 (KEEPCLK) in the system control register (offset 80h, see Section 4.29) is set.
•
The PC Card-16 resource manager is busy.
•
The PCI1410 CardBus master state machine is busy. A cycle may be in progress on CardBus.
•
The PCI1410 master is busy. There may be posted data from CardBus to PCI in the PCI1410.
•
Interrupts are pending.
•
The CardBus CCLK for either socket has not been stopped by the PCI1410 CCLKRUN manager.
The PCI1410 restarts the PCI clock using the CLKRUN protocol under any of the following conditions:
•
A PC Card-16 IREQ or a CardBus CINT has been asserted.
•
A CardBus CBWAKE (CSTSCHG) or PC Card-16 STSCHG/RI event occurs.
•
A CardBus attempts to start the CCLK using CCLKRUN.
•
A CardBus card arbitrates for the CardBus bus using CREQ.
•
A 16-bit DMA PC Card asserts DREQ.
3.8.2
CardBus PC Card Power Management
The PCI1410 implements its own card power management engine that can turn off the CCLK to a socket when there
is no activity to the CardBus PC Card. The PCI clock-run protocol is followed on the CardBus CCLKRUN interface
to control this clock management.
3.8.3
16-Bit PC Card Power Management
The COE bit (bit 7) of the ExCA power control register (ExCA offset 02h, see Section 5.3) and PWRDWN bit (bit 0)
of the ExCA global control register (ExCA offset1Eh, see Section 5.20) are provided for 16-bit PC Card power
management. The COE bit places the card interface in a high-impedance state to save power. The power savings
when using this feature are minimal. The COE bit will reset the PC Card when used, and the PWRDWN bit will not.
Furthermore, the PWRDWN bit is an automatic COE, that is, the PWRDWN performs the COE function when there
is no card activity.
NOTE: The 16-bit PC Card must implement the proper pullup resistors for the COE and
PWRDWN modes.
3–19
3.8.4
Suspend Mode
The SUSPEND signal, provided for backward compatibility, gates the PRST (PCI reset) signal and the GRST (global
reset) signal from the PCI1410. Besides gating PRST and GRST, SUSPEND also gates PCLK inside the PCI1410
in order to minimize power consumption.
Gating PCLK does not create any issues with respect to the power switch interface in the PCI1410. This is because
the PCI1410 does not depend on the PCI clock to clock the power switch interface. There are two methods to clock
the power switch interface in the PCI1410:
•
•
Use an external clock to the PCI1410 PCLK terminal
Use the internal oscillator
It should also be noted that asynchronous signals, such as card status change interrupts and RI_OUT, can be passed
to the host system without a PCI clock. However, if card status change interrupts are routed over the serial interrupt
stream, then the PCI clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator
nor an external clock is routed to the serial interrupt state machine. Figure 3–17 is a logic diagram.
xRST
xRSTIN
PCI1410
Core
SUSPEND
SUSPENDIN
GNT
PCLKIN
PCLK
Figure 3–17. Suspend Logic Diagram
Figure 3–18 is a signal diagram of the suspend function.
3–20
xRST
GNT
SUSPEND
PCLK
External Terminals
Internal Signals
xRSTIN
SUSPENDIN
PCLKIN
Figure 3–18. Signal Diagram of Suspend Function
3.8.5
Requirements for Suspend Mode
The suspend mode prevents the clearing of all register contents on the assertion of reset (PRST or GRST) which
would require the reconfiguration of the PCI1410 by software. Asserting the SUSPEND signal places the controller
PCI outputs in a high impedance state and gates the PCLK signal internally to the controller unless a PCI transaction
is currently in process (GNT is asserted). It is important that the PCI bus not be parked on the PCI1410 when
SUSPEND is asserted because the outputs are in a high-impedance state.
The GPIOs, MFUNC signals, and RI_OUT signals are all active during SUSPEND, unless they are disabled in the
appropriate PCI1410 registers.
3.8.6
Ring Indicate
The RI_OUT output is an important feature in power management, allowing a system to go into a suspended mode
and wake up on modem rings and other card events. TI-designed flexibility permits this signal to fit wide platform
requirements. RI_OUT on the PCI1410 can be asserted under any of the following conditions:
•
A 16-bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an
incoming call.
•
A powered down CardBus card asserts CSTSCHG (CBWAKE) requesting system and interface wake-up.
•
A powered CardBus card asserts CSTSCHG from the insertion/removal of cards or change in battery
voltage levels.
Figure 3–19 shows various enable bits for the PCI1410 RI_OUT function; however, it does not show the masking of
CSC events. See Table 3–8 for a detailed description of CSC interrupt masks and flags.
3–21
RI_OUT Function
CSTSMASK
RIENB
PC Card
Socket
Card
I/F
RINGEN
RI_OUT
CDRESUME
Figure 3–19. RI_OUT Functional Diagram
RI from the 16-bit PC Card interface is masked by bit 7 (RINGEN) in the ExCA interrupt and general control register
(ExCA offset 03h, see Section 5.4). This is programmed on a per-socket basis and is only applicable when a 16-bit
card is powered in the socket.
The CBWAKE signaling to RI_OUT is enabled through the same mask as the CSC event for CSTSCHG. The mask
bit (bit 0, CSTSMASK) is programmed through the socket mask register (CardBus offset 04h, see Section 6.2) in the
CardBus socket registers.
3.8.7
PCI Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure
required to let the operating system control the power of PCI functions. This is done by defining a standard PCI
interface and operations to manage the power of PCI functions on the bus. The PCI bus and the PCI functions can
be assigned one of four software-visible power management states that result in varying levels of power savings.
The four power management states of PCI functions are:
•
•
•
D0 – Fully-on state
D1 and D2 – Intermediate states
D3 – Off state
Similarly, bus power states of the PCI bus are B0–B3. The bus power states B0–B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to power manage the device power states on the PCI bus, the PCI function should
support four power management operations. These operations are:
•
•
•
•
Capabilities reporting
Power status reporting
Setting the power state
System wake up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register
(offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1410, a CardBus
bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h. The first
byte of each capability register block is required to be a unique ID of that capability. PCI power management has been
assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there are no more
items in the list, then the next item pointer should be set to 0. The registers following the next item pointer are specific
to the capabilities of their corresponding power management functions. The PCI power management capability
implements the register block outlined in Table 3–11.
3–22
Table 3–11. Power Management Registers
REGISTER NAME
Power management capabilities
PM data
PMCSR bridge support
extensions
OFFSET
Next-item pointer
Capability ID
Power management control/status
A0h
A4h
The power management capabilities register (offset A2h, see Section 4.39) provides information on the capabilities
of the function related to power management. The power management control/status register (offset A4h, see
Section 4.40) enables control of power management states and enables/monitors power management events. The
data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges.
3.8.8
CardBus Bridge Power Management
The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in
December of 1997. This specification follows the device and bus state definitions provided in the PCI Bus Power
Management Interface Specification published by the PCI Special Interest Group (SIG). The main issue addressed
in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake-up from D3hot or D3cold
without losing wake-up context (also called PME context).
The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges
for D3 wake up are as follows:
•
Preservation of device context: The specification states that a reset must occur when transitioning from D3
to D0. Some method to preserve wake-up context must be implemented so that the reset does not clear
the PME context registers.
•
Power source in D3cold if wake-up support is required from this state.
The Texas Instruments PCI1410 addresses these D3 wake-up issues in the following manner:
•
•
3.8.9
Two resets are provided to handle preservation of PME context bits:
–
Global reset (GRST) is used only on the initial boot up of the system after power up. It places the
PCI1410 in its default state and requires BIOS to configure the device before becoming fully functional.
–
PCI reset (PRST) now has dual functionality based on whether PME is enabled or not. If PME is
enabled, then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal
PCI reset. Please see the master list of PME context bits in Section 3.8.10.
Power source in D3cold if wake-up support is required from this state. Since VCC is removed in D3cold, an
auxiliary power source must be supplied to the PCI1410 VCC pins. Consult the PCI14xx Implementation
Guide for D3 Wake-Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges
for further information.
ACPI Support
The Advanced Configuration and Power Interface (ACPI) Specification provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI1410 offers a generic interface that is compliant with
ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI1410 PCI configuration space at offset
A8h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event
status and enable bits reside in general-purpose event status (offset A8h, see Section 4.43) and general-purpose
event enable (offset AAh, see Section 4.44) registers. The status and enable bits are implemented as defined by ACPI
and illustrated in Figure 3–20.
3–23
Status Bit
Event Input
Enable Bit
Event Output
Figure 3–20. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the Advanced Configuration and Power Interface (ACPI) Specification.
3.8.10 Master List of PME Context Bits and Global Reset Only Bits
If the PME enable bit (bit 8) of the power management control/status register (PCI offset A4h, see Section 4.40) is
asserted, then the assertion of PRST will not clear the following PME context bits. If the PME enable bit is not asserted,
then the PME context bits are cleared with PRST. The PME context bits are:
•
•
•
•
•
•
•
•
•
•
Bridge control register (PCI offset 3Eh, see Section 4.25): bit 6
Power management capabilities register (PCI offset A2h, see Section 4.39): bit 15
Power management control/status register (PCI offset A4h, see Section 4.40): bits 15, 8
ExCA power control register (ExCA offset 802h, see Section 5.3): bits 4, 3, 1, 0
ExCA interrupt and general control (ExCA offset 803h, see Section 5.4): bits 6, 5
ExCA card status-change-interrupt configuration register (ExCA offset 805h, see Section 5.6): bits 3–0
CardBus socket event register (CardBus offset 00h, see Section 6.1): bits 3–0
CardBus socket mask register (CardBus offset 04h, see Section 6.2): bits 3–0
CardBus socket present state register (CardBus offset 08h, see Section 6.3): bits 13–10, 7, 5–0
CardBus socket control register (CardBus offset 10h, see Section 6.5): bits 6–4, 2–0
Global reset will place all registers in their default state regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared by GRST are:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3–24
Subsystem vendor ID (PCI offset 40h, see Section 4.26): bits 15–0
Subsystem ID (PCI offset 42h, see Section 4.27): bits 15–0
PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31–1
System control register (PCI offset 80h, see Section 4.29): bits 31, 30, 27, 26, 24–14, 7–0
Multifunction routing register (PCI offset 8Ch, see Section 4.30): bits 27–0
Retry status register (PCI offset 90h, see Section 4.31): bits 7, 6, 3, 1
Card control register (PCI offset 91h, see Section 4.32): bits 7–5, 2–0
Device control register (PCI offset 92h, see Section 4.33): bits 7–5, 3–0
Diagnostic register (PCI offset 93h, see Section 4.34): bits 7–0
Socket DMA register 0 (PCI offset 94h, see Section 4.35): bits 1–0
Socket DMA register 1 (PCI offset 98h, see Section 4.36): bits 15–4, 2–0
General-purpose event enable register (PCI offset AAh, see Section 4.44): bits 15, 11, 8, 4–0
General-purpose output (PCI offset AEh, see Section 4.46): bits 4–0
Serial bus data (PCI offset B0h, see Section 4.47): bits 7–0
Serial bus index (PCI offset B1h, see Section 4.48): bits 7–0
Serial bus slave address register (PCI offset B2h, see Section 4.49): bits 7–0
Serial bus control and status register (PCI offset B3h, see Section 4.50): bits 7, 2
ExCA identification and revision register (ExCA offset 00h, see Section 5.1): bits 7–0
ExCA card status change register (ExCA offset 804h, see Section 5.5): bits 3–0
ExCA global control register (ExCA offset 1Eh, see Section 5.20): bits 3–0
4 PC Card Controller Programming Model
This section describes the PCI1410 PCI configuration registers that make up the 256-byte PCI configuration header
for each PCI1410 function. As noted, some bits are global in nature and are accessed only through function 0.
4.1 PCI Configuration Registers
The configuration header is compliant with the PCI Local Bus Specification as a CardBus bridge header and is PC 99
compliant as well. Table 4–1 shows the PCI configuration header, which includes both the predefined portion of the
configuration space and the user-definable registers.
Table 4–1. PCI Configuration Registers
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
PCI class code
BIST
Header type
Latency timer
Revision ID
08h
Cache line size
0Ch
CardBus socket/ExCA base-address
Secondary status
CardBus latency timer
Subordinate bus number
10h
Reserved
Capability pointer
14h
CardBus bus number
PCI bus number
18h
Memory base register 0
1Ch
Memory limit register 0
20h
Memory base register 1
24h
Memory limit register 1
28h
I/O base register 0
2Ch
I/O limit register 0
30h
I/O base register 1
34h
I/O limit register 1
38h
Bridge control
Interrupt pin
Subsystem ID
Interrupt line
Subsystem vendor ID
44h
Reserved
48h–7Ch
System control
80h
Reserved
84h–88h
Device control
8Ch
Card control
Retry status
90h
Socket DMA register 0
94h
Socket DMA register 1
98h
Reserved
Power management capabilities
Power management data
40h
PC Card 16-bit I/F legacy-mode base address
Multifunction routing
Diagnostic
3Ch
9Ch
Next-item pointer
Power management
control/status bridge
support extensions
Capability ID
Power management control/status
A0h
A4h
General-purpose event enable
General-purpose event status
A8h
General-purpose output
General-purpose input
ACh
Serial bus control and
status
Serial bus slave address
Reserved
Serial bus index
Serial bus data
B0h
B4h–FCh
4–1
A bit description table, typically included when a register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags, which appear in the type column of the bit description
table. Table 4–2 describes the field access tags.
Table 4–2. Bit Field Access Tag Descriptions
ACCESS TAG
NAME
R
Read
Field may be read by software.†
W
Write
Field may be written by software to any value.
S
Set
C
Clear
U
MEANING
Field may be set by a write of 1. Writes of 0 have no effect.
Field may be cleared by a write of 1. Writes of 0 have no effect.
Update
Field may be autonomously updated by the PCI1410.
† A bit may display either of two types of behavior when read. After
having been read it can maintain the value it had previously, or the
read process can cause it to be reset to 0.
4.2 Vendor ID Register
This 16-bit register contains a value allocated by the PCI Special Interest Group (SIG) and identifies the manufacturer
of the PCI device. The vendor ID assigned to TI is 104Ch.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Vendor ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
1
0
0
0
0
0
1
0
0
1
1
0
0
Register:
Offset:
Type:
Default:
Vendor ID
00h
Read-only
104Ch
4.3 Device ID Register
This 16-bit register contains a value assigned to the PCI1410 by TI. The device identification for the PCI1410 is
AC50h.
Bit
15
14
13
12
11
10
9
8
Type
R
R
R
R
R
R
R
R
Default
1
0
1
0
1
1
0
0
Name
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0
1
0
1
0
0
0
0
Device ID
Register:
Offset:
Type:
Default:
4–2
7
Device ID
02h
Read-only
AC50h
4.4 Command Register
The command register provides control over the PCI1410 interface to the PCI bus. All bit functions adhere to the
definitions in PCI Local Bus Specification. See Table 4–3 for the complete description of the register contents.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Command
Type
R
R
R
R
R
R
R
R/W
R
R/W
R/W
R
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Command
04h
Read-only, Read/Write
0000h
Table 4–3. Command Register
BIT
SIGNAL
TYPE
FUNCTION
15–10
RSVD
R
Reserved. Bits 15–10 return 0s when read.
9
FBB_EN
R
Fast back-to-back enable. The PCI1410 does not generate fast back-to-back transactions; therefore, bit 9
returns 0 when read.
8
SERR_EN
R/W
System error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR can
be asserted after detecting an address parity error on the PCI bus. Both bits 8 and 6 must be set for the
PCI1410 to report address parity errors.
0 = Disable SERR output driver (default)
1 = Enable SERR output driver
7
STEP_EN
R
Address/data stepping control. The PCI1410 does not support address/data stepping; therefore, bit 7 is
hardwired to 0.
6
PERR_EN
R/W
Parity error response enable. Bit 6 controls the response of the PCI1410 to parity errors through PERR. Data
parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting
SERR.
0 = PCI1410 ignores detected parity error (default)
1 = PCI1410 responds to detected parity errors
5
VGA_EN
R/W
VGA palette snoop. When bit 5 is set to 1, palette snooping is enabled (that is, the PCI1410 does not respond
to palette register writes and snoops the data). When bit 5 is 0, the PCI1410 treats all palette accesses like
all other accesses.
4
MWI_EN
R
Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory write
and invalidate commands. The PCI1410 controller does not support memory write and invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0.
3
SPECIAL
R
Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1410 does
not respond to special cycle operations; therefore, this bit is hardwired to 0.
2
MAST_EN
R/W
Bus master control. Bit 2 controls whether or not the PCI1410 can act as a PCI bus initiator (master). The
PCI1410 can take control of the PCI bus only when this bit is set.
0 = Disables the ability of the PCI1410 to generate PCI bus accesses (default)
1 = Enables the ability of the PCI1410 to generate PCI bus accesses
1
MEM_EN
R/W
Memory space enable. Bit 1 controls whether or not the PCI1410 can claim cycles in PCI memory space.
0 = Disables the PCI1410 from responding to memory space accesses (default)
1 = Enables the PCI1410 to respond to memory space accesses
0
IO_EN
R/W
I/O space control. Bit 0 controls whether or not the PCI1410 can claim cycles in PCI I/O space.
0 = Disables the PCI1410 from responding to I/O space accesses (default)
1 = Enables the PCI1410 to respond to I/O space accesses
4–3
4.5 Status Register
The status register provides device information to the host system. Bits in this register may be read normally. A bit
in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. All bit
functions adhere to the definitions in the PCI Local Bus Specification. PCI bus status is shown through each function.
See Table 4–4 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
Name
Type
Default
7
6
5
4
3
2
1
0
Status
R/C
R/C
R/C
R/C
R/C
R
R
R/C
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Register:
Offset:
Type:
Default:
Status
06h
Read-only, Read/Clear
0210h
Table 4–4. Status Register
4–4
BIT
SIGNAL
TYPE
FUNCTION
15
PAR_ERR
R/C
Detected parity error. Bit 15 is set when a parity error is detected (either address or data).
14
SYS_ERR
R/C
Signaled system error. Bit 14 is set when SERR is enabled and the PCI1410 signals a system error to the
host.
13
MABORT
R/C
Received master abort. Bit 13 is set when a cycle initiated by the PCI1410 on the PCI bus has been
terminated by a master abort.
12
TABT_REC
R/C
Received target abort. Bit 12 is set when a cycle initiated by the PCI1410 on the PCI bus was terminated
by a target abort.
11
TABT_SIG
R/C
Signaled target abort. Bit 11 is set by the PCI1410 when it terminates a transaction on the PCI bus with a
target abort.
10–9
PCI_SPEED
R
DEVSEL timing. These bits encode the timing of DEVSEL and are hardwired 01b, indicating that the
PCI1410 asserts PCI_SPEED at a medium speed on nonconfiguration cycle accesses.
Data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred, and the following conditions were met:
a. PERR was asserted by any PCI device including the PCI1410.
b. The PCI1410 was the bus master during the data parity error.
c. The parity error response bit is set in the command register (offset 04h, see Section 4.4).
8
DATAPAR
R/C
7
FBB_CAP
R
Fast back-to-back capable. The PCI1410 cannot accept fast back-to-back transactions; therefore, bit 7 is
hardwired to 0.
6
UDF
R
User-definable feature support. The PCI1410 does not support the user-definable features; therefore, bit 6
is hardwired to 0.
5
66MHZ
R
66-MHz capable. The PCI1410 operates at a maximum PCLK frequency of 33 MHz; therefore, bit 5 is
hardwired to 0.
4
CAPLIST
R
Capabilities list. Bit 4 returns 1 when read. This bit indicates that capabilities in addition to standard PCI
capabilities are implemented. The linked list of PCI power management capabilities is implemented in this
function.
3–0
RSVD
R
Reserved. Bits 3–0 return 0s when read.
4.6 Revision ID Register
The revision ID register indicates the silicon revision of the PCI1410.
Bit
7
6
5
4
Name
3
2
1
0
Revision ID
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Revision ID
08h
Read-only
01h
4.7 PCI Class Code Register
The class code register recognizes the PCI1410 as a bridge device (06h) and CardBus bridge device (07h) with a
00h programming interface.
Bit
23
22
21
20
19
18
17
16
15
14
Name
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCI class code
Base class
Subclass
Programming interface
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
PCI class code
09h
Read-only
06 0700h
4.8 Cache Line Size Register
The cache line size register is programmed by host software to indicate the system cache line size.
Bit
7
6
5
4
R/W
R/W
R/W
R/W
0
0
0
0
Name
Type
Default
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
0
Cache line size
Register:
Offset:
Type:
Default:
Cache line size
0Ch
Read/Write
00h
4–5
4.9 Latency Timer Register
The latency timer register specifies the latency timer for the PCI1410 in units of PCI clock cycles. When the PCI1410
is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires
before the PCI1410 transaction has terminated, then the PCI1410 terminates the transaction when its GNT is
deasserted.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Latency timer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Latency timer
0Dh
Read/Write
00h
4.10 Header Type Register
This register returns 02h when read, indicating that the PCI1410 configuration spaces adhere to the CardBus bridge
PCI header. The CardBus bridge PCI header ranges from PCI register 0 to 7Fh, and 80h–FFh are user-definable
extension registers.
Bit
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
1
0
Name
Header type
Register:
Offset:
Type:
Default:
Header type
0Eh
Read-only
02h
4.11 BIST Register
Because the PCI1410 does not support a built-in self-test (BIST), this register returns the value of 00h when read.
Bit
7
6
5
4
Name
3
2
1
0
BIST
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4–6
BIST
0Fh
Read-only
00h
4.12 CardBus Socket/ExCA Base-Address Register
The CardBus socket/ExCA base-address register is programmed with a base address referencing the CardBus
socket registers and the memory-mapped ExCA register set. Bits 31–12 are read/write and allow the base address
to be located anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 11–0 are read-only,
returning 0s when read. When software writes all 1s to this register, the value read back is FFFF F000h, indicating
that at least 4K bytes of memory address space are required. The CardBus registers start at offset 000h, and the
memory-mapped ExCA registers begin at offset 800h.
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
CardBus socket/ExCA base-address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
CardBus socket/ExCA base-address
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
CardBus socket/ExCA base-address
10h
Read-only, Read/Write
0000 0000h
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power management
register block resides. PCI header doublewords at A0h and A4h provide the power management (PM) registers. The
socket has its own capability pointer register. This register returns A0h when read.
Bit
7
6
5
Name
4
3
2
1
0
Capability pointer
Type
R
R
R
R
R
R
R
R
Default
1
0
1
0
0
0
0
0
Register:
Offset:
Type:
Default:
Capability pointer
14h
Read-only
A0h
4–7
4.14 Secondary Status Register
The secondary status register is compatible with the PCI-to-PCI bridge secondary status register and indicates
CardBus-related device information to the host system. This register is very similar to the PCI status register (offset
06h); status bits are cleared by writing a 1. See Table 4–5 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
Name
Type
Default
8
7
6
5
4
3
2
1
0
Secondary status
R/C
R/C
R/C
R/C
R/C
R
R
R/C
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Secondary status
16h
Read-only, Read/Clear
0200h
Table 4–5. Secondary Status Register
4–8
BIT
SIGNAL
TYPE
FUNCTION
15
CBPARITY
R/C
Detected parity error. Bit 15 is set when a CardBus parity error is detected (either address or data).
14
CBSERR
R/C
Signaled system error. Bit 14 is set when CSERR is signaled by a CardBus card. The PCI1410 does not
assert CSERR.
13
CBMABORT
R/C
Received master abort. Bit 13 is set when a cycle initiated by the PCI1410 on the CardBus bus has been
terminated by a master abort.
12
REC_CBTA
R/C
Received target abort. Bit 12 is set when a cycle initiated by the PCI1410 on the CardBus bus is terminated
by a target abort.
11
SIG_CBTA
R/C
Signaled target abort. Bit 11 is set by the PCI1410 when it terminates a transaction on the CardBus bus
with a target abort.
10–9
CB_SPEED
R
CDEVSEL timing. These bits encode the timing of CDEVSEL and are hardwired 01b, indicating that the
PCI1410 asserts CB_SPEED at a medium speed.
CardBus data parity error detected.
0 = The conditions for setting bit 8 have not been met.
1 = A data parity error occurred and the following conditions were met:
a. CPERR was asserted on the CardBus interface.
b. The PCI1410 was the bus master during the data parity error.
c. The parity error response bit is set in the bridge control.
8
CB_DPAR
R/C
7
CBFBB_CAP
R
Fast back-to-back capable. The PCI1410 cannot accept fast back-to-back transactions; therefore, bit 7
is hardwired to 0.
6
CB_UDF
R
User-definable feature support. The PCI1410 does not support the user-definable features; therefore, bit 6
is hardwired to 0.
5
CB66MHZ
R
66-MHz capable. The PCI1410 CardBus interface operates at a maximum CCLK frequency of 33 MHz;
therefore, bit 5 is hardwired to 0.
4–0
RSVD
R
Reserved. Bits 4–0 return 0s when read.
4.15 PCI Bus Number Register
This register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI1410 is
connected. The PCI1410 uses this register in conjunction with the CardBus bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
PCI bus number
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
PCI bus number
18h
Read/Write
00h
4.16 CardBus Bus Number Register
This register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI1410
is connected. The PCI1410 uses this register in conjunction with the PCI bus number and subordinate bus number
registers to determine when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
CardBus bus number
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
CardBus bus number
19h
Read/Write
00h
4.17 Subordinate Bus Number Register
This register is programmed by the host system to indicate the highest-numbered bus below the CardBus bus. The
PCI1410 uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine
when to forward PCI configuration cycles to its secondary buses.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
Subordinate bus number
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subordinate bus number
1Ah
Read/Write
00h
4–9
4.18 CardBus Latency Timer Register
This register is programmed by the host system to specify the latency timer for the PCI1410 CardBus interface in units
of CCLK cycles. When the PCI1410 is a CardBus initiator and asserts CFRAME, the CardBus latency timer begins
counting. If the latency timer expires before the PCI1410 transaction has terminated, then the PCI1410 terminates
the transaction at the end of the next data phase. A recommended minimum value for this register is 20h, which allows
most transactions to be completed.
Bit
7
6
5
4
Name
3
2
1
0
CardBus latency timer
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Default
Register:
Offset:
Type:
Default:
CardBus latency timer
1Bh
Read/Write
00h
4.19 Memory Base Registers 0, 1
The memory base registers indicate the lower address of a PCI memory address range. These registers are used
by the PCI1410 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register (offset 3Eh, see Section 4.25)
specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. The memory base register or the
memory limit register must be nonzero for the PCI1410 to claim any memory transactions through the CardBus
memory windows (that is, these windows are not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Type
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Memory base registers 0, 1
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory base registers 0, 1
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
4–10
Memory base register 0
1Ch
Memory base register 1
24h
Read-only, Read/Write
0000 0000h
4.20 Memory Limit Registers 0, 1
The memory limit registers indicate the upper address of a PCI memory address range. These registers are used
by the PCI1410 to determine when to forward a memory transaction to the CardBus bus and when to forward a
CardBus cycle to PCI. Bits 31–12 of these registers are read/write and allow the memory base to be located anywhere
in the 32-bit PCI memory space on 4-Kbyte boundaries. Bits 11–0 are read-only and always return 0s. Write
transactions to these bits have no effect. Bits 8 and 9 of the bridge control register specify whether memory windows
0 and 1 are prefetchable or nonprefetchable. The memory base register or the memory limit register must be nonzero
for the PCI1410 to claim any memory transactions through CardBus memory windows (that is, these windows are
not enabled by default to pass the first 4K bytes of memory to CardBus).
Bit
31
30
29
28
27
26
Name
Type
25
24
23
22
21
20
19
18
17
16
Memory limit registers 0, 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Memory limit registers 0, 1
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Memory limit registers 0, 1
20h, 28h
Read-only, Read/Write
0000 0000h
4.21 I/O Base Registers 0, 1
The I/O base registers indicate the lower address of a PCI I/O address range. These registers are used by the
PCI1410 to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle
to the PCI bus. The lower 16 bits of these registers locate the bottom of the I/O window within a 64-Kbyte page, and
the upper 16 bits (31–16) are a page register which locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits
31–2 are read/write. Bits 1 and 0 are read-only and always return 0s, forcing the I/O window to be aligned on a natural
doubleword boundary.
NOTE: Either the I/O base or the I/O limit register must be nonzero to enable any I/O
transactions.
Bit
31
30
29
28
27
26
25
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
Type
Default
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
I/O base registers 0, 1
Name
Type
24
I/O base registers 0, 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
I/O base registers 0, 1
2Ch, 34h
Read-only, Read/Write
0000 0000h
4–11
4.22 I/O Limit Registers 0, 1
The I/O limit registers indicate the upper address of a PCI I/O address range. These registers are used by the PCI1410
to determine when to forward an I/O transaction to the CardBus bus and when to forward a CardBus cycle to PCI.
The lower 16 bits of these registers locate the top of the I/O window within a 64-Kbyte page, and the upper 16 bits
are a page register that locates this 64-Kbyte page in 32-bit PCI I/O address space. Bits 15–2 are read/write and allow
the I/O limit address to be located anywhere in the 64-Kbyte page (indicated by bits 31–16 of the appropriate I/O base)
on doubleword boundaries.
Bits 31–16 are read-only and always return 0s when read. The page is set in the I/O base register. Bits 1 and 0 are
read-only and always return 0s, forcing I/O windows to be aligned on a natural doubleword boundary. Write
transactions to read-only bits have no effect. The PCI1410 assumes that the lower 2 bits of the limit address are 1s.
NOTE: The I/O base or the I/O limit register must be nonzero to enable an I/O transaction.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
I/O limit registers 0, 1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Name
Type
Default
I/O limit registers 0, 1
Register:
Offset:
Type:
Default:
I/O limit registers 0, 1
30h, 38h
Read-only, Read/Write
0000 0000h
4.23 Interrupt Line Register
The interrupt line register communicates interrupt line routing information.
Bit
7
6
5
4
Name
Type
Default
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Register:
Offset:
Type:
Default:
4–12
3
Interrupt line
Interrupt line
3Ch
Read/Write
FFh
4.24 Interrupt Pin Register
The value read from the interrupt pin register is function dependent and depends on the interrupt signaling mode,
selected through bits 2–1 (INTMODE field) of the device control register (offset 92h, see Section 4.33). The PCI1410
defaults to serialized PCI and ISA interrupt mode.
Bit
7
6
5
4
Name
3
2
1
0
Interrupt pin
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Interrupt pin
3Dh
Read-only
01h
4–13
4.25 Bridge Control Register
The bridge control register provides control over various PCI1410 bridging functions. See Table 4–6 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Bridge control
Type
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Bridge control
3Eh
Read-only, Read/Write
0340h
Table 4–6. Bridge Control Register
BIT
SIGNAL
TYPE
15–11
RSVD
R
10
POSTEN
R/W
Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables
posting of write data on burst cycles. Operating with write posting disabled inhibits performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not.
9
PREFETCH1
R/W
Memory window 1 type. Bit 9 specifies whether or not memory window 1 is prefetchable. This bit is socket
dependent. Bit 9 is encoded as:
0 = Memory window 1 is nonprefetchable.
1 = Memory window 1 is prefetchable (default).
R/W
Memory window 0 type. Bit 8 specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
0 = Memory window 0 is nonprefetchable.
1 = Memory window 0 is prefetchable (default).
R/W
PCI interrupt – IREQ routing enable. Bit 7 selects whether PC Card functional interrupts are routed to PCI
interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts routed to PCI interrupts (default)
1 = Functional interrupts routed by ExCAs
R/W
CardBus reset. When bit 6 is set, CRST is asserted on the CardBus interface. CRST can also be asserted
by passing a PRST assertion to CardBus.
0 = CRST deasserted
1 = CRST asserted (default)
Master abort mode. Bit 5 controls how the PCI1410 responds to a master abort when the PCI1410 is an
initiator on the CardBus interface.
0 = Master aborts not reported (default)
1 = Signal target abort on PCI and SERR (if enabled)
8
7
6
INTR
CRST
Reserved. Bits 15–11 return 0s when read.
5
MABTMODE
R/W
4
RSVD
R
3
VGAEN
R/W
VGA enable. Bit 3 affects how the PCI1410 responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
2
ISAEN
R/W
ISA mode enable. Bit 2 affects how the PCI1410 passes I/O cycles within the 64-Kbyte ISA range. This
bit is not common between sockets. When this bit is set, the PCI1410 does not forward the last 768 bytes
of each 1K I/O range to CardBus.
1
CSERREN
R/W
CSERR enable. Bit 1 controls the response of the PCI1410 to CSERR signals on the CardBus bus. This
bit is common between the two sockets.
0 = CSERR is not forwarded to PCI SERR.
1 = CSERR is forwarded to PCI SERR.
R/W
CardBus parity error response enable. Bit 0 controls the response of the PCI1410 to CardBus parity errors.
This bit is common between the two sockets.
0 = CardBus parity errors are ignored.
1 = CardBus parity errors are reported using CPERR.
0
4–14
PREFETCH0
FUNCTION
CPERREN
Reserved. Bit 4 returns 0 when read.
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register is used for system and option-card identification purposes and may be required
for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW)
in the system control register (offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Name
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Subsystem vendor ID
Register:
Offset:
Type:
Default:
Subsystem vendor ID
40h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
4.27 Subsystem ID Register
The subsystem ID register is used for system and option-card identification purposes and may be required for certain
operating systems. This register is read-only or read/write, depending on the setting of bit 5 (SUBSYSRW) in the
system control register (offset 80h, see Section 4.29).
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
Subsystem ID
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Subsystem ID
42h
Read-only (Read/Write if enabled by SUBSYSRW)
0000h
4.28 PC Card 16-bit I/F Legacy-Mode Base-Address Register
The PCI1410 supports the index/data scheme of accessing the ExCA registers, which is mapped by this register. An
address written to this register is the address for the index register and the address + 1 is the data address. Using
this access method, applications requiring index/data ExCA access can be supported. The base address can be
mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only, returning 1 when read. See
Section 5, ExCA Compatibility Registers, for register offsets.
Bit
31
30
29
28
27
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
Name
Type
Default
25
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
5
4
3
2
1
0
PC Card 16-bit I/F legacy-mode base address
Name
Type
26
PC Card 16-bit I/F legacy-mode base address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
PC Card 16-bit I/F legacy-mode base address
44h
Read-only, Read/Write
0000 0001h
4–15
4.29 System Control Register
System-level initializations are performed through programming this doubleword register. See Table 4–7 for a
complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
System control
R/W
R/W
R
R
R/W
R/W
R/C
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
System control
R/W
R/W
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
Register:
Type:
Offset:
Default:
4–16
System control
Read-only, Read/Write, Read/Clear
80h
0044 9060h
Table 4–7. System Control Register
BIT
SIGNAL
TYPE
FUNCTION
Serialized PCI interrupt routing step. Bits 31 and 30 configure the serialized PCI interrupt stream
signaling and accomplish an even distribution of interrupts signaled on the four PCI interrupt slots.
Bits 31 and 30 are encoded as follows:
31–30
SER_STEP
R/W
29–28
RSVD
R
27
OSEN
R/W
Internal oscillator enable.
0 = Internal oscillator disabled (default)
1 = Internal oscillator enabled.
26
SMIROUTE
R/W
SMI interrupt routing. Bit 26 selects whether IRQ2 or CSC is signaled when a write occurs to power
a PC Card socket.
0 = PC Card power change interrupts routed to IRQ2 (default)
1 = A CSC interrupt is generated on PC Card power changes.
25
SMISTATUS
R/C
SMI interrupt status. This bit is set when bit 24 (SMIENB) is set and a write occurs to set the socket
power. Writing a 1 to bit 25 clears the status.
0 = SMI interrupt signaled (default)
1 = SMI interrupt not signaled
24
SMIENB
R/W
SMI interrupt mode enable. When bit 24 is set and a write to the socket power control occurs, the SMI
interrupt signaling is enabled and generates an interrupt. This bit is shared and defaults to 0 (disabled).
23
RSVD
R
22
CBRSVD
R/W
21
VCCPROT
R/W
20
REDUCEZV
R/W
00 = INTA signaled in INTA IRQSER slots
01 = INTA signaled in INTB IRQSER slots
10 = INTA signaled in INTC IRQSER slots
11 = INTA signaled in INTD IRQSER slots
Reserved. Bits 29 and 28 return 0s when read.
Reserved. Bit 23 returns 0 when read.
CardBus reserved terminals signaling. When a CardBus card is inserted and bit 22 is set, the RSVD
CardBus terminals are driven low. When this bit is 0, these signals are placed in a high-impedance
state.
0 = Place CardBus RSVD in a high‘–impedance state
1 = Drive Cardbus RSVD low (default)
VCC protection enable.
0 = VCC protection enabled for 16-bit cards (default)
1 = VCC protection disabled for 16-bit cards
Reduced zoomed video enable. When this bit is enabled, pins ADDR25–ADDR22 of the card interface
for PC Card-16 cards are placed in the high-impedance state. This bit should not be set for normal ZV
operation. This bit is encoded as:
0 = Reduced zoomed video disabled (default)
1 = Reduced zoomed video enabled
19
CDREQEN
R/W
PC/PCI DMA card enable. When bit 19 is set, the PCI1410 allows 16-bit PC Cards to request PC/PCI
DMA using the DREQ signaling. DREQ is selected through the socket DMA register (offset 94h, see
Section 4.35).
0 = Ignore DREQ signaling from PC Cards (default)
1 = Signal DMA request on DREQ
18–16
CDMACHAN
R/W
PC/PCI DMA channel assignment. Bits 18–16 are encoded as:
0–3 = 8-bit DMA channels
4 = Not used (default)
5–7 = 16-bit DMA channels
15
MRBURSTDN
R/W
Memory read burst enable downstream. When bit 15 is set, memory read transactions are allowed to
burst downstream.
0 = Downstream memory read burst is disabled.
1 = Downstream memory read burst is enabled (default).
R/W
Memory read burst enable upstream. When bit 14 is set, the PCI1410 allows memory read transactions
to burst upstream.
0 = Upstream memory read burst is disabled (default).
1 = Upstream memory read burst is enabled.
14
MRBURSTUP
4–17
Table 4–7. System Control Register (Continued)
BIT
SIGNAL
TYPE
FUNCTION
13
SOCACTIVE
R
Socket activity status. When set, bit 13 indicates access has been performed to or from a PC card and
is cleared upon read of this status bit.
0 = No socket activity (default)
1 = Socket activity
12
RSVD
R
Reserved. Bit 12 returns 1 when read.
11
PWRSTREAM
R
Power stream in progress status bit. When set, bit 11 indicates that a power stream to the power switch
is in progress and a powering change has been requested. This bit is cleared when the power stream
is complete.
0 = Power stream is complete and delay has expired.
1 = Power stream is in progress.
10
DELAYUP
R
Power-up delay in progress status. When set, bit 9 indicates that a power-up stream has been sent to
the power switch and proper power may not yet be stable. This bit is cleared when the power-up delay
has expired.
9
DELAYDOWN
R
Power-down delay in progress status. When set, bit 10 indicates that a power-down stream has been
sent to the power switch and proper power may not yet be stable. This bit is cleared when the
power-down delay has expired.
R
Interrogation in progress. When set, bit 8 indicates an interrogation is in progress and clears when
interrogation completes. This bit is socket dependent.
0 = Interrogation not in progress (default)
1 = Interrogation in progress
8
7
AUTOPWRSWEN
R/W
Auto power switch enable.
0 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is disabled (default).
1 = Bit 5 (AUTOPWRSWEN) in ExCA power control register (ExCA offset 02h, see Section 5.3)
is enabled.
6
PWRSAVINGS
R/W
Power savings mode enable. When this bit is set, if a CB card is inserted, idle, and without a CB clock,
then the applicable CB state machine will not be clocked.
5
SUBSYSRW
R/W
Subsystem ID (see Section 4.27), subsystem vendor ID (see Section 4.26), ExCA identification and
revision (see Section 5.1) registers read/write enable.
0 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read/write.
1 = Subsystem ID, subsystem vendor ID, ExCA identification and revision registers are read-only
(default).
4
CB_DPAR
R/W
CardBus data parity SERR signaling enable
0 = CardBus data parity not signaled on PCI SERR
1 = CardBus data parity signaled on PCI SERR
3
CDMA_EN
R/W
PC/PCI DMA enable. Bit 3 enables PC/PCI DMA when set if MFUNC0–MFUNC6 are configured for
centralized DMA.
0 = Centralized DMA disabled (default)
1 = Centralized DMA enabled
2
ExCAPower
R/W
ExCA power control bit. Enabled by selecting the 82365SL mode.
0 = Enables 3.3 V
1 = Enables 5 V
1
KEEPCLK
R/W
Keep clock. This bit works with PCI and CB CLKRUN protocols.
0 = Allows normal functioning of both CLKRUN protocols (default)
1 = Does not allow CB clock or PCI clock to be stopped using the CLKRUN protocols
R/W
RI_OUT/PME multiplex enable.
0 = RI_OUT and PME are both routed to the RI_OUT/PME terminal. If both are enabled at the
same time, then RI_OUT has precedence over PME.
1 = Only PME is routed to the RI_OUT/PME terminal.
0
4–18
INTERROGATE
RIMUX
4.30 Multifunction Routing Register
The multifunction routing register is used to configure the MFUNC0–MFUNC6 terminals. These terminals may be
configured for various functions. All multifunction terminals default to the general-purpose input configuration. This
register is intended to be programmed once at power-on initialization. The default value for this register may also be
loaded through a serial bus EEPROM. See Table 4–8 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
Multifunction routing
Type
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Multifunction routing
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Multifunction routing
8Ch
Read-only, Read/Write
0000 0000h
Table 4–8. Multifunction Routing Register
BIT
SIGNAL
TYPE
31–28
RSVD
R
27–24
23–20
MFUNC6
MFUNC5
FUNCTION
Bits 31–28 return 0s when read.
R/W
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = CLKRUN
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
R/W
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0100 = IRQ4
1000 = CAUDPWM
1100 = LED_SKT
0001 = GPO4
0101 = RSVD
1001 = IRQ9
1101 = LED_SKT
0010 = PCGNT
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ15
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
19–16
MFUNC4
R/W
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC4 terminal provides the SCL signaling.
0000 = GPI3
0001 = GPO3
0010 = LOCK PCI
0011 = IRQ3
15–12
11–8
MFUNC3
MFUNC2
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
1111 = IRQ15
R/W
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = IRQSER
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
R/W
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2
0100 = IRQ4
1000 = CAUDPWM
1100 = RI_OUT
0001 = GPO2
0101 = IRQ5
1001 = IRQ9
1101 = RSVD
0010 = PCREQ
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ7
4–19
Table 4–8. Multifunction Routing Register (Continued)
BIT
SIGNAL
TYPE
FUNCTION
Multifunction terminal 1 configuration. These bits control the internal signal mapped to the MFUNC1 terminal
as follows:
7–4
MFUNC1
NOTE: When the serial bus mode is implemented by pulling up the VCCD0 and VCCD1 terminals, the
MFUNC1 terminal provides the SDA signaling.
R/W
0000 = GPI1
0001 = GPO1
0010 = RSVD
0011 = IRQ3
3–0
MFUNC0
R/W
0100 = IRQ4
0101 = IRQ5
0110 = ZVSTAT
0111 = ZVSEL0
1000 = CAUDPWM
1001 = IRQ9
1010 = IRQ10
1011 = IRQ11
1100 = LED_SKT
1101 = IRQ13
1110 = GPE
1111 = IRQ15
Multifunction terminal 0 configuration. These bits control the internal signal mapped to the MFUNC0 terminal
as follows:
0000 = GPI0
0100 = IRQ4
1000 = CAUDPWM
1100 = LED_SKT
0001 = GPO0
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = INTA
0110 = ZVSTAT
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = ZVSEL0
1011 = IRQ11
1111 = IRQ15
4.31 Retry Status Register
The retry status register enables the retry timeout counters and displays the retry expiration status. The flags are set
when the PCI1410 retries a PCI or CardBus master request and the master does not return within 215 PCI clock
cycles. The flags are cleared by writing a 1 to the bit. These bits are expected to be incorporated into the PCI
command, PCI status, and bridge control registers by the PCI SIG. See Table 4–9 for a complete description of the
register contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Retry status
R/W
R/W
R
R
R/C
R
R/C
R
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Retry status
90h
Read-only, Read/Write, Read/Clear
C0h
Table 4–9. Retry Status Register
4–20
BIT
SIGNAL
TYPE
FUNCTION
7
PCIRETRY
R/W
PCI retry timeout counter enable. Bit 7 is encoded:
0 = PCI retry counter disabled
1 = PCI retry counter enabled (default)
6
CBRETRY
R/W
CardBus retry timeout counter enable. Bit 6 is encoded:
0 = CardBus retry counter disabled
1 = CardBus retry counter enabled (default)
5–4
RSVD
R
3
TEXP_CB
R/C
2
RSVD
R
1
TEXP_PCI
R/C
0
RSVD
R
Reserved. Bits 5 and 4 return 0s when read.
CardBus target retry expired. Write a 1 to clear bit 3.
0 = Inactive (default)
1 = Retry has expired.
Reserved. Bit 2 returns 0 when read.
PCI target retry expired. Write a 1 to clear bit 1.
0 = Inactive (default)
1 = Retry has expired.
Reserved. Bit 0 returns 0 when read.
4.32 Card Control Register
The card control register is provided for PCI1130 compatibility. RI_OUT is enabled through this register. See
Table 4–10 for a complete description of the register contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Card control
R/W
R/W
R/W
R
R
R/W
R/W
R/C
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Card control
91h
Read-only, Read/Write, Read/Clear
00h
Table 4–10. Card Control Register
BIT
SIGNAL
TYPE
FUNCTION
7
RIENB
R/W
Ring indicate output enable.
0 = Disables any routing of RI_OUT signal (default).
1 = Enables RI_OUT signal for routing to the RI_OUT/PME terminal, when bit 0 (RIMUX) in the system
control register (see Section 4.29) is set to 0, and for routing to MFUNC2 or MFUNC4.
6
ZVENABLE
R/W
Compatibility ZV mode enable. When set, the PC Card socket interface ZV terminals enter a
high-impedance state. This bit defaults to 0.
This bit has no assigned function.
5
No function
R/W
4–3
RSVD
R
2
AUD2MUX
R/W
CardBus audio-to-IRQMUX. When set, the CAUDIO CardBus signal is routed to the corresponding
multifunction terminal which may be configured for CAUDPWM.
R/W
Speaker out enable. When bit 1 is set, SPKR on the PC Card is enabled and is routed to SPKROUT. The
SPKROUT terminal drives data only when the socket SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
R/C
Interrupt flag. Bit 0 is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. Bit 0 is set when a
functional interrupt is signaled from a PC Card interface. Write back a 1 to clear this bit.
0 = No PC Card functional interrupt detected (default).
1 = PC Card functional interrupt detected.
1
0
SPKROUTEN
IFG
Reserved. Bits 4 and 3 return 0 when read.
4–21
4.33 Device Control Register
The device control register is provided for PCI1130 compatibility. The interrupt mode select and the socket-capable
force bits are programmed through this register. See Table 4–11 for a complete description of the register contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Device control
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
0
1
1
0
0
1
1
0
Register:
Offset:
Type:
Default:
Device control
92h
Read-only, Read/Write
66h
Table 4–11. Device Control Register
4–22
BIT
SIGNAL
TYPE
FUNCTION
7
SKTPWR_LOCK
R/W
Socket power lock bit. When this bit is set to 1, software will not be able to power down the PC Card
socket while in D3. This may be necessary to support wake on LAN or RING if the operating system
is programmed to power down a socket when the CardBus controller is placed in the D3 state.
6
3VCAPABLE
R/W
3-V socket capable force
0 = Not 3-V capable
1 = 3-V capable (default)
5
IO16V2
R/W
Diagnostic bit. This bit defaults to 1.
4
RSVD
R
Reserved. Bit 4 returns 0 when read.
3
TEST
R/W
TI test. Only a 0 should be written to bit 3.
2–1
INTMODE
R/W
Interrupt signaling mode. Bits 2 and 1 select the interrupt signaling mode. The interrupt signaling
mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Parallel IRQ and parallel PCI interrupts
10 = IRQ serialized interrupts and parallel PCI interrupt
11 = IRQ and PCI serialized interrupts (default)
0
RSVD
R/W
Reserved. Bit 0 is reserved for test purposes. Only 0 should be written to this bit.
4.34 Diagnostic Register
The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s should be written
to it. See Table 4–12 for a complete description of the register contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Diagnostic
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
0
1
Register:
Offset:
Type:
Default:
Diagnostic
93h
Read/Write
21h
Table 4–12. Diagnostic Register
BIT
SIGNAL
TYPE
FUNCTION
7
TRUE_VAL
R/W
This bit defaults to 0. This bit is encoded as:
0 = Reads true values in PCI vendor ID and PCI device ID registers (default)
1 = Reads all 1s in the PCI vendor ID and PCI device ID registers
6
RSVD
R/W
Reserved. Bit 6 returns 0 when read.
5
CSC
R/W
CSC interrupt routing control
0 = CSC interrupts routed to PCI if ExCA 803 (see Section 5.4) bit 4 = 1
1 = CSC interrupts routed to PCI if ExCA 805 (see Section 5.6) bits 7–4 = 0000b (default)
In this case, the setting of ExCA 803 bit 4 is a don’t care.
4
DIAG4
R/W
Diagnostic RETRY_DIS. Delayed transaction disable.
3
DIAG3
R/W
2
DIAG2
R/W
Diagnostic RETRY_EXT. Extends the latency from 16 to 64.
Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215.
1
DIAG1
R/W
Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.
0
ASYNCINT
R/W
Asynchronous interrupt enable.
0 = CSC interrupt is not generated asynchronously
1 = CSC interrupt is generated asynchronously (default)
4–23
4.35 Socket DMA Register 0
The socket DMA register 0 provides control over the PC Card DMA request (DREQ) signaling. See Table 4–13 for
a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
Socket DMA register 0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Socket DMA register 0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket DMA register 0
94h
Read-only, Read/Write
0000 0000h
Table 4–13. Socket DMA Register 0
BIT
SIGNAL
TYPE
31–2
RSVD
R
1–0
4–24
DREQPIN
R/W
FUNCTION
Reserved. Bits 31–2 return 0s when read.
DMA request (DREQ). Bits 1 and 0 indicate which pin on the 16-bit PC Card interface acts as DREQ during
DMA transfers. This field is encoded as:
00 = Socket not configured for DMA (default).
01 = DREQ uses SPKR.
10 = DREQ uses IOIS16.
11 = DREQ uses INPACK.
4.36 Socket DMA Register 1
The socket DMA register 1 provides control over the distributed DMA (DDMA) registers and the PCI portion of DMA
transfers. The DMA base address locates the DDMA registers in a 16-byte region within the first 64K bytes of PCI
I/O address space. See Table 4–14 for a complete description of the register contents.
NOTE:32-bit transfers are not supported; the maximum transfer possible for 16-bit PC Cards
is 16 bits.
Bit
31
30
29
28
27
26
25
Name
Type
24
23
22
21
20
19
18
17
16
Socket DMA register 1
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Socket DMA register 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket DMA register 1
98h
Read-only, Read/Write
0000 0000h
Table 4–14. Socket DMA Register 1
BIT
SIGNAL
TYPE
31–16
RSVD
R
15–4
DMABASE
R/W
3
EXTMODE
R
2–1
0
XFERSIZE
DDMAEN
FUNCTION
Reserved. Bits 31–16 return 0s when read.
DMA base address. Locates the socket’s DMA registers in PCI I/O space. This field represents a 16-bit PCI
I/O address. The upper 16 bits of the address are hardwired to 0, forcing this window to within the lower 64K
bytes of I/O address space. The lower 4 bits are hardwired to 0 and are included in the address decode.
Thus, the window is aligned to a natural 16-byte boundary.
Extended addressing. This feature is not supported by the PCI4410 and always returns a 0.
R/W
Transfer size. Bits 2 and 1 specify the width of the DMA transfer on the PC Card interface and are
encoded as:
00 = Transfers are 8 bits (default).
01 = Transfers are 16 bits.
10 = Reserved
11 = Reserved
R/W
DDMA registers decode enable. Enables the decoding of the distributed DMA registers based on the value
of bits 15–4 (DMABASE field).
0 = Disabled (default)
1 = Enabled
4–25
4.37 Capability ID Register
The capability ID register identifies the linked list item as the register for PCI power management. The register returns
01h when read, which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and
the value.
Bit
7
6
5
4
Name
3
2
1
0
Capability ID
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register:
Offset:
Type:
Default:
Capability ID
A0h
Read-only
01h
4.38 Next-Item Pointer Register
The next-item pointer register indicates the next item in the linked list of the PCI power management capabilities.
Because the PCI1410 functions include only one capabilities item, this register returns 0s when read.
Bit
7
6
5
Name
4
3
2
1
0
Next-item pointer
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
4–26
Next-item pointer
A1h
Read-only
00h
4.39 Power Management Capabilities Register
This register contains information on the capabilities of the PC Card function related to power management. Both
PCI1410 CardBus bridge functions support D0, D1, D2, and D3 power states. See Table 4–15 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
Power management capabilities
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
1
1
1
1
1
1
0
0
0
1
0
0
0
0
1
Register:
Offset:
Type:
Default:
Power management capabilities
A2h
Read/Write, Read-only
FE21h
Table 4–15. Power Management Capabilities Register
BIT
SIGNAL
TYPE
FUNCTION
PME support. This 5-bit field indicates the power states from which the PCI1410 device functions may
assert PME. A 0 (zero) for any bit indicates that the function cannot assert the PME signal while in that
power state. These five bits return 11111b when read. Each of these bits is described below:
15
PME_Support
R/W
Bit 15 defaults to the value 1 indicating the PME signal can be asserted from the D3cold state. This bit is
R/W because wake-up support from D3cold is contingent on the system providing an auxiliary power source
to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to the VCC
terminals for D3cold wake-up support, then BIOS should write a 0 to this bit.
14–11
PME_Support
R
10
D2_Support
R
D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device
power state.
9
D1_Support
R
D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device
power state.
8–6
RSVD
R
Reserved. Bits 8–6 return 0s when read.
5
DSI
R
Device-specific initialization. Bit 5 returns 1 when read, indicating that the CardBus controller function
requires special initialization (beyond the standard PCI configuration header) before the generic class
device driver is able to use it.
4
AUX_PWR
R
Auxiliary power source. Bit 4 is meaningful only if bit 15 (PME_Support, D3cold) is set. When bit 4 is set,
it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way of a
proprietary delivery vehicle. When bit 4 is 0, it indicates that the function supplies its own auxiliary power
source.
3
PMECLK
R
PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the PCI1410 to
generate PME.
2–0
VERSION
R
Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power
management (PM) registers as described in the PCI Bus Power Management Interface Specification.
Bit 14 contains the value 1, indicating that the PME signal can be asserted from D3hot state.
Bit 13 contains the value 1, indicating that the PME signal can be asserted from D2 state.
Bit 12 contains the value 1, indicating that the PME signal can be asserted from D1 state.
Bit 11 contains the value 1, indicating that the PME signal can be asserted from the D0 state.
4–27
4.40 Power Management Control/Status Register
The power management control/status register determines and changes the current power state of the PCI1410
CardBus function. The contents of this register are not affected by the internally-generated reset caused by the
transition from D3hot to D0 state. All PCI, ExCA, and CardBus registers are reset as a result of a D3hot to D0 state
transition. TI-specific registers, PCI power management registers, and the legacy base address register are not reset.
See Table 4–16 for a complete description of the register contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
Power management control/status
R/C
R
R
R
R
R
R
R/W
R
R
R
R
R
R
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power management control/status
A4h
Read-only, Read/Write, Read/Write to Clear
0000h
Table 4–16. Power Management Control/Status Register
BIT
SIGNAL
TYPE
FUNCTION
15
PMESTAT
R/C
PME status. Bit 15 is set when the CardBus function would normally assert PME, independent
of the state of bit 8 (PME_EN). Bit 15 is cleared by a write back of 1, and this also clears the PME
signal if PME was asserted by this function. Writing a 0 to this bit has no effect.
14–13
DATASCALE
R
Data scale. This 2-bit field returns 0s when read. The CardBus function does not return any
dynamic data as indicated by bit 4 (DYN_DATA_PME_EN).
12–9
DATASEL
R
Data select. This 4-bit field returns 0s when read. The CardBus function does not return any
dynamic data as indicated by bit 4 (DYN_DATA_PME_EN).
8
PME_EN
R/W
PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, then assertion of PME
is disabled.
7–5
RSVD
R
Reserved. Bits 7–5 return 0s when read.
4
DYN_DATA_PME_EN
R
Dynamic data PME enable. Bit 4 returns 0 when read since the CardBus function does not report
dynamic data.
3–2
RSVD
R
Reserved. Bits 3–2 return 0s when read.
1–0
4–28
PWR_STATE
R/W
Power state. This 2-bit field is used both to determine the current power state of a function and
to set the function into a new power state. This field is encoded as:
00 = D0
01 = D1
10 = D2
11 = D3hot
4.41 Power Management Control/Status Bridge Support Extensions Register
The power management control/status register bridge support extensions support PCI bridge specific functionality.
See Table 4–17 for a complete description of the register contents.
Bit
7
6
Name
5
4
3
2
1
0
Power management control/status bridge support extensions
Type
R
R
R
R
R
R
R
R
Default
1
1
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power management control/status bridge support extensions
A6h
Read-only
C0h
Table 4–17. Power Management Control/Status Bridge Support Extensions Register
BIT
7
SIGNAL
BPCC_EN
TYPE
FUNCTION
R
BPCC_Enable. Bus power/clock control enable. This bit returns 1 when read.
This bit is encoded as:
0 = Bus power/clock control is disabled.
1 = Bus power/clock control is enabled (default).
A 0 indicates that the bus power/clock control policies defined in the PCI Bus Power Management
Interface Specification are disabled. When the bus power/clock control enable mechanism is disabled,
the bridge power management control/status register power state field (see Section 4.40, bits 1–0)
cannot be used by the system software to control the power or the clock of the bridge secondary bus. A
1 indicates that the bus power/clock control mechanism is enabled.
6
B2_B3
R
B2/B3 support for D3hot. The state of this bit determines the action that is to occur as a direct result of
programming the function to D3hot. This bit is only meaningful if bit 7 (BPCC_EN) is a 1. This bit is encoded
as:
0 = When the bridge is programmed to D3hot, its secondary bus will have its power removed (B3).
1 = When the bridge function is programmed to D3hot, its secondary bus PCI clock will be
stopped (B2). (Default)
5–0
RSVD
R
Reserved. Bits 5–0 return 0s when read.
4.42 Power Management Data Register
The power management data register returns 0s when read, since the CardBus functions do not report dynamic data.
Bit
7
6
5
Name
4
3
2
1
0
Power management data
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Power management data
A7h
Read-only
00h
4–29
4.43 General-Purpose Event Status Register
The general-purpose event status register contains status bits that are set when events occur that are controlled by
the general-purpose control register. The bits in this register and the corresponding GPE are cleared by writing a 1
to the corresponding bit location. The status bits in this register do not depend upon the state of a corresponding bit
in the general-purpose enable register. See Table 4–18 for a complete description of the register contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
General-purpose event status
R/C
R
R
R
R/C
R
R
R/C
R
R
R
R/C
R/C
R/C
R/C
R/C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose event status
A8h
Read-only, Read/Write to Clear
0000h
Table 4–18. General-Purpose Event Status Register
BIT
SIGNAL
TYPE
FUNCTION
15
ZV_STS
R/C
PC card ZV status. Bit 15 is set on a change in status of bit 6 (ZVENABLE) in the card control register
(offset 91h, see Section 4.32).
14–12
RSVD
R
11
PWR_STS
R/C
10–9
RSVD
R
8
VPP12_STS
R/C
4–30
Reserved. Bits 14–12 return 0s when read.
Power change status. Bit 11 is set when software has changed the power state of the socket. A change
in either VCC or VPP for the socket causes this bit to be set.
Reserved. Bits 10 and 9 return 0s when read.
12-Volt VPP request status. Bit 8 is set when software has changed the requested Vpp level to or from
12 Volts for the PC Card socket.
7–5
RSVD
R
4
GP4_STS
R/C
Reserved. Bits 7–5 return 0s when read.
GPI4 status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.
3
GP3_STS
R/C
GPI3 status. Bit 3 is set on a change in status of the MFUNC4 terminal input level.
2
GP2_STS
R/C
GPI2 status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.
1
GP1_STS
R/C
GPI1 status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.
0
GP0_STS
R/C
GPI0 status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.
4.44 General-Purpose Event Enable Register
The general-purpose event enable register contains bits that are set to enable a GPE signal. The GPE signal is driven
until the corresponding status bit is cleared and the event is serviced. The GPE can only be signaled if one of the
multifunction terminals, MFUNC6–MFUNC0, is configured for GPE signaling. See Table 4–19 for a complete
description of the register contents.
Bit
15
14
13
12
11
10
Name
Type
Default
9
8
7
6
5
4
3
2
1
0
General-purpose event enable
R/W
R
R
R
R/W
R
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose event enable
AAh
Read-only, Read/Write
0000h
Table 4–19. General-Purpose Event Enable Register
BIT
SIGNAL
TYPE
FUNCTION
15
ZV_EN
R/W
PC card socket ZV enable. When bit 15 is set, a GPE is signaled on a change in status of bit 6 (ZVENABLE)
in the card control register (offset 91h, see Section 4.32).
14–12
RSVD
R
11
PWR_EN
R/W
10–9
RSVD
R
8
VPP12_EN
R/W
7–5
RSVD
R
4
GP4_EN
R/W
GPI4 enable. When bit 4 is set, a GPE is signaled when there has been a change in status of the MFUNC5
terminal input level if configured as GPI4.
3
GP3_EN
R/W
GPI3 enable. When bit 3 is set, a GPE is signaled when there has been a change in status of the MFUNC4
terminal input level if configured as GPI3.
2
GP2_EN
R/W
GPI2 enable. When bit 2 is set, a GPE is signaled when there has been a change in status of the MFUNC2
terminal input if configured as GPI2.
1
GP1_EN
R/W
GPI1 enable. When bit 1 is set, a GPE is signaled when there has been a change in status of the MFUNC1
terminal input if configured as GPI1.
0
GP0_EN
R/W
GPI0 enable. When bit 0 is set, a GPE is signaled when there has been a change in status of the MFUNC0
terminal input if configured as GPI0.
Reserved. Bits 14–12 return 0s when read.
Power change enable. When bit 11 is set, a GPE is signaled when software has changed the power state
of the socket.
Reserved. Bits 10 and 9 return 0s when read.
12 Volt VPP request enable. When bit 8 is set, a GPE is signaled when software has changed the requested
VPP level to or from 12 Volts for the card socket.
Reserved. Bits 7–5 return 0s when read.
4–31
4.45 General-Purpose Input Register
The general-purpose input register provides the logical value of the data input from the GPI terminals, MFUNC5,
MFUNC4, and MFUNC2–MFUNC0. See Table 4–20 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
Name
8
7
6
5
4
3
2
1
0
General-purpose input
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
Register:
Offset:
Type:
Default:
General-purpose input
ACh
Read-only
00XXh
Table 4–20. General-Purpose Input Register
4–32
BIT
SIGNAL
TYPE
FUNCTION
15–5
RSVD
R
Reserved. Bits 15–5 return 0s when read.
4
GPI4_DATA
R
GPI4 data bit. The value read from bit 4 represents the logical value of the data input from the MFUNC5
terminal.
3
GPI3_DATA
R
GPI3 data bit. The value read from bit 3 represents the logical value of the data input from the MFUNC4
terminal.
2
GPI2_DATA
R
GPI2 data bit. The value read from bit 2 represents the logical value of the data input from the MFUNC2
terminal.
1
GPI1_DATA
R
GPI1 data bit. The value read from bit 1 represents the logical value of the data input from the MFUNC1
terminal.
0
GPI0_DATA
R
GPI0 data bit. The value read from bit 0 represents the logical value of the data input from the MFUNC0
terminal.
4.46 General-Purpose Output Register
The general-purpose output register is used for control of the general-purpose outputs. See Table 4–21 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
Name
9
8
7
6
5
4
3
2
1
0
General-purpose output
Type
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General-purpose output
AEh
Read-only, Read/Write
0000h
Table 4–21. General-Purpose Output Register
BIT
SIGNAL
TYPE
15–5
RSVD
R
FUNCTION
4
GPO4_DATA
R/W
GPO4 data bit. The value written to bit 4 represents the logical value of the data driven to the MFUNC5
terminal if configured as GPO4. Read transactions return the last data value written.
3
GPO3_DATA
R/W
GPIO3 data bit. The value written to bit 3 represents the logical value of the data driven to the MFUNC4
terminal if configured as GPO3. Read transactions return the last data value written.
2
GPO2_DATA
R/W
GPO2 data bit. The value written to bit 2 represents the logical value of the data driven to the MFUNC2
terminal if configured as GPO2. Read transactions return the last data value written.
1
GPO1_DATA
R/W
GPO1 data bit. The value written to bit 1 represents the logical value of the data driven to the MFUNC1
terminal if configured as GPO1. Read transactions return the last data value written.
0
GPO0_DATA
R/W
GPO0 data bit. The value written to bit 0 represents the logical value of the data driven to the MFUNC0
terminal if configured as GPO0. Read transactions return the last data value written.
Reserved. Bits 15–5 return 0s when read.
4.47 Serial Bus Data Register
The serial bus data register is for programmable serial bus byte reads and writes. This register represents the data
when generating cycles on the serial bus interface. See Table 4–22 for a complete description of the register
contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
Serial bus data
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus data
B0h
Read/Write
00h
Table 4–22. Serial Bus Data Register
BIT
7–0
SIGNAL
SBDATA
TYPE
FUNCTION
R/W
Serial bus data. This bit field represents the data byte in a read or write transaction on the serial interface.
On reads, the REQBUSY bit (bit 5) in the serial bus control and status register (offset B3h, see Section 4.50)
must be polled to verify that the contents of this register are valid.
4–33
4.48 Serial Bus Index Register
The serial bus index register is for programmable serial bus byte reads and writes. This register represents the byte
address when generating cycles on the serial bus interface. See Table 4–23 for a complete description of the register
contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
Serial bus index
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus index
B1h
Read/Write
00h
Table 4–23. Serial Bus Index Register
BIT
SIGNAL
TYPE
FUNCTION
7–0
SBINDEX
R/W
Serial bus index. This bit field represents the byte address in a read or write transaction on the serial interface.
4.49 Serial Bus Slave Address Register
The serial bus slave address register is for programmable serial bus byte read and write transactions. See Table 4–24
for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
Serial bus slave address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus slave address
B2h
Read/Write
00h
Table 4–24. Serial Bus Slave Address Register
BIT
7–1
0
4–34
SIGNAL
SLAVADDR
RWCMD
TYPE
FUNCTION
R/W
Serial bus slave address. This bit field represents the slave address of a read or write transaction on the
serial interface.
R/W
Read/write command. Bit 0 indicates the read/write command bit presented to the serial bus on byte read
and write accesses
0 = A byte write access is requested to the serial bus interface
1 = A byte read access is requested to the serial bus interface
4.50 Serial Bus Control and Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 4–25 for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
Serial bus control and status
R/W
R
R
R
R/C
R/W
R/C
R/C
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus control and status
B3h
Read-only, Read/Write, Read/Clear
00h
Table 4–25. Serial Bus Control and Status Register
BIT
SIGNAL
TYPE
FUNCTION
7
PROT_SEL
R/W
Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte
protocol is used on read commands. The word address byte (SBINDEX) in the serial bus index register (see
Section 4.48) is not output by the PCI1410 when bit 7 is set.
6
RSVD
R
Reserved. Bit 6 returns 0 when read.
5
REQBUSY
R
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.49). Bit 5 must be polled on reads from the serial bus interface. After the byte read access has
been requested, the read data is valid in the serial bus data register.
R
Serial EEPROM busy status. Bit 4 indicates the status of the PCI1410 serial EEPROM circuitry. Bit 4 is set
during the loading of the subsystem ID and other default values from the serial bus EEPROM.
0 = Serial EEPROM circuitry is not busy
1 = Serial EEPROM circuitry is busy
4
ROMBUSY
3
SBDETECT
R/C
Serial bus detect. Bit 3 is set when the serial bus interface is detected through pullup resistors on the VCCD0
and VCCD1 terminals after reset. If bit 3 is cleared, then the MFUNC4 and MFUNC1 terminals can be used
for alternate functions such as general-purpose inputs and outputs.
0 = Serial bus interface not detected
1 = Serial bus interface detected
2
SBTEST
R/W
Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock at normal operating frequency, 100 kHz (default)
1 = Serial bus clock frequency increased for test purposes
R/C
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.
0 = No error detected during user requested byte read or write cycle
1 = Data error detected during user requested byte read or write cycle
R/C
EEPROM data error status. Bit 0 indicates when a data error occurs on the serial bus interface during the
auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set on
invalid EEPROM data formats. See Section 3.6.1, Serial Bus Interface Implementation, for details on
EEPROM data format. Bit 0 is cleared by a write back of 1.
0 = No error detected during auto-load from serial bus EEPROM
1 = Data error detected during auto-load from serial bus EEPROM
1
0
REQ_ERR
ROM_ERR
4–35
4–36
5 ExCA Compatibility Registers
The ExCA registers implemented in the PCI1410 are register-compatible with the Intel 82365SL–DF PCMCIA
controller. ExCA registers are identified by an offset value that is compatible with the legacy I/O index/data scheme
used on the Intel 82365 ISA controller. The ExCA registers are accessed through this scheme by writing the register
offset value into the index register (I/O base) and reading or writing the data register (I/O base + 1). The I/O base
address used in the index/data scheme is programmed in the PC Card 16-bit I/F legacy mode base address register
(offset 44h, see Section 4.28). The offsets from this base address run contiguous from 00h to 3Fh for the socket. See
Figure 5–1 for an ExCA I/O mapping illustration.
Host I/O Space
PCI1410 Configuration Registers
Offset
Offset
CardBus Socket/ExCA Base Address
10h
PC Card
ExCA
Registers
Index
Data
16-Bit Legacy-Mode Base Address
00h
3Fh
44h
Figure 5–1. ExCA Register Access Through I/O
The TI PCI1410 also provides a memory-mapped alias of the ExCA registers by directly mapping them into PCI
memory space. They are located through the CardBus socket/ExCA base address register (offset 10h, see
Section 4.12) at memory offset 800h. See Figure 5–2 for an ExCA memory mapping illustration. This illustration also
identifies the CardBus socket register mapping, which is mapped into the same 4K window at memory offset 0h.
PCI1410 Configuration Registers
Offset
Host
Memory Space
Offset
00h
CardBus Socket/ExCA Base Address
10h
CardBus
Socket
Registers
20h
800h
16-Bit Legacy-Mode Base Address
44h
ExCA
Registers
844h
Figure 5–2. ExCA Register Access Through Memory
5–1
The interrupt registers in the ExCA register set, as defined by the 82365SL–DL specification, control such card
functions as reset, type, interrupt routing, and interrupt enables. Special attention must be paid to the interrupt routing
registers and the host interrupt signaling method selected for the PCI1410 to ensure that all possible PCI1410
interrupts can potentially be routed to the programmable interrupt controller. The ExCA registers that are critical to
the interrupt signaling are the ExCA interrupt and general control register (ExCA offset 03h, see Section 5.4) and the
ExCA card status-change-interrupt configuration register (ExCA offset 05h, see Section 5.6).
Access to I/O mapped 16-bit PC cards is available to the host system via two ExCA I/O windows. These are regions
of host I/O address space into which the card I/O space is mapped. These windows are defined by start, end, and
offset addresses programmed in the ExCA registers described in this section. I/O windows have byte granularity.
Access to memory mapped 16-bit PC Cards is available to the host system via five ExCA memory windows. These
are regions of host memory space into which the card memory space is mapped. These windows are defined by start,
end, and offset addresses programmed in the ExCA registers described in this section. Table 5–1 identifies each
ExCA register and its respective ExCA offset. Memory windows have 4K-byte granularity.
Table 5–1. ExCA Registers and Offsets
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
Identification and revision
800
00
Interface status
801
01
Power control
802
02
Interrupt and general control
803
03
Card status-change
804
04
Card status-change-interrupt configuration
805
05
Address window enable
806
06
I / O window control
807
07
I / O window 0 start-address low-byte
808
08
EXCA REGISTER NAME
5–2
I / O window 0 start-address high-byte
809
09
I / O window 0 end-address low-byte
80A
0A
I / O window 0 end-address high-byte
80B
0B
I / O window 1 start-address low-byte
80C
0C
I / O window 1 start-address high-byte
80D
0D
I / O window 1 end-address low-byte
80E
0E
I / O window 1 end-address high-byte
80F
0F
Memory window 0 start-address low-byte
810
10
Memory window 0 start-address high-byte
811
11
Memory window 0 end-address low-byte
812
12
Memory window 0 end-address high-byte
813
13
Memory window 0 offset-address low-byte
814
14
Memory window 0 offset-address high-byte
815
15
Card detect and general control
816
16
Reserved
817
17
Memory window 1 start-address low-byte
818
18
Memory window 1 start-address high-byte
819
19
Memory window 1 end-address low-byte
81A
1A
Memory window 1 end-address high-byte
81B
1B
Memory window 1 offset-address low-byte
81C
1C
Memory window 1 offset-address high-byte
81D
1D
Table 5–1. ExCA Registers and Offsets (Continued)
PCI MEMORY ADDRESS
OFFSET (HEX)
ExCA OFFSET
(HEX)
Global control
81E
1E
Reserved
81F
1F
Memory window 2 start-address low-byte
820
20
Memory window 2 start-address high-byte
821
21
Memory window 2 end-address low-byte
822
22
Memory window 2 end-address high-byte
823
23
Memory window 2 offset-address low-byte
824
24
Memory window 2 offset-address high-byte
825
25
Reserved
826
26
Reserved
827
27
Memory window 3 start-address low-byte
828
28
EXCA REGISTER NAME
Memory window 3 start-address high-byte
829
29
Memory window 3 end-address low-byte
82A
2A
Memory window 3 end-address high-byte
82B
2B
Memory window 3 offset-address low-byte
82C
2C
Memory window 3 offset-address high-byte
82D
2D
Reserved
82E
2E
Reserved
82F
2F
Memory window 4 start-address low-byte
830
30
Memory window 4 start-address high-byte
831
31
Memory window 4 end-address low-byte
832
32
Memory window 4 end-address high-byte
833
33
Memory window 4 offset-address low-byte
834
34
Memory window 4 offset-address high-byte
835
35
I/O window 0 offset-address low-byte
836
36
I/O window 0 offset-address high-byte
837
37
I/O window 1 offset-address low-byte
838
38
I/O window 1 offset-address high-byte
839
39
Reserved
83A
3A
Reserved
83B
3B
Reserved
83C
3C
Reserved
83D
3D
Reserved
83E
3E
Reserved
83F
3F
Memory window 0 page
840
–
Memory window 1 page
841
–
Memory window 2 page
842
–
Memory window 3 page
843
–
Memory window 4 page
844
–
5–3
5.1 ExCA Identification and Revision Register
The ExCA identification and revision register provides host software with information on 16-bit PC Card support and
Intel 82365SL-DF compatibility. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (see Section 4.29). See Table 5–2 for a complete description of the
register contents.
Bit
7
6
5
Name
4
3
2
1
0
ExCA identification and revision
Type
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Default
1
0
0
0
0
1
0
0
Register:
Offset:
Type:
Default:
ExCA identification and revision
CardBus socket address + 800h; ExCA offset 00h
Read-only, Read/Write
84h
Table 5–2. ExCA Identification and Revision Register
5–4
BIT
SIGNAL
TYPE
FUNCTION
7–6
IFTYPE
R
Interface type. These bits, which are hardwired as 10b, identify the 16-bit PC Card support provided by the
PCI1410. The PCI1410 supports both I/O and memory 16-bit PC cards.
5–4
RSVD
R/W
Reserved. Bits 5 and 4 can be used for Intel 82365SL-DF emulation.
3–0
365REV
R/W
Intel 82365SL-DF revision. This field stores the Intel 82365SL-DF revision supported by the PCI1410. Host
software can read this field to determine compatibility to the Intel 82365SL-DF register set. Writing 0010b to
this field puts the controller in 82365SL mode. This field defaults to 0100b upon PCI1410 reset.
5.2 ExCA Interface Status Register
The ExCA interface status register provides information on the current status of the PC Card interface. An X in the
default bit value indicates that the value of the bit after reset depends on the state of the PC Card interface. See
Table 5–3 for a complete description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
ExCA interface status
Type
R
R
R
R
R
R
R
R
Default
0
0
X
X
X
X
X
X
Register:
Offset:
Type:
Default:
ExCA interface status
CardBus socket address + 801h; ExCA offset 01h
Read-only
00XX XXXXb
Table 5–3. ExCA Interface Status Register
BIT
SIGNAL
TYPE
FUNCTION
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
6
CARDPWR
R
Card Power. Bit 6 indicates the current power status of the PC Card socket. This bit reflects how the ExCA
power control register (ExCA offset 02h, see Section 5.3) is programmed. Bit 6 is encoded as:
0 = VCC and VPP to the socket turned off (default)
1 = VCC and VPP to the socket turned on
5
READY
R
Ready. Bit 5 indicates the current status of the READY signal at the PC Card interface.
0 = PC Card not ready for data transfer
1 = PC Card ready for data transfer
R
Card write protect. Bit 4 indicates the current status of WP at the PC Card interface. This signal reports to
the PCI1410 whether or not the memory card is write protected. Furthermore, write protection for an entire
PCI1410 16-bit memory window is available by setting the appropriate bit in the ExCA memory window
offset-address high-byte register (see Section 5.18).
0 = WP is 0. PC Card is read/write.
1 = WP is 1. PC Card is read-only.
R
Card detect 2. Bit 3 indicates the status of CD2 at the PC Card interface. Software may use this and bit 2
(CDETECT1) to determine if a PC Card is fully seated in the socket.
0 = CD2 is 1. No PC Card is inserted.
1 = CD2 is 0. PC Card is at least partially inserted.
R
Card detect 1. Bit 2 indicates the status of CD1 at the PC Card interface. Software may use this and bit 3
(CDETECT2) to determine if a PC Card is fully seated in the socket.
0 = CD1 is 1. No PC Card is inserted.
1 = CD1 is 0. PC Card is at least partially inserted.
4
3
2
1–0
CARDWP
CDETECT2
CDETECT1
BVDSTAT
R
Battery voltage detect. When a 16-bit memory card is inserted, the field indicates the status of the battery
voltage detect signals (BVD1, BVD2) at the PC Card interface, where bit 1 reflects the BVD2 status and bit 0
reflects BVD1.
00 = Battery dead
01 = Battery dead
10 = Battery low; warning
11 = Battery good
When a 16-bit I/O card is inserted, this field indicates the status of SPKR (bit 1) and STSCHG (bit 0) at the
PC Card interface. In this case, the two bits in this field directly reflect the current state of these card outputs.
5–5
5.3 ExCA Power Control Register
The ExCA power control register provides PC Card power control. Bit 7 (COE) of this register controls the 16-bit output
enables on the socket interface, and can be used for power management in 16-bit PC Card applications. See
Table 5–4 and Table 5–5 for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
ExCA power control
R/W
R
R
R/W
R/W
R
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA power control
CardBus socket address + 802h; ExCA offset 02h
Read-only, Read/Write
00h
Table 5–4. ExCA Power Control Register 82365SL Support
BIT
SIGNAL
TYPE
FUNCTION
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410. This bit is
encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
7
COE
R/W
6
RSVD
R
5
AUTOPWRSWEN
R/W
Auto power switch enable. This bit is enabled by bit 7 of the system control register (offset 80h, see
Section 4.29).
0 = Automatic socket power switching based on card detects is disabled.
1 = Automatic socket power switching based on card detects is enabled.
PC Card power enable.
0 = VCC = VPP1 = VPP2 = No connection
1 = VCC is enabled and controlled by bit 2 (ExCAPower) of the system control register
(offset 80h, see Section 4.29), VPP1 and VPP2 are controlled according to bits 1–0
(EXCAVPP field).
4
CAPWREN
R/W
3–2
RSVD
R
1–0
5–6
EXCAVPP
Reserved. Bit 6 returns 0 when read.
R/W
Reserved. Bits 3 and 2 return 0s when read.
PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI1410 ignores
this field unless VCC to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as:
00 = No connection (default)
01 = VCC
10 = 12 V
11 = Reserved
Table 5–5. ExCA Power Control Register 82365SL-DF Support
BIT
SIGNAL
TYPE
FUNCTION
7
COE
R/W
Card output enable. Bit 7 controls the state of all of the 16-bit outputs on the PCI1410. This bit is encoded as:
0 = 16-bit PC Card outputs disabled (default)
1 = 16-bit PC Card outputs enabled
6–5
RSVD
R
4–3
EXCAVCC
R/W
2
RSVD
R
1–0
EXCAVPP
R/W
Reserved. Bits 6 and 5 return 0s when read.
VCC. Bits 4 and 3 are used to request changes to card VCC. This field is encoded as:
00 = 0 V (default)
01 = 0 V reserved
10 = 5 V
11 = 3.3 V
Reserved. Bit 2 returns 0 when read.
PC Card VPP power control. Bits 1 and 0 are used to request changes to card VPP. The PCI1410 ignores
this field unless VCC to the socket is enabled (that is, 5 V or 3.3 V). This field is encoded as:
00 = No connection (default)
01 = VCC
10 = 12 V
11 = Reserved
5–7
5.4 ExCA Interrupt and General Control Register
The ExCA interrupt and general control register controls interrupt routing for I/O interrupts, as well as other critical
16-bit PC Card functions. See Table 5–6 for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
ExCA interrupt and general control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA interrupt and general control
CardBus socket address + 803h; ExCA offset 03h
Read/Write
00h
Table 5–6. ExCA Interrupt and General Control Register
BIT
SIGNAL
TYPE
7
RINGEN
R/W
Card ring indicate enable. Bit 7 enables the ring indicate function of BVD1/RI. This bit is encoded as:
0 = Ring indicate disabled (default)
1 = Ring indicate enabled
6
RESET
R/W
Card reset. Bit 6 controls the 16-bit PC Card RESET, and allows host software to force a card reset. Bit 6
affects 16-bit cards only. This bit is encoded as:
0 = RESET signal asserted (default)
1 = RESET signal deasserted
5
CARDTYPE
R/W
Card type. Bit 5 indicates the PC Card type. This bit is encoded as:
0 = Memory PC Card installed (default)
1 = I/O PC Card installed
R/W
PCI interrupt CSC routing enable bit. When bit 4 is set (high), the card status change interrupts are routed
to PCI interrupts. When low, the card status change interrupts are routed using bits 7–4 (CSCSELECT field)
in the ExCA card status change interrupt configuration register (ExCA offset 05h, see Section 5.6). This bit
is encoded as:
0 = CSC interrupts are routed by ExCA registers (default).
1 = CSC interrupts are routed to PCI interrupts.
R/W
Card interrupt select for I/O PC Card functional interrupts. Bits 3–0 select the interrupt routing for I/O
PC Card functional interrupts. This field is encoded as:
0000 = No interrupt routing (default). CSC interrupts routed to PCI interrupts. This bit setting is
ORed with bit 4 (CSCROUTE) for backwards compatibility.
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0100 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
4
3–0
5–8
FUNCTION
CSCROUTE
INTSELECT
5.5 ExCA Card Status-Change Register
The ExCA card status-change register controls interrupt routing for I/O interrupts as well as other critical 16-bit PC
Card functions. The register enables these interrupt sources to generate an interrupt to the host. When the interrupt
source is disabled, the corresponding bit in this register always reads 0. When an interrupt source is enabled, the
corresponding bit in this register is set to indicate that the interrupt source is active. After generating the interrupt to
the host, the interrupt service routine must read this register to determine the source of the interrupt. The interrupt
service routine is responsible for resetting the bits in this register as well. Resetting a bit is accomplished by one of
two methods: a read of this register or an explicit writeback of 1 to the status bit. The choice of these two methods
is based on bit 2 (interrupt flag clear mode select) in the ExCA global control register (see Section 5.20). See
Table 5–7 for a complete description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
ExCA card status-change
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card status-change
CardBus socket address + 804h; ExCA offset 04h
Read-only
00h
Table 5–7. ExCA Card Status-Change Register
BIT
SIGNAL
TYPE
7–4
RSVD
R
Reserved. Bits 7–4 return 0s when read.
R
Card detect change. Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface.
This bit is encoded as:
0 = No change detected on either CD1 or CD2
1 = Change detected on either CD1 or CD2
3
2
CDCHANGE
READYCHANGE
R
FUNCTION
Ready change. When a 16-bit memory is installed in the socket, bit 2 includes whether the source of a
PCI1410 interrupt was due to a change on READY at the PC Card interface, indicating that the PC Card
is now ready to accept new data. This bit is encoded as:
0 = No low-to-high transition detected on READY (default)
1 = Detected low-to-high transition on READY
When a 16-bit I/O card is installed, bit 2 is always 0.
1
BATWARN
R
Battery warning change. When a 16-bit memory card is installed in the socket, bit 1 indicates whether the
source of a PCI1410 interrupt was due to a battery-low warning condition. This bit is encoded as:
0 = No battery warning condition (default)
1 = Detected battery warning condition
When a 16-bit I/O card is installed, bit 1 is always 0.
0
BATDEAD
R
Battery dead or status change. When a 16-bit memory card is installed in the socket, bit 0 indicates whether
the source of a PCI1410 interrupt was due to a battery dead condition. This bit is encoded as:
0 = STSCHG deasserted (default)
1 = STSCHG asserted
Ring indicate. When the PCI1410 is configured for ring indicate operation, bit 0 indicates the status of RI.
5–9
5.6 ExCA Card Status-Change-Interrupt Configuration Register
The ExCA card status-change-interrupt configuration register controls interrupt routing for card status-change
interrupts, as well as masking CSC interrupt sources. See Table 5–8 for a complete description of the register
contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
ExCA status-change-interrupt configuration
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card status-change-interrupt configuration
CardBus socket address + 805h; ExCA offset 05h
Read/Write
00h
Table 5–8. ExCA Card Status-Change-Interrupt Configuration Register
BIT
SIGNAL
TYPE
FUNCTION
Interrupt select for card status change. Bits 7–4 select the interrupt routing for card status change
interrupts.
0000 = CSC interrupts routed to PCI interrupts if bit 5 (CSC) of the diagnostic register (offset 93h, see
Section 4.34) is set to 1. In this case bit 4 (CSCROUTE) of the ExCA interrupt and general control register
(ExCA offset 03h, see Section 5.4) is a don’t care . This is the default setting.
0000 = No ISA interrupt routing if bit 5 (CSC) of the diagnostic register (offset 93h, see Section 4.34) is
set to 0. In this case, CSC interrupts are routed to PCI interrupts by setting bit 4 (CSCROUTE) of the ExCA
interrupt and general control register to 1 (see Section 5.4).
7–4
R/W
This field is encoded as:
0000 = No interrupt routing (default)
0001 = IRQ1 enabled
0010 = SMI enabled
0011 = IRQ3 enabled
0100 = IRQ4 enabled
0101 = IRQ5 enabled
0110 = IRQ6 enabled
0111 = IRQ7 enabled
1000 = IRQ8 enabled
1001 = IRQ9 enabled
1010 = IRQ10 enabled
1011 = IRQ11 enabled
1100 = IRQ12 enabled
1101 = IRQ13 enabled
1110 = IRQ14 enabled
1111 = IRQ15 enabled
3
CDEN
R/W
Card detect enable. Bit 3 enables interrupts on CD1 or CD2 changes. This bit is encoded as:
0 = Disables interrupts on CD1 or CD2 line changes (default)
1 = Enables interrupts on CD1 or CD2 line changes
2
READYEN
R/W
Ready enable. Bit 2 enables/disables a low-to-high transition on PC Card READY to generate a host
interrupt. This interrupt source is considered a card status change. This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
1
BATWARNEN
R/W
Battery warning enable. Bit 1 enables/disables a battery warning condition to generate a CSC interrupt.
This bit is encoded as:
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
R/W
Battery dead enable. Bit 0 enables/disables a battery dead condition on a memory PC Card or assertion
of the STSCHG I/O PC Card signal to generate a CSC interrupt.
0 = Disables host interrupt generation (default)
1 = Enables host interrupt generation
0
5–10
CSCSELECT
BATDEADEN
5.7 ExCA Address Window Enable Register
The ExCA address window enable register enables/disables the memory and I/O windows to the 16-bit PC Card. By
default, all windows to the card are disabled. The PCI1410 does not acknowledge PCI memory or I/O cycles to the
card if the corresponding enable bit in this register is 0, regardless of the programming of the memory or I/O window
start/end/offset address registers. See Table 5–9 for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
ExCA address window enable
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA address window enable
CardBus socket address + 806h; ExCA offset 06h
Read-only, Read/Write
00h
Table 5–9. ExCA Address Window Enable Register
BIT
SIGNAL
TYPE
FUNCTION
7
IOWIN1EN
R/W
I/O window 1 enable. Bit 7 enables/disables I/O window 1 for the PC Card. This bit is encoded as:
0 = I/O window 1 disabled (default)
1 = I/O window 1 enabled
6
IOWIN0EN
R/W
I/O window 0 enable. Bit 6 enables/disables I/O window 0 for the PC Card. This bit is encoded as:
0 = I/O window 0 disabled (default)
1 = I/O window 0 enabled
5
RSVD
R
Reserved. Bit 5 returns 0 when read.
4
MEMWIN4EN
R/W
Memory window 4 enable. Bit 4 enables/disables memory window 4 for the PC Card. This bit is
encoded as:
0 = Memory window 4 disabled (default)
1 = Memory window 4 enabled
3
MEMWIN3EN
R/W
Memory window 3 enable. Bit 3 enables/disables memory window 3 for the PC Card. This bit is
encoded as:
0 = Memory window 3 disabled (default)
1 = Memory window 3 enabled
2
MEMWIN2EN
R/W
Memory window 2 enable. Bit 2 enables/disables memory window 2 for the PC Card. This bit is
encoded as:
0 = Memory window 2 disabled (default)
1 = Memory window 2 enabled
R/W
Memory window 1 enable. Bit 1 enables/disables memory window 1 for the PC Card. This bit is
encoded as:
0 = Memory window 1 disabled (default)
1 = Memory window 1 enabled
R/W
Memory window 0 enable. Bit 0 enables/disables memory window 0 for the PC Card. This bit is
encoded as:
0 = Memory window 0 disabled (default)
1 = Memory window 0 enabled
1
0
MEMWIN1EN
MEMWIN0EN
5–11
5.8 ExCA I/O Window Control Register
The ExCA I/O window control register contains parameters related to I/O window sizing and cycle timing. See
Table 5–10 for a complete description of the register contents.
Bit
7
6
5
Name
Type
Default
4
3
2
1
0
ExCA I/O window control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA I/O window control
CardBus socket address + 807h; ExCA offset 07h
Read/Write
00h
Table 5–10. ExCA I/O Window Control Register
BIT
7
6
5
4
3
2
1
0
5–12
SIGNAL
WAITSTATE1
ZEROWS1
IOSIS16W1
DATASIZE1
WAITSTATE0
ZEROWS0
IOSIS16W0
DATASIZE0
TYPE
FUNCTION
R/W
I/O window 1 wait state. Bit 7 controls the I/O window 1 wait state for 16-bit I/O accesses. Bit 7 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
R/W
I/O window 1 zero wait state. Bit 6 controls the I/O window 1 wait state for 8-bit I/O accesses. Bit 6 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
R/W
I/O window 1 IOIS16 source. Bit 5 controls the I/O window 1 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width determined by DATASIZE1, bit 4 (default).
1 = Window data width determined by IOIS16.
R/W
I/O window 1 data size. Bit 4 controls the I/O window 1 data size. Bit 4 is ignored if bit 5 (IOSIS16W1) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
R/W
I/O window 0 wait state. Bit 3 controls the I/O window 0 wait state for 16-bit I/O accesses. Bit 3 has no effect
on 8-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel 82365SL-DF. This
bit is encoded as:
0 = 16-bit cycles have standard length (default).
1 = 16-bit cycles are extended by one equivalent ISA wait state.
R/W
I/O window 0 zero wait state. Bit 2 controls the I/O window 0 wait state for 8-bit I/O accesses. Bit 2 has
no effect on 16-bit accesses. This wait-state timing emulates the ISA wait state used by the Intel
82365SL-DF. This bit is encoded as:
0 = 8-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
R/W
I/O window 0 IOIS16 source. Bit 1 controls the I/O window 0 automatic data sizing feature that uses IOIS16
from the PC Card to determine the data width of the I/O data transfer. This bit is encoded as:
0 = Window data width is determined by DATASIZE0, bit 0 (default).
1 = Window data width is determined by IOIS16.
R/W
I/O window 0 data size. Bit 0 controls the I/O window 0 data size. Bit 0 is ignored if bit 1 (IOSIS16W0) is
set. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the start address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA I/O windows 0 and 1 start-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 start-address low-byte
CardBus socket address + 808h; ExCA offset 08h
ExCA I/O window 1 start-address low-byte
CardBus socket address + 80Ch; ExCA offset 0Ch
Read/Write
00h
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window start address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the start address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA I/O windows 0 and 1 start-address high-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 start-address high-byte
CardBus socket address + 809h; ExCA offset 09h
ExCA I/O window 1 start-address high-byte
CardBus socket address + 80Dh; ExCA offset 0Dh
Read/write
00h
5–13
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the lower 8 bits of the end address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA I/O windows 0 and 1 end-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 end-address low-byte
CardBus socket address + 80Ah; ExCA offset 0Ah
ExCA I/O window 1 end-address low-byte
CardBus socket address + 80Eh; ExCA offset 0Eh
Read/Write
00h
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window end address for I/O windows 0 and 1. The 8 bits of these
registers correspond to the upper 8 bits of the end address.
Bit
7
6
Name
Type
Default
4
3
2
1
0
ExCA I/O windows 0 and 1 end-address high-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
5–14
5
ExCA I/O window 0 end-address high-byte
CardBus socket address + 80Bh; ExCA offset 0Bh
ExCA I/O window 1 end-address high-byte
CardBus socket address + 80Fh; ExCA offset 0Fh
Read/write
00h
5.13 ExCA Memory Windows 0–4 Start-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the start address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA memory windows 0–4 start-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 start-address low-byte
CardBus socket address + 810h; ExCA offset 10h
ExCA memory window 1 start-address low-byte
CardBus socket address + 818h; ExCA offset 18h
ExCA memory window 2 start-address low-byte
CardBus socket address + 820h; ExCA offset 20h
ExCA memory window 3 start-address low-byte
CardBus socket address + 828h; ExCA offset 28h
ExCA memory window 4 start-address low-byte
CardBus socket address + 830h; ExCA offset 30h
Read/Write
00h
5–15
5.14 ExCA Memory Windows 0–4 Start-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the start address. In addition, the memory
window data width and wait states are set in this register. See Table 5–11 for a complete description of the register
contents.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA memory windows 0–4 start-address high byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 start-address high-byte
CardBus socket address + 811h; ExCA offset 11h
ExCA memory window 1 start-address high-byte
CardBus socket address + 819h; ExCA offset 19h
ExCA memory window 2 start-address high-byte
CardBus socket address + 821h; ExCA offset 21h
ExCA memory window 3 start-address high-byte
CardBus socket address + 829h; ExCA offset 29h
ExCA memory window 4 start-address high-byte
CardBus socket address + 831h; ExCA offset 31h
Read/Write
00h
Table 5–11. ExCA Memory Windows 0–4 Start-Address High-Byte Registers
5–16
BIT
SIGNAL
TYPE
FUNCTION
7
DATASIZE
R/W
Data size. Bit 7 controls the memory window data width. This bit is encoded as:
0 = Window data width is 8 bits (default).
1 = Window data width is 16 bits.
6
ZEROWAIT
R/W
Zero wait state. Bit 6 controls the memory window wait state for 8- and 16-bit accesses. This wait-state timing
emulates the ISA wait state used by the Intel 82365SL-DF. This bit is encoded as:
0 = 8- and 16-bit cycles have standard length (default).
1 = 8-bit cycles are reduced to equivalent of three ISA cycles.
16-bit cycles are reduced to equivalent of two ISA cycles.
5–4
SCRATCH
R/W
Scratch pad bits. Bits 5 and 4 have no effect on memory window operation.
3–0
STAHN
R/W
Start-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window
start address.
5.15 ExCA Memory Windows 0–4 End-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the end address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA memory windows 0–4 end-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 end-address low-byte
CardBus socket address + 812h; ExCA offset 12h
ExCA memory window 1 end-address low-byte
CardBus socket address + 81Ah; ExCA offset 1Ah
ExCA memory window 2 end-address low-byte
CardBus socket address + 822h; ExCA offset 22h
ExCA memory window 3 end-address low-byte
CardBus socket address + 82Ah; ExCA offset 2Ah
ExCA memory window 4 end-address low-byte
CardBus socket address + 832h; ExCA offset 32h
Read/Write
00h
5–17
5.16 ExCA Memory Windows 0–4 End-Address High-Byte Registers
These registers contain the high nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3,
and 4. The lower 4 bits of these registers correspond to bits A23–A20 of the end address. In addition, the memory
window wait states are set in this register. See Table 5–12 for a complete description of the register contents.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA memory windows 0–4 end-address high-byte
R/W
R/W
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 end-address high-byte
CardBus socket address + 813h; ExCA offset 13h
ExCA memory window 1 end-address high-byte
CardBus socket address + 81Bh; ExCA offset 1Bh
ExCA memory window 2 end-address high-byte
CardBus socket address + 823h; ExCA offset 23h
ExCA memory window 3 end-address high-byte
CardBus socket address + 82Bh; ExCA offset 2Bh
ExCA memory window 4 end-address high-byte
CardBus socket address + 833h; ExCA offset 33h
Read-only, Read/Write
00h
Table 5–12. ExCA Memory Windows 0–4 End-Address High-Byte Registers
5–18
BIT
SIGNAL
TYPE
FUNCTION
7–6
MEMWS
R/W
Wait state. Bits 7 and 6 specify the number of equivalent ISA wait states to be added to 16-bit memory
accesses. The number of wait states added is equal to the binary value of these two bits.
5–4
RSVD
R
3–0
ENDHN
R/W
Reserved. Bits 5 and 4 return 0s when read.
End-address high nibble. Bits 3–0 represent the upper address bits A23–A20 of the memory window end
address.
5.17 ExCA Memory Windows 0–4 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and
4. The 8 bits of these registers correspond to bits A19–A12 of the offset address.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA memory windows 0–4 offset-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 offset-address low-byte
CardBus socket address + 814h; ExCA offset 14h
ExCA memory window 1 offset-address low-byte
CardBus socket address + 81Ch; ExCA offset 1Ch
ExCA memory window 2 offset-address low-byte
CardBus socket address + 824h; ExCA offset 24h
ExCA memory window 3 offset-address low-byte
CardBus socket address + 82Ch; ExCA offset 2Ch
ExCA memory window 4 offset-address low-byte
CardBus socket address + 834h; ExCA offset 34h
Read/Write
00h
5–19
5.18 ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
These registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3,
and 4. The lower 6 bits of these registers correspond to bits A25–A20 of the offset address. In addition, the write
protection and common/attribute memory configurations are set in this register. See Table 5–13 for a complete
description of the register contents.
Bit
7
6
Name
Type
5
4
3
2
1
0
ExCA memory windows 0–4 offset-address high-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Default
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA memory window 0 offset-address high-byte
CardBus socket address + 815h; ExCA offset 15h
ExCA memory window 1 offset-address high-byte
CardBus socket address + 81Dh; ExCA offset 1Dh
ExCA memory window 2 offset-address high-byte
CardBus socket address + 825h; ExCA offset 25h
ExCA memory window 3 offset-address high-byte
CardBus socket address + 82Dh; ExCA offset 2Dh
ExCA memory window 4 offset-address high-byte
CardBus socket address + 835h; ExCA offset 35h
Read/Write
00h
Table 5–13. ExCA Memory Windows 0–4 Offset-Address High-Byte Registers
5–20
BIT
SIGNAL
TYPE
FUNCTION
7
WINWP
R/W
Write protect. Bit 7 specifies whether write operations to this memory window are enabled. This bit is
encoded as:
0 = Write operations are allowed (default).
1 = Write operations are not allowed.
6
REG
R/W
Bit 6 specifies whether this memory window is mapped to card attribute or common memory. This bit is encoded
as:
0 = Memory window is mapped to common memory (default).
1 = Memory window is mapped to attribute memory.
5–0
OFFHB
R/W
Offset-address high byte. Bits 5–0 represent the upper address bits A25–A20 of the memory window
offset address.
5.19 ExCA Card Detect and General Control Register
The ExCA card detect and general control register controls how the ExCA registers for the socket respond to card
removal, as well as reports the status of VS1 and VS2 at the PC Card interface. See Table 5–14 for a complete
description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
ExCA I/O card detect and general control
Type
R
R
R/W
R/W
R
R
R/W
R
Default
X
X
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA card detect and general control
CardBus socket address + 816h; ExCA offset 16h
Read-only, Read/Write
XX00 0000b
Table 5–14. ExCA Card Detect and General Control Register
BIT
7
6
5
SIGNAL
VS2STAT
VS1STAT
SWCSC
TYPE
FUNCTION
R
VS2 state. Bit 7 reports the current state of VS2 at the PC Card interface and, therefore, does not have
a default value.
0 = VS2 low
1 = VS2 high
R
VS1 state. Bit 6 reports the current state of VS1 at the PC Card interface and, therefore, does not have
a default value.
0 = VS1 low
1 = VS1 high
R/W
Software card detect interrupt. If bit 3 (CDEN) in the ExCA card status-change-interrupt configuration
register is set (ExCA offset 05h, see Section 5.6), then writing a 1 to bit 5 causes a card-detect
card-status-change interrupt for the associated card socket. If bit 3 (CDEN) in the ExCA card
status-change-interrupt configuration register is cleared to 0 (see Section 5.6), then writing a 1 to bit 5 has
no effect. A read operation of this bit always returns 0.
Card detect resume enable. If bit 4 is set to 1, then once a card detect change has been detected on CD1
and CD2 inputs, RI_OUT goes from high to low. RI_OUT remains low until bit 0 (card status change) in
the ExCA card status-change register is cleared (ExCA offset 04h, see Section 5.5). If this bit is a 0, then
the card detect resume functionality is disabled.
0 = Card detect resume disabled (default)
1 = Card detect resume enabled
4
CDRESUME
R/W
3–2
RSVD
R
1
REGCONFIG
R/W
0
RSVD
R
Reserved. Bits 3 and 2 return 0s when read.
Register configuration on card removal. Bit 1 controls how the ExCA registers for the socket react to a card
removal event. This bit is encoded as:
0 = No change to ExCA registers on card removal (default)
1 = Reset ExCA registers on card removal
Reserved. Bit 0 returns 0 when read.
5–21
5.20 ExCA Global Control Register
The ExCA global control register controls the PC Card socket. The host interrupt mode bits in this register are retained
for Intel 82365SL-DF compatibility. See Table 5–15 for a complete description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
ExCA global control
Type
R
R
R
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
ExCA global control
CardBus socket address + 81Eh; ExCA offset 1Eh
Read-only, Read/Write
00h
Table 5–15. ExCA Global Control Register
BIT
TYPE
FUNCTION
7–5
RSVD
R
4
No function
R/W
This bit has no assigned function.
R/W
Level/edge interrupt mode select. Bit 3 selects the signaling mode for the PCI1410 host interrupt. This bit
is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
R/W
Interrupt flag clear mode select. Bit 2 selects the interrupt flag clear mechanism for the flags in the ExCA
card status change register (ExCA offset 04h, see Section 5.5). This bit is encoded as:
0 = Interrupt flags are cleared by read of CSC register (default).
1 = Interrupt flags are cleared by explicit writeback of 1.
R/W
Card status change level/edge mode select. Bit 1 selects the signaling mode for the PCI1410 host interrupt
for card status changes. This bit is encoded as:
0 = Host interrupt is edge mode (default).
1 = Host interrupt is level mode.
R/W
Power-down mode select. When bit 0 is set to 1, the PCI1410 is in power-down mode. In power-down mode,
the PCI1410 card outputs are high impedance until an active cycle is executed on the card interface.
Following an active cycle, the outputs are again high impedance. The PCI1410 still receives DMA requests,
functional interrupts, and/or card status change interrupts; however, an actual card access is required to
wake up the interface. This bit is encoded as:
0 = Power-down mode is disabled (default).
1 = Power-down mode is enabled.
3
2
1
0
5–22
SIGNAL
INTMODE
IFCMODE
CSCMODE
PWRDWN
Reserved. Bits 7–5 return 0s when read.
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers
These registers contain the low byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0.
Bit
7
6
Name
Type
Default
5
4
3
2
1
0
ExCA I/O windows 0 and 1 offset-address low-byte
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 offset-address low-byte
CardBus socket address + 836h; ExCA offset 36h
ExCA I/O window 1 offset-address low-byte
CardBus socket address + 838h; ExCA offset 38h
Read-only, Read/Write
00h
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers
These registers contain the high byte of the 16-bit I/O window offset address for I/O windows 0 and 1. The 8 bits of
these registers correspond to the upper 8 bits of the offset address.
Bit
7
6
5
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Name
Type
Default
4
3
2
1
0
R/W
R/W
R/W
0
0
0
ExCA I/O windows 0 and 1 offset-address high-byte
Register:
Offset:
Register:
Offset:
Type:
Default:
ExCA I/O window 0 offset-address high-byte
CardBus socket address + 837h; ExCA offset 37h
ExCA I/O window 1 offset-address high-byte
CardBus socket address + 839h; ExCA offset 39h
Read/Write
00h
5–23
5.23 ExCA Memory Windows 0–4 Page Register
The upper 8 bits of a 4-byte PCI memory address are compared to the contents of this register when decoding
addresses for 16-bit memory windows. Each window has its own page register, all of which default to 00h. By
programming this register to a nonzero value, host software can locate 16-bit memory windows in any 1 of 256
16-Mbyte regions in the 4G-byte PCI address space. These registers are only accessible when the ExCA registers
are memory mapped, that is, these registers cannot be accessed using the index/data I/O scheme.
Bit
7
6
5
Name
Type
Default
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Register:
Offset:
Type:
Default:
5–24
4
ExCA memory windows 0–4 page
ExCA memory window 0 page
CardBus socket address + 840h
ExCA memory window 1 page
CardBus socket address + 841h
ExCA memory window 2 page
CardBus socket address + 842h
ExCA memory window 3 page
CardBus socket address + 843h
ExCA memory window 4 page
CardBus socket address + 844h
Read/Write
00h
6 CardBus Socket Registers
The 1997 PC Card Standard requires a CardBus socket controller to provide five 32-bit registers that report and
control socket-specific functions. The PCI1410 provides the CardBus socket/ExCA base address register (offset 10h,
see Section 4.12) to locate these CardBus socket registers in PCI memory address space (see Figure 6–1).
Table 6–1 gives the location of the socket registers in relation to the CardBus socket/ExCA base address.
The PCI1410 implements an additional register at offset 20h that provides power management control for the socket.
PCI1410 Configuration Registers
Offset
Host
Memory Space
Offset
00h
CardBus Socket/ExCA Base Address
CardBus
Socket
Registers
10h
20h
800h
16-Bit Legacy-Mode Base Address
ExCA
Registers
44h
844h
Figure 6–1. Accessing CardBus Socket Registers Through PCI Memory
Table 6–1. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
00h
Socket mask
04h
Socket present state
08h
Socket force event
0Ch
Socket control
10h
Reserved
14h
Reserved
18h
Reserved
1Ch
Socket power management
20h
6–1
6.1 Socket Event Register
The socket event register indicates a change in socket status has occurred. These bits do not indicate what the
change is, only that one has occurred. Software must read the socket present state register (CardBus offset 08h, see
Section 6.3) for current status. Bits 31–4 of this register are reserved and return 0 when read. The following discussion
describes bits 3–0. Each bit can be cleared by writing a 1 to that bit. The bits can be set to a 1 by software by writing
a 1 to the corresponding bit in the socket force event register (see Section 6.4). All bits are cleared by PCI reset. They
can be immediately set again if, when coming out of PC Card reset, the bridge finds the status unchanged (that is,
CSTSCHG reasserted or card detect is still true). Software must clear this register before enabling interrupts. If it is
not cleared when interrupts are enabled, then an interrupt is generated (but not masked) based on any bit that is set.
See Table 6–2 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Socket event
Name
Socket event
Type
R
R
R
R
R
R
R
R
R
R
R
R
R/C
R/C
R/C
R/C
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket event
CardBus socket address + 00h
Read-only, Read/Write to Clear
0000 0000h
Table 6–2. Socket Event Register
6–2
BIT
SIGNAL
TYPE
31–4
RSVD
R
FUNCTION
3
PWREVENT
R/C
Power cycle. Bit 3 is set when the PCI1410 detects that bit 3 (PWRCYCLE) in the socket present state
register (CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
2
CD2EVENT
R/C
CCD2. Bit 2 is set when the PCI1410 detects that bit 2 (CDETECT2) in the socket present state register
(CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
1
CD1EVENT
R/C
CCD1. Bit 3 is set when the PCI1410 detects that bit 1 (CDETECT1) in the socket present state register
(CardBus offset 08h, see Section 6.3) has changed state. This bit is cleared by writing a 1.
0
CSTSEVENT
R/C
CSTSCHG. Bit 0 is set when bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h,
see Section 6.3) has changed state. For CardBus cards, bit 0 is set on the rising edge of CSTSCHG. For
16-bit PC Cards, bit 0 is set on both transitions of CSTSCHG. This bit is reset by writing a 1.
Reserved. Bits 31–4 return 0s when read.
6.2 Socket Mask Register
The socket mask register allows software to control the CardBus card events that generate a status change interrupt.
The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register
(CardBus offset 00h, see Section 6.1). See Table 6–3 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Socket mask
Name
Socket mask
Type
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
Socket mask
Read-only, Read/Write
CardBus socket address + 04h
0000 0000h
Table 6–3. Socket Mask Register
BIT
SIGNAL
TYPE
31–4
RSVD
R
3
PWRMASK
FUNCTION
Reserved. Bits 31–4 return 0s when read.
R/W
Power cycle. Bit 3 masks bit 3 (PWRCYCLE) in the socket present state register (CardBus offset 08h, see
Section 6.3) from causing a status change interrupt.
0 = PWRCYCLE event does not cause CSC interrupt (default).
1 = PWRCYCLE event causes CSC interrupt.
2–1
CDMASK
R/W
Card detect mask. Bits 2 and 1 mask bits 1 and 2 (CDETECT1 and CDETECT2) in the socket present state
register (CardBus offset 08h, see Section 6.3) from causing a CSC interrupt.
00 = Insertion/removal does not cause CSC interrupt (default).
01 = Reserved (undefined)
10 = Reserved (undefined)
11 = Insertion/removal causes CSC interrupt.
0
CSTSMASK
R/W
CSTSCHG mask. Bit 0 masks bit 0 (CARDSTS) in the socket present state register (CardBus offset 08h,
see Section 6.3) from causing a CSC interrupt.
0 = CARDSTS event does not cause CSC interrupt (default).
1 = CARDSTS event causes CSC interrupt.
6–3
6.3 Socket Present State Register
The socket present state register reports information about the socket interface. Write transactions to the socket force
event register (CardBus offset 0Ch, see Section 6.4) are reflected here, as well as general socket interface status.
Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI1410
uses CCD1 and CCD2 during card identification, and changes on these signals during this operation are not reflected
in this register. See Table 6–4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Name
24
23
22
21
20
19
18
17
16
Socket present state
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
X
0
0
0
X
X
X
Name
Socket present state
Register:
Offset:
Type:
Default:
Socket present state
CardBus socket address + 08h
Read-only
3000 00XXh
Table 6–4. Socket Present State Register
BIT
SIGNAL
TYPE
FUNCTION
31
YVSOCKET
R
YV socket. Bit 31 indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The PCI1410
does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket force event
register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0.
30
XVSOCKET
R
XV socket. Bit 30 indicates whether or not the socket can supply VCC = X.X V to PC Cards. The PCI1410
does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the socket force event
register (CardBus offset 0Ch, see Section 6.4). This bit is hardwired to 0.
29
3VSOCKET
R
3-V socket. Bit 29 indicates whether or not the socket can supply VCC = 3.3 V to PC Cards. The PCI1410
does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force event
register (CardBus offset 0Ch, see Section 6.4).
28
5VSOCKET
R
5-V socket. Bit 28 indicates whether or not the socket can supply VCC = 5 V to PC Cards. The PCI1410
does support 5-V VCC; therefore, this bit is always set unless overridden by the socket force event register
(CardBus offset 0Ch, see Section 6.4).
27–14
RSVD
R
Reserved. Bits 27–14 return 0s when read.
13
YVCARD
R
YV card. Bit 13 indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y V.
12
XVCARD
R
XV card. Bit 12 indicates whether or not the PC Card inserted in the socket supports VCC = X.X V.
11
3VCARD
R
3-V card. Bit 11 indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 V.
10
5VCARD
R
5-V card. Bit 10 indicates whether or not the PC Card inserted in the socket supports VCC = 5 V.
R
Bad VCC request. Bit 9 indicates that the host software has requested that the socket be powered at an
invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
R
Data lost. Bit 8 indicates that a PC Card removal event may have caused lost data because the cycle did
not terminate properly or because write data still resides in the PCI1410.
0 = Normal operation (default)
1 = Potential data loss due to card removal
R
Not a card. Bit 7 indicates that an unrecognizable PC Card has been inserted in the socket. This bit is not
updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
9
8
7
6–4
BADVCCREQ
DATALOST
NOTACARD
Table 6–4. Socket Present State Register (Continued)
BIT
SIGNAL
TYPE
FUNCTION
6
IREQCINT
R
READY(IREQ)//CINT. Bit 6 indicates the current status of READY(IREQ)//CINT at the PC Card interface.
0 = READY(IREQ)//CINT low
1 = READY(IREQ)//CINT high
5
CBCARD
R
CardBus card detected. Bit 5 indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
4
16BITCARD
R
16-bit card detected. Bit 4 indicates that a 16-bit PC Card is inserted in the socket. This bit is not updated
until another card interrogation sequence occurs (card insertion).
3
PWRCYCLE
R
Power cycle. Bit 3 indicates the status of each card powering request. This bit is encoded as:
0 = Socket powered down (default)
1 = Socket powered up
2
CDETECT2
R
CCD2. Bit 2 reflects the current status of CCD2 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD2 low (PC Card may be present)
1 = CCD2 high (PC Card not present)
1
CDETECT1
R
CCD1. Bit 1 reflects the current status of CCD1 at the PC Card interface. Changes to this signal during
card interrogation are not reflected here.
0 = CCD1 low (PC Card may be present)
1 = CCD1 high (PC Card not present)
0
CARDSTS
R
CSTSCHG. Bit 0 reflects the current status of CSTSCHG at the PC Card interface.
0 = CSTSCHG low
1 = CSTSCHG high
6–5
6.4 Socket Force Event Register
The socket force event register is used to force changes to the socket event register (see Section 6.1) and the socket
present state register (see Section 6.3). Bit 14 (CVSTEST) in this register must be written when forcing changes that
require card interrogation. See Table 6–5 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Socket force event
Name
Socket force event
Type
R
W
W
W
W
W
W
W
W
R
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Type:
Offset:
Default:
6–6
Socket force event
Read-only, Write-only
CardBus socket address + 0Ch
0000 0000h
Table 6–5. Socket Force Event Register
BIT
SIGNAL
TYPE
FUNCTION
31–15
RSVD
R
Reserved. Bits 31–15 return 0s when read.
14
CVSTEST
W
Card VS test. When bit 14 is set, the PCI1410 re-interrogates the PC Card, updates the socket present state
register (CardBus offset 08h, see Section 6.3), and enables the socket control register (CardBus offset 10h,
see Section 6.5).
13
FYVCARD
W
Force YV card. Write transactions to bit 13 cause bit 13 (YVCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
12
FXVCARD
W
Force XV card. Write transactions to bit 12 cause bit 12 (XVCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
11
F3VCARD
W
Force 3-V card. Write transactions to bit 11 cause bit 11 (3VCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
10
F5VCARD
W
Force 5-V card. Write transactions to bit 10 cause bit 10 (5VCARD) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3). When set, this bit disables the socket control register
(CardBus offset 10h, see Section 6.5).
9
FBADVCCREQ
W
Force bad VCC request. Changes to bit 9 (BADVCCREQ) in the socket present state register (CardBus offset
08h, see Section 6.3) can be made by writing to bit 9.
8
FDATALOST
W
Force data lost. Write transactions to bit 8 cause bit 8 (DATALOST) in the socket present state register to
be written (CardBus offset 08h, see Section 6.3).
7
FNOTACARD
W
Force not a card. Write transactions to bit 7 cause bit 7 (NOTACARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
6
RSVD
R
Reserved. Bit 6 returns 0 when read.
5
FCBCARD
W
Force CardBus card. Write transactions to bit 5 cause bit 5 (CBCARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
4
F16BITCARD
W
Force 16-bit card. Write transactions to bit 4 cause bit 4 (16BITCARD) in the socket present state register
to be written (CardBus offset 08h, see Section 6.3).
3
FPWRCYCLE
W
Force power cycle. Write transactions to bit 3 cause bit 3 (PWREVENT) in the socket event register to be
written (CardBus offset 00h, see Section 6.1), and bit 3 (PWRCYCLE) in the socket present state register
is unaffected (CardBus offset 08h, see Section 6.3).
2
FCDETECT2
W
Force CCD2. Write transactions to bit 2 cause bit 2 (CD2EVENT) in the socket event register to be written
(CardBus offset 00h, see Section 6.1), and bit 2 (CDETECT2) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
1
FCDETECT1
W
Force CCD1. Write transactions to bit 1 cause bit 1 (CD1EVENT) in the socket event register to be written
(CardBus offset 00h, see Section 6.1), and bit 1 (CDETECT1) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
0
FCARDSTS
W
Force CSTSCHG. Write transactions to bit 0 cause bit 0 (CSTSEVENT) in the socket event register to be
written (CardBus offset 00h, see Section 6.1), and bit 0 (CARDSTS) in the socket present state register is
unaffected (CardBus offset 08h, see Section 6.3).
6–7
6.5 Socket Control Register
The socket control register provides control of the voltages applied to the socket and instructions for CB CLKRUN
protocol. The PCI1410 ensures that the socket is powered up only at acceptable voltages when a CardBus card is
inserted. See Table 6–6 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Name
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Socket control
Name
Socket control
Type
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket control
CardBus socket address + 10h
Read-only, Read/Write
0000 0000h
Table 6–6. Socket Control Register
BIT
SIGNAL
TYPE
31–8
RSVD
R
7
R/W
CB CLKRUN protocol instructions.
0 = CB CLKRUN protocol can only attempt to stop/slow the CB clock if the socket is idle and the
PCI CLKRUN protocol is preparing to stop/slow the PCI bus clock.
1 = CB CLKRUN protocol can attempt to stop/slow the CB clock if the socket is idle.
VCC control. Bits 6–4 request card VCC changes.
000 = Request power off (default)
100 = Request VCC = X.X V
001 = Reserved
101 = Request VCC = Y.Y V
010 = Request VCC = 5 V
110 = Reserved
011 = Request VCC = 3.3 V
111 = Reserved
6–4
VCCCTRL
R/W
3
RSVD
R
2–0
6–8
STOPCLK
VPPCTRL
FUNCTION
Reserved. Bits 31–8 return 0s when read.
R/W
Reserved. Bit 3 returns 0 when read.
VPP control. Bits 2–0 request card VPP changes.
000 = Request power off (default)
100 = Request VPP = X.X V
001 = Request VPP = 12 V
101 = Request VPP = Y.Y V
010 = Request VPP = 5 V
110 = Reserved
011 = Request VPP = 3.3 V
111 = Reserved
6.6 Socket Power Management Register
This register provides power management control over the socket through a mechanism for slowing or stopping the
clock on the card interface when the card is idle. See Table 6–7 for a complete description of the register contents.
Bit
31
30
29
28
27
26
Type
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
Name
25
24
23
22
21
20
19
18
17
16
R
R
R
R
R
R
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Socket power management
Name
Socket power management
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Socket power management
CardBus socket address + 20h
Read-only, Read/Write
0000 0000h
Table 6–7. Socket Power Management Register
BIT
SIGNAL
TYPE
31–26
RSVD
R
Reserved. Bits 31–26 return 0s when read.
FUNCTION
25
SKTACCES
R
Socket access status. This bit provides information on when a socket access has occurred. This bit is
cleared by a read access.
0 = A PC card access has not occurred (default).
1 = A PC card access has occurred.
24
SKTMODE
R
Socket mode status. This bit provides clock mode information.
0 = Clock is operating normally.
1 = Clock frequency has changed.
23–17
RSVD
R
Reserved. Bits 23–17 return 0s when read.
16
CLKCTRLEN
R/W
15–1
RSVD
R
0
CLKCTRL
R/W
CardBus clock control enable. When bit 16 is set, bit 0 (CLKCTRL) is enabled.
0 = Clock control is disabled (default).
1 = Clock control is enabled.
Reserved. Bits 15–1 return 0s when read.
CardBus clock control. This bit determines whether the CB CLKRUN protocol stops or slows the CB clock
during idle states. Bit 16 (CLKCTRLEN) enables this bit.
0 = Allows CB CLKRUN protocol to stop the CB clock (default).
1 = Allows CB CLKRUN protocol to slow the CB clock by a factor of 16.
6–9
6–10
7 Distributed DMA (DDMA) Registers
The DMA base address, programmable in PCI configuration space as bits 15–4 of socket DMA register 1 (offset 98h,
see Section 4.36), points to a 16-byte region in PCI I/O space where the DDMA registers reside. The names and
locations of these registers are summarized in Table 7–1. These PCI1410 register definitions are identical in function
to, but different in location from, those of the 8237 DMA controller. The similarity between the register models retains
some level of compatibility with legacy DMA and simplifies the translation required by the master DMA device when
it forwards legacy DMA writes to DMA channels.
While the DMA register definitions are identical to those in the 8237 of the same name, some register bits defined
in the 8237 do not apply to distributed DMA in a PCI environment. In such cases, the PCI1410 implements these
obsolete register bits as read-only nonfunctional bits. The reserved registers shown in Table 7–1 are implemented
as read-only and return 0s when read. Write transactions to reserved registers have no effect.
Table 7–1. Distributed DMA Registers
DDMA BASE
ADDRESS OFFSET
REGISTER NAME
Current address
Reserved
Page
Reserved
Reserved
00h
Base address
Current count
N/A
Reserved
Mode
04h
Base count
Multichannel
N/A
Status
Request
Command
08h
N/A
Reserved
Mask
Master clear
Reserved
0Ch
7.1 DDMA Current Address/Base-Address Register
The DDMA current address/base address register sets the starting (base) memory address of a DDMA transfer. Read
transactions from this register indicate the current memory address of a direct memory transfer.
For the 8-bit DDMA transfer mode, the current address register contents are presented on AD15–AD0 of the PCI bus
during the address phase. Bits 7–0 of the DDMA page register (see Section 7.2) are presented on AD23–AD16 of
the PCI bus during the address phase.
For the 16-bit DDMA transfer mode, the current address register contents are presented on AD16–AD1 of the PCI
bus during the address phase, and AD0 is driven to logic 0. Bits 7–1 of the DDMA page register (see Section 7.2)
are presented on AD23–AD17 of the PCI bus during the address phase, and bit 0 is ignored.
Bit
15
14
13
Name
Type
12
11
10
9
8
DDMA current address/base-address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Name
Type
Default
DDMA current address/base-address
Register:
Offset:
Type:
Default:
DDMA current address/base-address
DDMA base address + 00h
Read/Write
0000h
7–1
7.2 DDMA Page Register
The DDMA page register sets the upper byte of the address of a DDMA transfer. Details of the address represented
by this register are explained in Section 7.1, DDMA Current Address/Base Address Register.
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
0
0
0
R/W
R/W
R/W
R/W
0
0
0
0
0
Name
Type
Default
DDMA page
Register:
Offset:
Type:
Default:
DDMA page
DDMA base address + 02h
Read/Write
00h
7.3 DDMA Current Count/Base Count Register
The DDMA current count/base count register sets the total transfer count, in bytes, of a direct memory transfer. Read
transactions to this register indicate the current count of a direct memory transfer. In the 8-bit transfer mode, the count
is decremented by 1 after each transfer, and the count is decremented by 2 after each transfer in the 16-bit transfer
mode.
Bit
15
14
13
Name
Type
12
11
10
9
8
DDMA current count/base count
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
DDMA current count/base count
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
7–2
DDMA current count/base count
DDMA base address + 04h
Read/Write
0000h
7.4 DDMA Command Register
The DDMA command register enables and disables the DDMA controller. Bit 2 (DMAEN) defaults to 0 enabling the
DDMA controller. All other bits are reserved. See Table 7–2 for a complete description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
DDMA command
Type
R
R
R
R
R
R/W
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
DDMA command
DDMA base address + 08h
Read-only, Read/Write
00h
Table 7–2. DDMA Command Register
BIT
SIGNAL
TYPE
7–3
RSVD
R
2
DMAEN
R/W
1–0
RSVD
R
FUNCTION
Reserved. Bits 7–3 return 0s when read.
DDMA controller enable. Bit 2 enables and disables the distributed DMA slave controller in the PCI1410 and
defaults to the enabled state.
0 = DDMA controller enabled (default)
1 = DDMA controller disabled
Reserved. Bits 1 and 0 return 0s when read.
7.5 DDMA Status Register
The DDMA status register indicates the terminal count and DMA request (DREQ) status. See Table 7–3 for a
complete description of the register contents.
Bit
7
6
5
4
Name
3
2
1
0
DDMA status
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
DDMA status
DDMA base address + 08h
Read-only
00h
Table 7–3. DDMA Status Register
BIT
7–4
3–0
SIGNAL
DREQSTAT
TC
TYPE
FUNCTION
R
Channel request. In the 8237, bits 7–4 indicate the status of DREQ of each DMA channel. In the PCI1410,
these bits indicate the DREQ status of the single socket being serviced by this register. All four bits are set
when the PC Card asserts DREQ and are reset when DREQ is deasserted. The status of bit 0 (MASKBIT)
in the DDMA multichannel/mask register (see Section 7.9) has no effect on these bits.
R
Channel terminal count. The 8237 uses bits 3–0 to indicate the TC status of each of its four DMA channels.
In the PCI1410, these bits report information about a single DMA channel; therefore, all four of these register
bits indicate the TC status of the single socket being serviced by this register. All four bits are set when the
TC is reached by the DMA channel. These bits are reset when read or the DMA channel is reset.
7–3
7.6 DDMA Request Register
The DDMA request register requests a DDMA transfer through software. Any write to this register enables software
requests, and this register is to be used in block mode only.
Bit
7
6
5
4
3
2
1
0
Type
W
W
W
W
Default
0
0
0
W
W
W
W
0
0
0
0
0
Name
DDMA request
Register:
Offset:
Type:
Default:
DDMA request
DDMA base address + 09h
Write-only
00h
7.7 DDMA Mode Register
The DDMA mode register sets the DDMA transfer mode. See Table 7–4 for a complete description of the register
contents.
Bit
7
6
5
4
Name
Type
Default
3
2
1
0
DDMA mode
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
DDMA mode
DDMA base address + 0Bh
Read-only, Read/Write
00h
Table 7–4. DDMA Mode Register
BIT
7–6
7–4
SIGNAL
DMAMODE
TYPE
FUNCTION
R/W
Mode select. The PCI1410 uses bits 7 and 6 to determine the transfer mode.
00 = Demand mode select (default)
01 = Single mode select
10 = Block mode select
11 = Reserved
5
INCDEC
R/W
Address increment/decrement. The PCI1410 uses bit 5 to select the memory address in the DDMA current
address/base address register to increment or decrement after each data transfer. This is in accordance
with the 8237 use of this register bit and is encoded as follows:
0 = Addresses increment (default).
1 = Addresses decrement.
4
AUTOINIT
R/W
Auto initialization
0 = Auto initialization disabled (default)
1 = Auto initialization enabled
Transfer type. Bits 3 and 2 select the type of direct memory transfer to be performed. A memory write transfer
moves data from the PCI1410 PC Card interface to memory and a memory read transfer moves data from
memory to the PCI1410 PC Card interface. The field is encoded as:
00 = No transfer selected (default)
01 = Write transfer
10 = Read transfer
11 = Reserved
3–2
XFERTYPE
R/W
1–0
RSVD
R
Reserved. Bits 1 and 0 return 0s when read.
7.8 DDMA Master Clear Register
The DDMA master clear register resets the DDMA controller and all DDMA registers.
Bit
7
6
5
4
Type
W
W
W
W
Default
0
0
0
0
Name
3
2
1
0
W
W
W
W
0
0
0
0
DDMA master clear
Register:
Offset:
Type:
Default:
DDMA master clear
DDMA base address + 0Dh
Write-only
00h
7.9 DDMA Multichannel/Mask Register
The PCI1410 uses only the least significant bit of this register to mask the PC Card DMA channel. The PCI1410 sets
the mask bit when the PC Card is removed. Host software is responsible for either resetting the socket’s DMA
controller or enabling the mask bit. See Table 7–5 for a complete description of the register contents.
Bit
7
6
5
Name
4
3
2
1
0
DDMA multichannel/mask
Type
R
R
R
R
R
R
R
R/W
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
DDMA multichannel/mask
DDMA base address + 0Fh
Read-only
00h
Table 7–5. DDMA Multichannel/Mask Register
BIT
SIGNAL
TYPE
7–1
RSVD
R
0
MASKBIT
R/W
FUNCTION
Reserved. Bits 7–1 return 0s when read.
Mask select. Bit 0 masks incoming DREQ signals from the PC Card. When set, the socket ignores DMA
requests from the card. When cleared (or reset), incoming DREQ assertions are serviced normally.
0 = DDMA service provided on card DREQ
1 = Socket DREQ signal ignored (default)
7–5
7–6
8 Electrical Characteristics
8.1 Absolute Maximum Ratings Over Operating Temperature Ranges†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Clamping voltage range, VCCP, VCCCB, VCCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input voltage range, VI: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCCP + 0.5 V
Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCCB + 0.5 V
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCCI + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO: PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 to VCC + 0.5 V
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies for external input and bidirectional buffers. VI > VCC does not apply to fail-safe terminals. PCI terminals are measured with
respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured with
respect to VCCI. The limit specified applies for a dc condition.
2. Applies for external output and bidirectional buffers. VO > VCC does not apply to fail-safe terminals. PCI terminals are measured
with respect to VCCP instead of VCC. PC Card terminals are measured with respect to VCCCB. Miscellaneous signals are measured
with respect to VCCI. The limit specified applies for a dc condition.
8–1
8.2 Recommended Operating Conditions (see Note 3)
OPERATION
VCC
Core voltage
Commercial
VCCP
PCI I/O clamp voltage
oltage
Commercial
VCCCB
PC Card I/O clamp voltage
oltage
Commercial
VCCI
Miscellaneo s I/O clamp voltage
oltage
Miscellaneous
Commercial
3.3 V
3.3 V
5V
3.3 V
High-level
input
High
level in
ut voltage
PC Card
VI
VO¶
tt
Low-level
Low
level in
input
ut voltage
Input voltage
Output voltage
Input transition time (tr and tf)
PC Card
3
3.3
3.6
4.75
5
5.25
3.6
5
5.25
3
3.3
3.6
5V
4.75
5
5.25
3.3 V
0.5 VCCP
5V
5V
2
0.475 VCCCB
2.4
2
2
CD pinsk
VIL†
3.6
3.3
Miscellaneous‡
Fail safe§
PCI
MAX
3.3
3
3.3 V
VIH†
NOM
3
4.75
5V
3.3 V
PCI
MIN
2.4
3.3 V
0
5V
0
3.3 V
0
5V
V
V
V
V
VCCP
VCCP
VCCCB
VCCCB
V
VCCI
VCC
VCC
0.3 VCCP
0.8
0.325 VCCCB
0
0.8
Miscellaneous‡
Fail safe§
0
0.8
0
0.8
CD pinsk
0
0.75
PCI
0
PC Card
0
VCCP
VCCCB
Miscellaneous‡
Fail safe§
0
PCI
0
PC Card
0
Miscellaneous‡
Fail safe§
0
0
VCC
VCC
PCI and PC Card
Miscellaneous‡
and fail safe§
1
4
0
6
0
UNIT
VCCI
VCC
VCC
VCC
V
V
V
ns
TA
Operating ambient temperature range
0
25
70
°C
TJ#
Virtual junction temperature
0
25
115
°C
† Applies to external inputs and bidirectional buffers without hysteresis
‡ Miscellaneous terminals are 70, 62, 59, 60, 61, 64, 65, 67, 68, and 69 for the PGE packaged device; L11, M9, L8, K8, N9, K9, N10, L10, N11,
and M11 for the GGU packaged device; and W12, U10, P9, W10, V10, P10, W11, U11, P11, and R11 for the GHK packaged device (SUSPEND,
SPKROUT, RI_OUT, multifunction terminals (MFUNC0–MFUNC6), and power switch control pins).
§ Fail-safe terminals are 75, 117, 131, and 137 for the PGE packaged device; L12, D9, C6, and A4 for the GGU packaged device; and L19, E13,
F11, and A9 for the GHK packaged device (card detect and voltage sense pins).
¶ Applies to external output buffers
# These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
k CD terminals are 75 and 137 for the PGE packaged device; L12 and A4 for the GGU packaged device; and L19 and A9 for the GHK packaged
device.
NOTE 3: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
8–2
8.3 Electrical Characteristics Over Recommended Operating Conditions (unless
otherwise noted)
PARAMETER
TERMINALS
PCI and
Misc1§
VOH
High le el output
o tp t voltage
oltage (see Note 4)
High-level
Low level output voltage
Low-level
3.3 V
5V
IOH = –2 mA
MIN
5V
IOH = –0.15 mA
2.4
Misc2¶
IOH = –12 mA
2.1
Misc3#
IOH = –4 mA
2.1
PC Card
3.3 V
5V
3-state out
output,
ut, high-impedance
high-im edance state
output current
Out ut
Output
terminals
IOZH
3-state out
output,
ut, high-impedance
high-im edance state
output current
Out ut
Output
terminals
IIL
L
Low-level
l
l input
i
t currentt
0.1VCC
0.55
IOL = 0.7 mA
0.1VCC
5V
IOL = 0.7 mA
0.55
IOL = 12 mA
0.5
IOL = 4 mA
VI = VCC
0.5
3.6 V
5.25 V
VI = VCC
–1
3.6 V
VI = VCC†
VI = VCC†
10
VI = GND
VI = GND
–1
5.25 V
Input terminals
I/O terminals
In ut
Input
terminals
IOL = 6 mA
V
3.3 V
Misc3#
IOZL
IOL = 1.5 mA
3.6 V
5.25 V
–1
25
–10
VI = VCC‡
VI = VCC‡
10
10
5.25 V
Fail-safe
terminals
3.6 V
VI = VCC
10
VCCD
terminals||
3.6 V
VI = VCC
300
I/O terminals
High-level input current
V
µA
µA
µA
A
20
VI = VCC‡
VI = VCC‡
3.6 V
UNIT
2.4
3.3 V
PC Card
MAX
0.9VCC
0.9VCC
Misc2¶
IIH
TEST CONDITIONS
IOH = –0.5 mA
IOH = –0.15 mA
PCI and
Misc1§
VOL
OPERATION
25
µA
† For PCI terminals, VI = VCCP. For PC Card terminals, VI = VCCCB. For miscellaneous terminals, VI = VCCI
‡ For I/O terminals, input leakage (IIL and IIH) includes IOZ leakage of the disabled output.
§ Misc1 includes MFUNC6(69), MFUNC5(68), MFUNC4(67), MFUNC3(65), and MFUNC2(64)for the PGE packaged device; M11, N11, L10, N10,
and K9 for the GGU packaged device; and R11, P11, U11, W11, and P10 for the GHK packaged device.
¶ Misc2 includes MFUNC1(61), MFUNC0(60), and SERR(35) for the PGE packaged device; N9, K8, and M1 for the GGU packaged device; and
V10, W10, and R3 for the GHK packaged device..
# Misc3 includes SPKROUT(62) and RI_OUT(59) for the PGE packaged device; M9 and L8 for the GGU packaged device; and U10 and P9 for
the GHK packaged device.
|| VCCD pins include VCCD0(73) and VCCD1(74).
8–3
8.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
ALTERNATE
SYMBOL
PARAMETER
tc
twH
Cycle time, PCLK
twL
∆v/∆t
Pulse duration (width), PCLK low
tw
tsu
TEST CONDITIONS
MIN
MAX
UNIT
tcyc
thigh
30
ns
11
ns
11
ns
Slew rate, PCLK
tlow
tr, tf
Pulse duration (width), RSTIN
trst
1
ms
100
ms
Pulse duration (width), PCLK high
Setup time, PCLK active at end of RSTIN
1
trst-clk
4
V/ns
8.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data sheet uses the following conventions to describe time ( t ) intervals. The format is tA, where subscript A
indicates the type of dynamic parameter being represented. The following are used: tpd = propagation delay time,
td = delay time, tsu = setup time, and th = hold time.
ALTERNATE
SYMBOL
PARAMETER
tpd
PCLK-to-shared signal
valid delay time
tval
PCLK-to-shared signal
invalid delay time
tinv
Delay time, ten
Enable time, high
impedance-to-active
delay time from PCLK
ton
Delay time, tdis
Disable time,
active-to-high
impedance delay time
from PCLK
toff
Propagation delay time
time, See Note 4
td
TEST CONDITIONS
CL = 50 pF,
F,
See Note 4
MIN
MAX
2
11
UNIT
ns
2
2
tsu
Setup time before PCLK valid
tsu
7
th
Hold time after PCLK high
th
0
NOTE 4: PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
ns
28
ns
ns
ns
8.6 PC Card Cycle Timing
The PC Card cycle timing is controlled by the wait-state bits in the Intel 82365SL-DF compatible memory and I/O
window registers. The PC Card cycle generator uses the PCI clock to generate the correct card address setup and
hold times and the PC Card command active (low) interval. This allows the cycle generator to output PC Card cycles
that are as close to the Intel 82365SL-DF timing as possible while always slightly exceeding the Intel 82365SL-DF
values. This ensures compatibility with existing software and maximizes throughput.
The PC Card address setup and hold times are a function of the wait-state bits. Table 8–1 shows address setup time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–2 and Table 8–3 show command active time
in PCLK cycles and nanoseconds for I/O and memory cycles. Table 8–4 shows address hold time in PCLK cycles
and nanoseconds for I/O and memory cycles.
Table 8–1. PC Card Address Setup Time, tsu(A), 8-Bit and 16-Bit PCI Cycles
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
8–4
3/90
Memory
WS1
0
2/60
Memory
WS1
1
4/120
Table 8–2. PC Card Command Active Cycle Time, tc(A), 8-Bit PCI Cycles
WAIT-STATE BITS
ZWS
TS1 – 0 = 01
(PCLK/ns)
0
0
19/570
1
X
23/690
WS
I/O
Memory
0
1
7/210
00
0
19/570
01
X
23/690
10
X
23/690
11
X
23/690
00
1
7/210
Table 8–3. PC Card Command Active Cycle Time, tc(A), 16-Bit PCI Cycles
WAIT-STATE BITS
WS
I/O
Memory
y
ZWS
TS1 – 0 = 01
(PCLK/ns)
0
0
7/210
1
X
11/330
0
1
N/A
00
0
9/270
01
X
13/390
10
X
17/510
11
X
23/630
00
1
5/150
Table 8–4. PC Card Address Hold Time, th(A), 8-Bit and 16-Bit PCI Cycles
TS1 – 0 = 01
(PCLK/ns)
WAIT-STATE BITS
I/O
2/60
Memory
WS1
0
2/60
Memory
WS1
1
3/90
8–5
8–6
9 Mechanical Information
The PCI1410 is packaged in either a 144-ball GGU MicroStar BGA or a 144-pin PGE package. It is also packaged
in a 209-ball GHK MicroStar BGA that is pin compatible with the TI PCI4410. The PCI4410 is a single-socket CardBus
bridge with an integrated OHCI link. The following shows the mechanical dimensions for the GGU, GHK, and PDV
packages.
GGU (S-PBGA-N144)
PLASTIC BALL GRID ARRAY
9,60 TYP
12,10
SQ
11,90
0,80
N
M
L
K
J
H
G
F
E
D
C
B
A
0,80
1 2 3 4 5 6 7 8 9 10 11 12 13
0,95
0,85
1,40 MAX
Seating Plane
0,12
0,08
0,55
0,45
0,08 M
0,45
0,35
0,10
4073221/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
9–1
GHK (S-PBGA-N209)
PLASTIC BALL GRID ARRAY
16,10
SQ
15,90
14,40 TYP
0,80
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0,80
1
3
2
0,95
0,85
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
1,40 MAX
Seating Plane
0,12
0,08
0,55
0,45
0,08 M
0,45
0,35
0,10
4145273–2/B 12/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration.
9–2
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°–ā7°
0,75
0,45
1,45
1,35
Seating Plane
1,60 MAX
0,08
4040147 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
9–3
9–4
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