SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
D
D
D
D
D
D
D
D
SN54ABT16646 . . . WD PACKAGE
SN74ABT16646 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
1DIR
1CLKAB
1SAB
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2SAB
2CLKAB
2DIR
description
The
’ABT16646
devices
consist
of
bus-transceiver circuits, D-type flip-flops, and
control circuitry arranged for multiplexed
transmission of data directly from the input bus or
from the internal registers.
These devices can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the ’ABT16646 devices.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OE
1CLKBA
1SBA
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2SBA
2CLKBA
2OE
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port may be stored in either register or in both. The
select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry
used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition
between stored and real-time data. The direction control (DIR) determines which bus receives data when OE
is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the
other register.
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
description (continued)
The SN54ABT16646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
DATA I/O†
INPUTS
OPERATION OR FUNCTION
OE
DIR
CLKAB
CLKBA
SAB
SBA
A1–A8
B1–B8
X
X
↑
X
X
X
Input
Unspecified
Store A, B unspecified{
X
X
X
↑
X
X
Unspecified
Input
Store B, A unspecified{
H
X
↑
↑
X
X
Input
Input
Store A and B data
H
X
H or L
H or L
X
X
Input disabled
Input disabled
Isolation, hold storage
L
L
X
X
X
L
Output
Input
Real-time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
L
H
X
X
L
X
Input
Output
Real-time A data to B Bus
L
H
H or L
X
H
X
Input
Output
Stored A data to bus
† The data-output functions can be enabled or disabled by various signals at OE or DIR. Data-input functions always are enabled, i.e., data at the
bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
OE
L
DIR
L
CLKAB CLKBA
X
X
SAB
X
BUS B
BUS A
BUS A
BUS B
SCBS212D – JUNE 1992 – REVISED JULY 1999
SBA
L
OE
L
DIR
H
DIR
X
X
H
X
X
X
CLKAB CLKBA
↑
X
↑
X
↑
↑
SAB
L
SBA
X
BUS B
BUS A
BUS A
OE
CLKBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
BUS B
REAL-TIME TRANSFER
BUS B TO BUS A
CLKAB
X
SAB
SBA
X
X
X
X
X
X
STORAGE FROM
A, B, OR A AND B
OE
L
L
DIR
L
H
CLKAB
X
H or L
CLKBA
H or L
X
SAB
X
H
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
logic symbol†
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
1A1
56
1
55
54
2
G3
3 EN1 [BA]
3 EN2 [AB]
C4
G5
C6
3
G7
29
28
30
31
27
26
G10
10 EN8 [BA]
10 EN9 [AB]
C11
G12
C13
G14
≥1
5
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
7
1
2A3
2A4
2A5
2A6
2A7
2A8
≥1
7
51
49
9
48
10
47
12
45
13
44
14
43
15
16
≥1
8
1 14
12 11D
42
≥1
1B3
1B4
1B5
1B6
1B7
1B8
2B1
9
41
17
40
19
38
20
37
21
36
23
34
24
33
POST OFFICE BOX 655303
1B2
12 1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
4
1B1
2
8
13D 14
2A2
52
5 1
6D
6
4D
5
• DALLAS, TEXAS 75265
2B2
2B3
2B4
2B5
2B6
2B7
2B8
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
logic diagram (positive logic)
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
56
1
55
54
2
3
One of Eight Channels
1D
C1
1A1
5
52
1B1
1D
C1
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
To Seven Other Channels
29
28
30
31
27
26
One of Eight Channels
1D
C1
2A1
15
42
2B1
1D
C1
To Seven Other Channels
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• DALLAS, TEXAS 75265
5
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT16646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54ABT16646
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT16646
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
MIN
MAX
SN74ABT16646
MIN
–1.2
MAX
–1.2
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
0.55
0.55*
VCC = 5.5 V,, VI = VCC or GND
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
VCC = 0,
VCC = 5.5 V,
VO = 5.5 V
VI or VO ≤ 4.5 V
VCC = 5.5 V,
VO = 2.5 V
Outputs high
ICEX
IO§
0.55
A or B ports
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
Outputs high
±1
±1
±1
±20
±20
±20
10
10
10
µA
–10
–10
µA
±100
µA
50
µA
–180
mA
–180
50
–50
–180
–50
2
2
2
32
32
32
Outputs disabled
2
2
2
50
50
50
50
50
50
Control
inputs
VCC = 5.5 V,
Outputs enabled
One input at 3.4 V,,
Other inputs at
Outputs disabled
VCC or GND
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
50
50
50
Control
inputs
VI = 2.5 V or 0.5 V
Data inputs
∆ICC¶
Outputs low
4
Cio
A or B ports
VO = 2.5 V or 0.5 V
8
* On products compliant to MIL-PRF-38535, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
POST OFFICE BOX 655303
µ
µA
–10
50
–100
V
mV
±100
–50
V
V
100
Control
inputs
UNIT
2
0.55
IOL = 64 mA
IOZH‡
IOZL‡
Ci
MIN
–1.2
A or B ports
ICC
SN54ABT16646
2.5
Vhys
II
TA = 25°C
TYP†
MAX
• DALLAS, TEXAS 75265
mA
µA
pF
pF
7
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN54ABT16646
VCC = 5 V,
TA = 25°C
MIN
MIN
MAX
UNIT
MAX
fclock
tw
Clock frequency
Pulse duration, CLK high or low
4.3
125
4.3
125
MHz
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3.5
4
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0.5
0.5
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
SN74ABT16646
VCC = 5 V,
TA = 25°C
MIN
8
MIN
MAX
UNIT
MAX
fclock
tw
Clock frequency
125
4.3
4.3
ns
tsu
th
Setup time, A or B before CLKAB↑ or CLKBA↑
3
3
ns
Hold time, A or B after CLKAB↑ or CLKBA↑
0
0
ns
Pulse duration, CLK high or low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
125
MHz
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN54ABT16646
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
MIN
TYP
MAX
1.5
3.1
4
1
5
1.5
3.2
4.1
1
5
1
2.3
3.2
0.6
4
1
3
4.1
0.6
4.9
1
2.9
4.3
0.6
5.3
1
3.1
4.3
0.6
5.3
125
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
B or A
OE
A or B
OE
A or B
DIR
A or B
DIR
A or B
MAX
125
UNIT
MHz
1
3.4
4.6
0.6
5.9
1.5
3.5
5.3
1
6
1.5
3.9
5.6
1
6.4
1.5
3.1
4.4
1
4.7
1
3.2
4.5
0.6
5.8
1.5
3.4
5.1
1
6.7
2
4.2
5.9
1.2
7.1
1.5
3.6
5.1
1
6.2
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 2)
SN74ABT16646
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPZH
tPZL
tPHZ
tPLZ
MIN
TYP
MAX
1.5
3.1
4
1.5
4.9
1.5
3.2
4.1
1.5
4.7
1
2.3
3.2
1
3.9
1
3
4.1
1
4.6
1
2.9
4.3
1
5
1
3.1
4.3
1
5
1
3.4
4.6
1
5.5
1.5
3.5
4.9
1.5
5.7
1.5
3.9
4.9
1.5
5.4
1.5
3.1
4.1
1.5
4.5
125
CLKBA or CLKAB
A or B
A or B
B or A
SAB or SBA†
B or A
OE
A or B
OE
A or B
DIR
A or B
DIR
A or B
MAX
125
UNIT
MHz
1
3.2
4.5
1
5.4
1.5
3.4
4.8
1.5
5.6
2
4.2
5.7
2
6.7
1.5
3.6
5.1
1.5
5.9
ns
ns
ns
ns
ns
ns
ns
† These parameters are measured with the internal output state of the storage register opposite that of the bus input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SN54ABT16646, SN74ABT16646
16-BIT BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS212D – JUNE 1992 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
1.5 V
Input
1.5 V
Data Input
0V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
3V
1.5 V
Input
Output
Control
1.5 V
0V
tPLH
VOH
1.5 V
VOL
tPHL
VOH
Output
tPLZ
3.5 V
1.5 V
VOL
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
1.5 V
1.5 V
tPZL
tPHL
1.5 V
Output
1.5 V
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
1
5962-9450201QXA
ACTIVE
CFP
WD
56
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16646DGGR
ACTIVE
TSSOP
DGG
56
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16646DL
ACTIVE
SSOP
DL
56
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16646DLR
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74ABT16646DLRG4
ACTIVE
SSOP
DL
56
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ54ABT16646WD
ACTIVE
CFP
WD
56
1
TBD
Call TI
MSL Peak Temp (3)
74ABT16646DGGRE4
20
TBD
Lead/Ball Finish
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
48
1
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
25
24
NO. OF
LEADS**
48
56
A MAX
0.640
(16,26)
0.740
(18,80)
A MIN
0.610
(15,49)
0.710
(18,03)
4040176 / D 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only
Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA
GDFP1-F56 and JEDEC MO -146AB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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