LIBERATOR Key Features CL10K30A u Fully Compatible To The Altera® FLEX® 10KA Family u Prototype Your System With Altera FPGAs u Seamlessly Migrate Production To Clear Logic u No ASIC Engineering, No NRE, And No Test Vector Development u Very Fast, Dense Signal Routing Using Vertical Link Interconnect u "Gate Array" Option Eliminates Configuration EPROMs u Fabricated Using 0.35 Micron CMOS Process u Very Low Power Consumption (Active And Standby) u High Density - 30,000 Usable Gates - 1,728 Logic Elements - 12,288 RAM Bits - 189 Maximum User I/O Pins CL10KA Product Family Overview Parameter CL10K30A CL10K50V CL10K100A Typical Gates (Logic and RAM) 30,000 50,000 100,000 Maximum System Gates 69,000 116,000 158,000 1,728 2,880 4,992 216 360 624 6 10 12 12,288 20,480 24,576 189 274 406 -1, -2, -3 -1, -2, -3, -4 -1, -2, -3 144-pin TQFP 208-pin PQFP 240-pin PQFP 256-pin FBGA 240-pin PQFP 240-pin RQFP 356-pin SBGA 240-pin PQFP 240-pin RQFP 356-pin SBGA 484-pin FBGA 600-pin SBGA Logic Elements Logic Blocks Embedded Array Blocks Total RAM Bits Max User I/O Pins Speed Grades Packages 10KA tbl 01A March 2001 Page 1 LIBERATOR CL10K30A Description The LIBERATOR CL10KA family offers you all of the time-tomarket benefits of designing with programmable logic. Simply use Altera FLEX 10KA FPGAs to prototype and verify the design. Then, take five minutes to submit the bitstream using Clear Logic's web site! Within eight weeks, your system can be in volume production using compatible Clear Logic devices. LIBERATOR technology frees you to completely design, prototype, and verify your custom logic using Altera FLEX 10KA products. Clear Logic's innovative technology eliminates NRE costs, test vector development, ordering minimums, and long lead times. No re-simulation or re-layout is required, because Clear Logic offers an architecture that is exactly compatible to the functionality of the FPGA prototype. Clear Logic's NoFault® test technology ensures complete test coverage through the use of special scan test registers. The LIBERATOR family is based upon an array of logic elements. Each logic element contains a configurable look-up table for combinatorial functions and a register for sequential operations. Eight logic elements in a group form a block. Logic functions and signal routing are defined by Clear Logic's proprietary vertical metal links. Laser-based configuration allows quick-turn prototyping and eliminates NRE costs for photomasks. Inherent CL10KA family performance benefits include extremely consistent propagation delays, reduced power consumption, and improved immunity to noise and upset events. Configuration Page 2 The "Gate Array" configuration mode eliminates the need for external EPROMs or software configuration. The LIBERATOR device is already factory-configured when it is shipped. When using the device in the "Gate Array" mode, it powers up fully configured. In this mode, if the customer selects INIT_DONE option, this pin will always be high. LIBERATOR CL10K30A Additional Information For further information on designing with the LIBERATOR family, please refer to these documents: u AN-01: Requesting a First Article. This document provides instructions on how to request first articles by submitting a bitstream file to Clear Logic's web site. u AN-02: Clear Logic Packaging Guide. This document provides specifications and drawings for packages used by the CL10K family and other Clear Logic devices. u AN-13: LIBERATOR -- A New Way To Design. This document describes the most efficient path for custom logic designs up to 200K gates using FPGA design techniques and going to production with Clear Logic. u AN-14: CL10K Technology White Paper. This document outlines the technologies employed by the LIBERATOR family. u AN-15: LIBERATOR System Configuration. This document contains a detailed discussion of all aspects of configuring CL10K-based systems. u AN-16: Introduction to the Clear Logic Verilog Model Generator. Clear Logic now has Verilog models of your FPGA converted design. Learn what it is and how it can help you. u AN-17: Clear Logic LIBERATOR Design Models. This document outlines the capabilities and freedom available in the Clear Logic Verilog and VHDL design models. u AN-18: Debugging Designs Using Clear Logic Models. This document shows the enhanced troubleshooting capabilities that the Clear Logic LIBERATOR Verilog/VHDL design models bring to the system debugging process. Page 3 LIBERATOR CL10K30A Block Diagram Embedded Array Block (EAB) I/O Element (IOE) IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE IOE Column Interconnect Logic Array EAB Logic Building Block (LBB) IOE IOE IOE IOE Logic Element (LE) Row Interconnect EAB Local Interconnect Logic Array 10KA drw 01 IOE IOE IOE IOE Logical Memory Array (LMA) Page 4 IOE IOE IOE IOE IOE IOE LIBERATOR CL10K30A Pin Configuration 144-Pin TQFP 208-Pin PQFP 240-Pin PQFP/RQFP MSEL0 77 108 124 P1 MSEL1 76 107 123 R1 nSTATUS 35 52 60 T16 nCONFIG 74 105 121 N4 107 155 179 B2 CONF_DONE 2 2 2 C15 INIT_DONE 14 19 26 G16 106 154 178 B1 3 3 3 B16 nWS 142 206 238 B14 nRS 141 204 236 C14 nCS 144 208 240 A16 CS 143 207 239 A15 RDYnBSY 11 16 23 G14 CLKUSR 7 10 11 D15 DATA7 116 166 190 B5 DATA6 114 164 188 D4 DATA5 113 162 186 A4 DATA4 112 161 185 B4 DATA3 111 159 183 C3 DATA2 110 158 182 A2 DATA1 109 157 181 B3 DATA0 108 156 180 A1 TDI 105 153 177 C2 TDO 4 4 4 C16 TCK 1 1 1 B15 TMS 34 50 58 P15 51 59 R16 78, 80, 182, 184 90, 92, 210, 212 B9, E8, M9, R8 Pin Name DCLK nCE nCEO TRST Dedicated Inputs 54, 56, 124, 126 256-Pin FBGA 10K30A tbl 01A Page 5 LIBERATOR CL10K30A Pin Configuration 144-Pin TQFP 208-Pin PQFP 240-Pin PQFP/RQFP 55, 125 79, 183 91, 211 A9, L8 DEV_CLRn 122 180 209 D8 DEV_OE 128 186 213 C9 VCCINT 6, 25, 52, 53, 75, 93, 123 6, 23, 35, 43, 76, 77, 106, 109, 117, 137, 145, 181 5, 16, 27, 37, 47, 57, 77, 89, 96, 112, 122, 130, 140, 150, 160, E11, F5, F7, F9, F12, H6, H7, H10, J7, J10, J11, K9, L5, L7, L9, VCCIO 5, 24, 45, 61, 71, 94, 115, 134 5, 22, 34, 42, 66, 84, 98, 110, 118, 138, 146, 165, 178, 194 - D12, E6, F8, F10, G6, G8, G11, H11, J6, K6, K8, K11, L10, M6, N12 GNDINT 16, 57, 58, 84, 103, 127 10, 22, 32, 42, 52, 69, 21, 33, 49, 81, 82, 123, 85, 93, 104, 125, 135, 129, 151, 185 145, 155, 165, 176, GNDIO 15, 40, 50, 66, 85, 104, 129, 139 20, 32, 48, 89, 72, 91, 124, 130, 152, 171, 188, 201 - - - - - - 102 147 189 Pin Name Dedicated Clock Pins No connect Total user I/O Pins 256-Pin FBGA E5, E12, F6, F11, G7, G9, G10, H8, H9, J8, J9, K7, K10, L6, L11, 191 10K30A tbl 01B Page 6 LIBERATOR CL10K30A DC Electrical Specifications Absolute Maximum Ratings Symbol Min Max Unit Supply Voltage -0.5 4.6 V DC Input Voltage [1] -2.0 5.75 V IOUT DC Output Current, per Pin -25 25 mA TSTG Storage Temperature No Bias -65 150 °C TAMB Ambient Temperature Under Bias -65 135 °C TJ Junction Temperature Under Bias 135 °C VCC VI Parameter Conditions 10KA tbl 02 Recommended Operating Conditions Symbol Parameter VCCINT [2] Min Max Unit Supply Voltage, Internal Logic and Input Buffers Commercial Grade Devices Industrial Grade Devices 3.00 3.00 3.60 3.60 V V DC Input Voltage for 3.3V Operation Commercial Grade Devices Industrial Grade Devices 3.00 3.00 3.60 3.60 V V DC Input Voltage for 2.5V Operation Commercial Grade Devices Industrial Grade Devices 2.30 2.30 2.70 2.70 V V VI Input Voltage -0.5 5.75 V VO Output Voltage 0 VCCIO V TA Operating Temperature Commercial Temperature Range Industrial Temperature Range 0 -40 70 85 °C °C VCCIO VCCIO Conditions tR Input Signal Rise Time 40 ns tF Input Signal Fall Time 40 ns 10KA tbl 03B Page 7 LIBERATOR CL10K30A DC Electrical Specifications cont. DC Electrical Characteristics (over the operating range) Symbol Parameter Conditions Min Typ[3] Max Unit VIH Input HIGH Voltage Lower of 1.7 or 0.5 x VCCINT 5.75 V VIL Input LOW Voltage -0.5 0.3 x VCCINT V VOH 3.3-V High-Level TTL Output Voltage 3.3-V High-Level CMOS Output Voltage 3.3-V High-Level PCI Output Voltage 2.5-V High-Level Output Voltage VOL 3.3-V Low-Level TTL Output Voltage 3.3-V Low-Level CMOS Output Voltage 3.3-V Low-Level PCI Output Voltage 2.5-V Low-Level Output Voltage IOH = -8 mA DC, VCCIO = 3.00 V 2.4 V IOH = -0.1 mA DC, VCCIO = 3.00 V VCCIO-0.2 V IOH = -0.5 mA DC, VCCIO = 3 to 3.60 V 0.9 x VCCIO V IOH = -0.1 mA DC, VCCIO = 2.30 V 2.1 V IOH = -1 mA DC, VCCIO = 2.30 V 2.0 V IOH = -2 mA DC, VCCIO = 2.30 V 1.7 V IOL = 9 mA DC, VCCIO = 3.00 V 0.45 V 0.2 V 0.1 x VCCIO V IOL = 0.1 mA DC, VCCIO = 2.30 V 0.2 V IOL = 1 mA DC, VCCIO = 2.30 V 0.4 V IOL = 2 mA DC, VCCIO = 2.30 V 0.7 V IOL = 0.1 mA DC, VCCIO = 3.00 V IOL = 1.5 mA DC, VCCIO = 3 to 3.60 V IIN Input Leakage Current VI = 5.3V to -0.3V -10 10 µA IOZ Output Leakage Current VO = 5.3V to -0.3V -10 10 µA ICC0 Standby Current VI = GND, no load 10 mA 0.3 10KA tbl 04B Capacitance[4] Symbol Parameter Conditions C IN Input Capacitance COUT Output Capacitance Min Max Unit VIN = 0 V, f = 1.0 MHz 8 pF VOUT = 0 V, f = 1.0 MHz 8 pF 10K tbl 05B Page 8 LIBERATOR CL10K30A AC Electrical Specifications I/O Element Timing Parameters Symbol Parameter [5] Speed: -1 Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tIOD IOE Register Data Delay 2.2 2.6 3.4 ns tIOC IOE Register Control Signal Delay 0.3 0.3 0.5 ns tIOCO IOE Register Clock to Output Delay 0.2 0.2 0.3 ns IOE Combinatorial Delay 0.5 0.6 0.8 ns tIOCOMB tIOSU IOE Register Setup Time Before Clock 1.4 1.7 2.2 ns tIOH IOE Register Hold Time After Clock 0.9 1.1 1.4 ns tIOCLR IOE Register Clear Delay 0.7 0.8 1.0 ns tOD1 Output Buffer and Pad Delay Slow Slew Rate = off, VCCIO = VCCINT 1.9 2.2 2.9 ns tOD2 Output Buffer and Pad Delay Slow Slew Rate = off, VCCIO = Low Voltage 4.8 5.6 7.3 ns tOD3 Output Duffer and Pad Delay Slow Slew Rate = on 7.0 8.2 10.8 ns tZX Output Buffer Disable Delay[6] 2.2 2.6 3.4 ns tZX1 Output Buffer Disable Delay Slow Slew Rate = off, VCCIO = VCCINT[6] 2.2 2.6 3.4 ns 5.1 6.0 7.8 ns 7.3 8.6 11.3 ns tZX2 Output Buffer Disable Delay Slow Slew Rate = off, VCCIO = Low Voltage tZX3 [6] Output Buffer Disable Delay Slow Slew Rate = on [6] tINREG IOE Input Pad and Buffer to IOE Register Delay 4.4 5.2 6.8 ns tIOFD IOE Register Feedback Delay 3.8 4.5 5.9 ns IOE Input Pad and Buffer to Interconnect Delay 3.8 4.5 5.9 ns tINCOMB 10KA tbl 06C Page 9 LIBERATOR CL10K30A AC Electrical Specifications cont. External Timing Parameters[4] Symbol Parameter Speed: -1 Min Max Speed: -2 Min Max Speed: -3 Min Max Unit 17.0 ns tDRR Register to Register Delay via Four LEs, Three Row Interconnects, and Four Local Interconnects tINSU Setup Time with Global Clock at IOE Register 2.5 3.1 3.9 ns tINH Hold time with Global Clock at IOE Register 0.0 0.0 0.0 ns Output Data Hold Time After Clock 2.0 tOUTCO 11.0 5.4 13.0 2.0 6.2 2.0 8.3 ns 10KA tbl 07C Logic Element Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tLUT Look-up Table Delay for Data-in 0.8 1.1 1.5 ns tCLUT Look-up Table Delay for Carry-in 0.6 0.7 1.0 ns tRLUT Look-up Table Delay for LE Register Feedback 1.2 1.5 2.0 ns Data-in to Packed Register Delay 0.6 0.6 1.0 ns tEN LE Register Enable Delay 1.3 1.5 2.0 ns tCICO Carry-in to Carry-out Delay 0.2 0.3 0.4 ns tCGEN Data-in to Carry-out Delay 0.8 1.0 1.3 ns tCGENR LE Register Feedback to Carry-out Delay 0.6 0.8 1.0 ns tCASC Cascade Chain Routing Ddelay 0.9 1.1 1.4 ns tC LE Register Control Signal Delay 1.1 1.3 1.7 ns tCO LE Register Clock-to-output Delay 0.4 0.6 0.7 ns Combinatorial Delay 0.6 0.7 0.9 ns tPACKED tCOMB tSU LE Register Setup Time Before Clock 0.9 0.9 1.4 ns tH LE Register Hold Time After Clock 1.1 1.3 1.4 ns tPRE LE Register Preset Delay 0.5 0.6 0.8 ns tCLR LE Register Clear Delay 0.5 0.6 0.8 ns tCH Clock High Time 3.0 3.5 4.0 ns tCL Clock Low Time 3.0 3.5 4.0 ns 10KA tbl 08C Page 10 LIBERATOR CL10K30A AC Electrical Specifications cont. Interconnect Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tDIN2IOE Delay from Dedicated Input Pin to IOE Control Input 3.9 4.4 5.1 ns tDIN2LE Delay from Dedicated Input Pin to LE or EAB Control Input 1.2 1.5 1.9 ns Delay from Dedicated Input or Clock Pin to LE or EAB Data 3.2 3.6 4.5 ns tDCLK2IOE Delay from Dedicated Clock Pin to IOE Clock 3.0 3.5 4.6 ns tDCLK2LE Delay from Dedicated Clock Pin to LE or EAB Clock 1.2 1.5 1.9 ns tSAMELAB Delay from an LE to LE in Same LAB 0.1 0.1 0.2 ns tSAMEROW Delay for Driving a Row IOE, LE or EAB to a Row IOE, LE or EAB in the Same Row 2.3 2.4 2.7 ns Delay from an LE to IOE in the Same Column 1.3 1.4 1.9 ns tDIFFROW Delay for Driving a Column IOE, LE or EAB to an LE or EAB in a Different Row 3.6 3.8 4.6 ns tTWOROWS Delay for Driving a Row IOE or EAB to an LE or EAB in a Different Row 5.9 6.2 7.3 ns tLEPERIPH Delay from an LE to IOE Control Signal via the Peripheral Dontol Bus 3.5 3.8 4.1 ns tLABCARRY Delay from an LE Carry-out Signal to an LE Carry-in Signal in a Different LAB 0.3 0.4 0.5 ns tLABCASC Delay from an LE Cascade-out Signal to an LE Cascade-in Signal in a Different LAB 0.9 1.1 1.4 ns tDIN2DATA tSAMECOLUMN 10KA tbl 09C Page 11 LIBERATOR CL10K30A AC Electrical Specifications cont. EAB Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tEABDATA1 Delay from Data or Address to EAB for Combinatorial Input 5.5 6.5 8.5 ns tEABDATA2 Delay from Data or Address to EAB for Registered Input 1.1 1.3 1.8 ns tEABWE1 WE Delay to EAB for Combinatorial Input 2.4 2.8 3.7 ns tEABWE2 WE Delay to EAB for Registered Input 2.1 2.5 3.2 ns tEABCLK EAB Register Clock Delay 0.0 0.0 0.2 ns tEABCO EAB Register Clock-to-output Delay 1.7 2.0 2.6 ns 0.0 0.0 0.3 ns tEABBYPASS Bypass Register Delay tEABSU EAB Register Setup Time 1.2 1.4 1.9 ns tEABH EAB Register Hold Time 0.1 0.1 0.3 ns tAA Address Access Delay 4.2 5.0 6.5 ns tWP Write Pulse Width 3.8 4.5 5.9 ns tWDSU Data Setup Time Before Falling Edge of Write Pulse 0.1 0.1 0.2 ns tWDH Data Hold Time After Falling Edge of Write Pulse 0.1 0.1 0.2 ns tWASU Address Setup Time Before Rising Edge of Write Pulse 0.1 0.1 0.2 ns tWAH Address Hold After Falling Edge of Write Pulse 0.1 0.1 0.2 ns tWO Write Enable to Date Output Delay 3.7 4.4 6.4 ns tDD Data-in to Date-out Delay 3.7 4.4 6.4 ns tEABOUT Data-out Delay 0.0 0.1 0.6 ns tEABCH Clock High Time 3.0 3.5 4.0 ns tEABCL Clock Low Time 3.8 4.5 5.9 ns 10KA tbl 10C Page 12 LIBERATOR CL10K30A AC Electrical Specifications cont. EAB Timing Parameters[5] Speed: -1 Symbol tEABAA Parameter Min EAB Address Access Delay Max Speed: -2 Min 9.7 Max Speed: -3 Min 11.6 Max Unit 16.2 ns tEABRCCOMB EAB Asynchronous Read Cycle Time 9.7 11.6 16.2 ns tEABRCREG EAB Synchronous Read Cycle Time 5.9 7.1 9.7 ns 3.8 4.5 5.9 ns tEABWCCOMB EAB Asynchronous Write Cycle Time 4.0 4.7 6.3 ns tEABWCREG EAB Synchronous Write Cycle Time 9.8 11.6 16.6 ns tEABWP tEABDD EAB Write Pulse Width EAB Data-in to Data-out Delay 9.2 11.0 16.1 ns tEABDATACO EAB Clock-to-output Delay Using Output Registers 1.7 2.1 3.4 ns tEABDATASU EAB Data/Address Setup Time Using Input Register 2.3 2.7 3.5 ns tEABDATAH EAB Data/Address Hold Time Using Input Register 0.0 0.0 0.0 ns tEABWESU EAB WE Setup When Using Input Register 3.3 3.9 4.9 ns tEABWESH EAB WE Hold Time When Using Input Register 0.0 0.0 0.0 ns tEABWDSU EAB Data Setup Time to Falling Edge of Write Pulse When Not Using Input Registers 3.2 3.8 5.0 ns tEABWDH EAB Data Hold Time After Falling Edge of Write Pulse When Not Using Input Registers 0.0 0.0 0.0 ns tEABWASU EAB Address Setup Time to Rising Edge of Write Pulse When Not Using Input Registers 3.7 4.4 5.1 ns tEABWAH EAB Address Hold Time After Falling Edge of Write Pulse When Not Using Input Registers 0.0 0.0 0.0 ns tEABWO EAB WE to Data Output Delay 6.1 7.3 11.3 ns 10KA tbl 11C Page 13 LIBERATOR CL10K30A AC Electrical Specifications cont. External Bi-Directional Timing Parameters[5] Speed: -1 Symbol Parameter Min Max Speed: -2 Min Max Speed: -3 Min Max Unit tINSUBIDIR Setup for Bi-directional Pins with Global Clock at Adjacent LE Registers 4.2 4.9 6.8 ns tINHBIDIR Hold Time for Bi-directional Pins with Global Glock at Adjacent LE Registers 0.0 0.0 0.0 ns tOUTCOBIDIR Clock-to-output Delay for Bi-directional Pins with Global Clock at IOE Register 2.0 5.4 2.0 6.2 2.0 8.3 ns tXZBIDIR Synchronous IOE Output Buffer Disable Delay 6.2 7.5 9.8 ns tZXBIDIR Synchronous IOE Output Buffer Disable Delay, Slow Slew Rate = off 6.2 7.5 9.8 ns 10KA tbl 12C AC Test Conditions (A) VCCIO (B) 703 Ω VCCIO OUTPUT Includes jig capacitance All Input Pulses 703 Ω 3.0V 90% 90% OUTPUT 35 pF 8.06k Ω Includes jig capacitance 5 pF 8.06k Ω GND 10% 10% ≤ 3ns ≤ 3ns 10KA drw 02 A: Test fixture set-up A is for general testing. B: Test fixture set-up B is for high Z testing (tZX#). Notes to Tables 1. During transitions, inputs may undershoot to -2.0V or overshoot to 5.75V for periods shorter than 20ns. Otherwise, minimum DC input voltage is -0.5V. 2. Device inputs may be driven before VCCINT and VCCIO are powered. 3. Typical values are at VCC of 3.3 volts and ambient temperature of 25 ºC. 4. Guaranteed but not tested. Characterized initially, and after any design changes which may affect these parameters. 5. Internal timing delays are based on characterization, and cannot be explicitly tested. Internal timing parameters should be used for performance estimation only. 6. Use AC Test Conditions set-up B for these parameters. Revision History Page 14 20 Apr. 2000: Created new document 01 Dec. 2000: Updated package availability and additional literature available 04 Jan. 2001: Corrected table on AC Electrical Specifications 29 Mar. 2001: Added Pin Configuration for the FBGA 256-pin package LIBERATOR CL10K30A Ordering Information Part Number CL10K30ATC144-3 Temperature Range Commercial Package Type Altera Equivalent -3 EPF10K30ATC144-3 CL10K30ATC144-2 -2 EPF10K30ATC144-2 CL10K30ATC144-1 -1 EPF10K30ATC144-1 -3 EPF10K30ATI144-3 -3 EPF10K30AQC208-3 CL10K30AQC208-2 -2 EPF10K30AQC208-2 CL10K30AQC208-1 -1 EPF10K30AQC208-1 -3 EPF10K30AQI208-3 -3 EPF10K30AQC240-3 CL10K30AQC240-2 -2 EPF10K30AQC240-2 CL10K30AQC240-1 -1 EPF10K30AQC240-1 -3 EPF10K30AQI240-3 -3 EPF10K30AFC256-3 CL10K30AFC256-2 -2 EPF10K30AFC256-2 CL10K30AFC256-1 -1 EPF10K30AFC256-1 356-pin SBGA -3 EPF10K30ABC356-3 Use CL10K50VBC356* -2 EPF10K30ABC356-2 -1 EPF10K30ABC356-1 -3 EPF10K30ABI356-3 CL10K30ATI144-3 Industrial CL10K30AQC208-3 Commercial CL10K30AQI208-3 Industrial CL10K30AQC240-3 Commercial CL10K30AQI240-3 Industrial CL10K30AFC256-3 Commercial CL10K50VBC356-3 Commercial CL10K50VBC356-2 CL10K50VBC356-1 CL10K50VBI356-3 Industrial 144-pin TQFP Speed 208-pin Plastic QFP 240-pin Plastic QFP 256-pin FBGA 10K30A tbl 02 * The SBGA is not offered for the CL10K30A. Use the CL10K50V. This can be done by locking the I/Os in MAX+PLUS® II and recompiling to a CL10K50V. Test the part on your board with an Altera FLEX® EPF10K50V and then submit the bitstream to Clear Logic for production. Page 15 LIBERATOR CL10K30A Page 16