ISO150 Dual, Isolated, Bi-Directional DIGITAL COUPLER FEATURES APPLICATIONS ● REPLACES HIGH-PERFORMANCE OPTOCOUPLERS ● DATA RATE: 80M Baud, typ ● LOW POWER CONSUMPTION: 25mW Per Channel, max ● TWO CHANNELS, EACH BI-DIRECTIONAL, PROGRAMMABLE BY USER ● PARTIAL DISCHARGE TESTED: 2400Vrms ● CREEPAGE DISTANCE OF 16.5mm (DIP) ● DIGITAL ISOLATION FOR A/D, D/A CONVERSION ● ISOLATED UART INTERFACE ● MULTIPLEXED DATA TRANSMISSION ● ISOLATED PARALLEL TO SERIAL INTERFACE ● TEST EQUIPMENT ● MICROPROCESSOR SYSTEM INTERFACE ● ISOLATED LINE RECEIVER ● GROUND LOOP ELIMINATION ● LOW COST PER CHANNEL ● PLASTIC DIP AND SOIC PACKAGES DESCRIPTION The ISO150 is a two-channel, galvanically isolated data coupler capable of data rates of 80MBaud, typical. Each channel can be individually programmed to transmit data in either direction. Data is transmitted across the isolation barrier by coupling complementary pulses through high voltage 0.4pF capacitors. Receiver circuitry restores the pulses to standard logic levels. Differential signal transmission rejects isolation-mode voltage transients up to 1.6kV/µs. D2A R/T2A ISO150 avoids the problems commonly associated with optocouplers. Optically isolated couplers require high current pulses and allowance must be made for LED aging. The ISO150’s Bi-CMOS circuitry operates at 25mW per channel. ISO150 is available in a 24-pin DIP package and in a 28-lead SOIC. Both are specified for operation from –40˚C to 85˚C. GA VSB R/T2B D2B Channel 2 Side A Side B Channel 1 D1A SBOS032 R/T1A VSA GB R/T1B D1B International Airport Industrial Park • Mailing Address: PO Box 11400 Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706 Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 © 1993 Burr-Brown Corporation PDS-1213B Printed in U.S.A. August, 1994 SPECIFICATIONS TA = +25°C, VS = +5V unless otherwise noted. ISO150AP, AU PARAMETER ISOLATION PARAMETERS Rated Voltage, Continuous Partial Discharge, 100% Test(1) Creepage Distance (External) DIP—“P” Package SOIC—“U” Package Internal Isolation Distance Isolation Voltage Transient Immunity(2) Barrier Impedance Leakage Current DC PARAMETERS Logic Output Voltage, High, VOH Low, VOL Logic Output Short-Circuit Current Logic Input Voltage, High(3) Low(3) Logic Input Capacitance Logic Input Current Power Supply Voltage Range(3) Power Supply Current(4) Transmit Mode Receive Mode AC PARAMETERS Data Rate, Maximum(5) Data Rate, Minimum Propagation Time(6) Propagation Delay Skew(7) Pulse Width Distortion(8) Output Rise/Fall Time, 10% to 90% Mode Switching Time Receive-to-Transmit Transmit-to-Receive CONDITION MIN 60Hz 1s, 5pC 1500 2400 TYP IOH = 6mA IOL = 6mA Source or Sink VS–1 0 mm mm mm kV/µs Ω || pF µArms VS 0.4 30 2 0 3 DC 50MBaud DC 50MBaud VS 0.8 5 <1 5 0.001 14 7.2 16 CL = 50pF 50 DC 20 50pF 50pF 50pF 50pF 5.5 100 10 80 27 0.5 1.5 9 –40 –40 40 2 6 14 µA mA mA mA ns ns ns ns ns ns 85 125 75 V V mA V V pF nA V MBaud 13 75 TEMPERATURE RANGE Operating Range Storage Thermal Resistance,θJA UNITS Vrms Vrms 16 7.2 0.10 1.6 >1014 || 7 0.6 240Vrms, 60Hz CL = CL = CL = CL = MAX °C °C °C/W NOTES: (1) All devices receive a 1s test. Failure criterion is ≥5 pulses of ≥5pC. (2) The voltage rate-of-change across the isolation barrier that can be sustained without data errors. (3) Logic inputs are HCT-type and thresholds are a function of power supply voltage with approximately 0.4V hystersis—see text. (4) Supply current measured with both tranceivers set for the indicated mode. Supply current varies with data rate—see typical curves. (5) Calculated from the maximum Pulse Width Distortion (PWD), where Data Rate = 0.3/PWD. (6) Propagation time measured from VIN = 1.5V to VO = 2.5V. (7) The difference in propagation time of channel A and channel B in any combination of transmission directions. (8) The difference between progagation time of a rising edge and a falling edge. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® ISO150 2 PACKAGE INFORMATION(1) ABSOLUTE MAXIMUM RATINGS Storage Temperature ......................................................... –40°C to +125°C Supply Voltages, VS ...................................................................... –0.5 to 6V Transmitter Input Voltage, VI ............................................. –0.5 to VS + 0.5V Receiver Output Voltage, VO ............................................. –0.5 to VS + 0.5V R/TX Inputs ......................................................................... –0.5 to VS + 0.5V Isolation Voltage dV/dt, VISO ............................................................ 500kV/µs DX Short to Ground ...................................................................... Continuous Junction Temperature, TJ .................................................................... 175°C Lead Temperature (soldering, 10s) ..................................................... 260°C 1.6mm below seating plane (DIP package) ......................................... 300°C MODEL ISO150AP ISO150AU D1A R/T1A DIP R/T1A 2 VSA 3 24 D2A 22 GA GB Ground pin for transceivers 1B and 2B. Data in or data out for transceiver 1B. R/T1B held low makes D1B an input pin. D2B Data in or data out for transceiver 2B. R/T2B held low makes D2B an input pin. +5V supply pin for side B which powers transceivers 1B and 2B. GA Ground pin for transceivers 1A and 2A. VSA 3 GB 12 R/T1B 13 D1B 14 Data in or data out for transceiver 2A. R/T2A held low makes D2A in input pin. 14 R/T2B ELECTROSTATIC DISCHARGE SENSITIVITY 13 D2B This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. SOIC R/T1A 2 Receive/Transmit switch controlling transceiver 2A. 15 VSB TOP VIEW D1A 1 Receive/Transmit switch controlling D2B. VSB D2A D1B 12 Receive/Transmit switch controlling transceiver 1B. D1B R/T2A GB 10 Receive/Transmit switch controlling transceiver 1A. +5V supply pin for side A which powers transceivers 1A and 2A. R/T1B 23 R/T2A FUNCTION Data in or data out for transceiver 1A. R/T1A held low makes D1A an input pin. VSA R/T2B R/T1B 11 243-1 217-2 PIN DESCRIPTIONS PIN CONFIGURATION D1A 1 24-Pin Single-Wide DIP 28-Lead SOIC NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. NAME TOP VIEW PACKAGE DRAWING NUMBER PACKAGE ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 28 D2A 27 R/T2A 26 GA 17 VSB 16 R/T2B 15 D2B ® 3 ISO150 TYPICAL PERFORMANCE CURVES TA = +25°C, VS = +5V unless otherwise noted. SUPPLY CURRENT PER CHANNEL vs SUPPLY VOLTAGE CL = 15pF 10 No Load One Channel f = 1MHz = 2MBaud 4 40 Receive Mode 3 Power (mW) Supply Current (mA) POWER CONSUMPTION PER CHANNEL vs FREQUENCY 50 2 8 30 6 NOTE: Baud Rate = 2 • Frequency 20 4 Receive 1 Transmit 10 2 Transmit Mode 0 2 3 4 5 0 100k 6 1M 0 100M 10M Supply Voltage, VS (V) Frequency (Hz) SUPPLY CURRENT PER CHANNEL vs TEMPERATURE TYPICAL RISE AND FALL TIMES vs CAPACITIVE LOAD vs SUPPLY VOLTAGE 6 100 5 80 tr tf tr VS = 5.0V 4 tr, tf (ns) Supply Current (mA) 1 3 tf 60 VS = 3.0V 40 VS = 5.0V VS = 3.0V 2 20 0 1 –60 –40 –20 0 20 40 60 80 100 120 140 0 100 Temperature (°C) 200 300 400 500 Capacitive Load (pF) NORMALIZED RISE/FALL TIME vs TEMPERATURE PROPAGATION DELAY vs SUPPLY VOLTAGE 1.6 45 Relative tr, tf 1.4 Propagation Delay (ns) 1.5 CL = 50pF +1σ 1.3 1.2 Normalized to Average of Many Devices at 25°C 1.1 1.0 40 High to Low 35 30 Low to High 25 –1σ Pulse Width Distortion .9 20 –60 –40 –20 0 20 40 60 80 100 120 140 2.5 Temperature (°C) 3.5 4.0 4.5 Supply Voltage, VS (V) ® ISO150 3.0 4 5.0 5.5 Supply Current (mA) 5 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = +5V unless otherwise noted. PULSE WIDTH DISTORTION vs TEMPERATURE PROPAGATION DELAY vs TEMPERATURE 5 60 VS = 3.0V 50 Propagation Delay, tPD (ns) Pulse Width Distortion, PWD (ns) CL = 50pF 40 30 VS = 5.0V 20 10 0 4 VS = 5.0V CL = 50pF 3 2 1 0 –60 –40 –20 0 20 40 60 80 100 120 –60 –40 –20 140 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE OUTPUT VOLTAGE vs LOGIC INPUT VOLTAGE 2.0 1.8 5 VT HIGH, 125°C 1.6 4 1.2 1.0 VOUT (V) VIN (V) 1.4 VT LOW, –40°C 0.8 3 2 0.6 0.4 1 0.2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 Supply Voltage, VSS (V) 10m 2.1k 1m VISO = 1500Vrms 10µ 1.5 2.0 ISOLATION VOLTAGE vs FREQUENCY 10k Peak Isolation Voltage (V) Leakage Current (Arms) ISOLATION LEAKAGE CURRENT vs FREQUENCY 100m 100µ 1.0 VIN (V) VISO = 240Vrms Max DC Rating Degraded Performance 1k 100 10 1µ 100n 1 1 10 100 1k 10k 100k 1M 1k Frequency (Hz) 10k 100k 1M 10M 100M Frequency (Hz) ® 5 ISO150 TYPICAL PERFORMANCE CURVES (CONT) TA = +25°C, VS = +5V unless otherwise noted. TYPICAL INSULATION RESISTANCE vs TEMPERATURE 1016 Isolation Resistance (Ω) 1015 1014 1013 1012 1011 1010 0 20 40 60 80 100 120 140 160 180 Temperature (°C) Conventional isolation barrier testing applies test voltage far in excess of the rated voltage to catastrophically break down a marginal device. A device that passes the test may be weakened, and lead to premature failure. ISOLATION BARRIER Data is transmitted by coupling complementary logic pulses to the receiver through two 0.4pF capacitors. These capacitors are built into the ISO150 package with Faraday shielding to guard against false triggering by external electrostatic fields. The integrity of the isolation barrier of the ISO150 is verified by partial discharge testing. 2400Vrms, 60Hz, is applied across the barrier for one second while measuring any tiny discharge currents that may flow through the barrier. These current pulses are produced by localized ionization within the barrier. This is the most sensitive and reliable indicator of barrier integrity and longevity, and does not damage the barrier. A device fails the test if five or more current pulses of 5pC or greater are detected. APPLICATIONS INFORMATION Figure 1 shows the ISO150 connected for basic operation. Channel 1 is configured to transmit data from side B to A. Channel 2 is set for transmission from side A to B. The R/T pins for each of the four transceivers are shown connected to the required logic level for the transmission direction shown. The transmission direction can be controlled by logic signals applied to the R/T pins. Channel 1 and 2 can be independently controlled for the desired transmission direction. +5V(1) (Transmit) Channel 2 Data In D2A R/T2A (Receive) (2) (1) (1) Channel 2 Data Out VSB GA R/T2B D2B Channel 2 Side A NOTES: (1) Power Supplies and grounds on side A and side B are isolated. (2) Recommended bypass: 0.1µF in parallel with 1nF. Side B Channel 1 D1A Channel 1 Data Out R/T1A GB VSA (Receive) D1B (Transmit) (1) (1) +5V(1) FIGURE 1. Basic Operation Diagram. ® ISO150 R/T1B (2) 6 Channel 1 Data In LOGIC LEVELS A single pin serves as a data input or output, depending on the mode selected. Logic inputs are CMOS with thresholds set for TTL compatibility. The logic threshold is approximately 1.3V with 5V supplies and with approximately 400mV of hysteresis. Input logic thresholds vary with the power supply voltage. Drive the logic inputs with signals that swing the full logic voltage swing. The ISO150 will use somewhat greater quiescent current if logic inputs do not swing within 0.5V of the power supply rails. In receive mode, the data output can drive 15 standard LS-TTL loads. It will also drive CMOS loads. The output drive circuits are CMOS. PROPAGATION DELAY AND SKEW Logic transitions are delayed approximately 27ns through the ISO150. Some applications are sensitive to data skew— the difference in propagation delay between channel 1 and channel 2. Skew is less than 2ns between channel 1 and channel 2. Applications using more than one ISO150 must allow for somewhat greater skew from device to device. Since all devices are tested for delay times of 20ns min to 40ns max, 20ns is the largest device-to-device data skew. MODE CHANGES The transmission direction of a channel can be changed “on the fly” by reversing the logic levels at the channel’s R/T pins on both side A and side B. Approximately 75ns after the transceiver is programmed to receive mode its output is initialized “high”, and will respond to subsequent input-side changes in data. POWER SUPPLY Separate, isolated power supplies must be connected to side A and side B to provide galvanic isolation. Nominal rated supply voltage is 5V. Operation extends from 3V to 5.5V. Power supplies should be bypassed close to the device pins on both sides of the isolation barrier. The VS pin for each side powers the transceivers for both channel 1 and 2. The specified supply current is the total of both transceivers on one side, both operating in the indicated mode. Supply current for one transceiver in transmit mode and one in receive mode can be estimated by averaging the specifications for transmit and receive operation. Supply current varies with the data transmission rate—see typical curves. STANDBY MODE Quiescent current of each transceiver circuit is very low in transmit mode when input data is not changing (1nA typical). To conserve power when data transmission is not required, program both side A and B transceivers for transmit mode. Input data applied to either transceiver is ignored by the other side. High speed data applied to either transceiver will increase quiescent current. CIRCUIT LAYOUT The high speed of the ISO150 and its isolation barrier require careful circuit layout. Use good high speed logic layout techniques for the input and output data lines. Power supplies should be bypassed close to the device pins on both sides of the isolation barrier. Use low inductance connections. Ground planes are recommended. POWER-UP STATE The ISO150 transmits information across the barrier only when the input-side data changes logic state. When a transceiver is first programmed for receive mode, or is poweredup in receive mode, its output is initialized “high”. Subsequent changes of data applied to the input side will cause the output to properly reflect the input side data. Maintain spacing between side 1 and side 2 circuitry equal or greater than the spacing between the missing pins of the ISO150 (approximately 16mm for the DIP version). Sockets are not recommended. SIGNAL LOSS The ISO150’s differential-mode signal transmission and careful receiver design make it highly immune to voltage across the isolation barrier (isolation-mode voltage). Rapidly changing isolation-mode voltage can cause data errors. As the rate of change of isolation voltage is increased, there is a very sudden increase in data errors. Approximately 50% of ISO150s will begin to produce data errors with isolationmode transients of 1.6kV/µs. This may occur as low as 500V/µs in some devices. In comparison, a 1000Vrms, 60Hz isolation-mode voltage has a rate of change of approximately 0.5V/µs. Still, some applications with large, noisy isolation-mode voltage can produce data errors by causing the receiver output to change states. After a data error, subsequent changes in input data will produce correct output data. ® 7 ISO150 +5V DE LTC1485 +5V A BUS D1 Data (I/O) B D2A R/T2A GA VSB R/T2B D2B Channel 2 R0 Side A Side B RE Channel 1 D1A R/T1A VSA GB R/T1B DE/RE +5V "1" (+5V) FIGURE 2. Isolated RS-485 Interface. ® ISO150 8 D1B 9 ISO150 ® 50kΩ VCC1 VCC1 = VCC2 = +5V Isolated Supplies 50kΩ 1MΩ SDATA 19 20 TAG SCLK 18 DGND 14 23 CS 9 D7 26 REFD D5 11 EXT/INT 8 D6 10 D4 12 D3 13 D2 15 D1 16 SB/BTC AGND2 REF 7 6 5 D0 17 BYTE 21 25 PWRD +2.2µF +2.2µF R/C 22 2 CAP BUSY 24 4 VANA 27 AGND1 VDIG 28 R2IN R1IN 3 1 ADS7807 100Ω 100Ω BYTE 100Ω 100Ω 100nF 100nF 6.8µF 10µF D1A R/T1A VSA D2A R/T GA 2A D1A R/T1A VSA D2A R/T GA 2A 1Ω 1Ω FIGURE 3. ISO150 and ADS7807 is Used to Reduce Circuit Noise in a Mixed Signal Application. VIN 100Ω 200Ω 33.2Ω +5V VCC1 +5V VCC1 ISO150 +5V VCC1 ISO150 +5V VCC2 +5V +5V VCC2 GB R/T1B D1B VSB R/T2B D2B R/C GB R/T1B D1B VSB R/T2B D2B BUSY U2 QH QH QG QF QE QD QC QB 9 7 6 5 4 3 2 1 QA 15 74LS595 7 9 QH 6 QG 13 G QH 5 QF 12 RCLK 3 4 QD 2 QC QE 10 SRCLR 1 QB QA 15 Low Byte Enable High Byte Enable 11 SRCLK U3 14 SER VCC2 74LS595 13 G 12 RCLK 10 SRCLR 11 SRCLK 14 SER IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated