深圳市南天星电子科技有限公司 专业代理飞思卡尔 (Freescale) 飞思卡尔主要产品 8 位微控制器 16 位微控制器 数字信号处理器与控制器 i.MX 应用处理器 基于 ARM®技术的 Kinetis MCU 32/64 位微控制器与处理器 模拟与电源管理器件 射频器件（LDMOS，收发器） 传感器（压力，加速度，磁场， 触摸，电池） 飞思卡尔产品主要应用 汽车电子 数据连接 消费电子 工业控制 医疗保健 电机控制 网络 智能能源 深圳市南天星电子科技有限公司 电话：0755－83040796 传真：0755－83040790 邮箱：[email protected] 网址：www.soustar.com.cn 地址：深圳市福田区福明路雷圳大厦 2306 室 Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08PA4 Rev. 2, 12/20/2012 MC9S08PA4 MC9S08PA4 Series Supports: MC9S08PA4 Key features • 8-Bit S08 central processor unit (CPU) – Up to 20 MHz bus at 2.7 V to 5.5 V across temperature range of -40 °C to 105 °C – Supporting up to 40 interrupt/reset sources – Supporting up to four-level nested interrupt – On-chip memory – Up to 4 KB flash read/program/erase over full operating voltage and temperature – Up to 128 byte EEPROM; 2-byte erase sector; program and erase while executing flash – Up to 512 byte random-access memory (RAM) – Flash and RAM access protection • Power-saving modes – One low-power stop mode; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode • Clocks – Oscillator (XOSC) - loop-controlled Pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz – Internal clock source (ICS) - containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allowing 1% deviation across temperature range of 0 °C to 70 °C and 2% deviation across temperature range of -40 °C to 105 °C; up to 20 MHz • System protection – Watchdog with independent clock source – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode detection with reset – Illegal address detection with reset • Development support – Single-wire background debug interface – Breakpoint capability to allow three breakpoints setting during in-circuit debugging – On-chip in-circuit emulator (ICE) debug module containing two comparators and nine trigger modes • Peripherals – ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on rising and falling comparator output; filtering – ADC - 8-channel, 12-bit resolution; 2.5 µs conversion time; data buffers with optional watermark; automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware trigger – FTM - two 2-channel flex timer modulators modules; 16-bit counter; each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode – RTC - 16-bit real timer counter (RTC) – SCI - one serial communication interface (SCI/ UART) modules optional 13-bit break; full duplex non-return to zero (NRZ); LIN extension support • Input/Output – 18 GPIOs including one output-only pin – One 8-bit keyboard interrupt module (KBI) – Two, ultra-high current sink pins supporting 20 mA source/sink current • Package options – 20-pin SOIC – 16-pin TSSOP Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © 2011–2012 Freescale Semiconductor, Inc. Table of Contents 1 Ordering parts...........................................................................3 5.2 Switching specifications.....................................................12 1.1 Determining valid orderable parts......................................3 5.2.1 Control timing........................................................12 2 Part identification......................................................................3 5.2.2 Debug trace timing specifications.........................13 2.1 Description.........................................................................3 5.2.3 FTM module timing...............................................14 2.2 Format...............................................................................3 2.3 Fields.................................................................................3 5.3 Thermal specifications.......................................................15 5.3.1 Thermal characteristics.........................................15 2.4 Example............................................................................4 6 Peripheral operating requirements and behaviors....................16 3 Parameter Classification...........................................................4 6.1 External oscillator (XOSC) and ICS characteristics...........16 4 Ratings......................................................................................4 6.2 NVM specifications............................................................18 4.1 Thermal handling ratings...................................................4 6.3 Analog...............................................................................19 4.2 Moisture handling ratings..................................................5 6.3.1 ADC characteristics...............................................19 4.3 ESD handling ratings.........................................................5 6.3.2 Analog comparator (ACMP) electricals.................22 4.4 Voltage and current operating ratings...............................5 7 Dimensions...............................................................................23 5 General.....................................................................................6 7.1 Obtaining package dimensions.........................................23 5.1 Nonswitching electrical specifications...............................6 8 Pinout........................................................................................23 5.1.1 DC characteristics.................................................6 8.1 Signal multiplexing and pin assignments...........................23 5.1.2 Supply current characteristics...............................11 8.2 Device pin assignment......................................................24 5.1.3 EMC performance.................................................12 9 Revision history.........................................................................25 MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 2 Freescale Semiconductor, Inc. Ordering parts 1 Ordering parts 1.1 Determining valid orderable parts Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: PA4. 2 Part identification 2.1 Description Part numbers for the chip have fields that identify the specific part. You can use the values of these fields to determine the specific part you have received. 2.2 Format Part numbers for this device have the following format: MC 9 S08 PA AA B CC 2.3 Fields This table lists the possible values for each field in the part number (not all combinations are valid): Field Description Values MC Qualification status • MC = fully qualified, general market flow 9 Memory • 9 = flash based S08 Core • S08 = 8-bit CPU PA Device family • PA AA Approximate flash size in KB • 4 = 4 KB • 2 = 2 KB B Temperature range (°C) • V = –40 to 105 CC Package designator • WJ = 20-SOIC • TG = 16-TSSOP MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 3 Parameter Classification 2.4 Example This is an example part number: MC9S08PA4VWJ 3 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 1. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 4 Ratings 4.1 Thermal handling ratings Symbol Description Min. Max. Unit Notes TSTG Storage temperature –55 150 °C 1 TSDR Solder temperature, lead-free — 260 °C 2 1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 4 Freescale Semiconductor, Inc. Ratings 4.2 Moisture handling ratings Symbol MSL Description Moisture sensitivity level Min. Max. Unit Notes — 3 — 1 1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. 4.3 ESD handling ratings Symbol Description Min. Max. Unit Notes 1 VHBM Electrostatic discharge voltage, human body model -6000 +6000 V VCDM Electrostatic discharge voltage, charged-device model -500 +500 V Latch-up current at ambient temperature of 105°C -100 +100 mA ILAT 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 4.4 Voltage and current operating ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in below table may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this document. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor associated with the pin is enabled. Symbol Description Min. Max. Unit VDD Supply voltage –0.3 5.8 V IDD Maximum current into VDD — 120 mA VDIO Digital input voltage (except RESET, EXTAL, and XTAL) –0.3 VDD + 0.3 V VAIO Analog1, –0.3 VDD + 0.3 V –25 25 mA VDD – 0.3 VDD + 0.3 V ID VDDA RESET, EXTAL, and XTAL input voltage Instantaneous maximum current single pin limit (applies to all port pins) Analog supply voltage MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 5 General 1. Analog pins are defined as pins that do not have an associated general purpose I/O port function. 5 General 5.1 Nonswitching electrical specifications 5.1.1 DC characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 2. DC characteristics Symbol C — — VOH P Min Typical1 Max Unit — 2.7 — 5.5 V 5 V, Iload = -5 mA VDD - 0.8 — — V 3 V, Iload = -2.5 mA VDD - 0.8 — — V High current drive pins, high-drive strength2 5 V, Iload = -20 mA VDD - 0.8 — — V 3 V, Iload = -10 mA VDD - 0.8 — — V Max total IOH for all ports 5V — — -100 mA 3V — — -50 — — 0.8 V 3 V, Iload = 2.5 mA — — 0.8 V 5 V, Iload =20 mA — — 0.8 V 3 V, Iload = 10 mA — — 0.8 V mA Descriptions Operating voltage Output high voltage All I/O pins, standarddrive strength C P C IOHT VOL D P Output high current Output low voltage All I/O pins, standard- 5 V, Iload = 5 drive strength mA C P High current drive pins, high-drive strength2 C IOLT VIH VIL Vhys D P P C Output low current Max total IOL for all ports 5V — — 100 3V — — 50 Input high voltage All digital inputs VDD>4.5V 0.70 × VDD — — VDD>2.7V 0.75 × VDD — — Input low voltage All digital inputs VDD>4.5V — — 0.30 × VDD VDD>2.7V — — 0.35 × VDD Input hysteresis All digital inputs — 0.06 × VDD — — V V mV Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 6 Freescale Semiconductor, Inc. Nonswitching electrical specifications Table 2. DC characteristics (continued) Min Typical1 Max Unit VIN = VDD or VSS — 0.1 1 µA VIN = VDD or VSS — 0.1 1 µA Total leakage All input only and I/O VIN = VDD or combined for VSS all inputs and Hi-Z pins — — 2 µA — 30.0 — 50.0 kΩ PTA5/IRQ/TCLK/ RESET — 30.0 — 50.0 kΩ Single pin limit VIN < VSS, VIN > VDD -0.2 — 2 mA -5 — 25 Symbol C Descriptions |IIn| P Input leakage current All input only pins (per pin) |IOZ| P Hi-Z (offstate) leakage current All input/output (per pin) |IOZTOT| C RPU P Pullup resistors All digital inputs, when enabled (all I/O pins other than PTA5/ IRQ/TCLK/RESET RPU3 P Pullup resistors IIC D DC injection current4, 5, 6 Total MCU limit, includes sum of all stressed pins CIn C Input capacitance, all pins — — — 7 pF VRAM C RAM retention voltage — 2.0 — — V 1. Typical values are measured at 25 °C. Characterized, not tested. 2. Only PTB4, PTB5 support ultra high current output. 3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured externally on the pin. 4. All functional non-supply pins, except for PTA5, are internally clamped to VSS and VDD. 5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the large one. 6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is very low (which would reduce overall power consumption). Table 3. LVD and POR Specification Symbol C VPOR D VLVDH C Description POR re-arm voltage1, 2 Falling low-voltage detect threshold - high range (LVDV = 1)3 Min Typ Max Unit 1.5 1.75 2.0 V 4.2 4.3 4.4 V Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 7 Nonswitching electrical specifications Table 3. LVD and POR Specification (continued) 1. 2. 3. 4. Symbol C VLVW1H C VLVW2H C VLVW3H C VLVW4H C VHYSH C VLVDL C VLVDW1L C VLVDW2L C VLVDW3L C VLVDW4L Description Min Typ Max Unit Level 1 falling (LVWV = 00) 4.3 4.4 4.5 V Level 2 falling (LVWV = 01) 4.5 4.5 4.6 V Level 3 falling (LVWV = 10) 4.6 4.6 4.7 V Level 4 falling (LVWV = 11) 4.7 4.7 4.8 V High range low-voltage detect/warning hysteresis — 100 — mV Falling low-voltage detect threshold - low range (LVDV = 0) 2.56 2.61 2.66 V Level 1 falling (LVWV = 00) 2.62 2.7 2.78 V Level 2 falling (LVWV = 01) 2.72 2.8 2.88 V Level 3 falling (LVWV = 10) 2.82 2.9 2.98 V C Level 4 falling (LVWV = 11) 2.92 3.0 3.08 V VHYSDL C Low range low-voltage detect hysteresis — 40 — mV VHYSWL C Low range low-voltage warning hysteresis — 80 — mV VBG P Buffered bandgap output 4 1.14 1.16 1.18 V Falling lowvoltage warning threshold high range Falling lowvoltage warning threshold low range Maximum is highest voltage that POR is guaranteed. POR ramp time must be longer than 20us/V to get a stable startup. Rising thresholds are falling threshold + hysteresis. Voltage factory trimmed at VDD = 5.0 V, Temp = 25 °C MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 8 Freescale Semiconductor, Inc. Nonswitching electrical specifications 0.7 0.6 VDD = 3 V 0.5 VDD-VOH(V) 0.4 VDD = 5 V 0.3 0.2 0.1 0 1 2 3 4 IOH(mA) 5 6 Figure 1. Typical IOH Vs. VDD-VOH 0.8 0.7 VDD = 3 V 0.6 0.5 VDD = 5 V VDD-VOH(V) 0.4 0.3 0.2 0.1 0 5 10 15 IOH(mA) 20 25 Figure 2. Typical IOH Vs. VDD-VOH (High current drive) MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 9 Nonswitching electrical specifications 0.6 VDD = 3 V 0.5 0.4 VDD = 5 V VOL(V) 0.3 0.2 0.1 0 1 2 3 4 IOL(mA) 5 6 Figure 3. Typical IOL Vs. VOL 0.7 0.6 VDD = 3 V 0.5 VOL(V) 0.4 VDD = 5 V 0.3 0.2 0.1 0 5 10 15 IOL(mA) 20 25 Figure 4. Typical IOL Vs. VOL (High current drive) MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 10 Freescale Semiconductor, Inc. Nonswitching electrical specifications 5.1.2 Supply current characteristics This section includes information about power supply current in various operating modes. Table 4. Supply current characteristics Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit Temp 1 C Run supply current FEI mode, all modules on; run from flash RIDD 20 MHz 5 5.43 — mA -40 to 105 °C 10 MHz 3.46 — 1 MHz 1.71 — 5.35 — mA -40 to 105 °C mA -40 to 105 °C mA -40 to 105 °C mA -40 to 105 °C µA -40 to 105 °C C 2 C 20 MHz C 10 MHz 3.45 — 1 MHz 1.69 — 4.51 — 10 MHz 3.01 — 1 MHz 1.68 — 4.47 — C C 3 5 C 10 MHz 2.99 — 1 MHz 1.65 — P Run supply current FBE mode, all modules on; run from RAM RIDD 20 MHz 3 5.31 7.41 10 MHz 5 3.17 — 1 MHz 1.25 — 5.29 — C 20 MHz C 10 MHz 3.17 — 1 MHz 1.24 — 4.39 6.59 2.71 — 1.21 — 4.39 — P Run supply current FBE mode, all modules off and gated; run from RAM RIDD 20 MHz 3 5 10 MHz 1 MHz C 20 MHz C 10 MHz 2.71 — 1 MHz 1.20 — 3.62 — 10 MHz 2.27 — 1 MHz 1.11 — 3.61 — 10 MHz 2.31 — 1 MHz 1.10 — C C Wait mode current FEI mode, all modules on WIDD C 6 20 MHz 20 MHz C 5 RIDD C C 4 Run supply current FEI mode, all modules off and gated; run from flash 3 C C 20 MHz 20 MHz Stop3 mode supply current no clocks active (except 1 kHz LPO clock) S3IDD 3 5 3 — 5 5.4 — — 3 1.40 — -40 to 105 °C Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 11 Switching specifications Table 4. Supply current characteristics (continued) Num C Parameter Symbol Bus Freq VDD (V) Typical1 Max Unit Temp 7 C ADC adder to stop3 — — 5 96.0 — µA -40 to 105 °C C ADLPC = 1 — — 3 88.3 — — — 5 129 — µA -40 to 105 °C 3 126 — ADLSMP = 1 ADCO = 1 MODE = 10B ADICLK = 11B 8 C LVD adder to stop32 C 1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms. 5.1.3 EMC performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 5.2 Switching specifications 5.2.1 Control timing Table 5. Control timing Symbol Min Typical1 Max Unit fBus DC — 20 MHz fLPO 0.67 1.0 1.25 KHz textrst 1.5 × — — ns 34 × tcyc — — ns tMSSU 500 — — ns tMSH 100 — — ns Num C Rating 1 P Bus frequency (tcyc = 1/fBus) 2 P Internal low power oscillator frequency 3 D External reset pulse width2 4 D Reset low drive trstdrv 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes3 tSelf_reset Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 12 Freescale Semiconductor, Inc. Switching specifications Table 5. Control timing (continued) Num C 7 D Rating IRQ pulse width D 8 D Keyboard interrupt pulse width D 9 C C C C Symbol Min Asynchronous path2 tILIH 100 Synchronous path4 tIHIL 1.5 × tcyc Asynchronous path2 tILIH 100 Typical1 Max Unit — — ns — — ns — — ns Synchronous path tIHIL 1.5 × tcyc — — ns Port rise and fall time Normal drive strength (HDRVE_PTXx = 0) (load = 50 pF)5 — tRise — 10.2 — ns tFall — 9.5 — ns Port rise and fall time Extreme high drive strength (HDRVE_PTXx = 1) (load = 50 pF)5 — tRise — 5.4 — ns tFall — 4.6 — ns 1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. 2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after VDD rises above VLVD. 4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 5. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 105 °C. textrst RESET PIN Figure 5. Reset timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 6. IRQ/KBIPx timing 5.2.2 Debug trace timing specifications Table 6. Debug trace operating behaviors Symbol Description Min. Max. Unit tcyc Clock period Frequency dependent MHz twl Low pulse width 2 — ns twh High pulse width 2 — ns Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 13 Switching specifications Table 6. Debug trace operating behaviors (continued) Symbol Description Min. Max. Unit tr Clock and data rise time — 3 ns tf Clock and data fall time — 3 ns ts Data setup 3 — ns th Data hold 2 — ns Figure 7. TRACE_CLKOUT specifications TRACE_CLKOUT Ts Ts Th Th TRACE_D[3:0] Figure 8. Trace data specifications 5.2.3 FTM module timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 7. FTM input timing No. C Function Symbol Min Max Unit 1 D External clock frequency fTCLK 0 fBus/4 Hz 2 D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 14 Freescale Semiconductor, Inc. Thermal specifications tTCLK tclkh TCLK tclkl Figure 9. Timer external clock tICPW FTMCHn FTMCHn tICPW Figure 10. Timer input capture pulse 5.3 Thermal specifications 5.3.1 Thermal characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is userdetermined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 8. Thermal characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH -40 to 105 °C Junction temperature range TJ -40 to 150 °C Thermal resistance single-layer board 20-pin SOIC θJA 83 °C/W 16-pin TSSOP θJA 131 °C/W Thermal resistance four-layer board 20-pin SOIC θJA 55 °C/W 16-pin TSSOP θJA 89 °C/W MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 15 Peripheral operating requirements and behaviors The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts - chip internal power PI/O = Power dissipation on input and output pins - user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273 °C) Solving the equations above for K gives: K = PD × (TA + 273 °C) + θJA × (PD)2 where K is a constant pertaining to the particular part. K can be determined by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving the above equations iteratively for any value of TA. 6 Peripheral operating requirements and behaviors 6.1 External oscillator (XOSC) and ICS characteristics Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient) Symbol Min Typical1 Max Unit Low range (RANGE = 0) flo 32 — 40 kHz High range (RANGE = 1) FEE or FBE mode2 fhi 4 — 20 MHz C High range (RANGE = 1), high gain (HGO = 1), FBELP mode fhi 4 — 20 MHz C High range (RANGE = 1), low power (HGO = 0), FBELP mode fhi 4 — 20 MHz Num C 1 C C 2 D Characteristic Oscillator crystal or resonator Load capacitors C1, C2 See Note3 Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 16 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 9. XOSC and ICS specifications (temperature range = -40 to 105 °C ambient) (continued) Num C 3 D 4 5 Min Typical1 Max Unit Feedback resistor RF — — — MΩ Low Frequency, High-Gain Mode — 10 — MΩ High Frequency, LowPower Mode — 1 — MΩ High Frequency, High-Gain Mode — 1 — MΩ — — — kΩ — 200 — kΩ — — — kΩ 4 MHz — 0 — kΩ 8 MHz — 0 — kΩ 16 MHz — 0 — kΩ — 1000 — ms — 800 — ms — 3 — ms — 1.5 — ms tIRST — 20 50 µs fextal 0.03125 — 5 MHz 0 — 20 MHz Low Frequency, Low-Power Mode4 Series resistor Low Frequency Low-Power Mode 4 D Series resistor High Frequency Mode4 D Series resistor High Frequency, High-Gain Mode D D D 6 Symbol Characteristic C C C C 7 T 8 D D Crystal start-up time Low range = 32.768 KHz crystal; High range = 20 MHz crystal5, 6 High-Gain Mode Low-Power Low range, low power RS tCSTL Low range, high power High range, low power tCSTH High range, high power Internal reference start-up time Square wave input clock frequency RS FEE or FBE mode2 FBELP mode 9 P Average internal reference frequency trimmed fint_t — 32.768 — kHz 10 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz 11 P Δfdco_t — — ±2.0 %fdco C Total deviation of DCO output from trimmed frequency5 Over full voltage and temperature range Over fixed voltage and temperature range of 0 to 70 °C ±1.0 12 C FLL acquisition time5, 7 tAcquire — — 2 ms 13 C Long term jitter of DCO output clock (averaged over 2 ms interval)8 CJitter — 0.02 0.2 %fdco 1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. 2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3. See crystal or resonator manufacturer's recommendation. 4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0. 5. This parameter is characterized and not tested on each device. 6. Proper PC board layout procedures must be followed to achieve specifications. MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 17 Peripheral operating requirements and behaviors 7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. XOSC EXTAL XTAL RS RF Crystal or Resonator C1 C2 Figure 11. Typical crystal or resonator circuit 6.2 NVM specifications This section provides details about program/erase times and program/erase endurance for the flash and EEPROM memories. Table 10. Flash characteristics C Characteristic Symbol Min1 Typical2 Max3 Unit4 D Supply voltage for program/erase -40 °C to 105 °C Vprog/erase 2.7 — 5.5 V D Supply voltage for read operation VRead 2.7 — 5.5 V D NVM Bus frequency fNVMBUS 1 — 25 MHz D NVM Operating frequency fNVMOP 0.8 — 1.05 MHz D Erase Verify All Blocks tVFYALL — — 17030 tcyc D Erase Verify Flash Block tRD1BLK — — 16977 tcyc D Erase Verify EEPROM Block tRD1BLK — — 843 tcyc D Erase Verify Flash Section tRD1SEC — — 517 tcyc D Erase Verify EEPROM Section tDRD1SEC 0.10 0.10 0.11 ms D Read Once tRDONCE — — 455 tcyc D Program Flash (2 word) tPGM2 0.12 0.12 0.14 ms D Program Flash (4 word) tPGM4 0.20 0.21 0.24 ms D Program Once tPGMONCE 0.20 0.21 0.24 ms D Program EEPROM (1 Byte) tDPGM1 0.02 0.02 0.02 ms Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 18 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 10. Flash characteristics (continued) 1. 2. 3. 4. C Characteristic Symbol Min1 Typical2 Max3 Unit4 D Program EEPROM (2 Byte) tDPGM2 0.17 0.18 0.20 ms D Erase All Blocks tERSALL 96.01 100.78 125.80 ms D Erase Flash Block tERSBLK 95.98 100.75 125.76 ms D Erase Flash Sector tERSPG 19.10 20.05 25.05 ms D Erase EEPROM Sector tDERSPG 4.81 5.05 6.30 ms D Unsecure Flash tUNSECU 96.01 100.78 125.80 ms D Verify Backdoor Access Key tVFYKEY — — 469 tcyc D Set User Margin Level tMLOADU — — 442 tcyc C FLASH Program/erase endurance TL to TH = -40 °C to 105 °C nFLPE 10 k 100 k — Cycles C EEPROM Program/erase endurance TL to TH = -40 °C to 105 °C nFLPE 50 k 500 k — Cycles C Data retention at an average junction temperature of TJavg = 85°C after up to 10,000 program/erase cycles tD_ret 15 100 — years Minimun times are based on maximum fNVMOP and maximum fNVMBUS Typical times are based on typical fNVMOP and maximum fNVMBUS Maximum times are based on minimum fNVMOP and maximum fNVMBUS tcyc = 1 / fNVMBUS Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. 6.3 Analog 6.3.1 ADC characteristics Table 11. 5 V 12-bit ADC operating conditions Characteri stic Conditions Symb Min Typ1 Max Unit Comment Supply voltage Absolute VDDA 2.7 — 5.5 V — Delta to VDD (VDD-VDDAD) ΔVDDA -100 0 +100 mV )2 ΔVSSA -100 0 +100 mV Input voltage VADIN VREFL — VREFH V Input capacitance CADIN — 4.5 5.5 pF Ground voltage Delta to VSS (VSS-VSSA Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 19 Peripheral operating requirements and behaviors Table 11. 5 V 12-bit ADC operating conditions (continued) Characteri stic Conditions Input resistance Analog source resistance • • 12-bit mode fADCK > 4 MHz fADCK < 4 MHz • • 10-bit mode fADCK > 4 MHz fADCK < 4 MHz Symb Min Typ1 Max Unit Comment RADIN — 3 5 kΩ — RAS — — 2 kΩ External to MCU — — 5 — — 5 — — 10 — — 10 0.4 — 8.0 MHz — 0.4 — 4.0 8-bit mode (all valid fADCK) ADC conversion clock frequency High speed (ADLPC=0) fADCK Low power (ADLPC=1) 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. DC potential difference. SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS R AS z ADIN SIMPLIFIED CHANNEL SELECT CIRCUIT R ADIN ADC SAR ENGINE v ADIN v AS C AS R ADIN INPUT PIN INPUT PIN R ADIN R ADIN INPUT PIN C ADIN Figure 12. ADC input impedance equivalency diagram MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 20 Freescale Semiconductor, Inc. Peripheral operating requirements and behaviors Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Characteristic Conditions Supply current C Symb Min Typ1 Max Unit T IDDA — 133 — µA T IDDA — 218 — µA T IDDA — 327 — µA T IDDAD — 582 990 µA ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply current Stop, reset, module off T IDDA — 0.011 1 µA ADC asynchronous clock source High speed (ADLPC = 0) P fADACK 2 3.3 5 MHz 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — ±5.0 — Low power (ADLPC = 1) Conversion time (including sample time) Short sample (ADLSMP = 0) Sample time Short sample (ADLSMP = 0) T tADC Long sample (ADLSMP = 1) T tADS Long sample (ADLSMP = 1) Total unadjusted Error2 Differential NonLiniarity 12-bit mode T ETUE 10-bit mode P — ±1.5 ±2.0 8-bit mode P — ±0.7 ±1.0 12-bit mode T — ±1.0 — 10-bit mode4 DNL P — ±0.25 ±0.5 mode4 P — ±0.15 ±0.25 Integral Non-Linearity 12-bit mode T — ±1.0 — 10-bit mode T — ±0.3 ±0.5 8-bit mode T — ±0.15 ±0.25 8-bit INL ADCK cycles ADCK cycles LSB3 LSB3 LSB3 Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 21 Peripheral operating requirements and behaviors Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) Characteristic Conditions C Symb Min Typ1 Max Unit Zero-scale error5 12-bit mode C EZS — ±2.0 — LSB3 10-bit mode P — ±0.25 ±1.0 8-bit mode P — ±0.65 ±1.0 12-bit mode T — ±2.5 — 10-bit mode T — ±0.5 ±1.0 8-bit mode T — ±0.5 ±1.0 Quantization error ≤12 bit modes D EQ — — ±0.5 LSB3 Input leakage error7 all modes D EIL Temp sensor slope -40°C– 25°C D m mV/°C Full-scale error6 EFS IIn * RAS 25°C– 125°C Temp sensor voltage 25°C D LSB3 VTEMP25 mV — 3.266 — — 3.638 — — 1.396 — V 1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2. Includes quantization. 3. 1 LSB = (VREFH - VREFL)/2N 4. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 5. VADIN = VSSA 6. VADIN = VDDA 7. IIn = leakage current (refer to DC characteristics) 6.3.2 Analog comparator (ACMP) electricals Table 13. Comparator electrical specifications C Characteristic Symbol Min Typical Max Unit D Supply voltage VDDA 2.7 — 5.5 V T Supply current (Operation mode) IDDA — 10 20 µA D Analog input voltage VAIN VSS - 0.3 — VDDA V P Analog input offset voltage VAIO — — 40 mV C Analog comparator hysteresis (HYST=0) VH — 15 20 mV C Analog comparator hysteresis (HYST=1) VH — 20 30 mV T Supply current (Off mode) IDDAOFF — 60 — nA C Propagation Delay tD — 0.4 1 µs MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 22 Freescale Semiconductor, Inc. Dimensions 7 Dimensions 7.1 Obtaining package dimensions Package dimensions are provided in package drawings. To find a package drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number: If you want the drawing for this package Then use this document number 16-pin TSSOP 98ASH70247A 20-pin SOIC 98ASB42343B 8 Pinout 8.1 Signal multiplexing and pin assignments The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT functionality is available on each pin. Table 14. Pin availability by package pin-count Pin Number Lowest Priority <-- --> Highest 20-SOIC 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 PTA5 IRQ FTM1CH0 — RESET 2 2 PTA4 — ACMPO BKGD MS 3 3 — — — — VDD 4 4 — — — — VSS 5 5 PTB7 — — — EXTAL 6 6 PTB6 — — — XTAL 7 PTB51 — FTM1CH1 — — 8 8 PTB41 — FTM1CH0 — — 9 — PTC3 — — — — 10 — PTC2 — — — — 11 — PTC1 — — — — 12 — PTC0 — — — — 7 Table continues on the next page... MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. Freescale Semiconductor, Inc. 23 Pinout Table 14. Pin availability by package pin-count (continued) Pin Number Lowest Priority <-- --> Highest 20-SOIC 16-TSSOP Port Pin Alt 1 Alt 2 Alt 3 Alt 4 13 9 PTB3 KBI0P7 — TCLK1 ADP7 14 10 PTB2 KBI0P6 — — ADP6 15 11 PTB1 KBI0P5 TxD0 — ADP5 16 12 PTB02 KBI0P4 RxD0 TCLK0 ADP4 17 13 PTA3 KBI0P3 FTM0CH1 TxD0 ADP3 18 14 PTA2 KBI0P2 FTM0CH0 RxD0 ADP2 19 15 PTA1 KBI0P1 FTM0CH1 ACMP1 ADP1 20 16 PTA0 KBI0P0 FTM0CH0 ACMP0 ADP0 1. This is a high current drive pin when operated as output. 2. This is a true open-drain pin when operated as output. Note When an alternative function is first enabled, it is possible to get a spurious edge to the module. User software must clear any associated flags before interrupts are enabled. The table above illustrates the priority if multiple modules are enabled. The highest priority module will have control over the pin. Selecting a higher priority pin function with a lower priority function already enabled can cause spurious edges to the lower priority module. Disable all modules that share a pin before enabling another module. 8.2 Device pin assignment PTA5/IRQ/FTM1CH0/RESET 1 20 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA4/ACMPO/BKGD/MS VDD VSS 2 19 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 3 18 PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 4 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 PTB7/EXTAL 5 17 16 PTB6/XTAL 6 PTB5/FTM1CH11 PTB4/FTM1CH01 7 PTC3 8 9 PTC2 10 PTB0/KBI0P4/RxD0/TCLK0/ADP4 2 15 14 13 PTB3/KBI0P7/TCLK1/ADP7 12 PTC0 11 PTC1 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/ADP6 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 13. MC9S08PA4 20-pin SOIC package MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 24 Freescale Semiconductor, Inc. Revision history PTA5/IRQ/FTM1CH0/RESET PTA4/ACMPO/BKGD/MS VDD VSS PTB7/EXTAL PTB6/XTAL PTB5/FTM1CH11 PTB4/FTM1CH01 1 16 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 2 PTA2/KBI0P2/FTM0CH0/RxD0/ADP2 4 15 14 13 PTA3/KBI0P3/FTM0CH1/TxD0/ADP3 5 12 PTB0/KBI0P4/RxD0/TCLK0/ADP42 6 7 11 10 PTB2/KBI0P6/ADP6 8 9 3 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 PTB1/KBI0P5/TxD0/ADP5 PTB3/KBI0P7/TCLK1/ADP7 Pins in bold are not available on less pin-count packages. 1. High source/sink current pins 2. True open drain pins Figure 14. MC9S08PA4 16-pin TSSOP package 9 Revision history The following table provides a revision history for this document. Table 15. Revision history Rev. No. Date 1 12/2012 Substantial Changes Initial public release MC9S08PA4 Series Data Sheet, Rev. 2, 12/20/2012. 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