FREESCALE MM908E626AVPEK

深圳市南天星电子科技有限公司
专业代理飞思卡尔
(Freescale)
飞思卡尔主要产品
8 位微控制器
16 位微控制器
数字信号处理器与控制器
i.MX 应用处理器
基于 ARM®技术的 Kinetis MCU
32/64 位微控制器与处理器
模拟与电源管理器件
射频器件(LDMOS,收发器)
传感器(压力,加速度,磁场,
触摸,电池)
飞思卡尔产品主要应用
汽车电子
数据连接
消费电子
工业控制
医疗保健
电机控制
网络
智能能源
深圳市南天星电子科技有限公司
电话:0755-83040796
传真:0755-83040790
邮箱:[email protected]
网址:www.soustar.com.cn
地址:深圳市福田区福明路雷圳大厦 2306 室
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MM908E626
Rev 1.0, 11/2004
SEMICONDUCTOR TECHNICAL DATA
Advance Information
908E626
Freescale Semiconductor, Inc...
Integrated Stepper Motor Driver
with Embedded MCU and LIN Serial
Communication
STEPPER MOTOR DRIVER
WITH EMBEDDED MCU AND LIN
The 908E626 is an integrated single-package solution that includes a highperformance HC08 microcontroller with a SMARTMOS TM analog control IC.
The HC08 includes flash memory, a timer, enhanced serial communications
interface (ESCI), an analog-to-digital converter (ADC), serial peripheral
interface (SPI) (only internal), and an internal clock generator (ICG) module.
The analog control die provides fully protected H-Bridge outputs, voltage
regulator, autonomous watchdog, and local interconnect network (LIN)
physical layer.
The single-package solution, together with LIN, provides optimal
application performance adjustments and space-saving PCB design. It is well
suited for the control of automotive stepper applications like climate control
and light-levelling.
Features
• High-Performance M68HC08EY16 Core
• 16 K Bytes of On-Chip Flash Memory
• 512 Bytes of RAM
• Internal Clock Generation Module
• Two 16-Bit, 2-Channel Timers
• 10-Bit Analog-to-Digital Converter
• Four Low RDS(ON) Half-Bridge Outputs
DWB SUFFIX
CASE 1400-01
54-TERMINAL SOICWB-EP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MM908E626AVDWB/R2
-40°C to 115°C
54 SOIC
WB-EP
• 13 Microcontroller I/Os
908E626
Simplified
Application
Diagram
908E626
Simplified
Application
Diagram
Note Applications with
multiple stepper motors
in one system (e.g., climate
control) typically have a
central reverse battery
protection.
908E626
LIN
VREFH
VDDA
EVDD
VDD
VSUP[1:3]
HB1
HB2
VREFL
VSSA
EVSS
VSS
RST
RST_A
IRQ
IRQ_A
SS
PTB1/AD1
RXD
PTE1/RXD
PTD1/TACH1
FGEN
BEMF
PTD0/TACH0/BEMF
HB3
HB4
HVDD
GND[1:2] EP
Port A I/Os
Port B I/Os
Port C I/Os
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
S
N
Bipolar
Step
Motor
Switchable Internal
VDD Output
Microcontroller
Ports
908E626
2
For More Information On This Product,
Go to: www.freescale.com
FLSVPP
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
VDDA
PTA1/KBD1
PTA0/KBD0
EVDD
VDD
VSS
PTA6/SS
PTA5/SPSCK
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Security Module
Power-On Reset
Module
POWER
10 Bit Analog-toDigital Converter
Module
Single External IRQ
Module
24 Internal System
Integration Module
Internal Clock
Generator Module
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB2/AD2
PTB1/AD1
PTB0/AD0
VREFH
VDDA
VREFL
VSSA
IRQ
RST
OSC2
OSC1
User Flash Vector Space,
36 Bytes
Flash Programming (burn in)
ROM, 1024 Bytes
Monitor ROM, 310 Bytes
User RAM, 512 Bytes
User Flash, 15,872 Bytes
Control and Status Register,
64 Bytes
ALU
M68HC08 CPU
EVSS
CPU
Registers
VSSA
PORT A
VREFL
PORT B
PTE1/RXD
PTD1/TACH1
MCU Die
PTB0/AD0
PTA5/SPSCK
PTC1/MOSI
PTC0/MISO
PTE0/TXD
ADOUT
SPSCK
MOSI
MISO
SS
TXD
Analog
Multiplexer
VSUP
Prescaler
Chip Temp
Autonomous
Watchdog
SPI
&
CONTROL
Interrupt
Control
Module
Reset Control
Module
LIN Physical
Layer
Analog Die
RXD
Figure 1. 908E626 Simplified Internal Block Diagram
PTE0/TxD
PTE1/RxD
PTD0/TACH0
PTD1/TACH1
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTC1/MOSI
PTC0/MISO
BEMF Module
Prescaler Module
Arbiter Module
Periodic Wake-Up
Timebase Module
Configuration Register
Module
Serial Pheripheral
Interface Module
Computer Operating
Properly Module
Enhanced Serial
Communication
Interface Module
2-channel Timer
Interface Module B
2-Channel Timer
Interface Module A
5-Bit Keyboard
Interrupt Module
Single Breakpoint
Break Module
RST
Internal Bus
PTB1/AD1
DDRA
PTD0/TACH0
DDRC
SS
PORT C
LIN
DDRD
FGEN
PORT D
BEMF
FGEN
BEMF
FGEN
BEMF
FGEN
BEMF
FGEN
RST_A
DDRE
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Half Bridge
Driver &
Diagnostic
Switched VDD
Driver &
Diagnostic
Voltage
Regulator
VSUP1-3
PORT E
GND1-2
DDRB
Freescale Semiconductor, Inc...
VSUP
VSUP
VSUP
VSUP
HB4
HB3
HB2
HB1
HVDD
VDD
VSS
Freescale Semiconductor, Inc.
Figure 1. 908E626 Simplified Internal Block Diagram
IRQ_A
BEMF
IRQ
VREFH
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Transparent Top
View of Package
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
1
54
2
53
3
52
4
51
5
50
6
49
7
48
8
47
IRQ
RST
9
46
10
45
PTB1/AD1
PTD0/TACH0/BEMF
PTD1/TACH1
NC
FGEN
BEMF
11
44
12
43
16
39
RST_A
17
38
IRQ_A
SS
18
37
19
36
LIN
NC
NC
HB1
VSUP1
GND1
HB2
VSUP2
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
13
14
15
42
Exposed
Pad
41
40
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VREFH
VDDA
EVDD
EVSS
VSSA
VREFL
PTE1/RXD
RXD
VSS
NC
VDD
NC
NC
NC
HVDD
NC
HB4
VSUP3
GND2
HB3
NC
TERMINAL DEFINITIONS
A functional description of each terminal can be found in the System/Application Information section beginning on page 14.
Die
Terminal
Terminal Name
Formal Name
Definition
MCU
1
2
6
7
8
11
PTB7/AD7/TBCH1
PTB6/AD6/TBCH0
PTB5/AD5
PTB4/AD4
PTB3/AD3
PTB1/AD1
Port B I/Os
These terminals are special-function, bidirectional I/O port terminals that
are shared with other functional modules in the MCU.
MCU
3
4
5
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
Port C I/Os
These terminals are special-function, bidirectional I/O port terminals that
are shared with other functional modules in the MCU.
MCU
9
IRQ
External Interrupt
Input
MCU
10
RST
External Reset
MCU
12
13
PTD0/TACH0/BEMF
PTD1/TACH1
Port D I/Os
These terminals are special-function, bidirectional I/O port terminals that
are shared with other functional modules in the MCU.
–
14, 21, 22,
28, 33, 35,
36, 37, 39
NC
No Connect
Not connected.
MCU
42
PTE1/RXD
Port E I/O
MCU
43
48
VREFL
VREFH
ADC References
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
This terminal is an asynchronous external interrupt input terminal.
This terminal is bidirectional, allowing a reset of the entire system. It is
driven low when any internal reset source is asserted.
This terminal is a special-function, bidirectional I/O port terminal that can
is shared with other functional modules in the MCU.
These terminals are the reference voltage terminals for the analog-todigital converter (ADC).
For More Information On This Product,
Go to: www.freescale.com
908E626
3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
TERMINAL DEFINITIONS (continued)
A functional description of each terminal can be found in the System/Application Information section beginning on page 14.
Die
Terminal
Terminal Name
Formal Name
Definition
MCU
44
47
VSSA
VDDA
ADC Supply
Terminals
These terminals are the power supply terminals for the analog-to-digital
converter.
MCU
45
46
EVSS
EVDD
MCU Power Supply
Terminals
These terminals are the ground and power supply terminals, respectively.
The MCU operates from a single power supply.
MCU
49
50
52
53
54
PTA4/KBD4
PTA3/KBD3
PTA2/KBD2
PTA1/KBD1
PTA0/KBD0
Port A I/Os
These terminals are special-function, bidirectional I/O port terminals that
are shared with other functional modules in the MCU.
MCU
51
FLSVPP
Test Terminal
Analog
15
FGEN
Current Limitation
Frequency Input
Analog
16
BEMF
Back Electromagnetic
Force Output
Analog
17
RST_A
Internal Reset
Analog
18
IRQ_A
Internal Interrupt
Output
Analog
19
SS
Slave Select
Analog
20
LIN
LIN Bus
Analog
23
26
29
32
HB1
HB2
HB3
HB4
Half-Bridge Outputs
Analog
24
27
31
VSUP1
VSUP2
VSUP3
Power Supply
Terminals
These terminals are device power supply terminals.
Analog
25
30
GND1
GND2
Power Ground
Terminals
These terminals are device power ground connections.
Analog
34
HVDD
Switchable VDD
Output
This terminal is a switchable VDD output for driving resistive loads
requiring a regulated 5.0 V supply; e.g., 3-terminal Hall-effect sensors.
Analog
38
VDD
Voltage Regulator
Output
The +5.0 V voltage regulator output terminal is intended to supply the
embedded microcontroller.
Analog
40
VSS
Voltage Regulator
Ground
Ground terminal for the connection of all non-power ground connections
(microcontroller and sensors).
Analog
41
RXD
LIN Transceiver
Output
–
EP
Exposed Pad
Exposed Pad
908E626
4
For test purposes only. Do not connect in the application.
This is the input terminal for the half-bridge current limitation PWM
frequency.
This terminal gives the user information about back electromagnetic force
(BEMF).
This terminal is the bidirectional reset terminal of the analog die.
This terminal is the interrupt output terminal of the analog die indicating
errors or wake-up events.
This terminal is the SPI slave select terminal for the analog chip.
This terminal represents the single-wire bus transmitter and receiver.
This device includes power MOSFETs configured as four half-bridge
driver outputs. These outputs may be configured for step motor drivers,
DC motor drivers, or as high-side and low-side switches.
This terminal is the output of LIN transceiver.
The exposed pad terminal on the bottom side of the package conducts
heat from the chip to the PCB board.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any terminal may cause permanent damage to
the device.
Rating
Symbol
Value
Analog Chip Supply Voltage under Normal Operation (Steady-State)
VSUP(SS)
-0.3 to 28
Analog Chip Supply Voltage under Transient Conditions (Note 1)
VSUP(PK)
-0.3 to 40
VDD
-0.3 to 6.0
VIN (ANALOG)
-0.3 to 5.5
VIN (MCU)
VSS -0.3 to VDD +0.3
Unit
ELECTRICAL RATINGS
V
Supply Voltage
Microcontroller Chip Supply Voltage
Input Terminal Voltage
V
Analog Chip
Freescale Semiconductor, Inc...
Microcontroller Chip
mA
Maximum Microcontroller Current per Terminal
All Terminals Except VDD, VSS, PTA0:PTA6, PTC0:PTC1
IPIN(1)
±15
Terminals PTA0:PTA6, PTC0:PTC1
IPIN(2)
±25
Maximum Microcontroller VSS Output Current
IMVSS
100
mA
Maximum Microcontroller VDD Input Current
IMVDD
100
mA
LIN Supply Voltage
V
VBUS(SS)
-18 to 28
VBUS(DYNAMIC)
40
Human Body Model (Note 2)
VESD1
±3000
Machine Model (Note 3)
VESD2
±150
Charge Device Model (Note 4)
VESD3
±500
TSTG
-40 to 150
°C
TC
-40 to 115
°C
TJ(ANALOG)
-40 to 150
TJ(MCU)
-40 to 135
TSOLDER
245
All Outputs ON (Note 8), (Note 10)
RθJA1
24
Single Output ON (Note 9), (Note 10)
RθJA2
27
Normal Operation (Steady-State)
Transient Conditions (Note 1)
V
ESD Voltage
THERMAL RATINGS
Storage Temperature
Operating Case Temperature (Note 5)
°C
Operating Junction Temperature
Analog
MCU (Note 6)
Peak Package Reflow Temperature During Solder Mounting (Note 7)
°C
°C/W
Thermal Resistance (Junction to Ambient)
Notes
1. Transient capability for pulses with a time of t < 0.5 sec.
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
3.
ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 Ω).
4.
ESD3 testing is performed in accordance with Charge Device Model, robotic (CZAP =4.0 pF).
5.
6.
7.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.
In the 125°C to 135°C temperature range, the FLASH is guaranteed as read only.
Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
All outputs ON and dissipating equal power.
One output ON and dissipating power.
Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5 (thermal
vias connected to top ground plane).
8.
9.
10.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
5
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.
Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
VSUP
8.0
–
18
V
SUPPLY VOLTAGE
Nominal Operating Voltage
SUPPLY CURRENT
NORMAL Mode
IRUN
Freescale Semiconductor, Inc...
VSUP = 12 V, Power Die ON (PSON=1), MCU Operating Using Internal
Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC Enabled
mA
–
20
–
DIGITAL INTERFACE RATINGS (ANALOG DIE)
Output Terminals RST_A, IRQ_A
V
Low-State Output Voltage (IOUT = -1.5 mA)
VOL
–
–
0.4
High-State Output Voltage (IOUT = 1.0 µA)
VOH
3.85
–
–
Low-State Output Voltage (IOUT = -1.5 mA)
VOL
–
–
0.4
High-State Output Voltage (IOUT = 1.5 mA)
VOH
3.85
–
–
Output Terminal RXD–Capacitance (Note 11)
CIN
–
4.0
–
Input Logic Low Voltage
VIL
–
–
1.5
Input Logic High Voltage
VIH
3.5
–
–
CIN
–
4.0
–
pF
Terminals RST_A, IRQ_A –Pullup Resistor
RPULLUP1
–
10
–
kΩ
Terminal SS –Pullup Resistor
RPULLUP2
–
60
–
kΩ
RPULLDOWN
–
60
–
kΩ
IPULLUP
–
35
–
µA
Output Terminals BEMF, RXD
V
Input Terminals RST_A, FGEN, SS
V
Input Terminals RST_A, FGEN, SS –Capacitance (Note 11)
Terminals FGEN, MOSI, SPSCK–Pulldown Resistor
Terminal TXD–Pullup Current Source
pF
Notes
11. This parameter is guaranteed by process monitoring but is not production tested.
908E626
6
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.
Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SYSTEM RESETS AND INTERRUPTS
High-Voltage Reset
V
Threshold
VHVRON
27
30
33
Hysteresis
VHVRH
–
1.5
–
Threshold
VLVRON
3.6
4.0
4.7
V
Hysteresis
VLVRH
–
100
–
mV
Threshold
VHVION
17.5
21
23
Hysteresis
VHVIH
–
1.0
–
Threshold
VLVION
6.5
–
8.0
Hysteresis
VLVIH
–
0.4
–
Freescale Semiconductor, Inc...
Low-Voltage Reset
High-Voltage Interrupt
V
V
Low-Voltage Interrupt
°C
High-Temperature Reset (Note 12)
Threshold
TRON
–
170
–
Hysteresis
TRH
5.0
–
–
Threshold
TION
–
160
–
Hysteresis
TIH
5.0
–
–
4.75
5.0
5.25
–
–
100
°C
High-Temperature Interrupt (Note 13)
VOLTAGE REGULATOR
Normal Mode Output Voltage
V
VDDRUN
IOUT = 60 mA, 6.0 V < VSUP < 18 V
mV
VLR
Load Regulation
IOUT = 80 mA, VSUP = 9.0 V
Notes
12. This parameter is guaranteed by process monitoring but is not production tested.
13. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
7
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.
Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
–
–
1.4
VSUP -1.0
–
–
20
30
60
0
–
20
Unit
LIN PHYSICAL LAYER
Output Low Level
VLIN-LOW
TXD LOW, 500 Ω Pullup to VSUP
V
VLIN-HIGH
Output High Level
TXD HIGH, IOUT = 1.0 µA
Pullup Resistor to VSUP
Freescale Semiconductor, Inc...
V
RSLAVE
Leakage Current to GND
µA
IBUS_PAS_rec
Recessive State (-0.5 V < VLIN < VSUP)
µA
Leakage Current to GND (VSUP Disconnected)
Including Internal Pullup Resistor, VLIN @ -18 V
IBUS_NO_GND
–
-600
–
Including Internal Pullup Resistor, VLIN @ +18 V
IBUS
–
25
–
VIH
0.6 VLIN
–
VSUP
Dominant
VIL
0
–
0.4 VLIN
Threshold
VITH
–
VSUP /2
–
VIHY
0.01 VSUP
–
0.1 VSUP
V
LIN Receiver
Recessive
Input Hysteresis
908E626
8
kΩ
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller chip.
Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted reflect
the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
HALF-BRIDGE OUTPUTS (H1:H4)
Freescale Semiconductor, Inc...
Switch ON Resistance @ TJ = 25°C with ILOAD = 1.0 A
mΩ
High Side
RDS(ON)HB_HS
–
425
500
Low Side
RDS(ON)HB_LS
–
400
500
High-Side Overcurrent Shutdown
IHBHSOC
3.0
–
7.5
A
Low-Side Overcurrent Shutdown
IHBLSOC
3.0
–
7.5
A
Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)
ICL1
–
55
–
Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)
ICL2
210
260
315
Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)
ICL3
300
370
440
Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)
ICL4
450
550
650
Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)
ICL5
600
740
880
Half-Bridge Output HIGH Threshold for BEMF Detection
VBEMFH
–
-30
0
V
Half-Bridge Output LOW Threshold for BEMF Detection
VBEMFL
–
-60
-5.0
mV
VBEMFHY
–
30
–
mV
CSA = 1
RATIOH
7.0
12.0
14.0
CSA = 0
RATIOL
1.0
2.0
3.0
IHVDDOCT
24
30
40
mA
RATIOVSUP
4.8
5.1
5.35
–
Voltage/Temperature Slope
STtoV
–
19
–
mV/°C
Output Voltage @ 25°C
VT25
1.7
2.1
2.5
V
Low-Side Current Limitation @ TJ = 25°C
Hysteresis for BEMF Detection
mA
Low-Side Current-to-Voltage Ratio (VADOUT [V]/IHB [A])
V/A
SWITCHABLE VDD OUTPUT (HVDD)
Overcurrent Shutdown Threshold
VSUP DOWN-SCALER
Voltage Ratio (RATIOVSUP = VSUP /VADOUT)
INTERNAL DIE TEMPERATURE SENSOR
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
9
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the microcontroller
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 135°C unless otherwise noted. Typical values noted
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
TXD LOW to LIN LOW
t TXD-LIN-low
TXD HIGH to LIN HIGH
t TXD-LIN-high
–
–
–
–
-2.0
-2.0
–
–
4.0
4.0
–
–
6.0
6.0
8.0
8.0
2.0
2.0
-1.0
-2.0
-3.0
Unit
LIN PHYSICAL LAYER
µs
Freescale Semiconductor, Inc...
Propagation Delay (Note 14), (Note 15)
LIN LOW to RXD LOW
t LIN-RXD-low
LIN HIGH to RXD HIGH
t LIN-RXD-high
TXD Symmetry
t TXD-SYM
RXD Symmetry
t RXD-SYM
Output Falling Edge Slew Rate (Note 14), (Note 16)
SRF
80% to 20%
Output Rising Edge Slew Rate (Note 14), (Note 16)
V/µs
V/µs
SRR
1.0
2.0
3.0
SRS
-2.0
–
2.0
µs
t OSC
–
40
–
µs
AWD Period Low = 512 t OSC
t AWDPH
16
22
28
ms
AWD Period High = 256 t OSC
t AWDPL
8.0
11
14
ms
20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF
LIN Rise/Fall Slew Rate Symmetry (Note 14), (Note 16)
AUTONOMOUS WATCHDOG (AWD)
AWD Oscillator Period
Notes
14. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0:SRS1= 00).
15. See Figure 2, page 12.
16. See Figure 3, page 12.
908E626
10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
.
MICROCONTROLLER
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.
Freescale Semiconductor, Inc...
Module
Description
Core
High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz
Timer
Two 16-Bit Timers with Two Channels (TIM A and TIM B)
Flash
16 K Bytes
RAM
512 Bytes
ADC
10-Bit Analog-to-Digital Converter
SPI
SPI Module
ESCI
Standard Serial Communication Interface (SCI) Module
Bit-Time Measurement
Arbitration
Prescaler with Fine Baud-Rate Adjustment
ICG
Internal Clock Generation Module
BEMF Counter
Special Counter for SMARTMOS BEMF Output
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
11
Freescale Semiconductor, Inc.
Timing Diagrams
t TXD-LIN-low
t
t TXD-LIN-high
tTx-LIN-high
Tx-LIN-low
TXD
Tx
TXD
LIN
LIN
Recessive State
0.9 VSUP
VSUP
0.9
Recessive State
0.6 VSUP
VSUP
Freescale Semiconductor, Inc...
0.4 VSUP
VSUP
0.1
SUP
0.1 V
VSUP
Dominant State
Rx
RXD
t LIN-RXD-low
t
ttLIN-RXD-high
LIN-Rx-low
LIN-Rx-high
Figure 2. LIN Timing Description
∆t Fall-time
∆t Rise-time
0.8
VSUP
0.8 VSUP
0.8 VSUP
VSUP
∆V Fall
∆V Rise
0.2 VSUP
VSUP
0.2
0.2VSUP
VSUP
0.2
Dominant State
SRF =
∆V Fall
∆t Fall-time
SRR =
∆V Rise
∆t Rise-time
Figure 3. LIN Slew Rate Description
908E626
12
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Functional Diagrams
1.6
1.4
1.2
TJ = 25°C
Volts
Volts
1.0
0.8
0.6
0.2
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Amperes
Amperes
4.0
4.5
5.0
H-Bridge Low Side
Figure 4. Free Wheel Diode Forward Voltage
250
200
TA = 125°C
Dropout
Drop Out(mV)
(mV)
Freescale Semiconductor, Inc...
0.4
150
100
TA = 25°C
50
TA = -40°C
0
0
5
5.0
10
15
I
(mA)
I Load (mA)
20
25
LOAD
Figure 5. Dropout Voltage on HVDD
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
13
Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 908E626 device was designed and developed as a
highly integrated and cost-effective solution for automotive and
industrial applications. For automotive body electronics, the
908E626 is well suited to perform stepper motor control, e.g. for
climate or light-levelling control via a 3-wire LIN bus.
This device combines an standard HC08 MCU core
(68HC908EY16) with flash memory together with a
SMARTMOS IC chip. The SMARTMOS IC chip combines
power and control in one chip. Power switches are provided on
the SMARTMOS IC configured as four half-bridge outputs.
Other ports are also provided including a selectable HVDD
terminal. An internal voltage regulator is provided on the
SMARTMOS IC chip, which provides power to the MCU chip.
Also included in this device is a LIN physical layer, which
communicates using a single wire. This enables the device to
be compatible with 3-wire bus systems, where one wire is used
for communication, one for battery, and the third for ground.
Freescale Semiconductor, Inc...
FUNCTIONAL TERMINAL DESCRIPTION
See Figure 1, 908E626 Simplified Internal Block Diagram,
page 2, for a graphic representation of the various terminals
referred to in the following paragraphs. Also, see the terminal
diagram on page 3 for a depiction of the terminal locations on
the package.
Port A I/O Terminals
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. PTA0:PTA4 are shared with the keyboard interrupt
terminals, KBD0:KBD4.
The PTA5/SPSCK terminal is not accessible in this device
and is internally connected to the SPI clock terminal of the
analog die. The PTA6/SS terminal is likewise not accessible.
For details refer to the 68HC908EY16 datasheet.
Port B I/O Terminals
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. All terminals are shared with the ADC module. The
PTB6:PTB7 terminals are also shared with the Timer B module.
PTB0/AD0 is internally connected to the ADOUT terminal of
the analog die, allowing diagnostic measurements to be
calculated; e.g., current recopy, VSUP, etc. The PTB2/AD2
terminal is not accessible in this device.
For details refer to the 68HC908EY16 datasheet.
Port D I/O Terminals
PTD1/TACH1 and PTD0/TACH0/BEMF are specialfunction, bidirectional I/O port terminals that can also be
programmed to be timer terminals.
In step motor applications the PTD0 terminal should be
connected to the BEMF output of the analog die in order to
evaluate the BEMF signal with a special BEMF module of the
MCU.
PTD1 terminal is recommended for use as an output terminal
for generating the FGEN signal (PWM signal) if required by the
application.
Port E I/O Terminal
PTE1/RXD and PTE0/TXD are special-function,
bidirectional I/O port terminals that can also be programmed to
be enhanced serial communication.
PTE0/TXD is internally connected to the TXD terminal of the
analog die. The connection for the receiver must be done
externally.
External Interrupt Terminal (IRQ)
The IRQ terminal is an asynchronous external interrupt
terminal. This terminal contains an internal pullup resistor that
is always activated, even when the IRQ terminal is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
External Reset Terminal (RST)
Port C I/O Terminals
These terminals are special-function, bidirectional I/O port
terminals that are shared with other functional modules in the
MCU. For example, PTC2:PTC4 are shared with the ICG
module.
PTC0/MISO and PTC1/MOSI are not accessible in this
device and are internally connected to the MISO and MOSI SPI
terminals of the analog die.
A logic [0] on the RST terminal forces the MCU to a known
startup state. RST is bidirectional, allowing a reset of the entire
system. It is driven LOW when any internal reset source is
asserted.
This terminal contains an internal pullup resistor that is
always activated, even when the reset terminal is pulled LOW.
For details refer to the 68HC908EY16 datasheet.
For details refer to the 68HC908EY16 datasheet.
908E626
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Current Limitation Frequency Input Terminal (FGEN)
Freescale Semiconductor, Inc...
Input terminal for the half-bridge current limitation PWM
frequency. This input is not a real PWM input terminal; it should
just supply the period of the PWM. The duty cycle will be
generated automatically.
All VSUP terminals must be connected to get full chip
functionality.
Power Ground Terminals (GND1 and GND2)
Important The recommended FGEN frequency should be
in the range of 0.1 kHz to 20 kHz.
GND1 and GND2 are device power ground connections.
Owing to the low ON-resistance and current requirements of the
half-bridge driver outputs multiple terminals are provided.
Back Electromagnetic Force Output Terminal (BEMF)
GND1 and GND2 terminals must be connected to get full
chip functionality.
This terminal gives the user information about back
electromagnetic force (BEMF). This feature allows stall
detection and coil failures in step motor applications. In order to
evaluate this signal the terminal must be directly connected to
terminal PTD0/TACH0/BEMF.
Switchable VDD Output Terminal (HVDD)
Reset Terminal (RST_A)
+5.0 V Voltage Regulator Output Terminal (VDD)
RST_A is the bidirectional reset terminal of the analog die. It
is an open drain with pullup resistor and must be connected to
the RST terminal of the MCU.
The VDD terminal is needed to place an external capacitor to
stabilize the regulated output voltage. The VDD terminal is
intended to supply the embedded microcontroller.
Interrupt Terminal (IRQ_A)
IRQ_A is the interrupt output terminal of the analog die
indicating errors or wake-up events. It is an open drain with
pullup resistor and must be connected to the IRQ terminal of the
MCU.
Slave Select Terminal (SS)
This terminal is the SPI Slave Select terminal for the analog
chip. All other SPI connections are done internally. SS must be
connected to PTB1 or any other logic I/O of the microcontroller.
The HVDD terminal is a switchable VDD output for driving
resistive loads requiring a regulated 5.0 V supply; The output is
short-circuit protected.
Important The VDD terminal should not be used to supply
other loads; use the HVDD terminal for this purpose. The VDD,
EVDD, VDDA, and VREFH terminals must be connected
together.
Voltage Regulator Ground Terminal (VSS)
The VSS terminal is the ground terminal for the connection
of all non-power ground connections (microcontroller and
sensors).
Important VSS, EVSS, VSSA, and VREFL terminals must
be connected together.
LIN Bus Terminal (LIN)
LIN Transceiver Output Terminal (RXD)
The LIN terminal represents the single-wire bus transmitter
and receiver. It is suited for automotive bus systems and is
based on the LIN bus specification.
This terminal is the output of LIN transceiver. The terminal
must be connected to the microcontroller’s Enhanced Serial
Communications Interface (ESCI) module (RXD terminal).
Half-Bridge Output Terminals (HB1:HB4)
ADC Reference Terminals (VREFL and VREFH)
The 908E626 device includes power MOSFETs configured
as four half-bridge driver outputs. The HB1:HB4 outputs may
be configured for step motor drivers, DC motor drivers, or as
high-side and low-side switches.
VREFL and VREFH are the reference voltage terminals for
the ADC. It is recommended that a high-quality ceramic
decoupling capacitor be placed between these terminals.
The HB1:HB4 outputs are short-circuit and overtemperature
protected, and they feature current recopy, current limitation,
and BEMF generation. Current limitation and recopy are done
on the low-side MOSFETs.
Important VREFH is the high reference supply for the ADC
and should be tied to the same potential as VDDA via separate
traces. VREFL is the low reference supply for the ADC and
should be tied to the same potential as VSS via separate traces.
For details refer to the 68HC908EY16 datasheet.
Power Supply Terminals (VSUP1:VSUP3)
VSUP1:VSUP3 are device power supply terminals. The
nominal input voltage is designed for operation from 12 V
systems. Owing to the low ON-resistance and current
requirements of the half-bridge driver outputs, multiple VSUP
terminals are provided.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
ADC Supply Terminals (VDDA and VSSA)
VDDA and VSSA are the power supply terminals for the
analog-to-digital converter (ADC). It is recommended that a
high-quality ceramic decoupling capacitor be placed between
these terminals.
For More Information On This Product,
Go to: www.freescale.com
908E626
15
Freescale Semiconductor, Inc.
Important VDDA is the supply for the ADC and should be
tied to the same potential as EVDD via separate traces. VSSA
is the ground terminal for the ADC and should be tied to the
same potential as EVSS via separate traces.
For details refer to the 68HC908EY16 datasheet.
MCU Power Supply Terminals (EVDD and EVSS)
EVDD and EVSS are the power supply and ground
terminals. The MCU operates from a single power supply.
Freescale Semiconductor, Inc...
Fast signal transitions on MCU terminals place high, shortduration current demands on the power supply. To prevent
noise problems, take special care to provide power supply
bypassing at the MCU.
For details refer to the 68HC908EY16 datasheet.
Test Terminal (FLSVPP)
For test purposes only. Do not connect in the application.
Exposed Pad Terminal
The exposed pad terminal on the bottom side of the package
conducts heat from the chip to the PCB board. For thermal
performance the pad must be soldered to the PCB board. It is
recommended that the pad be connected to the ground
potential.
ANALOG DIE DESCRIPTION
Interrupts
Overcurrent Interrupt
The 908E626 has five different interrupt sources as
described in the following paragraphs. The interrupts can be
disabled or enabled via the SPI. After reset all interrupts are
automatically disabled.
If an overcurrent condition on a half-bridge or the HVDD
output is detected and the OCIE bit is set and an interrupt
generated.
Low-Voltage Interrupt
Interrupt Flag Register (IFR)
The Low-Voltage Interrupt (LVI) is related to the external
supply voltage, VSUP. If this voltage falls below the LVI
threshold, it will set the LVI flag. If the low-voltage interrupt is
enabled, an interrupt will be initiated.
With LVI the H-Bridges (high-side MOSFET only) are
switched off. All other modules are not influenced by this
interrupt.
Register Name and Address: IFR - $05
Bit7
6
5
4
3
2
0
0
LINF
HTF
LVF
HVF
0
0
0
0
0
0
Read
1
Bit0
OCF
0
0
0
Write
Reset
High-Voltage Interrupt
LINF—LIN Flag Bit
The High-Voltage Interrupt (HVI) is related to the external
supply voltage, VSUP. If this voltage rises above the HVI
threshold, it will set the HVI flag. If the High-Voltage Interrupt is
enabled, an interrupt will be initiated.
This read/write flag is set on the falling edge at the LIN data
line. Clear LINF by writing a logic [1] to LINF. Reset clears the
LINF bit. Writing a logic [0] to LINF has no effect.
With HVI the H-Bridges (high-side MOSFET only) are
switched off. All other modules are not influenced by this
interrupt.
• 1 = Falling edge on LIN data line has occurred.
• 0 = Falling edge on LIN data line has not occurred since
last clear.
HTF—High-Temperature Flag Bit
High-Temperature Interrupt
The High-Temperature Interrupt (HTI) is generated by the
on-chip temperature sensors. If the chip temperature is above
the HTI threshold, the HTI flag will be set. If the HighTemperature Interrupt is enabled, an interrupt will be initiated.
LIN Interrupt
If the LINIE bit is set, a falling edge on the LIN terminal will
generate an interrupt.
908E626
16
This read/write flag is set on a high-temperature condition.
Clear HTF by writing a logic [1] to HTF. If a high-temperature
condition is still present while writing a logic [1] to HTF, the
writing has no effect. Therefore, a high-temperature interrupt
cannot be lost due to inadvertent clearing of HTF. Reset clears
the HTF bit. Writing a logic [0] to HTF has no effect.
• 1 = High-temperature condition has occurred.
• 0 = High-temperature condition has not occurred.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Interrupt Mask Register (IMR)
LVF—Low-Voltage Flag Bit
This read/write flag is set on a low-voltage condition. Clear
LVF by writing a logic [1] to LVF. If a low-voltage condition is still
present while writing a logic [1] to LVF, the writing has no effect.
Therefore, a low-voltage interrupt cannot be lost due to
inadvertent clearing of LVF. Reset clears the LVF bit. Writing a
logic [0] to LVF has no effect.
• 1 = Low-voltage condition has occurred.
• 0 = Low-voltage condition has not occurred.
Register Name and Address: IMR - $04
Bit7
6
5
4
3
2
1
Bit0
0
0
LINIE
HTIE
LVIE
HVIE
OCIE
0
0
0
0
0
0
0
Read
0
Write
Reset
0
LINIE—LIN Line Interrupt Enable Bit
Freescale Semiconductor, Inc...
HVF—High-Voltage Flag Bit
This read/write flag is set on a high-voltage condition. Clear
HVF by writing a logic [1] to HVF. If high-voltage condition is still
present while writing a logic [1] to HVF, the writing has no effect.
Therefore, a high-voltage interrupt cannot be lost due to
inadvertent clearing of HVF. Reset clears the HVF bit. Writing a
logic [0] to HVF has no effect.
• 1 = High-voltage condition has occurred.
• 0 = High-voltage condition has not occurred.
This read-only flag is set on an overcurrent condition. Reset
clears the OCF bit. To clear this flag, write a logic [1] to the
appropriate overcurrent flag in the SYSSTAT Register. See
Figure 6, which shows the two signals triggering the OCF.
• 1 = High-current condition has occurred.
• 0 = High-current condition has not occurred.
HB_OCF
• 1 = Interrupt requests from LINF flag enabled.
• 0 = Interrupt requests from LINF flag disabled.
HTIE—High-Temperature Interrupt Enable Bit
This read/ write bit enables CPU interrupts by the hightemperature flag, HTF. Reset clears the HTIE bit.
• 1 = Interrupt requests from HTF flag enabled.
• 0 = Interrupt requests from HTF flag disabled.
OCF—Overcurrent Flag Bit
HVDD_OCF
This read/write bit enables CPU interrupts by the LIN flag,
LINF. Reset clears the LINIE bit.
LVIE—Low-Voltage Interrupt Enable Bit
This read/write bit enables CPU interrupts by the lowvoltage flag, LVF. Reset clears the LVIE bit.
• 1 = Interrupt requests from LVF flag enabled.
• 0 = Interrupt requests from LVF flag disabled.
HVIE—High-Voltage Interrupt Enable Bit
OCF
Figure 6. Principal Implementation for OCF
This read/write bit enables CPU interrupts by the highvoltage flag, HVF. Reset clears the HVIE bit.
• 1 = Interrupt requests from HVF flag enabled.
• 0 = Interrupt requests from HVF flag disabled.
OCIE—Overcurrent Interrupt Enable Bit
This read/write bit enables CPU interrupts by the overcurrent
flag, OCF. Reset clears the OCIE bit.
• 1 = Interrupt requests from OCF flag enabled.
• 0 = Interrupt requests from OCF flag disabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
17
Freescale Semiconductor, Inc.
Reset
The 908E626 chip has four internal reset sources and one
external reset source, as explained in the paragraphs below.
Figure 7 depicts the internal reset sources.
SPI REGISTERS
AWDRE Flag
AWD Reset
Sensor
VDD
HVRE Flag
High-Voltage
Reset Sensor
Freescale Semiconductor, Inc...
HTRE Flag
High-Temperature
Reset Sensor
RST_A
MONO
FLOP
Low-Voltage Reset
Figure 7. Internal Reset Routing
Reset Internal Sources
Reset External Source
Autonomous Watchdog
External Reset Terminal
AWD modules generates a reset because of a timeout
(watchdog function).
The microcontroller has the capability of resetting the
SMARTMOS device by pulling down the RST terminal.
High-Temperature Reset
Reset Mask Register (RMR)
To prevent damage to the device, a reset will be initiated if
the temperature rises above a certain value. The reset is
maskable with bit HTRE in the Reset Mask Register. After a
reset the high-temperature reset is disabled.
Register Name and Address: RMR - $06
Bit7
Read
6
5
4
3
2
0
0
0
0
0
TTEST
Bit0
HVRE
HTRE
0
0
Write
Low-Voltage Reset
The LVR is related to the internal VDD. In case the voltage
falls below a certain threshold, it will pull down the RST_A
terminal.
High-Voltage Reset
The HVR is related to the external VSUP voltage. In case the
voltage is above a certain threshold, it will pull down the RST_A
terminal. The reset is maskable with bit HVRE in the Reset
Mask Register. After a reset the high-voltage reset is disabled.
908E626
18
1
Reset
0
0
0
0
0
0
TTEST—High-Temperature Reset Test
This read/write bit is for test purposes only. It decreases the
overtemperature shutdown limit for final test. Reset clears the
HTRE bit.
• 1 = Low-temperature threshold enabled.
• 0 = Low-temperature threshold disabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
HVRE—High-Voltage Reset Enable Bit
HTRE—High-Temperature Reset Enable Bit
This read/write bit enables resets on high-voltage
conditions. Reset clears the HVRE bit.
This read/write bit enables resets on high-temperature
conditions. Reset clears the HTRE bit.
1 = High-voltage reset enabled.
• 1 = High-temperature reset enabled.
• 0 = High-temperature reset disabled.
0 = High-voltage reset disabled.
SERIAL PERIPHERAL INTERFACE
A complete data transfer via the SPI consists of 2 bytes. The
master sends address and data, slave system status, and data
of the selected address.
The serial peripheral interface (SPI) creates the
communication link between the microcontroller and the
908E626.
Freescale Semiconductor, Inc...
The interface consists of four terminals (see Figure 8):
•
•
•
•
SS —Slave Select
MOSI—Master-Out Slave-In
MISO—Master-In Slave-Out
SPSCK—Serial Clock (maximum frequency 4.0 MHz)
SS
Read/Write, Address, Parity
MOSI
R/W
A4
A3
A2
A1
A0
Data (Register write)
P
X
D7
D6
System Status Register
MISO
S7
S6
S5
S4
S3
S2
D5
D4
D3
D2
D1
D0
D1
D0
Data (Register read)
S1
S0
D7
D6
D5
D4
D3
D2
SPSCK
Rising edge of SPSCK
Change MISO/MOSI
Output
Falling edge of SPSCK
Sample MISO/MOSI
Input
Slave latch
register address
Slave latch
data
Figure 8. SPI Protocol
During the inactive phase of SS, the new data transfer is
prepared. The falling edge on the SS line indicates the start of
a new data transfer and puts MISO in the low-impedance mode.
The first valid data are moved to MISO with the rising edge of
SPSCK.
The MISO output changes data on a rising edge of SPSCK.
The MOSI input is sampled on a falling edge of SPSCK. The
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
data transfer is only valid if exactly 16 sample clock edges are
present in the active phase of SS.
After a write operation, the transmitted data is latched into
the register by the rising edge of SS. Register read data is
internally latched into the SPI at the time when the parity bit is
transferred. SS HIGH forces MISO to high impedance.
For More Information On This Product,
Go to: www.freescale.com
908E626
19
Freescale Semiconductor, Inc.
Master Address Byte
Bit X
Not used.
A4:A0
Master Data Byte
Contains the address of the desired register.
Contains data to be written or no valid data during a read
operation.
R/ W
Contains information about a read or a write operation.
Freescale Semiconductor, Inc...
• If R/ W = 1, the second byte of master contains no valid
information, slave just transmits back register data.
• If R/ W = 0, the master sends data to be written in the
second byte, slave sends concurrently contents of
selected register prior to write operation, write data is
latched in the SMARTMOS register on rising edge of SS.
Parity P
The parity bit is equal to “0” if the number of 1 bits is an even
number contained within R/ W, A4:A0. If the number of 1 bits is
odd, P equals “1”. For example, if R/ W = 1, A4:A0 = 00001,
then P equals “0.”
The parity bit is only evaluated during a write operation.
Slave Status Byte
Contains the contents of the System Status Register ($0c)
independent of whether it is a write or read operation or which
register was selected.
Slave Data Byte
Contains the contents of selected register. During a write
operation it includes the register content prior to a write
operation.
SPI Register Overview
Table 1 summarizes the SPI Register addresses and the bit
names of each register.
Table 1. List of Registers
Addr
Register Name
R/W
$01
H-Bridge Output
(HBOUT)
R
$02
H-Bridge Control
(HBCTL)
W
$03
System Control
(SYSCTL)
W
$04
Interrupt Mask
(IMR)
$05
Interrupt Flag
(IFR)
W
$06
Reset Mask
(RMR)
W
$07
Analog Multiplexer
Configuration (ADMUX)
$08
Reserved
W
Bit
7
6
5
4
3
2
1
0
HB4_H
HB4_L
HB3_H
HB3_L
HB2_H
HB2_L
HB1_H
HB1_L
OFC_EN
CSA
0
0
0
CLS2
CLS1
CLS0
PSON
SRS1
SRS0
0
0
0
0
0
0
LINIE
HTIE
LVIE
HVIE
OCIE
0
0
LINF
HTF
LVF
HVF
0
0
0
0
0
0
0
0
0
SS3
0
0
0
0
R
R
R
W
R
R
R
TTEST
W
R
0
0
OCF
0
HVRE
HTRE
SS2
SS1
SS0
0
0
0
0
W
R
$09
0
0
0
0
0
0
0
0
0
0
0
AWDRE
0
0
AWDF
AWDR
0
0
0
0
HVDDON
0
HVDD_OCF
0
LVF
HVF
Reserved
W
R
$0a
AWD Control
(AWDCTL)
W
$0b
Power Output
(POUT)
W
$0c
System Status
(SYSSTAT)
908E626
20
R
R
W
AWDRST
0
0
0
LINCL
HB_OCF
HTF
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Analog Die I/Os
Analog Multiplexer/ADOUT Terminal
LIN Physical Layer
The ADOUT terminal is the analog output interface to the
ADC of the MCU (see Figure 1, page 2). An analog multiplexer
is used to read six internal diagnostic analog voltages.
The LIN bus terminal provides a physical layer for single-wire
communication in automotive applications. The LIN physical
layer is designed to meet the LIN physical layer specification.
Freescale Semiconductor, Inc...
The LIN driver is a low-side MOSFET with internal current
limitation and thermal shutdown. An internal pullup resistor with
a serial diode structure is integrated, so no external pullup
components are required for the application in a slave node.
The fall time from dominant to recessive and the rise time from
recessive to dominant is controlled. The symmetry between
both slew rate controls is guaranteed.
The LIN terminal offers high susceptibility immunity level
from external disturbance, guaranteeing communication during
external disturbance.
The LIN transmitter circuitry is enabled by setting the PSON
bit in the System Control Register (SYSCTL). If the transmitter
works in the current limitation region, the LINCL bit in the
System Status Register (SYSSTAT) is set. Due to excessive
power dissipation in the transmitter, software is advised to
monitor this bit and turn the transmitter off immediately.
TXD Terminal
The TXD terminal is the MCU interface to control the state of
the LIN transmitter (see Figure 1, page 2). When TXD is LOW,
LIN output is low (dominant state). When TXD is HIGH, the LIN
output MOSFET is turned off. The TXD terminal has an internal
pullup current source in order to set the LIN bus in recessive
state in the event, for instance, the microcontroller could not
control it during system power-up or power-down.
Current Recopy
The analog multiplexer is connected to the four low-side
current sense circuits of the half-bridges. These sense circuits
offer a voltage proportional to the current through the low-side
MOSFET. High or low resolution is selectable: 5.0 V/2.5 A or
5.0 V/500 mA, respectively. (Refer to Half-Bridge Current
Recopy on page 25.)
Temperature Sensor
The 908E626 includes an on-chip temperature sensor. This
sensor offers a voltage that is proportional to the actual chip
junction temperature.
VSUP Prescaler
The VSUP prescaler permits the reading or measurement of
the external supply voltage. The output of this voltage is VSUP /
RATIOVSUP.
The different internal diagnostic analog voltages can be
selected with the ADMUX Register.
Analog Multiplexer Configuration Register (ADMUX)
Register Name and Address: ADMUX - $07
Read
RXD Terminal
Write
The RXD transceiver terminal is the MCU interface, which
reports the state of the LIN bus voltage. LIN HIGH (recessive
state) is reported by a high level on RXD, LIN LOW (dominant
state) by a low level on RXD.
Reset
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Bit7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
Bit0
SS3
SS2
SS1
SS0
0
0
0
0
SS3, SS2, SS1, and SS0—A/D Input Select Bits
These read/write bits select the input to the ADC in the
microcontroller according to Table 2, page 22. Reset clears
SS3, SS2, SS1, and SS0 bits.
For More Information On This Product,
Go to: www.freescale.com
908E626
21
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 2. Analog Multiplexer Configuration Register
SS3
SS2
SS1
SS0
Channel
0
0
0
0
Current Recopy HB1
0
0
0
1
Current Recopy HB2
0
0
1
0
Current Recopy HB3
0
0
1
1
Current Recopy HB4
0
1
0
0
VSUP Prescaler
0
1
0
1
Temperature Sensor
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
HVDDON—HVDD On Bit
This read/write bit enables HVDD output. Reset clears the
HVDDON bit.
• 1 = HVDD enabled.
• 0 = HVDD disabled.
Half-Bridges
Outputs HB1:HB4 provide four low-resistive half-bridge
output stages. The half-bridges can be used in H-Bridge, highside, or low-side configurations.
Reset clears all bits in the H-Bridge Output Register
(HBOUT) owing to the fact that all half-bridge outputs are
switched off.
HB1:HB4 output features:
Not Used
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
• Short circuit (overcurrent) protection on high-side and lowside MOSFETs.
• Current recopy feature (low side MOSFET).
• Overtemperature protection.
• Overvoltage and undervoltage protection.
• Current limitation feature (low side MOSFET).
Power Output Register (POUT)
Register Name and Address: POUT - $0b
Bit7
6
0
0
Read
Write
Reset
0
0
5
4
3
2
0
0
0
0
(Note 17)
(Note 17)
(Note 17)
(Note 17)
0
0
0
0
1
HVDDON
0
Bit0
0
(Note 17)
0
Notes
17. This bit must always be set to 0.
908E626
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
VSUP
Control
On/Off
High-Side Driver
Status
Charge Pump,
Overtemperature Protection,
Overcurrent Protection
BEMF
HBx
On/Off
Low-Side Driver
Status
Current
Limit
Current Recopy,
Current Limitation,
Overcurrent Protection
GND
Figure 9. Half-Bridge Push-Pull Output Driver
Half-Bridge Output Register (HBOUT)
Half-Bridge Control
Each output MOSFET can be controlled individually. The
general enable of the circuitry is done by setting PSON in the
System Control Register (SYSCTL). HBx_L and HBx_H form
one half-bridge. It is not possible to switch on both MOSFETs in
one half-bridge at the same time. If both bits are set, the highside MOSFET has a higher priority.
To avoid both MOSFETs (high side and low side) of one halfbridge being on at the same time, a break-before-make circuit
exists. Switching the high-side MOSFET on is inhibited as long
as the potential between gate and VSS is not below a certain
threshold. Switching the low-side MOSFET on is blocked as
long as the potential between gate and source of the high-side
MOSFET did not fall below a certain threshold.
Register Name and Address: HBOUT - $01
Bit7
6
5
4
3
2
1
Bit0
Read
HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L
Write
Reset
0
0
0
0
0
0
0
0
HBx_L—Low-Side On/Off Bits
These read/write bits turn on the low-side MOSFETs. Reset
clears the HBx_L bits.
• 1 = Low-side MOSFET turned on for half-bridge output x.
• 0 = Low-side MOSFET turned off for half-bridge output x.
HBx_H—High-Side On/Off Bits
These read/write bits turn on the high-side MOSFETs. Reset
clears the HBx_H bits.
1 = High-side MOSFET turned on for half-bridge output x.
0 = High-side MOSFET turned on for half-bridge output x.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
23
Freescale Semiconductor, Inc.
Half-Bridge Current Limitation
Each low-side MOSFET offers a current limit or constant
current feature. This features is realized by a pulse width
modulation on the low-side MOSFET. The pulse width
modulation on the outputs is controlled by the FGEN input and
the load characteristics. The FGEN input provides the PWM
frequency, whereas the duty cycle is controlled by the load
characteristics.
The recommended frequency range for the FGEN and the
PWM is 0.1 kHz to 20 kHz.
Functionality
Each low-side MOSFET switches off if a current above the
selected current limit was detected. The 908E626 offers five
different current limits (refer to Table 3, page 27, for current limit
values). The low-side MOSFET switches on again if a rising
edge on the FGEN input was detected (Figure 10).
H-Bridge low-side
MOSFET will be switched
off if select current limit is
reached.
Freescale Semiconductor, Inc...
Coil Current
H-Bridge low-side
MOSFET will be turned on
with each rising edge of
the FGEN input.
t (µs)
Half-Bridge
Low-Side Output
t (µs)
FGEN Input
(MCU PWM
Signal)
t (µs)
Minimum 50 µs
Figure 10. Half-Bridge Current Limitation
908E626
24
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Offset Chopping
If bit OFC_EN in the H-Bridge Control Register (HBCTL) is
set, HB1 and HB2 will continue to switch on the low-side
MOSFETs with the rising edge of the FGEN signal and HB3 and
HB4 will switch on the low-side MOSFETs with the falling edge
on the FGEN input. In step motor applications, this feature
allows the reduction of EMI due to a reduction of the di/dt
(Figure ).
Freescale Semiconductor, Inc...
Coil1 Current
Coil2 Current
FGEN Input
(MCU PWM
Signal)
HB1
HB2
Coil1…..
HB3
HB4
Coil2…..
Current in
VSUP Line
Figure 11. Offset Chopping for Step Motor Control
Half-Bridge Current Recopy
Half-Bridge BEMF Generation
Each low-side MOSFET has an additional sense output to
allow a current recopy feature. This sense source is internally
connected to a shunt resistor. The drop voltage is amplified and
switched to the analog multiplexer.
The BEMF output is set to “1” if a recirculation current is
detected in any half-bridge. This recirculation current flows via
the two freewheeling diodes of the power MOSFETs. The
BEMF circuitry detects that and generates a HIGH on the BEMF
output as long as a recirculation current is detected. This signal
provides a flexible and reliable detection of stall in step motor
applications. For this the BEMF circuitry takes advantage of the
instability of the electrical and mechanical behavior of a step
motor when blocked. In addition the signal can be used for open
load detection (absence of this signal) (see Figure 12,
page 26).
The factor for the current sense amplification can be selected
via bit CSA in the System Control Register.
• CSA = 1: Low resolution selected (500 mA measurement
range).
• CSA = 0: High resolution selected (2.5 A measurement
range).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
25
Freescale Semiconductor, Inc.
Coil Current
Voltage on 1
Freescale Semiconductor, Inc...
1
BEMF Signal
Figure 12. BEMF Signal Generation
Half-Bridge Overtemperature Protection
The half-bridge outputs provide an overtemperature prewarning with the HTF in the Interrupt Flag Register (IFR). In
order to protect the outputs against overtemperature, the HighTemperature Reset must be enabled. If this value is reached,
the part generates a reset and disables all power outputs.
The overvoltage/undervoltage status flags are cleared (and
the outputs re-enabled) by writing a logic [1] to the LVF/HVF
flags in the Interrupt Flag Register or by reset. Clearing this flag
is useless as long as a high- or low-voltage condition is present.
Half-Bridge Control Register (HBCTL)
Register Name and Address: HBCTL - $02
Half-Bridge Overcurrent Protection
Bit7
The half-bridges are protected against short to GND, short to
VSUP, and load shorts.
In the event an overcurrent on the high side is detected, the
high-side MOSFETs on all HB high-side MOSFETs are
switched off automatically. In the event an overcurrent on the
low side is detected, all HB low-side MOSFETs are switched off
automatically. In both cases, the overcurrent status flag
HB_OCF in the System Status Register (SYSSTAT) is set.
The overcurrent status flag is cleared (and the outputs reenabled) by writing a logic [1] to the HB_OCF flag in the System
Status Register or by reset.
Half-Bridge Overvoltage/Undervoltage
The half-bridge outputs are protected against undervoltage
and overvoltage conditions. This protection is done by the lowand high-voltage interrupt circuitry. If one of these flags (LVF,
HVF) is set, the outputs are automatically disabled.
908E626
26
6
Read
OFC_EN
CSA
0
0
5
4
3
0
0
0
2
1
Bit0
CLS2
CLS1
CLS0
0
0
0
Write
Reset
0
0
0
OFC_EN—H-Bridge Offset Chopping Enable Bit
This read/write bit enables offset chopping. Reset clears the
OFC_EN bit.
• 1 = Offset chopping enabled.
• 0 = Offset chopping disabled.
CSA—H-Bridges Current Sense Amplification Select Bit
This read/write bit selects the current sense amplification of
the H-Bridges. Reset clears the CSA bit.
• 1 = Current sense amplification set for measuring 0.5 A.
• 0 = Current sense amplification set for measuring 2.5 A.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
CLS2:CLS0—H-Bridge Current Limitation Selection Bits
SRS0:SRS1—LIN Slew Rate Selection Bits
These read/write bits select the current limitation value
according to Table 3. Reset clears the CLS2:CLS0 bits.
These read/write bits enable the user to select the
appropriate LIN slew rate for different baud rate configurations
as shown in Table 4.
Freescale Semiconductor, Inc...
Table 3. H-Bridge Current Limitation Value Selection Bits
The high speed slew rates are used, for example, for
programming via the LIN and are not intended for use in the
application.
CLS2
CLS1
CLS0
Current Limit
0
0
0
0
0
1
0
1
0
SRS1
SRS0
LIN Slew Rate
0
1
1
55 mA (typ)
0
0
Initial Slew Rate (20 kBaud)
1
0
0
260 mA (typ)
0
1
Slow Slew Rate (10 kBaud)
1
0
1
370 mA (typ)
1
0
High Speed II (8x)
1
1
0
550 mA (typ)
1
1
High Speed I (4x)
1
1
1
740 mA (typ)
No Limit
Table 4. LIN Slew Rate Selection Bits
System Status Register (SYSSTAT)
Switchable VDD Outputs
Register Name and Address: SYSSTAT - $0c
The HVDD terminal is a switchable VDD output terminal. It
can be used for driving external circuitry that requires a VDD
voltage. The output is enabled with bit PSON in the System
Control Register and can be switched on/off with bit HVDDON
in the Power Output Register. Low- or high-voltage conditions
(LVI/HVI) have no influence on this circuitry.
Bit7
Read
6
LINCL
0
Write
Reset
0
5
4
HVDD
_OCF
0
0
0
0
3
2
LVF
HVF
0
0
1
HB_
OCF
Bit0
HTF
0
0
HVDD Overtemperature Protection
LINCL — LIN Current Limitation Bit
Overtemperature protection is enabled if the hightemperature reset is enabled.
This read-only bit is set if the LIN transmitter operates in
current limitation region. Due to excessive power dissipation in
the transmitter, software is advised to turn the transmitter off
immediately.
HVDD Overcurrent Protection
The HVDD output is protected against overcurrent. In the
event the overcurrent limit is or was reached, the output
automatically switches off and the HVDD overcurrent flag in the
System Status Register is set.
Register Name and Address: SYSCTL - $03
6
5
PSON
SRS1
SRS0
0
0
0
Read
4
3
2
1
0
0
0
0
Reset
Bit0
0
0
0
• 1 = Overcurrent condition on HVDD has occurred.
• 0 = No overcurrent condition on HVDD has occurred.
0
(Note 17)
Write
HVDD_OCF—HVDD Output Overcurrent Flag Bit
This read/write flag is set on an overcurrent condition at the
HVDD terminal. Clear HVDD_OCF and enable the output by
writing a logic [1] to the HVDD_OCF Flag. Reset clears the
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no effect.
System Control Register (SYSCTL)
Bit7
• 1 = Transmitter operating in current limitation region.
• 0 = Transmitter not operating in current limitation region.
0
0
Notes
18. This bit must always be set to 0.
LVF—Low-Voltage Bit
This read only bit is a copy of the LVF bit in the Interrupt Flag
Register.
• 1 = Low-voltage condition has occurred.
• 0 = No low-voltage condition has occurred.
PSON—Power Stages On Bit
This read/write bit enables the power stages (half-bridges,
LIN transmitter and HVDD output). Reset clears the PSON bit.
• 1 = Power stages enabled.
• 0 = Power stages disabled.
HVF—High-Voltage Sensor Bit
This read-only bit is a copy of the HVF bit in the Interrupt Flag
Register.
• 1 = High-voltage condition has occurred.
• 0 = No high-voltage condition has occurred.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
27
Freescale Semiconductor, Inc.
HB_OCF—H-Bridge Overcurrent Flag Bit
This read / write flag is set on an overcurrent condition at the
H-Bridges. Clear HB_OCF and enable the H-Bridge driver by
writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit.
Writing a logic [0] to HB_OCF has no effect.
• 1 = Overcurrent condition on H-Bridges has occurred.
• 0 = No overcurrent condition on H-Bridges has occurred.
Autonomous Watchdog Control Register (AWDCTL)
Register Name and Address: AWDCTL - $0a
Read
Freescale Semiconductor, Inc...
This read-only bit is a copy of the HTF bit in the Interrupt Flag
Register.
6
5
0
0
0
4
AWDRE
Write
Reset
HTF—Overtemperature Status Bit
Bit7
AWDRST
0
0
0
3
2
0
0
(Note 17)
(Note 17)
0
0
0
1
Bit0
0
AWDR
0
0
Notes
19. This bit must always be set to 0.
• 1 = Overtemperature condition has occurred.
AWDRST—Autonomous Watchdog Reset Bit
• 0 = No overtemperature condition has occurred.
This write-only bit resets the Autonomous Watchdog timeout
period. AWDRST always reads 0. Reset clears AWDRST bit.
Autonomous Watchdog (AWD)
The Autonomous Watchdog module allows to protect the
CPU against code runaways.
The AWD is enabled if AWDRE in the AWDCTL Register is
set. If this bit is cleared, the AWD oscillator is disabled and the
watchdog switched off.
Watchdog
The watchdog function is only available in RUN mode. On
setting the AWDRE bit, watchdog functionality in RUN mode is
activated. Once this function is enabled, it is not possible to
disable it via software.
If the timer reaches end value and AWDRE is set, a system
reset is initiated. Operations of the watchdog function cease in
STOP mode. Normal operation will be continued when the
system is back to RUN mode.
To prevent a watchdog reset, the watchdog timeout counter
must be reset before it reaches the end value. This is done by
a write to the AWDRST bit in the AWDCTL Register.
• 1 = Reset AWD and restart timeout period.
• 0 = No effect.
AWDRE—Autonomous Watchdog Reset Enable Bit
This read/write bit enables resets on AWD timeouts. A reset
on the RST_A is asserted when the Autonomous Watchdog has
reached the timeout and the Autonomous Watchdog is
enabled. AWDRE is one-time setable (write once) after each
reset. Reset clears the AWDRE bit.
• 1 = Autonomous watchdog enabled.
• 0 = Autonomous watchdog disabled.
AWDR—Autonomous Watchdog Rate Bit
This read/write bit selects the clock rate of the Autonomous
Watchdog. Reset clears the AWDR bit.
• 1 = Fast rate selected (10 ms).
• 0 = Slow rate selected (20 ms).
Voltage Regulator
The 908E626 chip contains a low-power, low-drop voltage
regulator to provide internal power and external power for the
MCU. The VDD regulator accepts a unregulated input supply
and provides a regulated VDD supply to all digital sections of the
device. The output of the regulator is also connected to the VDD
terminal to provide the 5.0 V to the microcontroller.
908E626
28
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
FACTORY TRIMMING AND CALIBRATION
To enhance the ease-of-use of the 908E626, various
parameters (e.g. ICG trim value) are stored in the flash memory
of the device. The following flash memory locations are
reserved for this purpose and might have a value different from
the “empty” (0xFF) state:
In the event the application uses these parameters, one has
to take care not to erase or override these values. If these
parameters are not used, these flash locations can be erased
and otherwise used.
• 0xFD80:0xFDDF Trim and Calibration Values
• 0xFFFE:0xFFFF Reset Vector
PACKAGE THERMAL PERFORMANCE
Thermal Impedance (°C/W)
Thermal Impedance [ºC/W]
Freescale Semiconductor, Inc...
Figure 13 shows a thermal response curve for a package
mounted onto a thermally enhanced PCB.
Note The PCB board is a multi-layer board with two inner
copper planes (2s2p). The board conforms to JEDEC EIA/
JESD 51-5 and JESD51-7. Substrate thickness is 1.60 mm.
Top and bottom copper trace layers are 0.7 mm thick, with two
inner copper planes of 0.35 mm thickness. Thermal vias have
0.35 mm thick plating.
30
25
20
15
10
5
5.0
0
0.00001 0.0001
0.001
0.01
0.1
1
1.0
Time (s)
10
100
1000
10000
time[s]
Figure 13. Thermal Response of H-Bridge Driver with Package Soldered to a JEDEC PCB Board
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
29
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
DWB SUFFIX
54-TERMINAL SOIC WIDE BODY EXPOSED PAD
PLASTIC PACKAGE
CASE 1400-01
ISSUE B
10.3
5
7.6
7.4
B
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUMS B AND C TO BE DETERMINED AT THE
PLANE WHERE THE BOTTOM OF THE LEADS
EXIT THE PLASTIC BODY.
4. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURRS. MOLD
FLASH, PROTRUSION OR GATE BURRS SHALL
NOT EXCEED 0.15 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF HTE LEADS EXIT THE
PLASTIC BODY.
5. THIS DIMENSION DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH AND PROTRUSIONS SHALL
NOT EXCEED 0.25 MM PER SIDE. THIS
DIMENSION IS DETERMINED AT THE PLANE
WHERE THE BOTTOM OF THE LEADS EXIT THE
PLASTIC BODY.
6. THIS DIMENSION DOES NOT INCUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD SHALL NOT BE LESS THAN
0.07 MM.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1 MM AND
0.3 MM FROM THE LEAD TIP.
9. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM. THIS DIMENSION IS
DETERMINED AT THE OUTERMOST EXTREMES
OF THE PLASTIC BODY EXCLUSIVE OF MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTER-LEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTOM
OF THE PLASTIC BODY.
2.65
2.35
52X
1
Freescale Semiconductor, Inc...
9
C
54
0.65
PIN 1 INDEX
4
9
B
27
18.0
17.8
CL
B
28
A
5.15
54X
2X 27 TIPS
0.3
SEATING
PLANE
0.10 A
A B C
A
R0.08 MIN
C
C
0˚MIN
0.25
GAUGE PLANE
(1.43)
A
8˚
0˚
10.9
9.7
0.1
0.0
0.9
0.5
SECTION B-B
0.30 A B C
(0.29)
0.30
0.25
5.3
4.8
0.30 A B C
BASE METAL
(0.25)
0.38
0.22
6
0.13
M
PLATING
A B C
8
SECTION A-A
ROTATED 90˚ CLOCKWISE
VIEW C-C
908E626
30
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
908E626
31
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be
provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license
under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product
could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
[email protected]
For More Information On This Product,
Go to: www.freescale.com
MM908E626