QN8027 High Performance Digital FM Transmitter for Portable Devices 9 81 51 44 71 ： • Low Power Consumption • 7.0 mA of FCC output level • Integrated voltage regulator, direct connect to battery • Power saving IDLE mode • High Performance FM Transmitter (FMT) • 65dB Stereo SNR, 0.04% THD • Maximum 119 dBuVp RF output level with 42dB adjustable range 限 公 司 ， 18 66 An integrated crystal oscillator and on-chip digital calibration circuits eliminate external tuning components and enable tuning-free manufacturing. Support for 12/24MHz reference clocks allows the chip to use readily available system clocks. Integrated saturation detection and a programmable audio interface eliminate distortion, optimize audio fidelity, and support a wide range of input audio levels. A low power IDLE mode extends battery life. An integrated LDO enables direct connection to the battery and provides high PSRR for superior noise suppression, in particular TDMA noise from GSM/GPRS phones. • Ease of Integration • Small footprint, 3 x 3 x 0.95mm MSOP10 • Only 2 external passive components required • Adaptive antenna tuning • Low cellular and GPS band spurs • High Immunity to TDMA (GSM/GPRS) burst noise • Multiple crystal frequencies supported • I2C interface QQ The QN8027 integrates a complete transmitter function, from stereo audio input to RF antenna port, for worldwide FM band personal area broadcasting. It includes variable input gain programming, selectable pre-emphasis, precision low-spur MPX stereo encoding and pilot tone generation, low-noise PLL-based modulation, and an on-chip power amplifier with variable output level and RF band-pass filtering to ensure optimum transmit spectrum purity. • Worldwide FM Band Transmit • 76 MHz to 108 MHz full band tuning in 50/100/200 kHz step sizes • 50/75μs pre-emphasis 85 ， The QN8027 is a high performance, low power, fullfeatured single-chip stereo FM transmitter designed for portable audio/video players, automotive accessories, cell phones, and GPS personal navigation devices. The QN8027 covers frequencies from 76 MHz to 108 MHz in 50/100/200 kHz step sizes for worldwide FM band support. The QN8027 also supports RDS/RBDS data transmit. ___________ Key Features __________ 43 41 5 ________ General Description ________ • RDS/RBDS Transmit • Supports US and European data service, including TMC (Traffic Messaging Channel) • Robust Operation • -250C to +850C operation • ESD protection on all input and output pads 圳 市 金 合 讯 科 技 有 The QN8027’s small footprint, high integration with minimum external component count, and support for 12/24MHz clock frequencies make it easy to integrate into a variety of small form-factor low-power portable applications. Integrated low-phase noise digital synthesizers and extensive on-chip auto calibration ensures robust consistent performance over temperature and process variations. An integrated voltage regulator enables direct connection to a battery and provides high PSRR for superior noise suppression. A low-power IDLE mode extends battery life. • Automatic Input Audio Sensing • RF power automatically turned off if no input audio signal for 60s 深 ESD protection is on all pins. The QN8027 is fabricated in highly reliable CMOS technology. _____________________________ Typical Applications __________________________ Cell Phones / PDAs / Smart Phones Portable Audio & Media Players Rev 1.1 (04/10) GPS Personal Navigation Devices Automotive and Accessories Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 1 QN8027 Functional Block Diagram ..............................................................................................................................3 2 Pin Assignments ..............................................................................................................................................3 3 Electrical Specifications ..................................................................................................................................3 4 Functional Description ....................................................................................................................................3 4.2 Idle Mode..................................................................................................................................3 4.3 Audio Interface .........................................................................................................................3 4.4 Audio Processing ......................................................................................................................3 4.5 Channel Setting.........................................................................................................................3 4.6 RDS/RBDS ...............................................................................................................................3 QQ ： 71 44 51 Transmit Mode..........................................................................................................................3 Control Interface Protocol ...............................................................................................................................3 5.1 85 ， 5 4.1 81 1 9 CONTENTS I2C Serial Control Interface ......................................................................................................3 User Control Registers.....................................................................................................................................3 7 Package Description ........................................................................................................................................3 8 Solder Reflow Profile ......................................................................................................................................3 18 66 43 41 5 6 Package Peak Reflow Temperature ..........................................................................................3 8.2 Classification Reflow Profiles ..................................................................................................3 8.3 Maximum Reflow Times ..........................................................................................................3 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 8.1 Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 2 QN8027 REVISION HISTORY REVISION CHANGE DESCRIPTION DATE Datasheet draft. 12/08/08 0.21 Check the grammar and syntax, Update the data ,the key features, and user control registers, Delete the Section 4.6 Audio Encryption for Privacy , Modify the Vcc value ;modify the pin FMO back RFO; 02/23/09 0.22 Modify Table 6: match the notes with the parameters; add “at maximal power” 0.23 Add Ordering Information 81 9 0.1 51 03/18/09 44 03/19/09 2 Modify Figure 11: save to slave; and I C slave address 0.25 Modify register 07h [2:0] and the description of the register 10h [6:0] about PA 04/08/09 0.26 1. 2. 3. 4. Add section 4.7 Power Setting; Modify reg 00h Bit 7: wo → r/w; Delete reg 02h [7]: ‘and de-emphasis’; Modify reg 03h [7:6]: internal oscillator → crystal: [5:0] add ‘when use crystal on XTAL1/XTAL2’. 5. Modify reg 11h:FEDV→ FDEV 6. Modify reg 12h [7] No RDS →RDS disable; 04/08/09 0.27 Modify Vcc MAX: 4.2V J 5.0V 05/25/09 0.28 Modify the description of Reg 07h [2:0] 0.29 Update the data in Chapter 3. 1.0 Modify Reg06h[3:0] 0000Æ0100 1.1 Update the ITX value in Table 4 03/27/09 06/17/09 01/16/10 03/17/10 04/13/10 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 0.24 技 有 限 STATEMENT: 深 圳 市 金 合 讯 科 Users are responsible for compliance with local regulatory requirements for low power unlicensed FM broadcast operation. Quintic is not responsible for any violations resulting from user’s intentional or unintentional breach of regulatory requirements in personal or commercial use. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 3 QN8027 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 1 FUNCTIONAL BLOCK DIAGRAM 深 圳 市 金 合 讯 科 Figure 1: QN8027-SANC Functional Blocks Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 4 QN8027 1 10 ALI XTAL1 2 9 ARI VCC 3 8 VIO GND 4 7 RFO 5 6 51 44 SCL 85 ， QQ ： SDA 43 41 5 (Top View) 81 9 XTAL2 71 2 PIN ASSIGNMENTS Figure 2: QN8027 Device Pin Out NAME DESCRIPTION 1 XTAL2 On-chip crystal driver port 2. If using an external clock source, connect this pin to ground. 2 XTAL1 On-chip crystal driver port 1. If using an external clock source, connect this pin to inject the clock. 3 VCC 4 GND 5 RFO 6 SCL Clock for I2C serial bus. 7 SDA Bi-directional data line for I2C serial bus. 8 限 公 司 ， PINS 合 18 66 Table 1: Pin Descriptions 技 有 Voltage supply Ground 讯 科 Transmitter RF output – connect to matched antenna. IO voltage – specifies voltage limit for all digital pins. 9 ARI Analog audio input – right channel 10 ALI Analog audio input – left channel 深 圳 市 金 VIO Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 5 QN8027 3 ELECTRICAL SPECIFICATIONS Table 2: Absolute Maximum Ratings PARAMETER CONDITIONS MIN MAX UNIT V Supply voltage VCC to GND -0.3 5 VIO Logic signals SCL, SDA to GND -0.3 3.6 Ts Storage temperature -55 +150 51 81 Vbat 9 SYMBOL o C QQ ： 71 44 V PARAMETER CONDITIONS Vcc Supply voltage VCC to GND TA Operating temperature Vain L/R channel input signal level VIO Digital I/O voltage MIN TYP MAX UNIT 2.7 3.3 5.0 V +85 o 43 41 5 SYMBOL 85 ， Table 3: Recommended Operating Conditions -25 1.6 1000 1400 mV 3.6 V 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 Single ended peak to peak voltage C Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 6 QN8027 Table 4: DC Characteristics (Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3.V, f carrier=88 MHz and TA = 25oC). PARAMETER ITX Transmit mode supply current MIN TYP 7.01 Idle mode supply current Idle mode MAX UNIT 13.82 mA 1.2 mA 81 IIDLE CONDITIONS 9 SYMBOL High level input voltage VIL Low level input voltage 44 VIH 0.1*VIO 71 Low level output voltage ： VOL 0.9*VIO 0.7*VIO V V V QQ High level output voltage 0.4 V 85 ， VOH 51 Interface Notes: 43 41 5 1. RFO output at Min level. 2. RFO output at Max level. 18 66 Table 5: AC Characteristics (Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC). Crystal frequency accuracy MAX -20 UNIT MHz 20 ppm See also XSEL, R04[7]. Required by FCC standard. 深 圳 市 金 合 讯 科 Notes: 1. 2. Over temperature, and aging TYP 12 or 24 司 Fxtal_err2 公 Crystal or Clock frequency MIN 技 有 Fxtal1 CONDITIONS ， PARAMETERS 限 SYMBOL Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 7 QN8027 Table 6: Transmitter Characteristics (Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V, f carrier=88 MHz and TA = 25oC). MIN TYP Raudio_in Audio input impedance1 At pin ALI and ARI Caudio_in Audio input capacitance1 At pin ALI and ARI Gaudio_In Audio input gain RIN[1:0] = 10 -9 ΔGaudio_In Audio gain step For any gain setting 0.5 1 PETC = 1 71.3 75 PETC = 0 47.5 50 MONO, Δf = 22.5 kHz Tx audio THD αLR_tx L/R separation 2 BLR_tx L/R channel imbalance 1 L and R channel gain imbalance at 1 kHz offset from DC Mpilot 19 kHz pilot modulation 2, 5 Relative to 75 kHz deviation 85 ， STEREO, Δf = 67.5 kHz, Δfpilot = 6.75 kHz 司 ， 18 66 43 41 5 STEREO, Δf = 67.5 kHz, Δfpilot = 6.75 kHz 38 kHz sub-carrier suppression Output capacitance tuning range1 Pout RF output voltage swing3 RF Channel frequency = 88 MHz Power gain step Over process, temperature 限 技 有 讯 科 4 RF output spectrum mask 35 7 dB 1.5 78.7 52.5 dB μs dB 65 0.04 0.1 0.04 0.1 % 42 9.0 dB 1 dB 15 % dB 5 30 pF 82 119 dBμV 0.75 -2 dB 2 120 kHz to 240 kHz offset -50 -45 240 kHz to 600 kHz offset -45 -40 >600 kHz offset dB dBc -40 76 Fch Channel frequency step 50 Ferr Channel center frequency accuracy6 Fperr Pilot Tone frequency accuracy1,6 Fpk Modulation peak frequency deviation 深 pF 70 RF channel frequency 圳 Frf Over 76 MHz ~ 108 MHz 市 金 Pmask Power gain flatness 合 ΔPout 公 Ctune ΔGRF_Out 5 ： THDaudio_tx 1, 2 SUPsub kΩ 6 QQ Tx audio SNR1, 2 2 40 64 SNRaudio_tx MONO, Δf = 75 kHz UNIT 44 Pre-emphasis time constant1 2 71 τemph 5 MAX 9 CONDITIONS 81 PARAMETERS 51 SYMBOL 108 MHz 200 kHz -2 2 kHz -2 2 Hz 100 75 kHz Notes: Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 8 QN8027 SYMBOL 1. 2. 3. 4. 5. PARAMETERS CONDITIONS MIN TYP MAX UNIT Guaranteed by design. 1000mVp-p, 1 kHz tone at ALI pin, no input signal at ARI pin. Into matched antenna (see application note for details). Within operating band 76 MHz to 108 MHz. Value set with GAIN_TXPLT[3:0] (reg. 02h, bits 3:0). The user must conform to local regulatory requirements for low-power unlicensed FM broadcast operation when setting this value. Required by FCC standard. 44 51 81 9 6. 71 Table 7: Timing Characteristics PARAMETER CONDITIONS Chip power-up time 1 From rising edge of Power-On to PLL settled and transmitter ready for transmission. τchsw Channel switching time1 From any channel to any channel. 43 41 5 τpup MIN MAX UNIT 0.1 Sec 10 ms 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 Notes: 1. Guaranteed by design. TYP 85 ， SYMBOL QQ ： (Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC). Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 9 QN8027 Table 8: I2C Interface Timing Characteristics (Vcc = 2.7 ~ 5.0 V, TA = -25 ~ 85 oC, unless otherwise noticed. Typical values are at Vcc = 3.3V and TA = 25oC). PARAMETER CONDITIONS MIN TYP MAX UNIT 400 kHz I2C clock frequency tLOW Clock Low time 1.3 μs tHI Clock High time 0.8 μs tST SCL input to SDA falling edge start 1,3 0.6 SDA falling edge to SCL falling edge start3 0.6 SCL rising edge to SDA rising edge 2,3 tw Duration before restart3 Cb SCL, SDA capacitive loading3 51 44 85 ， tstp ns ns 900 43 41 5 SDA rising edge to next SCL rising edge3 μs 1.3 μs 10 pF 深 圳 市 金 合 讯 科 技 有 限 Notes: 2 1. Start signaling of I C interface. 2 2. Stop signaling of I C interface. 3. Guaranteed by design. ns 0.6 18 66 tdtc 20 300 ， SCL falling edge to next SDA rising edge3 ns 司 tdtHD Level from 70% to 30% μs 300 QQ SCL falling edge ： Level from 30% to 70% 3 tfc 71 SCL rising edge3 trc μs 公 tSTHD 81 fSCL 9 SYMBOL Figure 3: I2C Serial Control Interface Timing Diagram Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 10 QN8027 4 FUNCTIONAL DESCRIPTION The QN8027 is a high performance low power single chip FM transmitter IC that supports worldwide FM broadcast band operation. It has an IDLE mode for saving power. RDS/RBDS data service is also supported. 81 9 4.1 Transmit Mode 71 44 51 The QN8027 transmitter uses a highly digitized architecture. The input left and right analog audio signals are first adjusted by VGA, and then digitized by two high resolution ADCs into the digital domain. Pre-emphasis and MPX encoding are then performed. If RDS mode is enabled, the RDS signal will also be mixed with the MPX signal and the combined output will be fed into a high performance digital FM modulator which generates FM signal at RF carrier frequency. The FM signal is then filtered and amplified by the PA. 43 41 5 85 ， QQ ： The QN8027 can deliver up to 121dBμV output signal to an external antenna and/or matching network. An RF VGA provides a 42dB output power control range in 0.75 dB steps and can be programmed through the serial control bus. Output power control and in-band power flatness can be easily achieved by a calibration circuit. This wide range of control allow for various antenna configurations such as loop, monopole, or meandering traces on PCB. An integrated RF bandpass filter ensures optimal output spectrum purity. 4.2 Idle Mode ， 18 66 The QN8027 features a low power IDLE mode for fast turn around and power savings. After power up, the QN8027 will enter IDLE mode automatically. 司 4.3 Audio Interface 讯 科 技 有 限 公 The QN8027 has a highly flexible analog audio interface. For audio input, the signal is AC coupled with 3dB corner frequency less than 50Hz. It has 4 different input impedances and 15dB adjustable gain range. Digital gain provides more accurate gain control (in 1dB steps) to optimize the SNR and linearity. The gain setting can be manually set through the serial interface. 合 4.4 Audio Processing 市 金 The QN8027 supports audio AGC, programmable pre-emphasis. When there is no audio signal for a pre-determined period, AGC will power down the transmitter. A peak detector is also integrated to measure the input audio level. User can program VGA based on the peak value. 圳 Stereo signal is generated by the MPX circuit. It combines the left and right channel signals in the following way: 深 m ( t ) = [L ( t ) + R ( t ) ] + [L ( t ) − R ( t ) ] cos( 4π ft + 2θ 0 ) + α cos( 2π ft + θ 0 ) + d ( t ) cos( 6π ft + 3θ 0 ) Here, L(t) and R(t) correspond to the audio signals on left and right channels respectively, f = 19 kHz, θ is the initial phase of pilot tone and α is the magnitude of pilot tone, and d(t) is RDS signal. In mono mode, only the L+R portion of audio signal is transmitted. The 19 kHz pilot tone is generated by the MPX circuit which contributes 9% of peak modulation, and RDS signal will contribute 2.1% of peak modulation. A pre-emphasis function is also integrated with both 75μs and 50μs time constants. The time constant can be programmed through the serial control interface. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 11 QN8027 4.5 Channel Setting By programming channel index CH[9:0], the RF channel can be set to any frequency between 76 MHz ~ 108 MHz in 50 kHz steps. The channel index and RF frequency have the following relationship: 81 9 FRF = (76 + 0.05 x Channel Index), where FRF is the RF frequency in MHz. 71 44 51 The QN8027 has an integrated crystal oscillator and supports 12/24M Hz crystals. Alternatively, the QN8027 can be driven externally by clock source. QQ ： 4.6 RDS/RBDS 43 41 5 85 ， The QN8027 supports RDS/RBDS data transmitting, including station ID, Meta data, TMC information, etc. RDS/RBDS data communicates with an external MCU through the serial control interface. 4.7 Power Setting 18 66 Reg 10H[6:0] ‘PPA_TRGT’ is used for PA output power control. The PA output power expression of the PA output power is: ， Power = (0.62×PATRGT+71)dBuV 公 司 And the PA_TRRGT range is 20~75. 深 圳 市 金 合 讯 科 技 有 限 PA output power setting will not efficient immediately, it need to enter IDLE mode and re-enter TX mode, or when the frequency changed the PA output power setting will take effect. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 12 QN8027 5 CONTROL INTERFACE PROTOCOL The QN8027 supports an I2C serial interface. At power-on, all register bits are set to default values. 5.1 I2C Serial Control Interface 81 9 The QN8027 uses the Phillips I2C standard in the I2C serial interface. ： 71 44 51 The I2C (L2) bus is a simple bi-directional bus interface. The bus requires only serial data (SDA) and serial clock (SCL) signals. The bus is 8-bit oriented. Each device is recognized with a unique address. Each register is also recognized with a unique address. The L2 bus operates with a maximum frequency of 400 kHz. Each data put on the SDA must be 8 bits long (Byte) from MSB to LSB and each byte sent should be acknowledged by an “ACK” bit. In case a byte is not acknowledged, the transmitter should generate a stop condition or restart the transmission. If a stop condition is created before the whole transmission is completed, the remaining bytes will keep their old setting. In case a byte is not completely transferred, it will be discarded. 43 41 5 85 ， QQ Data transfer to and from the QN8027 can begin when a start condition is created. This is the case if a transition from HIGH to LOW on the SDA line occurs while the SCL is HIGH. The first byte transferred represents the address of the IC plus the data direction. The default IC address is 0x2C. A LOW LSB of this byte indicates data transmission (WRITE) while a HIGH LSB indicates data request (READ). This means that the first byte to be transmitted to the QN8027 should be “0x58” for a WRITE operation or “0x59” for a READ operation. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 The second byte is the starting register address (N) for write/read operation. The following bytes are register data for address N, N+1, N+2, etc. There is no limit on the number of bytes in each transmission. A transmission can be terminated by generating a stop condition, which is SDA transition from LOW to HIGH while SCL is HIGH. For write operation, master stops transmission after the last byte. For read operation, master doesn’t send ACK after receiving the last read back byte; then stops the transmission. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 13 QN8027 The timing diagrams below illustrate both write and read operations. I2C Write Operation SCL slave Address A6 A5 A4 A3 A2 A1 A0 Base Address R/W ACK by QN8027 D7 D6 D5 D4 D3 D2 D1 D0 Data Byte 1 ACK by ACK by 9 A7 I2C Start QN8027 QN8027 81 SDA D6 D5 D4 D3 D2 D1 D0 D7 D6 ACK by Data Byte 2 D5 D4 D3 D2 D1 D0 D7 D6 ACK by Data Byte 3 D0 ACK by Stop QN8027 ： A6 R/W ACK by A5 A4 slave Address A0 ACK by D6 D5 D4 D3 D2 D1 18 66 D7 A2 A1 Stop QN8027 SCL SDA A3 Base Address QN8027 I2C D1 D2 QQ A7 slave Address 43 41 5 SDA 85 ， SCL Start D3 Data Byte n I2C Read Operation I 2C D4 QN8027 QN8027 Start D5 44 D7 71 SDA 51 SCL Data Byte 1 R/W ACK by D7 D6 D5 ACK by D4 D3 Data Byte n micro D2 D1 D0 ACK by Stop micro 司 ， QN8027 D0 公 Figure 4: I2C Serial Control Interface Protocol Notes: 技 有 限 The default IC address is 0x2C. “0x58” for a WRITE operation, “0x59” for a READ operation. 深 圳 市 金 合 讯 科 1. 2. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 14 QN8027 6 USER CONTROL REGISTERS -------- THIS IS A PREVIEW LIST. Number and content of registers subject to change without notice -------There are 19 user accessible control registers. All registers not listed below are for manufacturing use only. REGISTER NAME 9 Summary of User Control Registers USER CONTROL FUNCTIONS 81 Table 9: SYSTEM Sets device modes, resets. 01h CH1 Lower 8 bits of 10-bit channel index. 02h GPLT Audio controls, gain of TX pilot frequency deviation. 03h REG_XTL XCLK pin control. 04h REG_VGA TX mode input impedance, crystal frequency setting. 05h CID1 Device ID numbers. 06h CID2 Device ID numbers. 07h STATUS Device status indicators. 08h RDSD0 RDS data byte 0. 09h RDSD1 RDS data byte 1. 0Ah RDSD2 RDS data byte 2. 0Bh RDSD3 RDS data byte 3. 0Ch RDSD4 RDS data byte 4. 0Dh RDSD5 RDS data byte 5. 11h FDEV 12h RDS 44 71 ： QQ 85 ， 43 41 5 18 66 ， PAC 司 10h RDS data byte 6. RDS data byte 7. 公 RDSD7 限 RDSD6 0Fh PA output power target control. Specify total TX frequency deviation. Specify RDS frequency deviation, RDS mode selection. 深 圳 市 金 合 讯 科 技 有 0Eh 51 00h Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 15 QN8027 Register Bit R/W Status: RO - Read Only: You can not program these bits. WO - Write Only: You can write and read these bits; the value you read back will be the same as written. R/W - Read/Write: You can write and read these bits; the value you read back can be different from the value written. Typically, the value is set by the chip itself. 9 Address: 00h 81 Word: SYSTEM Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 swrst recal txreq mono mute rdsrdy ch[9] r/w wo wo wo wo wo 71 ch[8] wo 0 6 RECAL 5 Reset all registers to default values 0 TXREQ 0 Keep the current value. 1 Reset to default values. Reset the state to initial states and recalibrate all blocks. 0 0 No reset. FSM runs normally. 1 Reset the FSM. After this bit is de-asserted, FSM will go through all the power up and calibration sequence. Transmission request: 0 讯 科 MUTE 0 市 金 合 3 圳 2 深 1:0 Stay in IDLE mode. Enter Transmit mode. Force MONO mode for transmission: 限 0 技 有 MONO 公 1 4 85 ， SWRST 43 41 5 7 Description 18 66 Default ， Symbol 司 Bit QQ ： wo Bit 0 (LSB) 51 Bit 6 44 Bit 7 (MSB) 0 Stereo mode. 1 MONO mode. Audio Mute enable: 0 Not Mute 1 Mute RDSRDY 0 RDS transmitting ready: If user want the chip transmitting all the 8 bytes in RDS0~RDS7, user should toggle this bit. Then the chip internally will fetch these bytes after completing transmitting of current group. CH[9:8] 01 Highest 2 bits of 10-bit channel index: Channel freq is (76+CH*0.05) MHz Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 16 QN8027 Word: CH1 Address: 01h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) ch[7] ch[6] ch[5] ch[4] ch[3] ch[2] ch[1] ch[0] wo wo wo wo wo wo wo wo 7:0 CH[7:0] 0000 0000 Lower 8 bits of 10-bit Channel index. Channel used for TX. Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 tc priv_en T1m_sel[1] T1m_sel[0] gain_txplt[3] wo wo wo wo wo Default 7 TC 1 ， 司 10 市 金 圳 GAIN_TXPLT[3:0] Rev 1.1 (04/10) wo wo wo Time constant (us) 50 75 priv_en Privacy mode 0 disabled 1 enabled Selection of 1 minute time for PA off when no audio. The real time is (58+t1m_sel) seconds 深 3:0 gain_txplt[0] Enable the privacy mode (audio scramble and RDS encryption) 限 技 有 讯 科 t1m_sel[1:0] 合 5:4 gain_txplt[1] 公 1 0 gain_txplt[2] Pre-emphasis time constant 0 priv_en Bit 0 (LSB) Description TC 6 Bit 1 Bit 2 43 41 5 Symbol 18 66 Bit QQ ： Address: 02h 85 ， Word: GPLT Description 51 Default 44 Symbol 71 Bit 81 9 Bit 7 (MSB) 1001 T1m_sel[1:0] time 00 58s 01 59s 10 60s 11 Infinity (never) Gain of TX pilot to adjust pilot frequency deviation. Refer to peak frequency deviation of MPX signal when audio input is full scale. GAIN_TXPLT[5:0] value 0111 7% * 75KHz 1000 8% * 75KHz Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 17 QN8027 9% * 75KHz 1010 10% * 75KHz Address: 03h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 xinj[1] xinj[0] xisel[5] xisel[4] xisel[3] xisel[2] xisel[1] wo wo wo wo wo wo wo 00 Select the reference clock source Clock source 00 Use crystal on XTAL1/XTAL2 01 Inject digital clock from XTAL1 Single end sine-wave injection on XTAL1 11 Crystal oscillator current control. 6.25uA*XISEL[5:0], 0-400uA when use crystal on XTAL1/XTAL2. 18 66 010000 Differential sine-wave injection on XTAL1/2 xsel gvga[2] wo wo Symbol 7 XSEL 合 Bit Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) gvga[1] gvga[0] GDB[1] GDB[0] rin[1] rin[0] wo wo wo wo wo wo Bit 5 限 Bit 6 讯 科 Bit 7 (MSB) Default 市 金 1 圳 深 6:4 GVGA[2:0] 公 Address: 04h 技 有 Word: REG_VGA 司 ， XISEL[5:0] 44 XINJ[1:0] 10 5:0 71 XINJ[1:0] ： 7:6 Description QQ Default wo 85 ， Symbol xisel[0] 43 41 5 Bit Bit 0 51 Bit 7 81 9 Word: REG_XTL 1001 011 Description Crystal frequency selection XSEL XTAL frequency (MHz) 0 12 1 24 TX input buffer gain (dB) VGAG[2:0] Rev 1.1 (04/10) RIN[1:0] 00 01 10 11 000 3 -3 -9 -15 001 6 0 -6 -12 010 9 3 -3 -9 Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 18 QN8027 -6 100 15 9 3 -3 101 18 12 6 0 11X Reserved 00 0 dB 01 1 dB 10 2 dB 11 reserved Input impedance (KΩ) 00 5 01 10 10 20 cid0[1] cid0[0] ro ro ro 4:2 CID1[2:0] 合 市 金 圳 深 技 有 CID0[2:0] CID2[1:0] Rev 1.1 (04/10) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) cid1[2] cid1[1] cid1[0] cid2[1] cid2[0] ro ro ro ro ro Default 讯 科 7:5 18 66 ， cid0[2] 1:0 40 司 Bit 5 公 Bit 6 限 Bit 7 (MSB) Symbol 51 RIN[1:0] Address: 05h (RO) Bit 44 TX mode input impedance for both L/R channels. 11 Word: CID1 81 Digital gain 71 10 GDB[1:0] 9 TX digital gain ： RIN[1:0] 0 QQ 1:0 00 6 85 ， GDB[1:0] 12 43 41 5 3:2 011 Description rrr reserved rrr Chip ID for product family 000 CID1[2:0] Product Family 000 FM 001-111 reserved rr Chip ID for minor revision 01 CID2[1:0] Minor revision 00 1 01 2 10 3 11 4 Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 19 QN8027 Word: CID2 Address: 06h (RO) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) cid3[3] cid3[2] cid3[1] cid3[0] cid4[3] cid4[2] cid4[1] cid4[0] ro ro ro ro ro ro ro ro Symbol Default 7:4 CID3[3:0] rrrr Description 44 Chip ID for product ID 0100 Product ： 71 CID3[2:0] QN8027 QQ 0100 rrrr Chip ID for major revision is 1+CID4 0100 CID4[3:0] 0000 Revision number 1 2 18 66 0001 43 41 5 CID4[3:0] reserved 85 ， others 3:0 51 Bit 81 9 Bit 7 (MSB) 3 0011 4 0100-1111 reserved Word: STATUS Bit 6 市 金 ro Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) aud_pk[1] aud_pk[0] rds_upd fsm[2] fsm[1] fsm[0] ro ro ro ro ro ro Default 7:4 aud_pk[3:0] rrrr 3 RDS_UPD r 2:0 FSM[2:0] rrr 圳 Symbol 深 Bit aud_pk[2] 合 aud_pk[3] ro Address: 07h 讯 科 Bit 7 (MSB) 技 有 限 公 司 ， 0010 Rev 1.1 (04/10) Description Audio peak value at ADC input is aud_pk[3:0]*45mV RDS TX: To transmit the 8 bytes in RDS0~RDS7, the user should toggle the register bit RDSRDY. Then the chip internally fetches these bytes after completing transmitting the current group. Once the chip has internally fetched these bytes, it will toggle this bit, and the user can write in another group. Top FSM state code Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 20 QN8027 FSM status 000 RESET 001 CALI 010 IDLE 011 TX_RSTB 100 PA calibration 101 Transmit 110 PA_OFF ： 71 44 51 81 9 FSM[2:0] reserved Bit 5 rdsd0[7] rdsd0[6] rdsd0[5] rdsd0[4] wo wo wo wo 7:0 RDSD0 00000000 rdsd0[3] Bit 2 rdsd0[2] wo Bit 1 rdsd0[1] wo wo Bit 0 (LSB) rdsd0[0] wo Description 司 Default Bit 3 RDS data byte0 to be sent: Data written into RDSD0~RDSD7 can not be sent out if user didn’t toggle RDSRDY to allow the data to be loaded into the internal transmitting buffer. 公 Symbol 讯 科 技 有 限 Bit Bit 4 ， Bit 6 43 41 5 Bit 7 (MSB) Address: 08h 18 66 Word: RDSD0 85 ， QQ 111 Address: 09h 合 Word: RDSD1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) rdsd1[7] rdsd1[6] rdsd1[5] rdsd1[4] rdsd1[3] rdsd1[2] rdsd1[1] rdsd1[0] wo wo wo wo wo wo wo wo 深 圳 市 金 Bit 7 (MSB) Bit Symbol Default 7:0 RDSD1[7:0] 0000 0000 Rev 1.1 (04/10) Description RDS data byte 1 Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 21 QN8027 Word: RDSD2 Address: 0Ah Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) rdsd2[7] rdsd2[6] rdsd2[5] rdsd2[4] rdsd2[3] rdsd2[2] rdsd2[1] rdsd2[0] wo wo wo wo wo wo wo wo Default 7:0 RDSD2[7:0] 0000 0000 RDS data byte 2 Address: 0Bh ： Word: RDSD3 Description 44 Symbol 71 Bit 51 81 9 Bit 7 (MSB) Bit 4 Bit 3 rdsd3[7] rdsd3[6] rdsd3[5] rdsd3[4] rdsd3[3] wo wo wo wo wo Symbol Default 7:0 RDSD3[7:0] 0000 0000 rdsd3[2] rdsd3[1] rdsd3[0] wo wo wo Description RDS data byte 3 Address: 0Ch ， Word: RDSD4 Bit 0 (LSB) Bit 2 18 66 Bit Bit 1 QQ Bit 5 85 ， Bit 6 43 41 5 Bit 7 (MSB) rdsd4[7] rdsd4[6] rdsd4[5] wo wo wo 7:0 RDSD4[7:0] 技 有 讯 科 Symbol Bit 3 Bit 2 Bit 1 Bit 0 (LSB) rdsd4[4] rdsd4[3] rdsd4[2] rdsd4[1] rdsd4[0] wo wo wo wo wo Default Description 0000 0000 RDS data byte 4 市 金 合 Bit Bit 4 司 Bit 5 公 Bit 6 限 Bit 7 (MSB) 圳 Word: RDSD5 Address: 0Dh Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) rdsd5[7] rdsd5[6] rdsd5[5] rdsd5[4] rdsd5[3] rdsd5[2] rdsd5[1] rdsd5[0] wo wo wo wo wo wo wo wo 深 Bit 7 (MSB) Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 22 QN8027 Bit Symbol Default 7:0 RDSD5[7:0] 0000 0000 RDS data byte 5 Address: 0Eh 9 Word: RDSD6 Description Bit 0 (LSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 rdsd6[7] rdsd6[6] rdsd6[5] rdsd6[4] rdsd6[3] rdsd6[2] rdsd6[1] wo wo wo wo wo wo 44 51 81 Bit 7 (MSB) wo Default 7:0 RDSD6[7:0] 0000 0000 RDS data byte 6 Address: 0Fh Bit 6 Bit 5 Bit 4 rdsd7[7] rdsd7[6] rdsd7[5] rdsd7[4] wo wo wo wo Bit 2 Bit 1 Bit 0 (LSB) rdsd7[3] rdsd7[2] rdsd7[1] rdsd7[0] wo wo wo wo Bit 3 司 ， 18 66 Bit 7 (MSB) 43 41 5 Word: RDSD7 Description QQ Symbol 85 ， Bit ： 71 wo rdsd6[0] Default 7:0 RDSD7[7:0] 0000 0000 Description 公 Symbol RDS data byte 7 技 有 限 Bit Address: 10h 讯 科 Word: PAC Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) pa_trgt[6] pa_trgt[5] pa_trgt[4] pa_trgt[3] pa_trgt[2] pa_trgt[1] pa_trgt[0] wo wo wo wo wo wo wo 市 金 txpd_clr Bit 6 合 Bit 7 (MSB) 深 圳 wo Bit Symbol Default 7 TXPD_CLR 0 6:0 PA_TRGT[6:0] 111 1111 Rev 1.1 (04/10) Description TX aud_pk clear signal: Audio peak value is max-hold and stored in aud_pk[3:0]. Once TXPD_CLR is toggled, the aud_pk value is cleared and restarted again. PA output power target is 0.62*PA_TRGT+71dBu. Valid values are 2075. Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 23 QN8027 Word: FDEV Address: 11h Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) tx_fdev[7] tx_fdev[6] tx_fdev[5] tx_fdev[4] tx_fdev[3] tx_fdev[2] tx_fdev[1] tx_fdev[0] wo wo wo wo wo wo wo wo 7:0 TX_FDEV[7:0] 10000001 Specify total TX frequency deviation: TX frequency deviation = 0.58 kHz*TX_FDEV. TX_FDEV[7:0] value Bit 7 (MSB) rdsen Bit 6 rdsfdev[6] Bit 4 rdsfdev[5] wo Bit 3 rdsfdev[4] wo rdsfdev[3] wo Bit 2 rdsfdev[2] wo Bit 1 rdsfdev[1] wo wo Bit 0 (LSB) rdsfdev[0] wo Symbol Default 7 RDSEN 0 限 RDS enable: 技 有 RDSFDEV[6:0] 000 0110 0 RDS disable 1 RDS enable Specify RDS frequency deviation: RDS frequency deviation = 0.35KHz*RDSFDEV. RDSFDEV[6:0] Value 000 0000 – 111 1111 0~127 深 圳 市 金 合 讯 科 6 Description 公 Bit 司 ， wo Bit 5 43 41 5 Address: 12h 18 66 Word: RDS 0 ~ 255 85 ， 0000 0000 - 1111 1111 44 Description 71 Default ： Symbol QQ Bit 51 81 9 Bit 7 (MSB) Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 24 QN8027 7 ORDERING INFORMATION Part Number Package 3x3 mm Body [MSOP10] 81 9 The QN8027 is a high performance, low power, full-featured singlechip stereo FM transmitter designed for portable audio/video players, automotive accessories, cell phones, and GPS personal navigation devices. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 QN8027-SANC Description Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 25 QN8027 8 PACKAGE DESCRIPTION 85 ， QQ ： 71 44 51 81 9 10-Lead plastic package – 3x3 mm Body [MSOP] Symbol 18 66 43 41 5 Figure 5: MSOP10 Package Outline Dimensions A1 Board standoff A2 Package thickness 司 Overall package height 限 公 A ， Description Millimeters Minimum Nominal Maximum 0.820 0.95 1.100 0.020 - 0.150 0.750 0.85 0.950 0.180 0.23 0.280 Lead width c Lead thickness 0.090 - 0.230 D Package’s outside, X-axis 2.900 3.00 3.100 e Lead pitch E Package’s outside, Y-axis 2.900 3.00 3.100 E1 Lead to lead, Y-axis 4.750 4.90 5.050 Foot length 0.400 0.60 0.800 0° - 6° 深 讯 科 合 圳 θ 市 金 L 技 有 b Foot to board angle 0.50 (BSC) Notes: 1. 2. Pin 1 visual index feature may vary, but must be located within the area indicated in the drawing. Dimensioning and tolerance per ASME Y 14.5M. BSC: Basic Dimension. The theoretically exact value is shown without tolerance. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 26 QN8027 43 41 5 85 ， QQ ： 71 44 51 81 9 Carrier Tape Dimensions Figure 6: MSOP10 Carrier Tape Drawing 18 66 NOTES: 1. 10 sprocket hole pitch cumulative tolerance +0.2mm maximum. U ， 2. Camber not to exceed 1mm in 100mm: <1mm/100mm. 深 圳 市 金 合 讯 科 技 有 限 公 司 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 27 QN8027 9 SOLDER REFLOW PROFILE 9.1 Package Peak Reflow Temperature 81 9 QN8027 is assembled in a lead-free MSOP package. Since the geometrical size of QN8027 is 3 mm × 3 mm × 0.95 mm, the volume and thickness is in the category of volume<350 mm3 and thickness<1.6 mm in Table 4-2 of IPC/JEDEC J-STD020C. The peak reflow temperature is: 71 The temperature tolerance is +0oC and -5oC. Temperature is measured at the top of the package. 44 51 Tp = 260 o C QQ ： 9.2 Classification Reflow Profiles Profile Feature Specification* 85 ， Average Ramp-Up Rate (tsmax to tP) Temperature Min (Tsmin) Pre-heat: 43 41 5 Temperature Max (Tsmax) Time (ts) 18 66 Temperature (TL) Time maintained above: Time (tL) ， Peak/Classification Temperature (Tp) 公 司 Time within 5°C of Actual Peak Temperature (tp) 150°C 200°C 60-180 seconds 217°C 60-150 seconds 260°C 20-40 seconds 6°C/second max. 8 minutes max. 技 有 Time 25°C to Peak Temperature 限 Ramp-Down Rate 3°C/second max. 深 圳 市 金 合 讯 科 *Note: All temperatures are measured at the top of the package. Figure 7: Reflow Temperature Profile Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 28 QN8027 9.3 Maximum Reflow Times 讯 科 技 有 限 公 司 ， 18 66 43 41 5 85 ， QQ ： 71 44 51 81 9 All package reliability tests were performed and passed with a pre-condition procedure that repeat a reflow profile, which conforms to the requirements in Section 9.2, three (3) times. 合 CONTACT INFORMATION Quintic Microelectronics (China) 3211 Scott Blvd., Suite 203 Santa Clara, CA 95054 Tel: +1.408.970.8808 Fax: +1.408.970.8829 Email: [email protected] Web: www.quinticcorp.com Building 8 B-301A Tsinghua Science Park 1st East Zhongguancun Rd, Haidian Beijing, China 100084 Tel: +86 (10) 8215-1997 Fax: +86 (10) 8215-1570 Web: www.quinticcorp.com 深 圳 市 金 Quintic Corporation (USA) HU HU U U H Quintic Microelectronics and Quintic are trademarks of Quintic Corporation. All Rights Reserved. Rev 1.1 (04/10) Copyright ©2010 by Quintic Corporation Confidential Information contained herein is covered under Non-Disclosure Agreement (NDA). Page 29