SAMSUNG K9HDG08U5A

Rev.1.0, May. 2010
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
Final
32Gb A-die NAND Flash
Multi-Level-Cell (2bit/cell)
datasheet
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SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
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Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or otherwise.
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may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
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ⓒ 2009 Samsung Electronics Co., Ltd. All rights reserved.
-1-
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
Revision History
Revision No.
History
Draft Date
Remark
Editor
0.0
1. Initial issue
Nov. 12, 2009
Draft
S.M.Lee
0.1
1. Value of Random Read is changed.
2. Package size is amended. (14x18 -> 13x18)
3. Package configuration for K9HDG08U5A-L and K9PFG08U5A-L is amended.
4. Pin descriptions for VccQ and VssQ are added.
5. Voltage on any pin relative to VSS for VccQ=1.8V is added in table 2.1.
6. Temperature Under Bias(TBIAS) is deleted.
7. Table 2.3 DC AND OPERATING CHARACTERISTICS is modified. (VccQ=1.8V
added)
8. Frequency condition of Capacitance is changed from 1.0Mhz to 100Mhz.
9. Dummy Busy Time for Intelligent Copy-Back Read(tCBSY2) is added.
10. Dummy Busy Time for Intelligent Copy-Back Program(tDCBSYR2) is added.
11. Max. value of Cache Busy in Read Cache(tDCBSYR) is changed from 400us to
90us.
12. RE Pulse Width(tRP) is changed from 15ns to 12ns.
13. Read Cycle Time is changed from 30ns to 25ns.
14. RE Access Time(tREA) is changed from 25ns to 20ns.
15. CE Access Time(tCEA) is changed from 35ns to 25ns.
16. WE High to RE Low for Random data out(tWHR2) is changed from 300ns to 180ns.
17. Set feature command(EFh) is added.
18. Get feature command(EEh) is added.
Nov. 25, 2009
Draft
S.M.Lee
0.2
1. Product list is amended.
2. VccQ=1.8V is deleted.
3. Part ID of 52-LGA is fixed from K8XXG08UXA-LCB0/LIB0 to K8XXG08UXA-MCB0/
MIB0.
4. Package thickness of K9HDB08U5A is fixed from 0.65mm to 0.75mm.
5. Description for Interleaving operation is deleted.
6. F2h command is deleted.
7. Meaning is swapped between tCBSY2 and tDCBSYR2.
8. tCWAW is added.
9. Value of tWHR2 is changed from 180ns to 300ns.
10. tFEAT is added.
11. Additional res
iction of Addressing for Program operation is described.
Dec. 12, 2009
Draft
S.M.Lee
0.3
1. Description of tWW is amended.
2. The value of tCBSY2 is changed from 5ms to 500us.
3. The value of tDCBSYR2 is changed from 500us to 5ms.
4. Two-plane Copy-Back Program command is fixed.
5. Description of Status read for Intelligent Copy-Back Program is added.
Dec. 29, 2009
Draft
H.K.Kim
May. 17, 2010
Final
Y.E.Yoon
1.0
1. Pin Configuration of 48 TSOP is added.
2. 4.26 00h address ID Cycle is added.
3. 4.27 40h address ID Cycle is added.
4. 40h address ID definition table is added.
5. tCWAW at the register read out model is added.
6. Random read Time(tR) is changed from 80 μs to 250 μs.
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.
-2-
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
Table Of Contents
32Gb A-die NAND Flash 1
1.0 Introduction ................................................................................................................................................................. 5
1.1 Product List......................................................................................................................................................5
1.2 Features ..........................................................................................................................................................5
1.3 General Description................................................................................................................................................ 5
1.4 Pin Configuration (52LGA) ..................................................................................................................................... 6
1.4.1 Package Dimensions ....................................................................................................................................... 6
1.5 Package Configuration (52LGA)............................................................................................................................. 7
1.5.1 Package Dimensions ....................................................................................................................................... 7
1.6 Package Configuration (52LGA)............................................................................................................................. 8
1.6.1 Package Dimensions ....................................................................................................................................... 8
1.7 Pin Configuration (48TSOP, mono) ......................................................................................................................... 9
1.7.1 Package Dimensions ........................................................................................................................................ 9
1.8 Pin Configuration (48TSOP, DDP) .......................................................................................................................... 10
1.8.1 Package Dimensions ........................................................................................................................................ 10
1.9 Pin Configuration (48TSOP, QDP) .......................................................................................................................... 11
1.9.1 Package Dimensions ........................................................................................................................................ 11
1.10 Pin Description ..................................................................................................................................................... 12
2.0 PRODUCT INTRODUCTION..................................................................................................................................... 15
2.1 Absolute Maximum Ratings ..............................................................................................................................16
2.2 Recommended Operating Conditions .................................................................................................................... 16
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.) .................................. 16
2.4 Valid Block.............................................................................................................................................................. 17
2.5 AC Test Condition .................................................................................................................................................. 17
2.6 Capacitance(TA=25°C, VCC=3.3V, f=100MHz) ..................................................................................................... 17
2.7 Mode Selection....................................................................................................................................................... 18
2.8 Program/Erase Characteristics .........................................................................................................................18
2.9 AC Timing Characteristics for Command / Address / Data Input ........................................................................... 19
2.10 AC Characteristics for Operation.......................................................................................................................... 19
3.0 NAND Flash Technical Notes .................................................................................................................................... 20
3.1 Initial Invalid Block(s).............................................................................................................................................. 20
3.2 Identifying Initial Invalid Block(s) ............................................................................................................................ 20
3.3 Error in write or read operation ............................................................................................................................... 21
3.4 Addressing for program operation .......................................................................................................................... 23
3.5 System Interface Using CE don’t-care. .................................................................................................................. 25
4.0 TIMING DIAGRAMS .................................................................................................................................................. 26
4.1 Command Latch Cycle ........................................................................................................................................... 26
4.2 Address Latch Cycle............................................................................................................................................... 26
4.3 Input Data Latch Cycle ........................................................................................................................................... 27
4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)..................................................................................... 27
4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L) .................................................................... 28
4.6 Status Read Cycle .................................................................................................................................................. 28
4.7 Read Operation ...................................................................................................................................................... 29
4.8 Read Operation(Intercepted by CE) ....................................................................................................................... 29
4.9 Random Data Output In a Page ............................................................................................................................. 30
4.10 Cache Read Operation......................................................................................................................................... 31
4.11 Two-Plane Page Read Operation with Two-Plane Random Data Out ................................................................. 32
4.12 Two-Plane Cache Read Operation with Two-Plane Random Data Out (1/2)....................................................... 33
4.13 Two-Plane Cache Read Operation with Two-Plane Random Data Out (2/2)....................................................... 34
4.14 Page Program Operation...................................................................................................................................... 34
4.15 Page Program Operation with Random Data Input .............................................................................................. 35
4.16 Copy-Back Program Operation with Random Data Input ..................................................................................... 36
4.17 Intelligent Copy-Back Program(1/2) ..................................................................................................................... 37
4.18 Cache Program Operation(available only within a block) ..................................................................................... 39
4.19 Two-Plane Copy-Back Program ............................................................................................................................ 40
4.20 Two-Plane Intelligent Copy-Back Program(1/3) .................................................................................................... 41
4.21 Two-Plane Page Program Operation .................................................................................................................... 44
4.22 Two-Plane Cache Program Operation ................................................................................................................ 45
4.23 Block Erase Operation.......................................................................................................................................... 46
4.24 Two-Plane Block Erase Operation ....................................................................................................................... 47
-3-
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
4.25 Read ID Operation................................................................................................................................................ 48
4.26 00h Address ID Cycle............................................................................................................................................ 48
4.27 40h Address ID Cycle............................................................................................................................................ 48
4.27.1 ID Definition Table........................................................................................................................................... 49
5.0 DEVICE OPERATION ............................................................................................................................................... 51
5.1 Page Read.............................................................................................................................................................. 51
5.2 Cache Read............................................................................................................................................................ 52
5.3 Two-plane Page Read............................................................................................................................................ 54
5.4 Two-plane Cache Read .......................................................................................................................................... 55
5.5 Page Program ......................................................................................................................................................... 56
5.6 Copy-back Program................................................................................................................................................ 57
5.7 Intelligent Copy-Back Program ................................................................................................................................ 58
5.8 Cache Program ....................................................................................................................................................... 59
5.9 Register Read Out Mode 1..................................................................................................................................... 62
5.10 Register Read Out Mode 2................................................................................................................................... 62
5.11 Two-plane Register Read Out Mode 1 ................................................................................................................. 63
5.12 Two-plane Register Read Out Mode 2 ................................................................................................................. 64
5.13 Two-plane Page Program..................................................................................................................................... 65
5.14 Two-plane Copy-back Program ............................................................................................................................ 66
5.15 Two-Plane Intelligent Copy-back Program(1/2)..................................................................................................... 69
5.16 Two-plane Cache Program................................................................................................................................... 72
5.17 Block Erase .......................................................................................................................................................... 73
5.18 Two-plane Block Erase......................................................................................................................................... 73
5.19 Read Status.......................................................................................................................................................... 74
5.20 Read Id ................................................................................................................................................................. 75
5.21 Reset .................................................................................................................................................................... 75
5.22 Output driver setting ............................................................................................................................................. 76
5.23 Ready/busy............................................................................................................................................................ 78
5.24 00h Address ID Cycle............................................................................................................................................ 79
5.25 40h Address ID Cycle............................................................................................................................................ 79
5.26 Device Identification Table Read Operation .......................................................................................................... 79
6.0 DATA PROTECTION & POWER UP SEQUENCE.................................................................................................... 81
6.1 WP AC Timing guide .............................................................................................................................................. 82
-4-
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
datasheet
FLASH MEMORY
1.0 Introduction
1.1 Product List
Part Number
Density
K9GBG08U0A-M
32Gb
K9LCG08U1A-M
64Gb
K9HDG08U5A-M
128Gb
Interface
VccQ Range
Vcc Range
Organization
PKG Type
Conventional
2.7V ~ 3.6V
2.7V ~ 3.6V
x8
52LGA
48TSOP
1.2 Features
• Voltage Supply
- Core voltage : 3.3V(2.7V ~ 3.6V)
- I/O voltage : 3.3V(2.7V~ 3.6V)
• Organization of Single die
- Memory Cell Array : 8,832 x 519K x 8bit
- Data Register
: (8K + 640) x 8bit
• Automatic Program and Erase
- Page Program : (8K + 640)Byte
- Block Erase : (1M + 80K)Byte
• Page Read Operation
- Page Size : (8K + 640)Byte
- Random Read(tR) : 250μs(Average Typ.), 300μs(Average Max.)
- Serial Access : 25ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Write Cycle Time
- Program time : 1.3ms(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- ECC : 40bit/(1K+80)Byte
- Endurance & Data Retention : Please refer to the Qualification report
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
- K9GBG08U0A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9LCG08U1A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9HDG08U5A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9GBG08U0A-SCB0/SIB : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
- K9LCG08U0A-SCB0/SIB0 : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
- K9HDG08U1A-SCB0/SIB0 : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
1.3 General Description
The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation
can be performed in typical 1.3ms on the 8,832-byte page and an erase operation can be performed in typical 1.5ms on a (1M+80K)byte block. Data in
the data register can be read out at Read cycle time(tRC) per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9XXG08XXA′s extended reliability of P/E cycles which are presented in the
Qualification report by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These NAND devices are an optimum solution for
large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
-5-
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.4 Pin Configuration (52LGA)
K9GBG08U0A-MCB0/MIB0
A
8
C
B
NC
E
D
G
F
H
NC
NC
K
J
L
M
N
NC
NC
VssQ
7
NC
6
/RE
Vcc
NC
NC
NC
NC
Vss
IO7
VccQ
NC
Vcc
IO5
5
/CE
4
3
NC
CLE
2
R/B
NC
IO6
IO0
/WE
NC
Vss
NC
IO4
IO2
IO1
/WP
NC
Vss
NC
VssQ
IO3
1
ALE
NC
0
NC
NC
NC
NC
VccQ
NC
NC
NC
NC
NC
NC
OA
OB
OC
OD
OE
OF
1.4.1 Package Dimensions
52-LGA (measured in millimeters)
Bottom View
13.00±0.10
8
13.00±0.10
2.00 x 5 = 10.00
2.00 x 3 = 6.00
1.00
7
6 5 4 3 2
A
2.00
1
B
0
1.30
Top View
(Datum A)
#A1
18.00±0.10
E
5.00
F
G
2.50
H
J
2.00
K
L
M
N
41-∅0.70±0.05
12-∅1.00±0.05
∅0.1 M C AB
18.00±0.10
0.10 C
-6-
∅0.1
0.65(Max.)
Side View
M C AB
2.00 x 4 + 5.00 = 13.00
18.00±0.10
1.00
4.475
D
(Datum B)
2.00 x 6 = 12.00
B
C
6.50
A
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.5 Package Configuration (52LGA)
K9LCG08U1A-MCB0/MIB0
A
8
NC
C
B
E
D
G
F
H
NC
NC
K
J
L
M
N
NC
NC
VssQ
7
/RE1
NC
IO7-2
R/B2
IO6-2
IO5-2
VccQ
6
Vcc
/RE2
IO7-1
Vss
IO5-1
Vcc
5
4
R/B1
/CE1
/CE2
CLE1
CLE2
3
/WE1
/WP2
IO6-1
IO4-1
IO0-1
IO2-1
Vss
IO4-2
IO3-2
2
ALE2
Vss
IO1-1
/WP1
VssQ
IO3-1
1
ALE1
NC
0
/WE2
IO0-2
IO1-2
VccQ
IO2-2
NC
NC
NC
NC
NC
NC
OA
OB
OC
OD
OE
OF
1.5.1 Package Dimensions
52-LGA (measured in millimeters)
Bottom View
13.00±0.10
8
13.00±0.10
2.00 x 5 = 10.00
2.00 x 3 = 6.00
1.00
7
6 5 4 3 2
A
2.00
1
B
0
1.30
Top View
(Datum A)
#A1
18.00±0.10
E
5.00
F
G
2.50
H
J
2.00
K
L
M
N
41-∅0.70±0.05
12-∅1.00±0.05
∅0.1 M C AB
18.00±0.10
0.10 C
-7-
0.65(Max.)
Side View
∅0.1
M C AB
2.00 x 4 + 5.00 = 13.00
18.00±0.10
1.00
4.475
D
(Datum B)
2.00 x 6 = 12.00
B
C
6.50
A
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.6 Package Configuration (52LGA)
K9HDG08U5A-MCB0/MIB0
A
C
B
G
F
H
K
J
NC
NC
8
E
D
L
M
NC
N
NC
VssQ
R/B2-2
7
R/B2-1
6
/RE1
Vcc
R/B1-2
IO7-2
IO6-2
IO7-1
Vss
/RE2
IO5-2
IO5-1
VccQ
Vcc
5
4
/CE1-1
/CE1-2
R/B1-1
/WP2
IO6-1
IO4-1
IO4-2
CLE1
CLE2
/WE1
IO0-1
IO2-1
Vss
IO3-2
3
2
ALE2
Vss
IO1-1
/WP1
IO3-1
VssQ
1
ALE1
/CE2-1
0
/WE2
IO0-2
IO1-2
VccQ
IO2-2
NC
NC
NC
NC
NC
OB
OC
OD
OE
OF
/CE2-2
OA
1.6.1 Package Dimensions
52-LGA (measured in millimeters)
Bottom View
13.00±0.10
8
13.00±0.10
2.00 x 5 = 10.00
2.00 x 3 = 6.00
1.00
7
6 5 4 3 2
A
2.00
1
B
0
1.30
Top View
(Datum A)
#A1
18.00±0.10
E
5.00
F
G
2.50
H
J
2.00
K
L
M
N
41-∅0.70±0.05
12-∅1.00±0.05
∅0.1 M C AB
18.00±0.10
0.10 C
-8-
0.75(Max.)
Side View
∅0.1
M C AB
2.00 x 4 + 5.00 = 13.00
18.00±0.10
1.00
4.475
D
(Datum B)
2.00 x 6 = 12.00
B
C
6.50
A
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.7 Pin Configuration (48TSOP, mono)
K9GBG08U0A-SCB0/SIB0
Vcc
Vss
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
Vss
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Standard Type
12mm x 20mm
Vss
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
VccQ
Vcc
Vss
N.C
VccQ
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
Vss
1.7.1 Package Dimensions
48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
12.40
0.488 MAX
12.00
0.472
+0.003
( 0.25 )
0.010
#1
0.008-0.001
0.50
0.0197
0.16 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
-9-
1.20
0.047MAX
0.05
0.002 MIN
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.8 Pin Configuration (48TSOP, DDP)
K9LBG08U0A-SCB0/SIB0
Vcc
Vss
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
Vss
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Standard Type
12mm x 20mm
Vss
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
VccQ
Vcc
Vss
N.C
VccQ
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
Vss
1.8.1 Package Dimensions
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
0.10
MAX
0.004
Unit :mm/Inch
#48
#24
#25
12.40
0.488 MAX
12.00
0.472
+0.003
( 0.25 )
0.010
#1
0.008-0.001
0.50
0.0197
0.16 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
- 10 -
1.20
0.047MAX
0.05
0.002 MIN
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
1.9 Pin Configuration (48TSOP, QDP)
K9HBG08U1A-SCB0/SIB0
Vcc
Vss
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
Vss
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss
N.C
N.CN.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
VccQ
Vcc
Vss
N.C
VccQ
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
Vss
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-pin TSOP1
Standard Type
12mm x 20mm
1.9.1 Package Dimensions
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm
48 - TSOP1 - 1220BF
1.20MAX
1.05.±0.3
(
#48
0.80 Dp 0~0.05)
(
°)
p0
1.
20
D
0D
+0.07
( 10
p
1 .0
0.16 -0.03
(13°)
(1.00)
#1
(1.00)
0~
0.
05
)
(1.00)
#25
0.10
MAX
0.075
0.02 MIN
+0.075
)
15
0.
(R
0.4625±0.15
0.4625±0.15
18.40.±0.10
(18.80)
( 13
°)
(19.00)
(R
(R
0 .2
5)
0 .2
0°~ 8
0.25TYP
(10°)
(R
0.
15
)
)
)
15
(0.25)
#24
.1 5
0.
(R
0.50TYP
[0.50±0.06]
)
12.00.±0.10
.0 5
(2
-
~0
0
(R
0.125 -0.035
0.20 -0.03
+0.07
(1.00)
5)
°
20.00.±0.20
(0.50)
0.45 ~ 0.75
- 11 -
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
1.10 Pin Description
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to
high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high, commands are
latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising
edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not
return to standby mode in program or erase operation.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent program/erase protection during power transitions. The internal high voltage generator is
reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition
when the chip is deselected or when outputs are disabled.
Vcc
POWER
VCC is the power supply for device.
VccQ
Vss
VssQ
N.C
I/O POWER
The VccQ is the power supply for input and/or output signals.
GROUND
I/O GROUND
The VssQ is the power supply ground
NO CONNECTION
Lead is not internally connected.
NOTE :
Connect all Vcc and Vss pins of each device to common power supply outputs.
Do not leave either Vcc or Vss disconnected.
The K9GBG08U0A has one CE pins(CE) and R/B pins(R/B).
The K9LCG08U1A has two CE pins(CE1 to CE2) and R/B pins(R/B1 to R/B2).
The K9HDG08U5A has four CE pins(CE1-1 to CE2-2) and R/B pins(R/B1-1 to R/B2-2).
For K9HDG08X5A,
CE1-1, CE2-1 and R/B1-1, R/B2-1 are mapped to I/O0-1 ~ I/O7-1.
CE1-2, CE2-2 and R/B1-2, R/B2-2 are mapped to I/O0-2 ~ I/O7-2.
- 12 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Functional Block Diagram
VCC
VSS
A14 - A33
X-Buffers
Latches
& Decoders
A0 - A13
Y-Buffers
Latches
& Decoders
NAND Flash
ARRAY
Data Register & S/A
Y-Gating
Command
Command
Register
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
I/0 0
Output
Driver
Global Buffers
R/B
I/0 7
CLE ALE WP
Array Organization of Single Die
1 Block = 128 Pages
(1M+ 80K) Bytes
1 Page = (8K + 640)Bytes
1 Block = (8K + 640)B x 128 Pages
= (1M +80K) Bytes
1 Device = (8K + 640)B x 128 Pages x 4,152 Blocks
= 36,670,464 Kbits
531,456 Pages
(=4,152 Blocks)
8 bit
8K Bytes
640 Bytes
I/O 0 ~ I/O 7
Page Register
8K Bytes
I/O 2
640 Bytes
I/O 3
I/O 0
I/O 1
1st Cycle
A0
A1
A2
A3
2nd Cycle
A8
A9
A10
A11
3rd Cycle
A14
A15
A16
A17
4th Cycle
A22
A23
A24
A25
5th Cycle
A30
A31
A32
A33
I/O 5
I/O 6
I/O 7
A4
A5
A6
A7
A12
A13
*L
*L
A18
A19
A20
A21
A26
A27
A28
A29
*L
*L
*L
*L
I/O 4
NOTE :
Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
* Row Address consists of Page address (A14 ~ A20) & Plane address(A21) & Block address(A22 ~ the last address)
- 13 -
Column Address
Row Address;
Page Address : A14 ~ A20
Plane Address : A21
Block Address : A22 ~ A33
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Spare Blocks Arrangement
The device has 56 spare blocks to increase valid blocks. Extended blocks can be accessed by the following address.
Page Address
(Hexadecimal)
00000h
Block 0
00080h
Block 1
00100h
Block 2
00180h
Block 3
00200h
Block 4
00280h
Block 5
Main Blocks
(4096 Blocks)
ㆍ
ㆍ
ㆍ
7FF00h
Block 4094
7FF80h
Block 4095
80000h
Block 4096
80080h
Block 4097
ㆍ
ㆍ
ㆍ
81B00h
Block 4150
81B80h
Block 4151
- 14 -
Extended Blocks
(56 Blocks)
Final Rev. 1.0
FLASH MEMORY
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
2.0 PRODUCT INTRODUCTION
NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities
by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low.
Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address
respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc. require just one cycle
bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution..
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the
three row address cycles are used. Device operations are selected by writing specific commands into the command register. The table below defines the
specific commands of the K9XXG08UXA.
Command Sets
1st Set
2nd Set
Read
Function
00h
30h
Read for Copy-Back
00h
35h
Intelligent Copy-Back Read
00h
3Ah
Cache Read
31h
-
Read Start for Last Page Cache Read
3Fh
-
Page Program
80h
10h
Cache Program
80h
15h
Copy-Back Program
85h
10h
Intelligent Copy-Back Program
8Ch
15h
Block Erase
60h
D0h
85h
-
05h
E0h
60h----60h
30h
60h----60h
35h
Two-Plane Intelligent Copy-Back Read
60h----60h
3Ah
(1) (3)
00h----05h
E0h
Random Data Input
(1)
Random Data Output
(1)
Two-Plane Read (3)
Two-Plane Read for Copy-Back
(3)
Two-Plane Random Data Output
Two-Plane Cache Read
(3)
Two-Plane Page Program
(2)
60h----60h
33h
80h----11h
81h----10h
Two-Plane Copy-Back Program(2)
85h----11h
81h----10h
Two-Plane Intelligent Copy-Back Program
8Ch----11h
8Ch----15h
Two-Plane Cache Program(2)
80h----11h
81h----15h
Two-Plane Block Erase
60h----60h
D0h
Acceptable Command during busy
Read ID
90h
-
Read Status
70h
-
O
O
Read Status1
F1h
-
Set Feature
EFh
-
Get Feature
EEh
-
Reset
FFh
-
NOTE :
1) Random Data Input/Output can be executed in a page.
2) Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3) Two-Plane Random Data out must be used after Two-Plane Read or Two-Plane Cache Read operation
Caution :
Any undefined command inputs are prohibited except for above command set.
- 15 -
O
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
2.1 Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Storage Temperature
Symbol
Rating
VCC
-0.6 to +4.6
Unit
VIN
VccQ=3.3V
-0.6 to +4.6
VI/O
VccQ=3.3V
-0.6 to +4.6
K9XXG08XXA-XCB0/XIB0
Short Circuit Current
V
TSTG
-65 to +100
°C
Ios
5
mA
NOTE :
1) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2.2 Recommended Operating Conditions
(Voltage reference to GND, K9XXG08UXA-XCB0 :TA=0 to 70°C(1), K9XXG08UXA-XIB :vTA=-40 to 85°C(1))
Parameter
Symbol
Min
Typ.
Max
Supply Voltage
VCC
2.7
3.3
3.6
Supply Voltage
VSS
0
0
0
I/O Voltage
VccQ(3.3V)
2.7
3.3
3.6
I/O Voltage
VssQ
0
0
0
Unit
V
NOTE:
1) Data retention is not guaranteed on the operating condition temperature under/over.
2.3 DC And Operating Characteristics(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
VccQ=3.3V
Min
Typ
Max
-
30
50
tRC=25ns
CE=VIL, IOUT=0mA
Page Read with Serial
Access
ICC1
Program
ICC2
-
Erase
ICC3
-
Stand-by Current(CMOS)
ISB
CE=VccQ-0.2, WP=0V/VccQ
-
10
50
Input Leakage Current
ILI(2)
VIN=0 to VccQ(max)
-
-
±10
(1)
Unit
Output Leakage Current
(2)
ILO
VOUT=0 to VccQ(max)
-
-
±10
Input High Voltage
VIH(3)
-
0.8 xVccQ
-
VccQ +0.3
Input Low Voltage, All inputs
VIL(3)
-
-0.3
-
0.2 xVccQ
Output High Voltage Level
VOH
IOH=-400μA
2.4
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
8
10
-
NOTE :
1) The typical value of the K9LCG08U1A’s ISB is 20μA and the maximum value is 100μA.
The typical value of the K9HDG08U5A’s ISB is 40μA and the maximum value is 200μA.
2) The maximum value of K9HDG08U5A’s are ±20μA.
3) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less.
4) Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
- 16 -
mA
μA
V
mA
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
2.4 Valid Block
Parameter
Symbol
Min
Typ.
Max
4,036
K9GBG08U0A
K9LCG08U1A
8,072
NVB
K9HDG08U5A
Unit
4,152
-
8,304
16,144
Blocks
16,608
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits which cause status failure during program and erase operation. Do
not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment
3) The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.
* Each Single die in K9LCG08U1A and K9HDG08U5A has maximum 116 invalid blocks.
2.5 AC Test Condition
(K9XXG08UXA-XCB0 :TA=0 to 70°C, K9XXG08UXA: Vcc=2.7V ~ 3.3V,unless otherwise noted)
Parameter
K9XXG08UXA
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL = 5pF
2.6 Capacitance(TA=25°C, VCC=3.3V, f=100MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
K9GBG08U0A
K9LCG08U1A
Test Condition
K9HDG08U5A
Min
Max
Min
Max
Unit
CI/O
VIL=0V
-
8
-
13
pF
CI/O(W)*
VIL=0V
-
5
-
10
pF
CIN
VIN=0V
-
8
-
13
pF
CIN(W)*
VIN=0V
-
5
-
10
pF
NOTE :
1) Capacitance is periodically sampled and not 100% tested.
2) CI/O(W) and CIN(W) are tested at wafer level.
- 17 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
2.7 Mode Selection
CLE
ALE
CE
H
L
L
H
H
L
L
L
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
Mode
RE
WP
L
H
X
L
H
X
L
L
H
H
H
L
H
H
H
H
Data Input
X
Data Output
H
X
During Read(Busy)
X
H
During Program(Busy)
X
(1)
X
WE
Read Mode
Write Mode
Command Input
Address Input(5clock)
Command Input
Address Input(5clock)
X
X
X
H
During Erase(Busy)
X
X
X
L
Write Protect
H
X
X
0V/VCC(2)
Stand-by
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
2.8 Program/Erase Characteristics
Symbol
Min
Typ
Max
Unit
Program Time
Parameter
tPROG
-
1.3
5
ms
Dummy Busy Time for Two-Plane Program
tDBSY
-
0.5
1
μs
Dummy Busy Time for Cache Program
tCBSY(4)
-
-
5
ms
Dummy Busy Time for Intelligent Copy-Back Program
tCBSY2(4)
-
-
500
μs
Number of Partial Program Cycles in the Same Page
Block Erase Time
Nop
-
-
1
cycle
tBERS
-
1.5
10
ms
NOTE :
1) Typical program time is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2) Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.
3) Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the page group A and B.
Page Group A: Page 0, 1, 3, 5, 7, 9, 11, ... ,115, 117, 119, 121, 123, 125
Page Group B: Page 2, 4, 6, 8, 10, 12, ... , 118, 120, 122, 124, 126, 127
4) tCBSY and tCBSY2 depend on the timing between internal programming time and data in time.
- 18 -
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
datasheet
FLASH MEMORY
2.9 AC Timing Characteristics for Command / Address / Data Input
Symbol
Min
Max
Unit
CLE Setup Time
Parameter
tCLS(1)
12
-
ns
CLE Hold Time
tCLH
5
-
ns
CE Setup Time
tCS(1)
20
-
ns
CE Hold Time
tCH
5
-
ns
WE Pulse Width
tWP
12
-
ns
ALE Setup Time
tALS(1)
12
-
ns
ALE Hold Time
tALH
5
-
ns
Data Setup Time
tDS(1)
12
-
ns
Data Hold Time
tDH
5
-
ns
Write Cycle Time
tWC
25
-
ns
WE High Hold Time
tWH
10
-
ns
tADL(2)
300
-
ns
Address to Data Loading Time
NOTE :
1) The transition of the corresponding control pins must occur only once while WE is held low.
2) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
2.10 AC Characteristics for Operation
Symbol
Min
Max
Unit
ALE to RE Delay
Parameter
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
tCWAW
300
-
ns
tRR
20
-
ns
Command Write cycle to Address Write cycle Time for Random data
input
Ready to RE Low
RE Pulse Width
tRP
12
-
ns
WE High to Busy
tWB
-
100
ns
WP High/Low to WE Low
tWW
100
-
ns
Read Cycle Time
tRC
25
-
ns
RE Access Time
tREA
-
20
ns
CE Access Time
tCEA
-
25
ns
RE High to Output Hi-Z
tRHZ
-
100
ns
CE High to Output Hi-Z
tCHZ
-
30
ns
CE High to ALE or CLE Don’t Care
tCSD
0
-
ns
RE High to Output Hold
tRHOH
15
-
ns
RE Low to Output Hold
tRLOH
5
-
ns
tREH
10
-
ns
RE High Hold Time
Output Hi-Z to RE Low
RE High to WE Low
tIR
0
-
ns
tRHW
100
-
ns
WE High to RE Low
tWHR
120
-
ns
WE High to RE Low for Random data out
tWHR2
300
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
10/30/100(1)
μs
Busy time for Set Feature and Get Feature
tFEAT
-
1
μs
Cache Busy in Read Cache (following 31h and 3Fh)
tDCBSYR
-
90
Dummy Busy Time for Intelligent Copy-Back Read
tDCBSYR2
-
5
NOTE :
1) If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 10μs.
2) 90us is applied for the average maximum value.
- 19 -
(2)
μs
ms
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
3.0 NAND Flash Technical Notes
3.1 Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information
regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices
with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it
is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via
address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3.2 Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s)
status is defined by the 1st byte in the spare area. Samsung makes sure that the first or the last page of every initial invalid block has non-FFh data at the
column address of 0 or 8,192.The initial invalid block information is also erasable in most cases, and it is impossible to recover the information once it has
been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial
invalid block table via the following suggested flow chart. Any intentional erasure of the initial invalid block information is prohibited.
Start
Block No = 1
Read FFh Check
Column 0 or 8192
of the First page
Block No. = Block No. + 1
Fail
Pass
Read FFh Check
Column 0 or 8192
of the last page
Pass
Fail
Entry Bad Block 1)
No
Last Block
Yes
End
Flow chart to create initial invalid block table.
NOTE:
1) No erase operation is allowed to detected bad blocks.
- 20 -
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
FLASH MEMORY
3.3 Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement
should be done upon erase or program error.
Failure Mode
Write
Read
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Up to 40 Bit Failure
Verify ECC -> ECC Correction
Note) Users are required to employ randomizer function in the NAND controller to meet target endurance of the device.
ECC
: Error Correcting Code --> RS Code or BCH Code etc.
Example) 40 bit correction / (1K+80) byte
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
- 21 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
*
Erase Error
No
Verify ECC
Reclaim the Error
Yes
Yes
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
1
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
2
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
- 22 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
3.4 Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of
the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed.
Therefore, LSB doesn’t need to be page 0.
Paired page in ’Group A’ must has been programmed before page in ’Group B’ program execution.
Page 127
(128)
Page 127
(128)
:
:
(32)
Page 31
(1)
Page 31
:
:
Page 2
Page 1
Page 0
(3)
(2)
(1)
Page 2
Page 1
Page 0
Data register
Data register
From the LSB page to MSB page
DATA IN: Data (1)
(3)
(32)
(2)
e.g.) Random page program (Prohibition)
DATA IN: Data (1)
Data (128)
- 23 -
Data (128)
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
FLASH MEMORY
Paired Page Address Information
Paired Page Address(1/2)
Paired Page Address(2/2)
Group A
Group B
Group A
Group B
00h
02h
3Fh
42h
01h
04h
41h
44h
03h
06h
43h
46h
05h
08h
45h
48h
07h
0Ah
47h
4Ah
09h
0Ch
49h
4Ch
0Bh
0Eh
4Bh
4Eh
0Dh
10h
4Dh
50h
0Fh
12h
4Fh
52h
11h
14h
51h
54h
13h
16h
53h
56h
15h
18h
55h
58h
17h
1Ah
57h
5Ah
19h
1Ch
59h
5Ch
1Bh
1Eh
5Bh
5Eh
1Dh
20h
5Dh
60h
1Fh
22h
5Fh
62h
21h
24h
61h
64h
23h
26h
63h
66h
25h
28h
65h
68h
27h
2Ah
67h
6Ah
29h
2Ch
69h
6Ch
2Bh
2Eh
6Bh
6Eh
2Dh
30h
6Dh
70h
2Fh
32h
6Fh
72h
31h
34h
71h
74h
33h
36h
73h
76h
35h
38h
75h
78h
37h
3Ah
77h
7Ah
39h
3Ch
79h
7Ch
3Bh
3Eh
7Bh
7Eh
3Dh
40h
7Dh
7Fh
NOTE :
When program operation is abnormally aborted (e.g. power-down, reset), not only page data under program but also paired page data may be damaged.
- 24 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
3.5 System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 8,832byte data registers are
utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle
time on the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.
≈
≈
CLE
≈
Program Operation with CE don’t-care
I/Ox
≈
ALE
80h
Address(5Cycles)
tCS
≈
≈≈
WE
≈ ≈
≈
CE
≈ ≈
CE don’t-care
Data Input
tCH
Data Input
10h
tCEA
CE
CE
tREA
tWP
RE
WE
I/O0~7
out
≈
CLE
≈
Read Operation with CE don’t-care
CE don’t-care
≈
ALE
tR
≈
R/B
≈≈
≈ ≈ ≈
RE
≈
WE
I/Ox
≈ ≈
CE
00h
Address(5Cycle)
Data Output(serial access)
30h
- 25 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.0 TIMING DIAGRAMS
4.1 Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
I/Ox
Command
4.2 Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE
tWP
tWP
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALS
tALH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
ALE
tDS
I/Ox
tDH
Col. Add1
tDS
tDH
Col. Add2
- 26 -
tDS
tDH
Row Add1
tDS
tDH
Row Add2
tDS
tDH
Row Add3
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.3 Input Data Latch Cycle
tCLH
≈
CLE
tCH
≈
CE
tWC
≈
ALE
tWP
≈
tALS
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/Ox
DIN final
DIN 1
≈
DIN 0
4.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tCHZ
tREH
≈
tREA
tREA
tREA
RE
tRHZ
tRHZ
I/Ox
Dout
Dout
≈
tRHOH
≈
tRR
R/B
NOTE :
1) Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2) tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
- 27 -
Dout
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.5 Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
≈
CE
tRC
tCHZ
tREH
≈
tRP
RE
tREA
tRHOH
tRLOH
≈
tCEA
I/Ox
tRHZ
tREA
Dout
≈
Dout
≈
tRR
R/B
NOTE :
1) Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2) tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
4.6 Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tWHR
RE
tDS
I/Ox
tDH
tIR
70h/F1h
tREA
tRHZ
tRHOH
Status Output
- 28 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.7 Read Operation
tCLR
CLE
CE
tWC
WE
tWB
tAR
ALE
tR
tRHZ
tRC
≈
RE
I/Ox
00h
Col. Add1
Col. Add2
Row Add1
Column Address
Row Add2 Row Add3
30h
Dout N
Dout N+1
≈ ≈
tRR
Dout M
Row Address
Busy
R/B
4.8 Read Operation(Intercepted by CE)
tCLR
CLE
CE
tCSD
WE
tCHZ
tWB
tAR
ALE
tRC
tR
RE
tRR
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
Dout N
30h
Row Address
Busy
R/B
- 29 -
Dout N+1
Dout N+2
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.9 Random Data Output In a Page
CLE
CE
WE
tWB
tRHW
tAR
ALE
tR
tRC
RE
tRR
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
30h/35h
Dout N
Busy
CLE
tCLR
CE
WE
tRHW
tWHR2
ALE
tREA
RE
I/Ox
05h
Col. Add1
05h
Col. Add1
Column Address
R/B
Dout N+1
Dout N+1
Row Address
Col. Add2
E0h
Dout M
Column Address
R/B
1
- 30 -
Dout M+1
1
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.10 Cache Read Operation
CLE
CE
tWC
WE
ALE
tDCBSYR tRC
≈
tR
RE
tWB
tWB
≈
tRR
I/Ox
00h
Col. Add2 Row Add1 Row Add2 Row Add3 30h
Col. Add1
31h
D0
D1
D0UT
31h
Page Address M
Col. Add. 0
R/B
1
CLE
CE
WE
ALE
tDCBSYR tRC
tDCBSYR tRC
tWB
tWB
tRR
31h
D0
D1
≈
tRR
≈
tRR
I/Ox
≈
tWB
D0UT
31h
Page Address M+2
Col. Add. 0
D0
D1
≈
RE
≈
≈
tDCBSYR tRC
D0UT
Page Address M+3
Col. Add. 0
R/B
1
NOTE :
1) The column address will be reset to 0 by the 31h and 3Fh command input.
2) Cache Read operation is available only within a block.
- 31 -
3Fh
D0
D1
Page Address M+4
Col. Add. 0
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.11 Two-Plane Page Read Operation with Two-Plane Random Data Out
CLE
CE
tW
tWC
tW
tWC
WE
tWB
ALE
tR
RE
I/Ox
60h
60h
Row Add1 Row Add2 Row Add3
Row Address
30h
Row Address
page address : Page M
plane address: Fixed ’Low’
block address : Block N
R/B
Row Add1 Row Add2 Row Add3
page address : Page M
plane address: Fixed ’High’
block address : Block N
Busy
1
CLE
tCLR
CE
tW
tWC
WE
tWHR2
ALE
tREA
tRC
RE
I/Ox
00h
05h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address Row Address
column address
R/B
:
Col. Add1 Col. Add2
Dout
N
E0h
Column Address
Valid
column address
:
Valid
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’Low’
block address : Block N
1
2
CLE
tCLR
tCLR
CE
tW
tWC
WE
ALE
tWHR2
tWHR2
tREA
tREA
tRHW
tRC
tRC
RE
I/Ox
E0h
Dout
N
Dout
N+1
R/B
2
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
05h
Col. Add1 Col. Add2
E0h
Column Address Row Address
Column Address
column address: Fixed ’Low’
page address Page M
plane address : Fixed ’High’
block address : Block N
column address
- 32 -
Dout
N+1
:
Valid
Dout
M
Dout
M+1
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.12 Two-Plane Cache Read Operation with Two-Plane Random Data Out (1/2)
CLE
CE
tW
tWC
tW
tWC
WE
tWB
ALE
tR
RE
I/Ox
60h
60h
Row Add1 Row Add2 Row Add3
Row Address
33h
Row Address
page address : Page M
plane address: Fixed ’Low’
block address : Block N
R/B
Row Add1 Row Add2 Row Add3
page address : Page M
plane address: Fixed ’High’
block address : Block N
Busy
1
CLE
tCLR
CE
tW
tWC
WE
tWHR2
tDCBSYR
tREA
ALE
tRC
RE
tWB
I/Ox
31h
00h
R/B
05h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Col. Add1 Col. Add2
E0h
Column Address Row Address
Column Address
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’Low’
block address : Block N
column address
:
Dout
N
Dout
N+1
Valid
2
1
Max. 127 times repeatable
CLE
tCLR
CE
tW
tWC
tW
tWC
WE
tWHR2
tDCBSYR
tREA
ALE
tRC
RE
I/Ox
tWB
Dout
N+1
R/B
2
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
05h
Col. Add1 Col. Add2
E0h
Column Address Row Address
Column Address
column address: Fixed ’Low’
page address Page M
plane address : Fixed ’High’
block address : Block N
column address
Dout
M
Dout
M+1
3Fh
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address Row Address
:
Valid
Max. 127 times repeatable
- 33 -
column address : Fixed ’Low’
page address : Page M+n
plane address : Fixed ’Low’
block address : Block N
3
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.13 Two-Plane Cache Read Operation with Two-Plane Random Data Out (2/2)
CLE
tCLR
tCLR
CE
tW
tWC
WE
tWHR2
tWHR2
tREA
ALE
tREA
tRC
tRC
RE
I/Ox
05h
Col. Add1 Col. Add2
Dout
N
E0h
Dout
N+1
00h
Column Address
column address
:
Valid
R/B
3
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
05h
Col. Add1 Col. Add2
Dout
M
E0h
Column Address Row Address
Column Address
column address: Fixed ’Low’
page address Page M+n
plane address : Fixed ’High’
block address : Block N
column address
:
Dout
M+1
Valid
NOTE :
1) The column address will be reset to 0 by the 3Fh command input.
2) Cache Read operation is available only within a block.
3) Make sure to terminate the operation with 3Fh command. If the operation is terminated by 31h command, monitor I/O 6 (Ready/Busy) by issuing Status Read Command
(70h) and make sure the previous page read operation is completed. If the page read operation is completed, issue FFh reset before next operation.
4.14 Page Program Operation
CLE
CE
tWC
≈
tWC
tWC
WE
tWB
tADL
tPROG
tWHR
ALE
I/Ox
80h
Co.l Add1 Col. Add2
Serial Data
Column Address
Input Command
Row Add1
Row Add2 Row Add3
Row Address
≈ ≈
RE
Din
Din
N
M
1 up to m Byte
Serial Input
70h
Program
Command
NOTE :
tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 34 -
I/O0
Read Status
Command
≈
R/B
10h
I/O0=0 Successful Program
I/O0=1 Error in Program
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.15 Page Program Operation with Random Data Input
CLE
CE
tCWAW
tWC
≈
tWC
WE
tADL
tADL
ALE
80h
I/Ox
Col. Add1
Col. Add2
Row Add1
Serial Data
Column Address
Input Command
Din
N
Row Add2 Row Add3
≈ ≈
RE
Din
M
85h
Col. Add2
Col. Add1
Serial Input Random Data Column Address
Input Command
Row Address
R/B
1
CLE
CE
tCWAW
≈
WE
tADL
tWB
tPROG
tWHR
ALE
M
85h
Col. Add2
Col. Add1
Random Data Column Address
Input Command
R/B
Din
J
Din
K
Serial Input
10h
70h
Program
Command
1
NOTE :
1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 35 -
I/O0
Read Status
Command
≈
I/Ox
≈ ≈
RE
I/O0=0 Successful Program
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.16 Copy-Back Program Operation with Random Data Input
CLE
CE
tWC
WE
tWB
ALE
tRC
tR
I/Ox
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address
Data 1
35h
≈ ≈
RE
Data N
85h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address
Row Address
Row Address
≈
R/B
1
Busy
Copy-Back Data
Input Command
CLE
CE
tWHR
WE
tPROG
tWB
ALE
RE
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address
Row Address
Data N
70h
10h
I/Ox
Read Status Command
≈
R/B
Data 1
≈ ≈
I/Ox
tADL
Busy
1
I/O0=0 Successful Program
I/O0=1 Error in Program
NOTE :
1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
- 36 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.17 Intelligent Copy-Back Program(1/2)
CLE
CE
tWC
WE
tWB
ALE
tR
tRC
I/Ox
00h
00h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address
Data 1
30h
≈ ≈
RE
00h
Data N
Column Address
Row Address
≈
R/B
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Busy
Data out
3Ah
Row Address
Intelligent Copy-Back Read
Input Command
1
CLE
CE
tWC
tWB
≈
WE
ALE
tCBSY2
tRC
≈
RE
Column Address
Data N 15h
Data 1
Data N
00h
Col. Add1 Col. Add2
Column Address
Row Address
≈
R/B
Data 1
≈ ≈
8Ch Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
≈
I/Ox
≈ ≈
tDCBSYR2
Busy
Busy
1
Data out
2
- 37 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Intelligent Copy-Back Program(2/2)
CLE
CE
tWC
tWB
≈
WE
ALE
tCBSY2
RE
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3 Data
3Ah 1
Column Address
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
8Ch
Row Address
Column Address
Data 1
≈ ≈
tDCBSYR2
Data N 15h
Row Address
≈
2
≈
R/B
Busy
Busy
CLE
CE
≈
tWC
WE
ALE
tWB
tRC
≈
RE
Data N
8Ch
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Column Address
R/B
3
Data 1
≈ ≈
Data 1
I/Ox
≈ ≈
tPROG
Row Address
Data out
- 38 -
Data N 10h
3
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.18 Cache Program Operation(available only within a block)
CLE
CE
≈
≈
tWC
WE
tCBSY
tWB
ALE
tADL
RE
Din
N
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
I/Ox
Serial Data Column Address
Input Command
Row Address
≈ ≈
tADL
Din
M
Serial Input
80h
15h
Program
Command
(Dummy)
≈
R/B
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
Max. 127 times repeatable
Last Page Input & Program
Din
N
1
CLE
CE
WE
tWB tPROG*2
ALE
Din
N
I/Ox
≈ ≈
RE
Din
10h
M
Program Confirm
Command
(True)
70h
I/O
R/B
≈
1
NOTE :
1) tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
2) Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data
has not finished,
the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the ( last -1)th page - (command input cycle time + address input cycle time + Last page data loading time)
Maximum tPROG is 10ms in this case.
e.g.) Cache Program
tCBSY
R/B
I/Ox
Address &
15h
Data Input
Col. Add1,2 & Row Add1,2
Data
80h
tCBSY
80h
Address &
Data Input
15h
tPROG*2
tCBSY
80h
- 39 -
Address &
Data Input
15h
80h
Address &
Data Input
10h
70h
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.19 Two-Plane Copy-Back Program
CLE
CE
tWC
tWC
WE
tR
tWB
ALE
RE
Row Add1 Row Add2 Row Add2
60h
I/Ox
Row Address
Row Address
Plane Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
35h
Column Address
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘Low‘
≈
R/B
Row Add1 Row Add2 Row Add2
60h
00h Col. Add1 Col. Add2
E0h
Dout
Column Address
Column Address : Valid
1
CLE
CE
tWC
tWC
WE
tDBSY
tWB
I/Ox
Dout
Dout
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
R/B
00h Col. Add1 Col. Add2
Row Address
≈
≈ ≈
RE
≈ ≈≈
ALE
E0h
Dout
Column Address
Column Address : Valid
85h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
11h
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘Low‘
2
1
CLE
CE
tWC
WE
tDBSY
tPROG
tWB
tWB
ALE
RE
I/Ox
Dout
Row Add1 Row Add2 Row. Add3
11h
81h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
R/B
2
10h
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
- 40 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.20 Two-Plane Intelligent Copy-Back Program(1/3)
CLE
CE
tWC
tWC
WE
tR
tWB
ALE
RE
60h
I/Ox
60h
Row Add1 Row Add2 Row Add2
Row Address
Row Address
Plane Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
30h
Column Address
05h Col. Add1 Col. Add2
Row Address
Column Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘Low‘
≈
R/B
Row Add1 Row Add2 Row Add2
Column Address : Valid
1
CLE
CE
tWC
WE
E0h
Dout
Dout
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
R/B
05h Col. Add1 Col. Add2
Dout
E0h
≈ ≈
I/Ox
≈
≈ ≈
RE
≈
ALE
Dout
60h
Column Address
Column Address : Valid
1
2
CLE
CE
tWC
tWC
≈
WE
tDBSY
tDCBSYR2
tWB
tWB
ALE
60h
Row Add1 Row Add2 Row Add2
8Ch Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
3Ah
Row Address
Plane Address : Fixed ‘High‘
≈
R/B
Column Address
Plane Address : Fixed ‘Low‘
2
Din
Din
8Ch Col. Add1 Col. Add2
11h
Row Address
Column Address
≈
I/Ox
≈ ≈
RE
3
- 41 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Two-Plane Intelligent Copy-Back Program(2/3)
CLE
CE
tWC
tWC
≈
WE
tCBSY2
tWB
ALE
Col. Add2 Row Add1 Row Add2 Row. Add3
I/Ox
Din
≈ ≈
RE
Din
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
15h
Row Address
Plane Address : Fixed ‘High‘
Row Address
E0h
Column Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘Low‘
≈
R/B
Column Address
05h Col. Add1 Col. Add2
Column Address : Valid
3
4
CLE
CE
tWC
tWC
WE
I/Ox
Dout
Dout
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
R/B
05h Col. Add1 Col. Add2
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
E0h
Dout
Column Address
≈ ≈≈
RE
≈ ≈≈
ALE
Row Add1 Row Add2 Row Add2
60h
Dout
60h
Row Address
Column Address : Valid
Plane Address : Fixed ‘Low‘
4
5
CLE
CE
tWC
≈
WE
tDCBSYR2
tWB
tDBSY
tWB
ALE
I/Ox
Row Add1 Row Add2 Row Add2
8Ch Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
3Ah
Column Address
Row Address
Din
≈ ≈
RE
Din
8Ch Col. Add1 Col. Add2 Row Add1
11h
Column Address
Row Address
R/B
Plane Address : Fixed ‘Low‘
5
Plane Address : Fixed ‘High‘
≈
≈
Plane Address : Fixed ‘High‘
6
- 42 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Two-Plane Intelligent Copy-Back Program(3/3)
CLE
CE
tWC
≈
WE
tCBSY2
tWB
I/Ox
Row Add1 Row Add2 Row. Add3
Din
≈ ≈
RE
Din
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
15h
Column Address
Row Address
R/B
05h Col. Add1 Col. Add2
Row Address
Dout
Column Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘Low‘
≈
E0h
≈ ≈≈
ALE
Dout
Column Address : Valid
6
7
CLE
CE
tWC
≈
WE
00h Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
I/Ox
Column Address
Row Address
Column Address : Fixed ‘Low‘
Plane Address : Fixed ‘High‘
R/B
05h Col. Add1 Col. Add2
E0h
Dout
Column Address
Dout
8Ch Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
Column Address : Valid
Din
≈ ≈
RE
≈ ≈≈
ALE
Din
11h
Row Address
Plane Address : Fixed ‘Low‘
8
7
CLE
CE
tWC
≈
WE
tDBSY
tWB
tWB
tPROG
ALE
11h
8Ch Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
≈
R/B
Din
Din
10h
Row Address
Plane Address : Fixed ‘High‘
≈
I/Ox
≈ ≈
RE
8
- 43 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.21 Two-Plane Page Program Operation
CLE
CE
≈
tWC
WE
tDBSY
tWB
ALE
I/Ox
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
80h
Serial Data Column Address
Input Command
Page Row Address
≈ ≈
RE
Din
N
Din
M
11h
Program
1 up to 8,832 Byte Command
(Dummy)
Data Serial Input
81h
≈
R/B
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3
tDBSY :
typ. 500ns
max. 1μs
1
CLE
≈
CE
WE
tWB
tPROG
tWHR
ALE
I/Ox
Din
N
Row Add3
≈ ≈
RE
Din
M
10h
70h/F1h
Program Confirm
Command
(True)
I/O
Read Status Command
≈
R/B
I/O0=0 Successful Program
I/O0=1 Error in Program
1
e.g.) Two-Plane Page Program
I/O0~7
tPROG
tDBSY
R/B
80h
Address & Data Input
Col. Add1,2 & Row Add 1,2,3
8,832 Byte Data
11h
81h
NOTE
Address & Data Input
10h
Col. Add1,2 & Row Add 1,2,3
8,832 Byte Data
column address : Valid
page address : Page M
plane address: Fixed ’High’
block address : Block N
column address : Valid
page address : Page M
plane address : Fixed ’Low’
block address : Block N
NOTE :
Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
- 44 -
70h/F1h
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.22 Two-Plane Cache Program Operation
≈
CLE
≈
CE
tADL
tADL
tWC
≈
tWC
WE
tDBSY
tWB
≈
≈
ALE
I/Ox
80h
DIN
0
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add2
DIN
8831
81h
11h
Row Address
DIN
0
Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
Column Address
Row Address
≈
Column Address
DIN
1
≈ ≈
RE
R/B
1
≈
≈
CE
≈
≈
CLE
tADL
≈
≈
tWC
WE
tDBSY
tCBSY
tWB
≈
≈
≈
≈
ALE
tWB
DIN
1
DIN
8831
15h
80h Col. Add1
80h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add2
program
Command
(Cache)
Column Address
DIN
0
DIN
1
≈ ≈
DIN
0
DIN
8831
11h
81h
Row Address
≈
≈
I/Ox
≈ ≈
RE
R/B
1
2
≈
CLE
≈
CE
tADL
≈
tWC
WE
tPROG*
tWB
RE
I/Ox
81h
Col. Add1 Col. Add2 Row Add1 Row Add2 Row. Add3
DIN
1
Row Address
≈
Column Address
DIN
0
≈ ≈
≈
≈
ALE
R/B
DIN
8831
10h
program
Confirm
Command
(True)
2
NOTE :
1) tPROG = Program time for the last page + Program time for the ( last -1)th page - (command input cycle time + address input cycle time + Last page data loading time)
2) Make sure to terminate the operation with 80h-10h- command sequence. If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready/Busy) by issuing Status Read Command (70h) and make sure the previous page program operation is completed. If the page program operation is completed issue FFh reset before next
operation.
- 45 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.23 Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
tWHR
ALE
RE
I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Row Address
Read Status
Command
- 46 -
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.24 Two-Plane Block Erase Operation
CLE
CE
tWC
tWC
WE
ALE
RE
I/OX
60h
60h
Row Add1 Row Add2 RowD0h
Add3
Row Add1 Row Add2 Row Add3
Row Address
D0h
Row Address
R/B
Block Erase Setup Command1
Block Erase Setup Command2
Erase Confirm Command
1
CLE
CE
WE
tWB
tWHR
tBERS
ALE
RE
70h/F1h
D0h
I/OX
I/O 0
Busy
R/B
I/O 0 = 0 Successful Erase
I/O 0 = 1 Error in Erase
Erase Confirm Command
1
Read Status Command
e.g.) Address Restriction for Two-Plane Block Erase Operation
R/B
I/O0~7
tBERS
60h
Address
Row Add1,2,3
Page Address : Fixed ’Low’
Plane Address : Fixed ’Low’
Block Address : Block N
60h
D0h
A9Address
~ A25
D0h
Row Add1,2,3
Page Address : Fixed ’Low’
Plane Address : Fixed ’High’
Block Address : Block N
- 47 -
70h/F1h
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.25 Read ID Operation
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox
90h
Read ID Command
00h/40h
Address 1cycle
ECh
Device
Code
3rd cyc.
4th cyc.
5th cyc.
6th cyc.
Maker Code Device Code
NOTE :
1) Address 00h is for Samsung legacy and 40h is for new JEDEC ID information.
4.26 00h Address ID Cycle
Device
1st Cycle
Dvice Code(2nd)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
ECh
D7h
94h
76h
64h
43h
1st Cycle
Dvice Code(2nd)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
4Ah
45h
44h
45h
43h
01h
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
4.27 40h Address ID Cycle
Device
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
- 48 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
4.27.1 ID Definition Table
Description
st
1 Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
6th Byte
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc.
Page Size, Block Size, Redundant Area Size.
Plane Number, ECC Level, Organization.
Device Technology, EDO, Interface.
3rd ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
0
0
1
1
Internal Chip Number
1
2
4
8
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Number of
Simultaneously
Programmed Pages
1
2
4
8
Interleave Program
Between multiple chips
Not Support
Support
Cache Program
Not Support
Support
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4th ID Data
Description
Page Size
(w/o redundant area )
2KB
4KB
8KB
Reserved
Block Size
(w/o redundant area )
128KB
256KB
512KB
1MB
Reserved
Reserved
Reserved
Reserved
Redundant Area Size
( byte / Page Size)
Reserved
128B
218B
400B
436B
640B
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
- 49 -
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5th ID Data
Description
I/O7
I/O6
I/O5
I/O4
I/O3 I/O2
0
0
1
1
Plane Number
1
2
4
8
ECC Level
1bit / 512B
2bit / 512B
4bit / 512B
8bit / 512B
16bit / 512B
24bit / 1KB
40bit/ 1KB
Reserved
0
0
0
0
1
1
1
1
Reserved
0
0
1
1
0
0
1
1
I/O1
I/O0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
6th ID Data
Description
Device Version
50nm
40nm
30nm
20nm
Reserved
Reserved
Reserved
Reserved
EDO
Not Support
Support
Interface
Conventional
Toggle mode
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
Reserved
0
0
0
40h Address ID Definition Table
Byte
Description
IDQ7
0
DQ6
DQ4
DQ3
DQ2
DQ1
DQ0
0
0
1
0
1
0
J
1
E
0
1
0
0
0
1
0
1
2
D
0
1
0
0
0
1
0
0
3
E
0
1
0
0
0
1
0
1
4
C
0
1
0
0
0
0
1
1
5
Legacy Asynchronous SDR
Toggle Mode DDR
Synchronous DDR
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
- 50 -
1
DQ5
0
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
5.0 DEVICE OPERATION
5.1 Page Read
Page read is initiated by writing 00h-30h to the command register along with five address cycles. The 8,832 bytes of data within the selected page are
transferred to the cache registers via data registers in less than tR. The system controller can detect the completion of this data transfer(tR) by analyzing
the output of R/B pin. Once the data in a page is loaded into the cache registers, they may be read out in Read cycle time(tRC) by sequentially pulsing
RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column
address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address
of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated
multiple times regardless of how many times it is done in a page.
Read Operation
≈
CLE
≈
CE
≈≈
WE
≈
ALE
RE
I/Ox
tR
≈
R/B
00h
Address(5Cycle)
Data Output(Serial Access)
30h
Col. Add.1,2 & Row Add.1,2,3
Data Field
Spare Field
- 51 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Random Data Output In a Page
tR
R/B
RE
I/Ox
00h
Address
5Cycles
Data Output
30h/35h
Col. Add.1,2 & Row Add.1,2,3
05h
Address
2Cycles
E0h
Data Output
Col. Add.1,2
Data Field
Spare Field
Data Field
Spare Field
5.2 Cache Read
Cache Read is an extension of Page Read, which is executed with 8,832byte data registers, and is available only within a block. Since the device has 1
page of cache memory, serial data output may be executed while data in the memory cell is read into data registers.
Cache read is also initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched.
Therefore only five address cycles and 30h command initiates that operation after initial power up. The 8,832 bytes of data within the selected page are
transferred to the cache registers via data registers in less than tR. After issuing Cache Read command(31h), read data in the data registers is transferred
to cache registers for a short period of time(tDCBSYR). While the data in the cache registers is read out in Read cycle time(tRC) by sequentially pulsing RE,
data of next page is transferred to the data registers. By issuing Last Cache Read command(3Fh), last data is transferred to the cache registers from the
data registers after the completion of transfer from memory cell to data registers.
- 52 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Cache Read
The device has a Read operation with cache registers that enables the high speed read operation shown below. When the block address changes, this
sequence has to be started from the beginning.
CLE
CE
WE
ALE
RE
00h
I/Ox
30h
Column
Address
Page Row
Address
1
3
2
31h
0
1
Column 0
tDCBSYR
tR
2
3
4
8831 31h
Page Address N
0
1
2
3
8831
Page Address N+1
tDCBSYR
R/B
1
CLE
CE
WE
ALE
RE
5
I/Ox
0
1
2
3
8831 3Fh
6
7
0
1
2
3
8831
Page Address N+2
tDCBSYR
R/B
1
3
Cache register
1
2
Data register
Page N
1
Page N
30h
5
Page N 4
Page N+1
3
Page N+1
7
Page N+1 6
Page N+2
Page N+2
5
Page N+2
31h & RE clock
31h & RE clock
3Fh & RE clock
NOTE :
-. If the 31h command is issued to the device, the data content of the next page is transferred to the data registers during serial data out from the cache registers, and therefore
the tR (Data transfer from memory cell to data register) will be reduced.
1) Normal read. Data is transferred from Page N to cache registers through data registers. During this time period, the device outputs Busy state for tR max.
2) After the Ready/Busy returns to Ready, 31h command is issued and data is transferred to cache registers from data registers again. This data transfer takes tDCBSYR max
and the completion of this time period can be detected by Ready/Busy signal.
3) Data of Page N+1 is transferred to data registers from cell while the data of Page N in cache registers can be read out by RE clock simultaneously.
4) The 31h command makes data of Page N+1 transfer to cache registers from data registers after the completion of the transfer from cell to data registers. The device outputs
Busy state for tDCBSYR max..This Busy period depends on the combination of the internal data transfer time from cell to data registers and the serial data out time.
5) Data of Page N+2 is transferred to data registers from cell while the data of Page N+1 in cache registers can be read out by RE clock simultaneously.
6) The 3Fh command makes the data of Page N+2 transfer to the cache registers from the data registers after the completion of transfer from cell to data registers. The device
outputs Busy state for tDCBSYR max.This Busy period depends on the combination of the internal data transfer time from cell to data registers and the transfer from data
registers to cache registers.
7) Data of Page N+2 in cache registers can be read out, but since the 3Fh command does not transfer the data from the memory cell to data registers, the device can accept
new command input immediately after the completion of serial data out.
- 53 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.3 Two-plane Page Read
Two-Plane Page Read is an extension of Page Read, for a single plane with 8,832 byte data registers. Since the device is equipped with two memory
planes, activating the two sets of 8,832 byte data registers enables a random read of two pages. Two-Plane Page Read is initiated by repeating command
60h followed by three address cycles twice. In this case, only same page of same block can be selected from each plane.
After Read Confirm command(30h) the 17,664 bytes of data within the selected two page are transferred to the cache registers via data registers in less
than tR. The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin.
Once the data is loaded into the cache registers, the data output of first plane can be read out by issuing command 00h with Five Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command sequences. Two-Plane
Page Read must be used in the block which has been programmed with Two-Plane Page Program.
Two-Plane Page Read Operation with Two-Plane Random Data Out
tR
R/B
I/OX
60h
Address (3 Cycle)
60h
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
Address (3 Cycle)
30h
Row Add.1,2,3
page address : Page M
plane address: Fixed ’High’
block address : Block N
1
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
column address : Fixed ’Low’
page address : Page M
plane address: Fixed ’Low’
block address : Block N
1
E0h
Address (2 Cycle)
Data Output
Col. Add.1,2
column address
:
Valid
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
2
column address : Fixed ’Low’
page address : Page M
plane address: Fixed ’High’
block address : Block N
E0h
Address (2 Cycle)
Col. Add.1,2
column address
- 54 -
:
Valid
Data Output
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.4 Two-plane Cache Read
Two-Plane Cache Read is an extension of Cache Read, for a single plane with 8,832 byte data registers. Since the device is equipped with two memory
planes, activating the two sets of 8,832 byte data registers enables a cache read of two pages. Two-Plane Cache Read is initiated by repeating command
60h followed by three address cycles twice. In this case only same page of same block can be selected from each plane.
After Read Confirm command(33h) the 17,664 bytes of data within the selected two page are transferred to the cache registers via data registers in less
than tR. After issuing Cache Read command(31h), read data in the data registers is transferred to cache registers for a short period of time(tDCBSYR).
Once the data is loaded into the cache registers from data registers, the data output of first plane can be read out by issuing command 00h with Five
Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the identical command
sequences. The detail sequence of Two-Plane Cache Read is shown below.
Two-Plane Cache Read Operation with Two-Plane Random Data Out
tR
R/B
I/OX
60h
60h
Address (3 Cycle)
Row Add.1,2,3
33h
Address (3 Cycle)
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address : Block N
1
tDCBSYR
R/B
I/Ox
31h
00h
Address (5 Cycle)
E0h
Address (2 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
Data Output
Col. Add.1,2
column address : Fixed ’Low’
page address : Page M
plane address: Fixed ’Low’
block address : Block N
column address
Valid
:
Max. 127 repeatable
1
2
R/B
I/Ox
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Data Output
Col. Add.1,2
column address : Fixed ’Low’
page address : Page M
plane address: Fixed ’High’
block address : Block N
2
E0h
Address (2 Cycle)
05h
column address
:
Valid
Max. 127 repeatable
3
tDCBSYR
R/B
I/Ox
3Fh
00h
Address (5 Cycle)
Col. Add. 1,2 & Row Add.1,2,3
Data Output
Col. Add.1,2
column address : Fixed ’Low’
page address : Page M + N
plane address: Fixed ’Low’
block address : Block N
3
E0h
Address (2 Cycle)
05h
column address
:
Valid
4
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
4
column address : Fixed ’Low’
page address : Page M + N
plane address: Fixed ’High’
block address : Block N
E0h
Address (2 Cycle)
Col. Add.1,2
column address
- 55 -
:
Valid
Data Output
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.5 Page Program
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the same page without
an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential order in a block. A page program cycle
consists of a serial data loading period in which up to 8,832bytes of data may be loaded into the data registers via cache registers, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data
loading. The words other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address
for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be
operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate
the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby
freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only
the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/
O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains
in Read Status command mode until another valid command is written to the command register.
Program & Read Status Operation
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
10h
Pass
I/O0
70h
Col. Add.1,2 & Row Add.1,2,3
"1"
Data
Fail
Random Data Input In a Page
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
Col. Add.1,2 & Row Add1,2,3
Data
85h
Address & Data Input
Col. Add.1,2
Data
10h
70h
I/O0
"1"
Fail
- 56 -
Pass
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.6 Copy-back Program
Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit
error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a
sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the
address of the source page moves the whole 8,832byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In
the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy DataInput command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the
program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the
Write Status Bit(I/O 0) may be checked. The command register remains in Read Status command mode until another valid command is written to the
command register.
During copy-back program, data modification is possible using random data input command (85h) as shown below.
Page Copy-Back Program Operation
tR
tPROG
≈
R/B
Add.(5Cycles)
00h
Data Output
35h
≈
I/Ox
Col. Add.1,2 & Row Add.1,2,3
Source Address
85h
Add.(5Cycles)
10h
70h
"0"
I/O0
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Pass
"1"
Fail
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
Page Copy-Back Program Operation with Random Data Input
tPROG
tR
≈
R/B
00h
Add.(5Cycles)
35h
Col. Add.1,2 & Row Add.1,2,3
Source Address
Data Output
≈
I/Ox
85h
Add.(5Cycles)
Data
Col. Add.1,2 & Row Add.1,2,3
85h
Add.(2Cycles)
Data
10h
Col. Add.1,2
Destination Address
There is no limitation for the number of repetition.
- 57 -
70h
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.7 Intelligent Copy-Back Program
Intelligent Page Copy-Back Program Operation
tR
tDCBSYR2
tCBSY2
≈
R/B
Data Output
30h
Col. Add.1,2 & Row Add.1,2,3
Source Address 1
00h
Add.(5Cycles)
3Ah
Col. Add.1,2 & Row Add.1,2,3
Source Address 2
8Ch
Add.(5Cycles)
Data Input
≈
Add.(5Cycles)
00h
≈
I/Ox
15h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Source Address 1
tCBSY2
≈
tDCBSYR2
≈
Add.(5Cycles)
3Ah
Col. Add.1,2 & Row Add.1,2,3
Source Address 3
8Ch
Add.(5Cycles)
Source Address 2
tPROG
≈
Add.(5Cycles)
Data Input
≈
8Ch
15h
Data Output
Source Address N
R/B
I/Ox
Data Input
Col. Add.1,2 & Row Add.1,2,3
Destination Address
≈
00h
≈
Data Output
≈
I/Ox
≈
≈
R/B
10h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
NOTE :
1) Intelligent Copy-Back Program operation is allowed only within the same memory plane.
- 58 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.8 Cache Program
Cache Program is an extension of Page Program, which is executed with 8,832byte data registers, and is available only within a block. Since the device
has 1 page of cache memory, serial data input may be executed while data stored in data registers are programmed into memory cell.
After writing the first set of data up to 8,832byte into the selected cache registers, Cache Program command (15h) instead of actual Page Program (10h)
is inputted to make cache registers free and to start internal program operation. To transfer data from cache registers to data registers, the device remains
in Busy state for a short period of time(tCBSY) and has its cache registers ready for the next data-input while the internal programming gets started with
the data loaded into data registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy
status bit(I/O 6). Pass/fail status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the
Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is initiated only
when the pending program cycle is finished and the data registers are available for the transfer of data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal programming. If the system monitors the progress of programming only with R/B, the
last page of the target programming sequence must be programmed with actual Page Program command (10h).
Cache Program(1/2)
tCBSY
R/B
I/Ox
80h
Address &
Data Input*
15h
Col. Add1,2 & Row Add1,2,3
Data
tCBSY
80h
Address &
Data Input
15h
Col. Add1,2 & Row Add1,2,3
Data
tPROG*2
tCBSY
80h
Address &
Data Input
15h
Col. Add1,2 & Row Add1,2,3
Data
Address &
10h
Data Input
Col. Add1,2 & Row Add1,2,3
Data
80h
70h
NOTE :
1) Cache Program operation is available only within a block.
2) Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data
has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the ( last -1)th page - (Program command cycle time + Last page data loading time)
Maximum tPROG is 10ms in this case.
- 59 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Cache Program(2/2)
CLE
≈
CE
WE
ALE
80h
Add1
Add2
Add3
Add4
Din
N
Add5
R/B
Din
M
80h
15h
Add1
Add2
Add3
Add4
Add5
tCBSY
1
2
≈
I/Ox
≈
RE
Max. 127 times repeatable
1
Last Page Input & Program
CLE
≈
CE
WE
ALE
Add2
Add3
R/B
Add4
Add5
Din
N
Din
M
I/O
tPROG*
3
1
70h
10h
4
≈
I/Ox
≈
RE
Last Page Input & Program
Cache register
1
page K
page K
data register
2
page K+1
3
page K+1
page K
3
Page K
Page K
Page K
15h
4
4
Page K+1
10h
NOTE :
- Issuing the 15h command to the device after serial data input initiates the program operation with cache registers.
1) Data for Page K is input to cache registers.
2) Data is transferred to the data registers by the 15h command. During the transfer the Ready/Busy outputs Busy State (tCBSY).
3) Data for Page K+1 is input to cache registers while the data of the Page K is being programmed.
4) The programming with cache registers is terminated by the 10h command . When the device becomes Ready, it shows that the internal programming of the Page K+1 is
completed.
tPROG* = Program time for the last page + Program time for the ( last -1)th page - (command input cycle time + address input cycle time + Last page data loading time)
Maximum tPROG is 10ms in this case.
- 60 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Pass/Fail status for each page programmed by the Cache Program operation can be detected by the Read Status operation.
• I/O 0 : Pass/Fail of the current page program operation.
• I/O 1 : Pass/Fail of the previous page program operation.
The Pass/Fail status on I/O 0 and I/O 1 are valid under the following conditions.
• Status on I/O 0 : True Ready/Busy is Ready state.
The True Ready/Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
• Status on I/O 1 :Cache Read/Busy is Ready State.
The Cache Ready/Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.
I/O1 =>
Invalid
Page1
Page1
I/O0 =>
Invalid
Invalid
Page2
80h....15h
70h
Status
Out
Page 1
80h....15h
Status
Out
70h
70h
Status
Out
80h....15h
Page 2
Page N-1
R/B pin
Cache
Ready/Busy
True
Ready/Busy
Page 2
Page 1
1
I/O1 =>
Page N-2
Invalid
Page N
I/O0 =>
Invalid
Invalid
Page N-1
80h....15h
Page N-1
70h
Status
Out
80h....10h
70h
Status
Out
70h
Status
Out
Page N
R/B pin
Cache
Ready/Busy
True
Ready/Busy
1
Page N-1
Page N
During both True Ready/Busy and Cache Ready/Busy return to Ready state, the Pass/Fail for previous
page and current page can be shown through I/O 1 and I/O 0 concurrently.
- 61 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.9 Register Read Out Mode 1
At program operation, loaded data to the register can be read out before program confirm command(10h). The sequence is as follow.
Register Read Out
R/B
tCWAW
I/Ox
Address & Data Input
80h
Address
00h
Col Add1,2 &
Row Add1,2,3
Col Add1,2 & Row Add1,2,3
Date
Address
05h
Data Output
E0h
Col Add1,2
NOTE :
Register read out operation is prohibited during cache program operation.
5.10 Register Read Out Mode 2
If program operation ended in fail, programmed data in fail can be read out from the register. The sequence is as follow.
Register Read Out
tPROG
R/B
"1" Fail
I/Ox
80h
Address & Data Input
10h
70h
Col Add1,2 & Row Add1,2,3
Data
1
R/B
I/Ox
00h
1
Address
Col Add1,2 &
Row Add1,2,3
05h
I/O0
Address
E0h
Col Add1,2
NOTE :
Register read out operation is prohibited during cache program operation.
- 62 -
Data Output
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.11 Two-plane Register Read Out Mode 1
At two-plane program operation, loaded data to the register can be read out before program confirm command(10h). The sequence is as follow.
Two-Plane Register Read Out Mode 1
tDBSY
R/B
I/Ox
80h
Address & Data Input
11h
column address : Valid
page address : Page M
plane address : Fixed ’Low’
block address : Block N
R/B
Address & Data Input
81h
column address : Valid
page address : Page M
plane address : Fixed ’High’
block address : Block N
Note*2
1
tCWAW
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’Low’
block address : Block N
1
Address (2 Cycle)
E0h
Data Output
Col. Add.1,2
column address : Valid
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
2
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’High’
block address : Block N
Address (2 Cycle)
Col. Add.1,2
column address : Valid
NOTE :
1) It is noticeable that physically same row address is applied to two planes .
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
3) Register read out operation is prohibited during cache program operation.
- 63 -
E0h
Data Output
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.12 Two-plane Register Read Out Mode 2
If two-plane program operation ended in fail, programmed data in fail can be read out from the register. The sequence is as follow.
Two-Plane Register Read Out Mode 2
tDBSY
R/B
I/Ox
tPROG
"1" Fail
80h Address & Data Input 11h
column address : Valid
page address : Page M
plane address : Fixed ’Low’
block address : Block N
81h Address & Data Input 10h
Note*2
70h
I/O0
column address : Valid
page address : Page M
plane address : Fixed ’High’
block address : Block N
1
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’Low’
block address : Block N
1
Address (2 Cycle)
E0h
Data Output
Col. Add.1,2
column address : Valid
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
2
column address : Fixed ’Low’
page address : Page M
plane address : Fixed ’High’
block address : Block N
Address (2 Cycle)
Col. Add.1,2
column address : Valid
NOTE :
1) It is noticeable that physically same row address is applied to two planes .
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
3) Register read out operation is prohibited during cache program operation.
- 64 -
E0h
Data Output
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.13 Two-plane Page Program
Two-Plane Page Program is an extension of Page Program, for a single plane with 8,832 byte data registers. Since the device is equipped with two memory planes, activating the two sets of 8,832 byte data registers enables a simultaneous programming of two pages.
After writing the first set of data up to 8,832 byte into the selected data registers via cache registers, Dummy Page Program command (11h) instead of
actual Page Program command (10h) is inputted to finish data-loading of the first plane. Since no programming process is involved, R/B remains in Busy
state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device returns to Ready state by polling the
Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the 81h command and address sequences. After inputting data
for the last plane, actual True Page Program(10h) instead of dummy Page Program command (11h) must be followed to start the programming process.
The operation of R/B and Read Status is the same as that of Page Program. Although two planes are programmed simultaneously, pass/fail is not available for each page when the program operation completes. Status bit of I/O 0 is set to "1" when any of the pages fails.
Restriction in addressing with Two-Plane Page Program is shown below.
Two-Plane Page Program
tDBSY
R/B
I/O0 ~ 7
80h
Address & Data Input
11h
tPROG
81h
Address & Data Input
"0"
10h
70h/F1h
I/O0
Note*2
column address : Valid
page address : Page M
plane address: Fixed ’Low’
block address: Block N
"1"
Fail
column address : Valid
page address : Page M
plane address: Fixed ’High’
block address: Block N
NOTE :
1) It is noticeable that same row address except for the Plane address is applied to the two blocks
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Data
Input
80h
11h
81h
10h
Plane 0
(2076 Block)
Plane 1
(2076 Block)
Block 0
Block 1
Block 2
Block 3
Block 4148
Block 4150
Block 4149
Block 4151
- 65 -
Pass
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.14 Two-plane Copy-back Program
Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 8,832 byte data registers. Since the device is equipped
with two memory planes, activating the two sets of 8,832 byte data registers enables a simultaneous programming of two pages.
Two-Plane Copy-Back Program Operation
tR
R/B
I/OX
60h
Address (3 Cycle)
60h
35h
Address (3 Cycle)
Row Add.1,2,3
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address: Block N
1
R/B
I/Ox
00h
Address (5 Cycle)
Address (2 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
Data Output
Col. Add.1,2
column address: Valid
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’Low’
block address: Block N
1
E0h
2
R/B
I/Ox
00h
Address (5 Cycle)
Address (2 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’High’
block address: Block N
2
E0h
Data Output
Col. Add.1,2
3
column address: Valid
tPROG
tDBSY
R/B
I/Ox
85h
Add.(5Cycles)
11h
81h
Add.(5Cycles)
10h
Note2
3
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2 & Row Add.1,2,3
Destination Address
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’High’
block address: Block N
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’Low’
block address: Block N
- 66 -
70h/F1h
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Plane0
Final Rev. 1.0
FLASH MEMORY
Plane1
Source page
Source page
Target page
Target page
(1) : Two-Plane Read for Copy Back
(2) : Two-Plane Random Data Out
(1)
(2)
(3)
Data Field
(1)
Spare Field
(2)
(3)
Data Field
(3) : Two-Plane Copy-Back Program
Spare Field
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
- 67 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Two-Plane Copy-Back Program Operation with Random Data Input
tR
R/B
I/OX
60h
Address (3 Cycle)
60h
35h
Address (3 Cycle)
Row Add.1,2,3
Row Add.1,2,3
page address : Fixed ’Low’
plane address: Fixed ’Low’
block address: Block N
page address : Valid
plane address: Fixed ’High’
block address: Block N
1
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
E0h
Data Output
Col. Add.1,2
column address: Valid
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’Low’
block address: Block N
1
Address (2 Cycle)
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
2
Address (2 Cycle)
E0h
Data Output
Col. Add.1,2
3
column address: Valid
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’High’
block address: Block N
tDBSY
R/B
I/Ox
85h
Add.(5Cycles)
Data
85h
Data
11h
Note2
Col. Add.1,2 & Row Add.1,2,3
3
Add.(2Cycles)
Col. Add.1,2
4
Destination Address
column address: Valid
column address: Valid
page address : Page M
plane address: Fixed ’Low’
block address: Block N
tPROG
R/B
I/Ox
81h
4
Add.(5Cycles)
Data
85h
Col. Add.1,2 & Row Add.1,2,3
Add.(2Cycles)
Col. Add.1,2
Destination Address
column address: Valid
page address : Page M
plane address: Fixed ’High’
block address: Block N
column address: Valid
NOTE :
1) Copy-Back Program operation is allowed only within the same memory plane.
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
- 68 -
Data
10h
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.15 Two-Plane Intelligent Copy-back Program(1/2)
Two-Plane Intelligent Copy-Back Program Operation
tR
R/B
I/OX
60h
60h
Address (3 Cycle)
30h
Address (3 Cycle)
Row Add.1,2,3
Row Add.1,2,3
page address : Page M
plane address: Fixed ’Low’
block address: Block N
page address : Page M
plane address: Fixed ’High’
block address: Block N
1
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
E0h
Data Output
Col. Add.1,2
column address: Valid
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’Low’
block address: Block N
1
Address (2 Cycle)
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
E0h
Col. Add.1,2
3
tDCBSYR2
R/B
I/OX
60h
Address (3 Cycle)
60h
Row Add.1,2,3
Address (3 Cycle)
3Ah
Row Add.1,2,3
page address : Page M+1
plane address: Fixed ’Low’
block address: Block N
3
Data Output
column address: Valid
column address: Fixed "Low"
page address : Page M
plane address: Fixed ’High’
block address: Block N
2
Address (2 Cycle)
page address : Page M+1
plane address: Fixed ’High’
block address: Block N
4
tCBSY2
tDBSY
R/B
I/Ox
8Ch
Add.(5Cycles)
Data Input
11h
8Ch
Add.(5Cycles)
Data Input
15h
Note2
4
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2 & Row Add.1,2,3
Destination Address
column address: Fixed "Low"
page address : Page N
plane address: Fixed ’High’
block address: Block N
column address: Fixed "Low"
page address : Page N
plane address: Fixed ’Low’
block address: Block N
- 69 -
5
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Two-Plane Intelligent Copy-back Program(2/2)
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
E0h
Data Output
Col. Add.1,2
column address: Valid
column address: Fixed "Low"
page address : Page M+1
plane address: Fixed ’Low’
block address: Block N
5
Address (2 Cycle)
6
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
E0h
Data Output
Col. Add.1,2
7
column address: Valid
column address: Fixed "Low"
page address : Page M+1
plane address: Fixed ’High’
block address: Block N
6
Address (2 Cycle)
tPROG
tDBSY
R/B
I/Ox
8Ch
Add.(5Cycles)
Data Input
11h
8Ch
Add.(5Cycles)
Data Input
Note2
7
Col. Add.1,2 & Row Add.1,2,3
Destination Address
Col. Add.1,2 & Row Add.1,2,3
Destination Address
column address: Fixed "Low"
page address : Page N+1(Final)
plane address: Fixed ’Low’
block address: Block N
column address: Fixed "Low"
page address : Page N+1(Final)
plane address: Fixed ’High’
block address: Block N
NOTE :
1) Two-Plane Intelligent Copy-Back Program operation is allowed only within the same memory plane.
2) Any command between 11h and 8Ch is prohibited except 70h/F1h and FFh.
- 70 -
10h
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
datasheet
FLASH MEMORY
Pass/Fail status for each page programmed by the Intelligent Copy-Back Program operation can be detected by the Read Status operation.
• I/O 0 : Pass/Fail of the current page program operation.
• I/O 1 : Pass/Fail of the previous page program operation.
The Pass/Fail status on I/O 0 and I/O 1 are valid under the following conditions.
• Status on I/O 0 : True Ready/Busy is Ready state.
The True Ready/Busy is output on I/O 5 by Read Status operation or R/B pin after the 10h command.
• Status on I/O 1 :Cache Read/Busy is Ready State.
The Cache Ready/Busy is output on I/O 6 by Read Status operation or R/B pin after the 15h command.
CASE 1
I/O1 =>
Invalid
Valid
I/O0 =>
Invalid
Invalid
00h....3Ah
8Ch....15h
70h
Status
Out
00h....3Ah
70h
Status
Out
R/B pin
Cache
Ready/Busy
True
Ready/Busy
Page N
Read for Copy-Back
Page N - 1
Copy-Back Program
Page N + 1
Read for Copy-Back
CASE 2
I/O1 =>
Invalid
Invalid
I/O0 =>
Invalid
Valid
00h....3Ah
8Ch....15h
70h
Status
Out
R/B pin
Cache
Ready/Busy
True
Ready/Busy
Page N
Read for Copy-Back
Page N - 1
Copy-Back Program
- 71 -
70h
Status
Out
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.16 Two-plane Cache Program
Two-Plane Cache Program is an extension of Cache Program, for a single plane with 8,832 byte data registers. Since the device is equipped with two
memory planes, activating the two sets of 8,832 byte data registers enables a simultaneous programming of two pages.
Two-Plane Cache Program Operation
tDBSY
R/B
I/OX
80h
Address & Data Input
11h
tCBSY
81h
column address : Valid
page address : Page M
plane address: Fixed ’Low’
block address: Block N
Address & Data Input
15h
column address : Valid
page address : Page M
plane address: Fixed ’High’
block address: Block N
Max. 127 Times repeatable
1
tDBSY
tPROG
R/B
I/Ox
Address & Data Input
80h
1
11h
81h
column address : Valid
page address : Page M+n
plane address: Fixed ’Low’
block address: Block N
Address & Data Input
10h
column address : Valid
page address : Page M+n
plane address: Fixed ’High’
block address: Block N
NOTE :
1) It is noticeable that same row address except for A20 is applied to the two blocks
2) Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
3) Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the previous program cycle with the cache data
has not finished, the actual program cycle of the last page is initiated only after completion of the previous cycle, which can be expressed as the following formula.
tPROG = Program time for the last page + Program time for the ( last -1)th page
- (Program command cycle time + Last page data loading time)
80h
Cache register
1
11h
81h
1
Data register
2
3
15h
2
3
3
Plane 0
(2076 Block)
Plane 1
(2076 Block)
Block 0
Block 1
Block 2
Block 3
Block 4148
Block 4150
Block 4149
Block 4151
- 72 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.17 Block Erase
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only
Plane address and Block address are valid while Page address is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally
erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is
completed, the Write Status Bit(I/O 0) may be checked.
Block Erase Operation
tBERS
R/B
"0"
60h
I/Ox
Address Input(3Cycle)
Pass
I/O0
70h
D0h
"1"
Row Add 1,2,3
Fail
5.18 Two-plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by three address cycles) may be repeated up
to twice for erasing up to two blocks. Only one block should be selected from each plane. The Erase Confirm command(D0h) initiates the actual erasing
process. The completion is detected by monitoring R/B pin or Ready/Busy status bit (I/O 6).
Two-Plane Block Erase Operation
tBERS
R/B
I/OX
60h
Address (3 Cycle)
Row Add 1,2,3
page address : Fixed ’Low’
plane address :Fixed ’Low’
block address : Block N
60h
Address (3 Cycle)
Row Add 1,2,3
page address : Fixed ’Low’
plane address : Fixed ’High’
block address : Block N
- 73 -
D0h
70h/F1h
"0"
I/O0
"1"
Fail
Pass
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.19 Read Status
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase
operation is completed successfully. After writing 70h or F1h command to the command register, a read cycle outputs the content of the Status Register to
the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to the table for specific 70h
Status Register definitions and F1h status Register definitions. The command register remains in Status Read mode until further commands are issued to
it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles.
Status Register Definition for 70h Command
Cache
Program
Intelligent
Copy-Back
Program
Pass/Fail(N)
Pass/Fail(N)
I/O
Page
Program
Block
Erase
I/O 0
Pass/Fail
Pass/Fail
I/O 1
Not Use
Not Use
I/O 2
Not Use
Not Use
Not Use
I/O 3
Not Use
Not Use
Not Use
I/O 4
Not Use
Not Use
Not Use
I/O 5
I/O 6
I/O 7
Read
Cache Read
Intelligent
Copy-Back
Read
Definition
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
Not Use
Not Use
Not Use
Not Use
Don’t -cared
Not Use
Not Use
Not Use
Not Use
Don’t -cared
Not Use
Not Use
Not Use
Not Use
Not Use
Don’t -cared
Not Use
True
Ready/Busy
True
Ready/Busy
Not Use
True
Ready/Busy
True
Ready/Busy
Ready/Busy
Ready/Busy
Cache
Ready/Busy
Cache
Ready/Busy
Ready/Busy
Write Protect
Write Protect
Write Protect
Write Protect
Write Protect
Pass/Fail(N-1) Pass/Fail(N-1)
Busy : "0"
Ready : "1"
Cache Ready/ Cache Ready/
Busy : "0"
Busy
Busy
Ready : "1"
Write Protect
Write Protect
Protected : "0"
Not Protected : "1"
NOTE :
1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2) N : current page, N-1: previous page.
Status Register Definition for F1h Command
I/O
Page
Program
Block
Erase
Cache
Program
Intelligent
Copy-Back
Program
Read
Cache
Read
Intelligent
Copy-Back
Read
I/O 0
Chip
Pass/Fail
Chip
Pass/Fail
Chip
Pass/Fail(N)
Chip
Pass/Fail(N)
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
I/O 1
Plane0
Pass/Fail
Plane0
Pass/Fail
Plane0
Pass/Fail(N)
Plane0
Pass/Fail(N)
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
I/O 2
Plane1
Pass/Fail
Plane1
Pass/Fail
Plane1
Pass/Fail(N)
Plane1
Pass/Fail(N)
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
I/O 3
Not Use
Not Use
Plane0
Pass/Fail(N-1)
Plane0
Pass/Fail(N-1)
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
I/O 4
Not Use
Not Use
Plane1
Pass/Fail(N-1)
Plane1
Pass/Fail(N-1)
Not Use
Not Use
Not Use
Pass : "0"
Fail : "1"
I/O 5
Not Use
Not Use
True
Ready/Busy
True
Ready/Busy
Not Use
True
Ready/Busy
True
Ready/Busy
Busy : "0"
Ready : "1"
I/O 6
Ready/Busy
Ready/Busy
Cache
Ready/Busy
Cache
Ready/Busy
Ready/Busy
Cache
Ready/Busy
Cache
Ready/Busy
Busy : "0"
Ready : "1"
I/O 7
Write Protect
Write Protect
Write Protect
Write Protect
Write Protect
Write Protect
Write Protect
Protected : "0"
Not Protected : "1"
NOTE :
1) I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
2) N : current page,
N-1 : previous page.
- 74 -
Definition
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.20 Read Id
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Six read cycles
sequentially output the manufacturer code(ECh), and the device code and 3rd, 4th, 5th, 6th cycle ID respectively. The command register remains in Read
ID mode until further commands are issued to it.
Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR
ALE
tWHR
RE
I/OX
Device
tREA
00h
ECh
Address. 1cycle
Maker code
90h
Device
Code
3rd Cyc.
4th Cyc.
5th Cyc.
6th Cyc.
Device code
Device Code (2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
D7h
94h
76h
64h
43h
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
5.21 Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or
erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially
programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high.
Refer to table for device status after reset operation. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written.
RESET Operation
tRST
R/B
I/OX
FFh
Device Status
Operation mode Mode
After Power-up
After Reset
00h Command is latched
Waiting for next command
- 75 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.22 Output driver setting
The device supports four kinds of output driver setting for matching the system characteristics. The nominal output drive strength is the power-on default
value. The host is able to select a different drive strength setting using the SET FEATURES (EFh) command with following 10h address (driver setting
feature address). The output impedance range from minimum to maximum covers process, voltage, and temperature variations. Devices are not guaranteed to be at the nominal value. The users can tune the output driver impedance of the data by setting the driver strength register value. (See Configuration Register Table) Table 5 shows which output driver would be tuned and the strength according to setting data. Upon power-up, the register will revert
to the default setting. Table 6 & Table 7 shows the output driver strength impedance values of each strength and pull-up and pull down output impedance
mismatch.
Driver Strength Register Setting
CE
CLE
ALE
tADL
tWC
WE
tWB
RE
(1)
I/Ox
EFh
10h
B0
B1
B2
B3
R/B
NOTE :
1) B0-B3 are parameters identifying new settings for the feature specified.
Table 5. Output Driver Setting
B0 Value
Driver Strength
00h~01h
Reserved
02h
Driver Multiplier : underdriver1
03h
Reserved
04h
Driver Multiplier : 1 (default)
05h
Reserved
06h
Driver Multiplier :overdriver1
07h
Reserved
09h
Reserved
0Ah ~FFh
Reserved
- 76 -
tFEAT
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
Driver strength register getting
CE
CLE
ALE
WE
RE
(1)
I/Ox
EEh
EFh
10h
B0
B1
B2
B3
tFEAT
R/B
Table 6. Output Drive Strength Impedance Values
Output Strength
Rpd/Rpu
Rpd
Overdrive1
Rpu
Rpd
Nominal
Rpu
Rpd
Underdrive
Rpu
VOUT to VssQ
Minimum
Nominal
Maximum
VccQ(3.3V)
VccQ(3.3V)
VccQ(3.3V)
Units
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
VccQ × 0.2
ohms
VccQ × 0.5
ohms
VccQ × 0.8
ohms
Table 7. Pull-up and Pull-down Output Impedance Mismatch
Min
Max
VccQ(3.3V)
VccQ(3.3V)
Drive Strength
Unit
Notes
Overdrive 1
0
ohms
1, 2
Nominal
0
ohms
1, 2
Underdrive
0
ohms
1, 2
NOTE :
1) Mismatch is the absolute value between pull-up and pull-down impedances. Both are measured at the same temperature and voltage.
2) Test conditions: VccQ = VccQ(min), Vout = VccQ × 0.5, TA = TOPER
- 77 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.23 Ready/busy
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/
B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address
loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs
to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart. Its value can be determined by the following guidance.
Rp
VCC
ibusy
3.3V device - VOL : 0.4V, VOH : 2.4V
Ready Vcc
R/B
open drain output
VOH
CL
VOL
Busy
tf
tr
GND
Device
Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
2.4
200
tr,tf [s]
2m
Ibusy [A]
Ibusy
200n
150
1.2
100
100n
1m
0.8
tr
0.6
50
3.6
1K
tf
3.6
3.6
2K
3K
Rp(ohm)
4K
3.6
Rp value guidance
Rp(min, 3.3V part) =
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
- 78 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
5.24 00h Address ID Cycle
Device
1st Cycle
Dvice Code(2nd)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
ECh
D7h
94h
76h
64h
43h
1st Cycle
Dvice Code(2nd)
3rd Cycle
4th Cycle
5th Cycle
6th Cycle
4Ah
45h
44h
45h
43h
01h
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
5.25 40h Address ID Cycle
Device
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
5.26 Device Identification Table Read Operation
The device supports the device ID table read operation to give more ID information such as the device‘s organization, features, timings and other parameters. Refer to the Device ID Table Read timing diagram below.
Values in the Device ID Table are static and shall not change.
Device ID Table Read
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
ECh
Value of Device ID Table
40h
- 79 -
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
Final Rev. 1.0
FLASH MEMORY
Device ID table definitions
Byte
O/M
Description
Value
Revision information and features block
0-3
M
Parameter page signature
Byte 0: “J” (= 4Ah)
Byte 1: “E” (= 45h)
Byte 2: “S” (= 53h)
Byte 3: “D” (= 44h)
4-5
M
Revision number
2-15: Reserved (0)
1: 1 = supports revision 1.0
0: Reserved (0)
02h, 00h
6-7
M
Features supported
0-15 Reserved (0)
<To be defined based on feature discussions.>
TBD
8-10
M
Optional commands supported
0-23: Reserved (0)
<To be defined based on command set discussions.>
TBD
Reserved (0)
All 00h
11-3111-31
4Ah, 45h, 53h, 44h
Manufacturer information block
32-43
M
Device manufacturer (12 ASCII characters)
53h, 41h, 4Dh, 53h
55h, 4Eh, 47h, 20h
20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
4Bh, 39h, 36h, 41h, 47h
44h, 38h, 55h, 30h, 4Dh
20h, 20h, 20h, 20h, 20h
20h, 20h, 20h, 20h, 20h
64-69
M
JEDEC manufacturer ID (6 bytes)
ECh, 00h, 00h,00h,00h,00h
70-71
TBD
TBD
TBD
72-79
Reserved (0)
Memory organization block
80-83
M
Number of data bytes per page
00h, 20h, 00h, 00h
84-85
M
Number of spare bytes per page
00h, 02h
86-89
M
TBD
TBD
90-91
M
TBD
TBD
92-95
M
Number of pages per block
40h, 00h, 00h, 00h
96-99
M
Number of blocks per logical unit
38h, 10h, 00h, 00h
100
M
Number of logical unit
01h
101-255
TBD
TBD
TBD
Redundant parameter pages
255-511
M
Redundant parameter pages
Value of byte 0-255
512-767
M
Redundant parameter pages
Value of byte 0-255
From768
O
Additional redundant parameter pages.
TBD
NOTE :
Values in the Device ID Table are TBD
- 80 -
Final Rev. 1.0
datasheet
K9GBG08U0A
K9LCG08U1A K9HDG08U5A
FLASH MEMORY
6.0 DATA PROTECTION & POWER UP SEQUENCE
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions
whenever Vcc is below about 2V. The Reset command(FFh) must be issued to all CEs as the first command after the NAND Flash device is powered on.
Each CE will be busy for a maximum of 5ms after a RESET command is issued. In this time period, the acceptable command is 70h/F1h.
WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. The two step command sequence for program/erase provides additional software protection.
≈
AC Waveforms for Power Transition
Vcc : ~ 2.7V
VccQ : (3.3V) : ~2.7V
100μs
(2)
≈
VCC/VCCQ
Vcc : ~ 2.7V
VccQ : (3.3V) : ~2.7V
≈
≈
CLE
≈
CE
Don’t care
≈
High
≈
WP
≈
Don’t care
≈
WE
I/Ox
≈
FFh
R/B
100μs
5ms max
Invalid
≈
Operation
Don’t care
NOTE :
1) During the initialization, the device consumes a maximum current of 50mA (ICC1)
2) Vcc should be reached the valid voltage no later than VccQ.
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K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
Final Rev. 1.0
FLASH MEMORY
6.1 WP AC Timing guide
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:
Program Operation
≈
1. Enable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
≈
2. Disable Mode
WE
I/O
80h
10h
WP
R/B
tww(min.100ns)
Erase Operation
≈
1. Enable Mode
WE
I/O
60h
D0h
WP
R/B
tww(min.100ns)
≈
2. Disable Mode
WE
60h
I/O
D0h
WP
R/B
tww(min.100ns)
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