S3C6410X66-YB40 USER'S MANUAL S3C6410X RISC Microprocessor February 29, 2008 Preliminary REV 0.00 Email:[email protected] HotTel:+86-21-58998693 S3C6410X66-YB40 S3C6410X_UM_REV0.00 Email:[email protected] HotTel:+86-21-58998693 PRODUCT OVERVIEW PRODUCT OVERVIEW 1 ARCHITECTURAL OVERVIEW The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low-power capabilities, high performance Application Processor solution for mobile phones and general applications. To provide optimized H/W performance for the 2.5G & 3G communication services, the S3C6410 adopts 64/32-bit internal bus architecture. The 64/32-bit internal bus architecture is composed of AXI, AHB and APB buses. It also includes many powerful hardware accelerators for tasks such as motion video processing, audio processing, 2D graphics, display manipulation and scaling. An integrated Multi Format Codec (MFC) supports encoding and decoding of MPEG4/H.263/H.264 and decoding of VC1. This H/W Encoder/Decoder supports real-time video conferencing and TV out for both NTSC and PAL mode. Graphic 3D (hereinafter 3D Engine) is a 3D Graphics Hardware Accelerator which can accelerate OpenGL ES 1.1 & 2.0 rendering. This 3D Engine includes two programmable shaders: one vertex shader and one pixel shader. The S3C6410 has an optimized interface to external memory. This optimized interface to external memory is capable of sustaining the high memory bandwidths required in high-end communication services. The memory system has dual external memory ports, DRAM and Flash/ROM/DRAM port. The DRAM port can be configured to support mobile DDR, DDR, mobile SDRAM and SDRAM. The Flash/ROM/DRAM port supports NOR-Flash, NAND-Flash, OneNAND, CF, ROM type external memory and mobile DDR, DDR, mobile SDRAM and SDRAM. To reduce total system cost and enhance overall functionality, the S3C6410 includes many hardware peripherals such as a Camera Interface, TFT 24-bit true color LCD controller, System Manager (power management & etc.), 4-channel UART, 32-channel DMA, 4-channel Timers, General Purpose I/O Ports, I2S-Bus interface, I2C-BUS interface, USB Host, USB OTG Device operating at high speed (480Mbps), 3-channel SD/MMC Host Controller and PLLs for clock generation. The ARM subsystem is based on the ARM1176JZF-S core. It includes separate 16KB Instruction and 16KB data caches, 16KB Instruction and 16KB Data TCM. It also includes a full MMU to handle virtual memory management. The ARM1176JZF-S is a single chip MCU, which includes support for JAVA acceleration. The ARM1176JZF-S includes a dedicated vector floating point coprocessor allowing efficient implementation of various encryption schemes as well as high quality 3D graphics applications. The S3C6410X adopts the de-facto standard AMBA bus architecture. These powerful, industry standard features allow the S3C6410X to support many of the industry standard Operating Systems. By providing a complete set of common system peripherals, the S3C6410X minimizes overall system costs and eliminates the need to configure additional components. The S3C6410X is implemented using an advanced 90nm CMOS process. The low-power, simple, elegant and fully static-design scheme is particularly suitable for costsensitive and power-sensitive applications. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-1 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1 FEATURES This section summarizes the features of the S3C6410. Figure 1-1 is an overall block diagram of the S3C6410X. Figure 1-1 S3C6410 Block Diagram Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-2 S3C6410X66-YB40 Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 PRODUCT OVERVIEW 1.1.1 S3C6410X RISC MICROPROCESSOR FEATURES SUMMARY The features of S3C6410X RISC Microprocessor include: • The ARM1176JZF-S based CPU subsystem with Java acceleration engine and 16KB/16KB I/D Cache and 16KB/16KB I/D TCM. • 533MHz at 1.2V and 634MHz at TBD V respectively. • 8-bit ITU 601/656 Camera interface up to 4M pixel for scaled and 16M pixel for unscaled resolution. • Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 30fps@SD and decoding of VC1 video up to 30fps@SD. • 2D graphics acceleration with BitBlit and rotation. • 3D graphics acceleration with 4M triangles/s @133Mhz (Transform only) • AC-97 audio codec interface and PCM serial audio interface. • 1/2/4bpp Palletized or 16bpp/24bpp Non-Palletized Color-TFT • I2S and I2C interface support. • Dedicated IrDA port for FIR, MIR and SIR. • Flexibly configurable GPIOs. • Port USB 2.0 OTG supporting high speed as Device (480Mbps, on-chip transceiver). • Port USB 1.1 Host supporting full speed (12Mbps, on-chip transceiver). • SD/MMC/SDIO/CE-ATA Host Controller • Real time clock, PLL, timer with PWM and watch dog timer. • 32 channel DMA controller. • Support 8x8 key matrix. • Advanced power management for mobile applications. • Memory Subsystem − SRAM/ROM/NOR Flash Interface with x8 or x16 data bus. − Muxed OneNAND Interface with x16 data bus. − NAND Flash Interface with x8 data bus. − SDRAM Interface with x16(Port0) or x32(Port1) data bus. − Mobile SDRAM Interface with x16(Port0) or x32(Port1) data bus − Mobile DDR Interface with x16(Port0/1) or x32(Port1 ) data bus Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-3 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1.2 MICROPROCESSOR The ARM1176JZF-S processor incorporates an integer unit that implements the ARM11 ARM architecture v6. It supports the ARM, Thumb™ instruction sets and Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers. The features of ARM1176JZF-S processor include: • High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced Extensible Interface (AXI) level two interfaces supporting prioritized multiprocessor implementations. • Integer unit with integral EmbeddedICE-RT logic. • Eight-stage pipeline. • Branch prediction with return stack. • Low interrupt latency configuration. • coprocessors CP14 and CP15. • Instruction and Data Memory Management Units (MMUs), managed using MicroTLB structures backed by a unified Main TLB. • Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM). • Virtually indexed and physically addressed caches. • 64-bit interface to both caches. • Vector Floating-Point (VFP) coprocessor support. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-4 S3C6410X66-YB40 Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 PRODUCT OVERVIEW 1.1.3 MEMORY SUBSYSTEM The S3C6410X microprocessor provides the following Memory Subsystem features: • High bandwidth Memory Matrix subsystem • Two independent external memory ports (1 SROM port and 1 DRAM ports) • Matrix architecture increases overall bandwidth with the simultaneous access capability 1.1.3.1 SROM Memory Port configurable to support the following memory types: • • • • Support SRAM/ROM/NOR Flash Interface − x8 or x16 data bus − Address range support: max. 26-bit (128MB) Muxed OneNAND Flash interface − x16 data bus − Support muxed type OneNAND. NAND Flash Boot Loader − System can be booted from NAND when system initialization begins − Supports both SLC and MLC NAND Flash memory CF interface − • Compatible with CF+ and CompactFlash Spec (Rev 3.0) SDRAM Interface − x16 data bus for Memory Port0 − 1.8/ 2.5V/3.3V interface voltage − Density support: ∗ Memory Port0: up to 1Gb • Mobile SDRAM Interface − x16 data bus with 133Mbps/pin data rate for Memory Port0 − 133MHz address and command bus speed − 1.8/ 2.5V/3.3V interface voltage for Memory Port0 − 1.8/ 2.5V interface voltage for Memory Port1 − Density support: up to 1Gb − Mobile SDRAM feature support: ∗ ∗ ∗ • DS (Driver Strength Control) TCSR (Temperature Compensated Self-Refresh Control) PASR (Partial Array Self-Refresh Control) Mobile DDR Interface − x16 data bus for Memory Port0, x32 data bus for Memory Port1 − 1.8/ 2.5V/3.3V interface voltage − Density support: up to 1Gb Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-5 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1.3.2 DRAM port configurable to support the following memory types: • • • SDRAM Interface − x16/x32 data bus − 1.8/ 2.5V interface voltage − Density support: up to 2Gb Mobile SDRAM Interface − Only x32 data bus with 133Mbps/pin data rate − 133MHz address and command bus speed − 1.8/ 2.5V interface voltage − Density support: up to 2Gb − Mobile SDRAM feature support: ∗ DS (Driver Strength Control) ∗ TCSR (Temperature Compensated Self-Refresh Control) ∗ PASR (Partial Array Self-Refresh Control) Mobile DDR Interface − x16 or x32 data bus with 266Mbs/pin double data rate (DDR) − 1.8/ 2.5V interface voltage − Density support: up to 2Gb 1.1.4 MULTIMEDIA ACCELERATION The S3C6410 microprocessor provides the following Multimedia Acceleration features: 1.1.4.1 Camera Interface • • • • • • • • • • • ITU-R 601/ITU-R 656 format input support. 8-bit input is supported Both progressive and interlaced input are supported Camera input resolution up to 4096x4096 in YCbCr 4:2:2 format. − 4096x4096 input resolution assumes the hardware down-scaling units will be bypass − Up to 2048x2048 input resolution can optionally be input to the hardware down-scaling unit Resolution down-scaling hardware support for input resolutions up to 2048x2048 Codec/Preview output image generation (RGB 16/18/24-bit format and YCbCr 4:2:0/4:2:2 format) Image windowing and digital zoom-in function Test pattern generation Image mirror and rotation supports Y-mirror, X-mirror, 90’, 180’ and 270’ rotation H/W Color Space Conversion LCD controller direct path supported Image effect supported. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-6 S3C6410X66-YB40 Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 PRODUCT OVERVIEW 1.1.4.2 Multi Format Codec (MFC) • Multi Format Codec − MPEG-4 part-II simple profile encoding/decoding − H.264/AVC baseline encoding/decoding − H.263 profile3 encoding/decoding − VC1 decoding − Multi-part cell and Multi Standard are supported • Encoding tools − [-16,+16] 1/2 and 1/4 pel accuracy motion estimation using the full-search algorithm − Variable block sizes: 16x16, 16x8, 8x16 and 8x8 − Unrestricted motion vector − MPEG-4 AC/DC prediction − H.264/AVC intra-prediction (hardwired mode decision) − In-loop deblocking filter for both H.264 and H.263 P3 − Error resilience tools − MPEG-4 resync. Marker and data-partitioning with RVLC − MPEG-4/AVC FMO − Bit-rate control (CBR and VBR) • Decoding tools − Support all features of the standards • Pre/post rotation/mirroring − 8 mirroring/rotation modes 1.1.4.3 JPEG Codec • • • Compression/decompression up to UXGA size Encoding format: YCbCr 4:2:2 / RGB565 Decoding format: YCbCr 4:4:4/4:2:2/4:2:0 or gray 1.1.5 2D GRAPHICS ACCELERATOR The S3C6410X microprocessor supports the following 2D Graphics Accelerator features: • Line/Point drawing, BitBLT and Color Expansion /Text Drawing 1.1.6 3D GRAPHICS ACCELERATOR • • • • • • • • 4M triangles/s @133MHz (Transform Only) 75.8M pixels/s fill-rates @133MHz (shaded pixels) Programmable Shader Model 3.0 support 128-bit (32-bit x 4) Floating-point Vertex Shader - Geometry-texture cache support 128-bit (32-bit x 4) Floating-point two Fragment Shaders Max. 4K x 4K frame-buffer (16/32-bpp) 32-bit depth buffer (8-bit stencil/24-bit Z) Texture format: 1/2/4/8/16/32-bpp RGB, YUV 422, S3TC Compressed Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-7 S3C6410X66-YB40 PRODUCT OVERVIEW • • • • Support max. 8 surfaces (max. 8 user-defined textures) API Support: OpenGL ES 1.1 & 2.0, D3D Mobile Intelligent Host Interface - 15 input data-types, Vertex Buffer & Vertex Cache H/W Clipping (Near & Far) • 8-stage five-threaded Shader architecture • • Primitive assembly & hard-wired triangle setup engine One pixels/cycle hard-wired rasterizer • One texturing engine (one bilinear-filtered texel/cycle each) - Nearest/bilinear/trilinear filtering - 8-layered multi-texturing support Fragment processing: Alpha/Stencil/Z/Dither/Mask/ROP Memory bandwidth optimization through hierarchical caching - L1/L2 Texture-caches, Z/Color caches System bus interface - Host interface: 32-bit AHB (AMBA 2.0) - Memory Interface: two 64-bit AXI (AMBA 3.0) channels • • • Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1.6 IMAGE ROTATOR The S3C6410X microprocessor supports the following Image Rotator features: • Image format: YCbCr 4:2:2 (interleave), YCbCr 4:2:0 (non-interleave), RGB565 and RGB888(unpacked) • Rotate degree: 90, 180, 270, flip vertical and flip horizontal • Image size: 2048x2048 Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-8 S3C6410X66-YB40 S3C6410X_UM_REV0.00 Email:[email protected] HotTel:+86-21-58998693 PRODUCT OVERVIEW 1.1.7 DISPLAY CONTROL The S3C6410 microprocessor provides the following Display Control features: 1.1.7.1 TFT LCD Interface • • • • • • • 1/2/4/8bpp Palletized or 16/18/24-bpp Non-Palletized Color-TFF supports Typical actual screen size: 640 x 480, 320 x 240, 800 x 480 Maximum 16M virtual screen size Support 5 Window Layer for PIP or OSD Realtime overlay plane multiplexing Programmable OSC window positioning 16-level alpha blending 1.1.7.2 Video Post Processor • • • • • Video input format conversion Video/Graphic scaling up/down or zooming in/out Color space conversion from YCbCr to RGB and from RGB to YCbCr Dedicated local interface for display Dedicated scaler for TV Encoder 1.1.7.3 TV (NTSC/PAL) Video Encoder with Image Enhancer • • Support NTSC-M,J / PAL-B,D,G,H,I,M,Nc compliant video format Built in the MIE(Mobile Image Enhancer) Engine − − − − − Black & White Stretch Blue Stretch & Flesh-Tone Correction Dynamic Horizontal Peaking & LTI Black and White Noise reduction Full Size and Wide Size Video-Out 1.1.8 AUDIO INTERFACE The S3C6410 microprocessor provides the following Audio Interface features: 1.1.8.1 AC97 Controller • • • • Variable sampling rate (48kHz and below) Single Codec Controller 1 port stereo inputs/1 port stereo outputs/mono MIC input 16-bit stereo (2-channel) audio 1.1.8.2 PCM serial Audio Interface • • • Master mode bi-directional serial audio interface Accepts an external input clock to generate exact Audio timings Optional DMA-based operation Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-9 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1.8.3 IIS-Bus Interface • • • • • • 2 ch IIS-bus 2ea and 5.1ch IIS-bus 1ea for the audio-codec interface Optional DMA-based operation Serial, 8/16/24-bit per channel data transfers Supports IIS, MSB-justified and LSB-justified data format Can operate in Master or Slave mode Various bit clock frequency and codec clock frequency support − 16,24,32,48 fs of bit clock frequency and 256,384,512,768 fs of codec clock frequency • Supports 8kHz ~ 192kHz sampling frequency. 1.1.9 USB SUPPORT The S3C6410 microprocessor provides the following USB Support features: 1.1.9.1 USB OTG 2.0 High Speed • • Complies with the On-The-Go Supplement to the USB 2.0 Specification (Revision 1.0a) Supports high speed (480Mbps), full speed (12Mbps, Device only), low speed (1.5Mbps, Host only) • Configures as USB 1.1 full/low speed DRD(Dual-Role Device), Host-only or Device only controller 1.1.9.2 USB Host • • • • 2-port USB Host Complies with OHCI Rev. 1.0 Compatible with the USB Specification version 1.1 Supports full speed up to 12Mbps 1.1.10 IRDA V1.1 The S3C6410 microprocessor provides the following IrDA v1.1 features: • • • Dedicated IrDA for v1.1 (1.152Mbps and 4 Mbps) Supports FIR (4Mbps), Internal 64-byte Tx/Rx FIFO 1.1.11 SERIAL COMMUNICATION The S3C6410X microprocessor provides the following Serial Communication features: 1.1.11.1 UART • • • • • • • • 4-channel UART with DMA-based or interrupt-based operation Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive Supports external clock for the UART operation (EXT_UCLK0, refer to UART chapter) Programmable baud rate Supports IrDA 1.0 SIR (115.2Kbps) mode Loop back mode for testing Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO Non-integer clock divides in Baud clock generation Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-10 S3C6410X66-YB40 Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 PRODUCT OVERVIEW 1.1.11.2 IIC-Bus Interface • 2-ch Multi-Master IIC-Bus • Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbps in the standard mode • up to 400 Kbps in the fast mode 1.1.11.3 SPI Interface • 2ch Serial Peripheral Interface • 64byte buffters for receive/transmit • DMA-based or interrupt-based operation • 50Mbps Master Tx/Rx, 50Mbps Slave Tx, 20Mbps Slave Rx 1.1.11.4 MIPI HSI • A uni-direction high speed serial interface • Supports Tx and Rx • 128 Byte (32-bit x 32) Tx FIFO • 256 Byte (32-bit x 64) Rx FIFO • TX : PCLK bps, RX : up to 100Mbps 1.1.12 MODEM & HOST INTERFACE The S3C6410 microprocessor provides the following Modem Interface features: 1.1.12.1 Parallel Modem Chip Interface • Asynchronous direct SRAM interface style interface • 16-bit parallel bus for data transfer • On-chip 8K bytes internal dual-port SRAM buffer • Interrupt request for data exchange • Programmable interrupt port address • Support from 1.8V to 3.3V I/O voltage range • AP Booting for Modem procedure provides a dual-port memory as a Modem boot memory. 1.1.12.1 Host Interface • Asynchronous indirect SRAM interface style interface (i80 interface) • 16-bit protocol register • On-chip Write FIFO and Read FIFO (each 288-word) to support indirect burst transfer • Single R/W on the SFR/memory in the system memory map • Burst R/W on the SFR/memory in the system memory map • Repeated Burst Write on the SFR/memory in the system memory map • Supports Modem Booting that enables HOST to control AP boot without AP-dedicated nand flash. Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-11 S3C6410X66-YB40 PRODUCT OVERVIEW 1.1.13 GPIO (GENERAL PURPOSE I/O) The S3C6410 microprocessor provides the following GPIO features: • 187 Flexibly configurable GPIO 1.1.14 INPUT DEVICES The S3C6410 microprocessor provides the following Input Devices features: 1.1.14.1 Keypad Interface • Support 8x8 Key Matrix • Provides internal debounce filter 1.1.14.2 A/D Converter and Touch Screen Interface • 8-ch multiplexed ADC • Max. 1M samples/sec and 10-bit/12-bit resolution Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-12 Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 S3C6410X66-YB40 S3C6410X_UM_REV0.00 Email:[email protected] HotTel:+86-21-58998693 PRODUCT OVERVIEW 1.1.15 STORAGE DEVICES The S3C6410 microprocessor provides the following Storage Devices features: 1.1.15.1 SD/MMC Host Controller • • • • • • • Multimedia Card Protocol version 4.0 compatible SD Memory Card Protocol version 2.0 compatible SDIO Card Protocol version 1.0 compatible 128 words FIFO for Tx/Rx DMA based or Interrupt based operation 3 channel SD/MMC Host Controller Support CE-ATA interface 1.1.16 SYSTEM PERIPHERALS The S3C6410 microprocessor provides the following System Peripherals features: 1.1.16.1 DMA controller • • • • 4 General DMAs embedded. 8-channel supported per each DMA; totally 32 channel is supported. Supports memory to memory, peripheral to memory, memory to peripheral, and peripheral to peripheral Burst transfer mode to enhance the transfer rate. 1.1.16.2 Vectored Interrupt Controller • • • • • • • • • Supports for 64 vectored IRQ interrupts Fixed hardware interrupt priority levels Programmable interrupt priority levels Hardware interrupt priority level masking IRQ and FIQ generation Raw interrupt status Interrupt request status Privileged mode support for restricted access Support for ARM v6 processor VIC port, enabling faster interrupt servicing 1.1.16.3 TrustZone Protection Controller • • • Provides a software interface to the protection bits in a secure system in a TrustZone design Protection bits to enable programming of up to 24 areas of memory as secure or non-secure AMBA APB interface Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-13 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.1.16.4 Timer with PWM (Pulse Width Modulation) • • • • 4-ch 32-bit Timer with PWM Programmable duty cycle, frequency, and polarity Dead-zone generation Support external clock source 1.1.16.5 16-bit Watchdog Timer • Interrupt request or system reset at time-out 1.1.16.6 RTC (Real Time Clock) • • • • Full clock features: msec, sec, min, hour, day, week, month, year 32.768kHz operation Alarm interrupts Time-tick interrupts 1.1.17 SECURITY SUB-SYSTEM • • • • • • • AES accelerator : ECB, CBC, CTR mode support DES/3DES accelerator : ECB, CBC mode support SHA-1 Hash engine H/W HMAC support Random Number Generator : PRNG 320-bit generation per 160 cycles FIFO-Rx/Tx : (two 32-word) for input and output streaming. DMA I/F to SDMA1(Security DMA 1) 1.1.18 SYSTEM MANAGEMENT The S3C6410 microprocessor provides the following System Management features: • Little Endian format support 1.1.19 SYSTEM OPERATING FREQUENCIES The S3C6410 microprocessor provides the following System Operation Frequencies features: • • ARM1176JZF-S core clock rate maximum is 533MHz@ TBD V System operating clock generation − Three on-chip PLLs, APLL, MPLL & EPLL − APLL generates an independent ARM operating clock − MPLL generates the system reference clock − EPLL generates clocks for peripheral IPs Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-14 S3C6410X66-YB40 S3C6410X_UM_REV0.00 Email:[email protected] HotTel:+86-21-58998693 PRODUCT OVERVIEW 1.2 POWER MANAGEMENT • • • Clock-off control for individual components Various power-down modes are available such as Idle, Stop and Sleep mode Wake-up by one of external interrupts or by various interrupt sources. Refer system controller manual. 1.3 ELECTRICAL CHARACTERISTICS • Operating Conditions − Supply Voltage for Logic Core: VDD_INT 1.2V, VDD_ARM depends on Operation Frequency − Memory Port 0(VDDM0) : 1.8/2.5V/3.3V − Memory Port1 (VDDM1) : 1.8/2.5V − External I/O Interface: 1.8/2.5/3.3V • Operational Frequency − 533MHz@ TBD V 1.4 PACKAGE • 424-Pin FBGA Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-15 S3C6410X66-YB40 PRODUCT OVERVIEW Email:[email protected] HotTel:+86-21-58998693 S3C6410X_UM_REV0.00 1.5 PIN ASSIGNMENTS 424 FBGA #A1 INDEX MARK 25 24 23 22 21 2019 1817 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE Figure 1-2. Pin Assignments Preliminary product information describe products that are in development, for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice. 1-16