STMICROELECTRONICS L6564T

L6564T
10-pin transition-mode PFC controller
Features
■
Guaranteed for extreme temperature range
(outdoor)
■
Fast “bi-directional” input voltage feedforward
(1/V2 correction)
■
Accurate adjustable output overvoltage
protection
■
Protection against feedback loop
disconnection (latched shutdown)
■
Inductor saturation protection
■
AC brownout detection
■
Low (≤100 µA) startup current
■
6 mA max. operating bias current
■
1% (@ TJ = 25 °C) internal reference voltage
■
-600/+800 mA totem pole gate driver with
active pull-down during UVLO
■
SSOP10
Applications
■
PFC pre-regulators for:
– High-end AC-DC adapter/charger
– Desktop PC, server, web server
– IEC61000-3-2 or JEITA-MITI compliant
SMPS
■
SMPS for LED luminaires
SSOP10 package
Figure 1.
Block diagram
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Doc ID 022671 Rev 1
1/33
www.st.com
33
Contents
L6564T
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2
Feedback failure protection (FFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5
Inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6
Power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 25
7
Application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9
Ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2/33
Doc ID 022671 Rev 1
L6564T
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Summary of L6564 idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SSO10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Doc ID 022671 Rev 1
3/33
List of figures
L6564T
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
4/33
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IC consumption vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
IC consumption vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Vcc Zener voltage vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Startup and UVLO vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Feedback reference vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
E/A output clamp levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UVLO saturation vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OVP levels vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Inductor saturation threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Vcs clamp vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ZCD sink/source capability vs. TJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ZCD clamp level vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
R discharge vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Line drop detection threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VMULTpk - VVFF dropout vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFC_OK threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PFC_OK FFD threshold vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Multiplier characteristics @ VFF = 1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multiplier characteristics @ VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Multiplier gain vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gate drive clamp vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Gate drive output saturation vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Delay to output vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Startup timer period vs. TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output voltage setting, OVP and FFP functions: internal block diagram . . . . . . . . . . . . . . 18
Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristic . . 20
RFF·CFF as a function of 3rd harmonic distortion introduced in the input current . . . . . . . 21
THD optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
THD optimization: standard TM PFC controller (left side) and L6564T (right side) . . . . . . 23
Effect of boost inductor saturation on the MOSFET current and detection method . . . . . . 24
Interface circuits that let DC-DC converter's controller IC disable the L6564T. . . . . . . . . . 25
Demonstration board EVL6564-100W, wide-range mains: electrical schematic . . . . . . . . 27
L6564 100 W TM PFC: compliance with EN61000-3-2 standard . . . . . . . . . . . . . . . . . . . . 28
L6564 100 W TM PFC: compliance with JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . . 28
L6564 100 W TM PFC: input current waveform @230-50 Hz - 100 W load . . . . . . . . . . . . 28
L6564 100W TM PFC: input current waveform @100 V-50 Hz - 100 W load . . . . . . . . . . 28
SSO10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 022671 Rev 1
L6564T
1
Description
Description
The L6564T is a current-mode PFC controller operating in transition mode (TM) and
represents the compact version of the L6563S as it embeds the same driver, reference and
control stages in a very compact 10-pin SO package.
The highly linear multiplier, along with a special correction circuit that reduces crossover
distortion of the mains current, allows wide-range-mains operation with an extremely low
THD even over a large load range.
The output voltage is controlled by means of a voltage-mode error amplifier and an accurate
(1% @TJ = 25 °C) internal voltage reference. The loop stability is optimized by the voltage
feedforward function (1/V2 correction), which in this IC uses a proprietary technique that
also considerably improves line transient response in case of both mains drops and surges
(“bidirectional”).
In addition to overvoltage protection able to control the output voltage during transient
conditions, the IC also provides protection against feedback loop failures or erroneous
settings. Other on-board protection functions allow brownout conditions and boost inductor
saturation to be safely handled.
The totem-pole output stage, capable of a 600 mA source and 800 mA sink current, is
suitable for a high power MOSFET or IGBT drive. This, combined with the other features
and the possibility to operate with ST's proprietary fixed-off-time control, makes the device
an excellent solution for SMPS up to 400 W that requires compliance with EN61000-3-2 and
JEITA-MITI standards.
Doc ID 022671 Rev 1
5/33
Maximum ratings
L6564T
2
Maximum ratings
2.1
Absolute maximum ratings
Table 1.
2.2
Absolute maximum ratings
Symbol
Pin
Parameter
Value
Unit
Vcc
10
IC supply voltage (Icc ≤20 mA)
Self-limited
V
---
1, 3, 6
Max. pin voltage (Ipin ≤1 mA)
Self-limited
V
---
2, 4, 5
Analog inputs and outputs
-0.3 to 8
V
IZCD
7
Zero current detector max. current
-10 (source)
10 (sink)
mA
VFF pin
5
+/- 1750
V
Other pins
1 to 4
6 to 10
Maximum withstanding voltage range
test condition: CDF-AEC-Q100-002
“human body model”
Acceptance criteria: “normal performance”
+/- 2000
V
Value
Unit
Thermal data
Table 2.
Thermal data
Symbol
RthJA
Max. thermal resistance, junction-to-ambient
120
°C/W
Ptot
Power dissipation @TA = 50 °C
0.75
W
Junction temperature operating range
-40 to 150
°C
Storage temperature
-55 to 150
°C
TJ
Tstg
6/33
Parameter
Doc ID 022671 Rev 1
L6564T
Pin connection
3
Pin connection
Figure 2.
Pin connection
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Table 3.
Pin description
n°
Name
1
INV
Function
Inverting input of the error amplifier. The information on the output voltage of the PFC preregulator is fed into the pin through a resistor divider.
The pin normally features high impedance.
2
COMP
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
1) to achieve stability of the voltage control loop and ensure high power factor and low THD.
To avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
below 2.4 V the gate driver output is inhibited (burst-mode operation).
3
MULT
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.
CS
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET’s turn-off.
A second comparison level at 1.7 V detects abnormal currents (e.g. due to boost inductor
saturation) and, on this occurrence, activates a safety procedure that temporarily stops the
converter and limits the stress of the power components.
VFF
Second input to the multiplier for 1/V2 function. A capacitor and a parallel resistor must be
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak
voltage on pin MULT (3), compensates the control loop gain dependence on the mains voltage.
Never connect the pin directly to GND but with a resistor ranging from 100 K ohm (minimum) to
2 M ohm (maximum). This pin is internally connected to a comparator in order to provide the
brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (not latched)
the IC and brings its consumption to a considerably lower level. The IC restarts as the voltage
at the pin goes above 0.88 V.
4
5
Doc ID 022671 Rev 1
7/33
Pin connection
Table 3.
n°
L6564T
Pin description (continued)
Name
Function
6
PFC_OK
PFC pre-regulator output voltage monitoring/disable function. This pin senses the output
voltage of the PFC pre-regulator through a resistor divider and is used for protection purposes.
If the voltage on the pin exceeds 2.5 V the IC stops switching and restarts as the voltage on the
pin falls below 2.4 V. However, if at the same time the voltage of the INV pin falls below 1.66 V,
a feedback failure is assumed. In this case the device is latched off. Normal operation can be
resumed only by cycling Vcc. bringing its value lower than 6 V before moving up to the turn-on
threshold.
If the voltage on this pin is brought below 0.23 V the IC is shut down. To restart the IC the
voltage on the pin must go above 0.27 V. This can be used as a remote on/off control input.
7
ZCD
Boost inductor’s demagnetization sensing input for transition-mode operation. A negative-going
edge triggers MOSFET’s turn-on.
8
GND
Ground. Current return for both the signal part of the IC and the gate driver.
9
GD
Gate driver output. The totem pole output stage is able to drive power MOSFET’s and IGBT’s
with a peak current of 600 mA source and 800 mA sink. The high-level voltage of this pin is
clamped at about 12 V to avoid excessive gate voltages.
10
Vcc
Supply voltage of both the signal part of the IC and the gate driver. Sometimes a small bypass
capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of
the IC.
8/33
Doc ID 022671 Rev 1
L6564T
4
Electrical characteristics
Electrical characteristics
TJ = -40 to 125 °C, VCC = 12 V, CO = 1 nF between pin GD and GND, CFF = 1 µF and
RFF = 1 MΩ between pin VFF and GND; unless otherwise specified.
Table 4.
Electrical characteristics
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
Supply voltage
Vcc
Operating range
After turn-on
VccOn
Turn-on threshold
(1)
11
VccOff
Turn-off threshold
(1)
Vcc for resuming from latch
OVP latched
Vccrestart
Hys
Hysteresis
VZ
Zener voltage
10.3
22.5
V
12
13.2
V
8.7
9.5
10.5
V
5
6
7
V
2.7
V
25
28
V
2.3
Icc = 20 mA
22.5
Supply current
Startup current
Before turn-on, Vcc=10 V
90
180
µA
Quiescent current
After turn-on, VMULT = 1 V
4
5.5
mA
ICC
Operating supply current
@ 70 kHz
5
6.0
mA
320
µA
Idle state quiescent current
VPFC_OK> VPFC_OK_S AND VINV <
VFFD
180
Iqdis
VPFC_OK<VPFC_OK_D
1.5
2.5
µA
VPFC_OK>VPFC_OK_S OR
VCOMP<2.3V
2.2
3.2
µA
VMULT = 0 to 3 V
-0.2
-1
µA
Istart-up
Iq
Iq
Quiescent current
Multiplier input
IMULT
Input bias current
VMULT
Linear operation range
0 to 3
VCLAMP
Internal clamp level
IMULT = 1 mA
∆Vcs
∆VMULT
Output max. slope
Gain (2)
KM
V
9
9.5
V
VMULT = 0 to 0.4 V, VVFF = 1 V
VCOMP = upper clamp
1.33
1.66
V/V
VMULT = 1 V, VCOMP= 4 V
0.375 0.45 0.525
V
TJ = 25 °C
2.475
2.5 2.525
2.45
2.55
Error amplifier
VINV
IINV
Voltage feedback input threshold
10.3 V < Vcc < 22.5 V
Line regulation
Vcc = 10.3 V to 22.5 V
Input bias current
VINV = 0 to 4 V
VINVCLAMP Internal clamp level
Gv
(3)
Voltage gain
V
2
5
mV
-0.2
-1
µA
IINV = 1 mA
8
9
V
Open loop
60
80
dB
Doc ID 022671 Rev 1
9/33
Electrical characteristics
Table 4.
Electrical characteristics (continued)
Symbol
GB
ICOMP
VCOMP
L6564T
Parameter
Test condition
Min. Typ. Max. Unit
Gain-bandwidth product
1
MHz
Source current
VCOMP = 4 V, VINV = 2.4 V
1.5
4
mA
Sink current
VCOMP = 4 V, VINV = 2.6 V
2
4.5
mA
Upper clamp voltage
ISOURCE = 0.5 mA
5.7
6.2
6.7
Burst-mode voltage
(3)
2.3
2.4
2.5
Lower clamp voltage
ISINK = 0.5 mA (3)
2.1
2.25
2.4
Threshold on current sense
(3)
1.6
1.7
1.8
V
E/A input pull-up current
After VCS > VCS_th, before restarting
5
10
13
µA
20
50
100
µs
75
150
350
150
300
700
V
Boost inductor saturation detector
VCS_th
IINV
Startup timer
tSTART_DEL Startup delay
tSTART
First cycle after wake-up
Timer period
µs
Restart after VCS > VCS_th
Current sense comparator
ICS
Input bias current
tLEB
Leading edge blanking
70
Delay to output
td(H-L)
VCSclamp
Vcsofst
Current sense reference clamp
Current sense offset
VCS = 0
1
µA
150
300
ns
70
200
350
ns
0.97
1.08
1.2
V
VMULT = 0 V, VVFF = 3 V
40
70
VMULT = 3 V, VVFF = 3 V
20
VPFC_OK = 0 to 2.6 V
-0.1
VCOMP = upper clamp,
VMULT =1 V, VVFF = 1 V
mV
PFC_OK functions
IPFC_OK
Input bias current
VPFC_OK_C Clamp voltage
IPFC_OK = 1 mA
VPFC_OK_S OVP threshold
(1)
Voltage rising
VPFC_OK_R Restart threshold after OVP
(1)
VPFC_OK_D Disable threshold
(1)
VPFC_OK_D Disable threshold
(1)
VPFC_OK_E Enable threshold
(1)
VPFC_OK_E Enable threshold
(1)
VFFD
10/33
Feedback failure detection
threshold (VINV falling)
µA
9.5
V
2.435
2.5 2.565
V
Voltage falling
2.34
2.4
2.46
V
Voltage falling
0.08
0.40
V
Voltage falling Tj = 25 °C
0.17
0.29
V
Voltage rising
0.10
0.43
V
Voltage rising Tj = 25 °C
0.21
0.27
0.32
V
1.61
1.66
1.71
V
VPFC_OK = VPFC_OK_S
Doc ID 022671 Rev 1
8.5
-1
0.23
L6564T
Table 4.
Electrical characteristics
Electrical characteristics (continued)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
Voltage feedforward
VVFF
Linear operation range
∆V
Dropout VMULTpk-VVFF
1
3
Vcc < VccOn
850
Vcc > or = to VccOn
20
V
mV
∆VVFF
Line drop detection thresh.
Below peak value
30
70
110
mV
∆VVFF
Line drop detection thresh.
Below peak value Tj =25°C
50
70
90
mV
Tj = 25 °C
7.5
10
12.5
RDISCH
Internal discharge resistor
kΩ
5
20
VDIS
Disable threshold
(2)
Voltage falling
0.725
0.8 0.875
V
VEN
Enable threshold
(2)
Voltage rising
0.845 0.88 0.915
V
Zero current detector
VZCDH
Upper clamp voltage
IZCD = 2.5 mA
5.0
5.7
VZCDL
Lower clamp voltage
IZCD = - 2.5 mA
-0.3
0
0.3
V
VZCDA
Arming voltage
(positive-going edge)
1.1
1.4
1.9
V
VZCDT
Triggering voltage
(negative-going edge)
0.5
0.7
1
V
IZCDb
Input bias current
1
µA
VZCD = 1 to 4.5 V
V
IZCDsrc
Source current capability
-2.0
-4
mA
IZCDsnk
Sink current capability
2.0
5
mA
Gate driver
VOL
Output low voltage
Isink = 100 mA
0.6
VOH
Output high voltage
Isource = 5 mA
Isrcpk
Peak source current
-0.6
A
Isnkpk
Peak sink current
0.8
A
9.5
1.4
10.3
V
V
tf
Voltage fall time
30
60
ns
tr
Voltage rise time
45
150
ns
12
15
V
1.2
V
VOclamp
Output clamp voltage
Isource = 5 mA; Vcc = 20 V
UVLO saturation
Vcc= 0 to VCCon, Isink= 2 mA
1. Parameters tracking each other.
(
VMULT ⋅ VCOMP − 2.5
2. The multiplier output is given by: Vcs = VCS_Ofst + K M ⋅
2
3. Parameters tracking each other.
10
)
V
VFF
Doc ID 022671 Rev 1
11/33
Typical electrical performance
L6564T
5
Typical electrical performance
Figure 3.
IC consumption vs. VCC
Figure 4.
100
IC consumption vs. TJ
10
Operating
10
Quiescent
Disabled or
during OV P
1
I c current (m A)
1
I cc [m A]
VCC=12V
Co = 1nF
f =70kHz
Co=1nF
f =70kHz
Tj = 25°C
0.1
Latched off
0.1
Before Start up
0.01
VccOFF
VccON
0.01
0. 001
0
5
10
15
20
25
-50
30
-25
0
25
50
Figure 5.
75
100
125
150
175
Tj (C)
Vcc [V ]
Vcc Zener voltage vs. TJ
Figure 6.
28
Startup and UVLO vs. TJ
13
V CC-ON
12
27
11
26
10
V
V
VCC-OFF
25
9
24
8
23
7
6
22
-50
-25
0
25
50
75
100
125
150
175
-50
Tj (C)
12/33
-25
0
25
50
75
Tj (C)
Doc ID 022671 Rev 1
100
125
150
175
L6564T
Typical electrical performance
Figure 7.
Feedback reference vs. TJ
Figure 8.
2. 6
E/A output clamp levels vs. TJ
7
Uper Clam p
6
VCC = 12V
2.55
5
V COM P (V )
pi n INV (V )
V CC = 12V
2. 5
4
3
Lower Clamp
2
2.45
1
0
2. 4
-50
Figure 9.
-25
0
25
50
75
Tj (C)
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tj (C)
UVLO saturation vs. TJ
Figure 10. OVP levels vs. TJ
2. 5
1
0.9
2. 48
VCC = 0V
0.8
OV P T h
2. 46
P FC_OK l evels (V )
0.7
V
0.6
0.5
0.4
2. 44
2. 42
2. 4
0.3
Resta rt Th
0.2
2. 38
0.1
2. 36
0
-50
-50
-25
0
25
50
75
100
125
150
175
Tj (C)
Doc ID 022671 Rev 1
-25
0
25
50
75
100
125
150
175
Tj (C)
13/33
Typical electrical performance
L6564T
Figure 11. Inductor saturation threshold vs. TJ Figure 12. Vcs clamp vs. TJ
1.9
1. 4
1.8
1.7
1. 3
VCSx (V )
CS pi n (V )
1.6
1.5
VCC = 12V
VCOMP =Upper clamp
1. 2
1.4
1.3
1. 1
1.2
1.1
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
Figure 13. ZCD sink/source capability vs. TJ
125
150
175
Figure 14. ZCD clamp level vs. TJ
8
7
Si nk curren t
Upper Clamp
6
6
4
5
V ZCD pin (V )
2
IZCDsrc (mA)
100
Tj (C)
Tj (C)
V CC = 12V
0
-2
4
VCC = 12V
Izcd =±2.5mV
3
2
Source current
-4
1
-6
0
Lower Cl amp
-8
-50
-1
-25
0
25
50
75
100
125
150
175
-50
14/33
-25
0
25
50
75
Tj (C)
Tj (C)
Doc ID 022671 Rev 1
100
125
150
175
L6564T
Typical electrical performance
Figure 15. R discharge vs. TJ
Figure 16. Line drop detection threshold vs. TJ
20
90
18
80
16
70
14
60
12
mV
kOhm
50
10
40
8
30
6
20
4
10
2
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
Figure 17. VMULTpk - VVFF dropout vs. TJ
100
125
150
175
150
175
Figure 18. PFC_OK threshold vs. TJ
0.4
1. 5
0.35
1
0.3
0. 5
0.25
Th (V )
2
⎯ (m V)
75
Tj (C)
Tj (C)
0
ON
0.2
-0. 5
0.15
-1
0.1
-1. 5
0.05
-2
OFF
0
-50
-25
0
25
50
75
Tj (C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tj (C)
Figure 19. PFC_OK FFD threshold vs. TJ
2
1.9
VFFD Th (V )
1.8
1.7
1.6
1.5
1.4
-50
-25
0
25
50
75
100
12 5
150
175
Tj (C)
Doc ID 022671 Rev 1
15/33
Typical electrical performance
L6564T
Figure 21. Multiplier characteristics
@ VFF = 3 V
Figure 20. Multiplier characteristics
@ VFF = 1 V
700
1. 2
VCOMP
1. 1
V COM P
Upper voltage cl am p
1
600
Upper vo ltage
l
5 .5
5 .0V
0. 9
4.5 V
500
4. 0V
400
0. 8
V CS (V )
V CS (m V)
5. 5V
0. 7
0. 6
0. 5
5. 0V
4. 5V
300
3.5 V
4. 0V
0. 4
200
0. 3
3. 5V
0. 2
3.0
100
3. 0V
0. 1
2. 6V
2.6 V
0
0
0
0.1
0.2
0. 3
0. 4
0.5
0.6
0.7
0. 8
0.9
1
1.1
0
0. 5
1
1. 5
2
V MULT (V )
VM UL T (V )
Figure 22. Multiplier gain vs. TJ
2. 5
3
3. 5
Figure 23. Gate drive clamp vs. TJ
12. 9
0. 5
V CC = 20V
12.85
0. 4
Gai n (1/V )
12. 8
V
VCC = 12V
VCOMP = 4V
VMULT = VFF= 1V
12.75
0. 3
12. 7
0. 2
-50
-25
0
25
50
75
100
125
150
175
12.65
-50
Tj (C)
16/33
Doc ID 022671 Rev 1
-25
0
25
50
75
Tj (C)
100
125
150
175
L6564T
Typical electrical performance
Figure 24. Gate drive output saturation vs. TJ Figure 25. Delay to output vs. TJ
12
300
High level
10
250
TD(H-L) (n s)
V
8
6
200
VCC = 12V
150
4
100
Low level
2
50
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tj (C)
Tj (C)
Figure 26. Startup timer period vs. TJ
450
After OCP
400
350
Ti m e (us)
300
250
Timer
200
150
100
First Cicle
50
0
-50
-25
0
25
50
75
100
125
150
175
Tj (C)
Doc ID 022671 Rev 1
17/33
Application information
L6564T
6
Application information
6.1
Overvoltage protection
Normally, the voltage control loop keeps the output voltage Vo of the PFC pre-regulator
close to its nominal value, set by the ratio of the resistors R1 and R2 of the output divider. A
pin of the device (PFC_OK) has been dedicated to monitor the output voltage with a
separate resistor divider (R3 high, R4 low, see Figure 27). This divider is selected so that
the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value, usually
larger than the maximum Vo that can be expected.
Example: VO = 400 V, VOX = 434 V. Select: R3 = 8.8 MΩ; then: R4 = 8.8 MΩ ·2.5/(434-2.5) =
51 kΩ.
When this function is triggered, the gate drive activity is immediately stopped until the
voltage on the pin PFC_OK drops below 2.4 V. Note that R1, R2, R3 and R4 can be selected
without any constraints. The unique criterion is that both dividers have to sink a current from
the output bus which needs to be significantly higher than the bias current of both INV and
PFC_OK pins.
Figure 27. Output voltage setting, OVP and FFP functions: internal block diagram
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18/33
Doc ID 022671 Rev 1
L6564T
6.2
Application information
Feedback failure protection (FFP)
The OVP function described above handles “normal” overvoltage conditions, i.e. those
resulting from an abrupt load/line change or occurring at startup. In case the overvoltage is
generated by a feedback disconnection, for instance when the upper resistor of the output
divider (R1) fails to open, the comparator detects the voltage at pin INV. If the voltage is
lower than 1.66 V and the OVP is active, the FFP is triggered, the gate drive activity is
immediately stopped, the device is shut down, its quiescent consumption is reduced below
180 µA and the condition is latched as long as the supply voltage of the IC is above the
UVLO threshold. To restart the system it is necessary to recycle the input power, so that the
Vcc voltage of the L6564T goes below 6 V.
The pin PFC_OK doubles its function as a not-latched IC ‘Disable’: a voltage below 0.23 V
shuts down the IC, reducing its consumption below 2 mA. To restart the IC simply let the
voltage at the pin go above 0.27 V.
Note that these functions offer complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK divider failing short or open or a PFC_OK pin floating results in shutting down the
IC and stopping the pre-regulator.
6.3
Voltage feedforward
The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. So does the crossover frequency FC of the overall open-loop gain because the gain
has a single pole characteristic. This leads to a large trade-off in the design.
For example, setting the gain of the error amplifier to get FC = 20 Hz @ 264 Vac means
having FC 4 Hz @ 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow
control loop causes large transient current flow during rapid line or load changes that are
limited by the dynamics of the multiplier output. This limit is considered when selecting the
sense resistor to let the full load power pass under minimum line voltage conditions, with
some margin. But a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage feedforward can compensate for the gain variation with the line voltage and allow
the minimizing of all the above-mentioned issues. It consists in deriving a voltage
proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2
corrector) and providing the resulting signal to the multiplier that generates the current
reference for the inner current control loop (see Figure 28).
Doc ID 022671 Rev 1
19/33
Application information
L6564T
Figure 28. Voltage feedforward: squarer/divider (1/V2) block diagram and transfer characteristic
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In this way a change of the line voltage causes an inversely proportional change of the half
sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the
multiplier output is halved and vice versa) so that the current reference is adapted to the new
operating conditions with (ideally) no need for invoking the slow dynamics of the error
amplifier. Additionally, the loop gain is constant throughout the input voltage range, which
significantly improves dynamic behavior at low line and simplifies loop design.
In fact, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated is affected by a
considerable amount of ripple at twice the mains frequency that causes distortion of the
current reference (resulting in high THD and poor PF); if it is too large there is a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator's output voltage in response to large line
voltage changes. Clearly a trade-off was required.
The L6564T realizes a NEW voltage feed forward that, with a technique that makes use of
just two external parts, strongly minimizes this time constant trade-off issue whichever
voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor
RFF, both connected from pin VFF (#5) to ground, complete an internal peak-holding circuit
that provides a DC voltage equal to the peak of the rectified sine wave applied on pin MULT
(#3). In this way, in case of sudden line voltage rise, CFF is rapidly charged through the low
impedance of the internal diode; in case of line voltage drop, an internal “mains drop”
detector enables a low impedance switch which suddenly discharges CFF avoiding long
settling time before reaching the new voltage level. The discharge of CFF is stopped as its
voltage equals the voltage on the MULT pin or if the voltage on the VFF pin falls below 0.88
V, to prevent the “Brownout protection” function from being improperly activated (see
Section 6.3).
As a result of the VFF pin functionality, an acceptably low steady-state ripple and low current
distortion can be achieved with a limited undershoot or overshoot on the pre-regulator's
output.
20/33
Doc ID 022671 Rev 1
L6564T
Application information
The twice-mains-frequency (2• fL) ripple appearing across CFF is triangular with a peak-topeak amplitude that, with good approximation, is given by:
∆VFF =
2 VMULTpk
1 + 4fLRFF CFF
where fL is the line frequency. The amount of 3rd harmonic distortion introduced by this
ripple, related to the amplitude of its 2• fL component, is:
100
2π fLRFF CFF
D3 % =
Figure 29 shows a diagram that helps choose the time constant RFF·CFF based on the
amount of maximum desired 3rd harmonic distortion. Note that there is a minimum value for
the time constant RFF · CFF below which improper activation of the VFF fast discharge may
occur. In fact, the twice-mains-frequency ripple across CFF under steady-state conditions
must be lower than the minimum line drop detection threshold (∆VFF_min = 40 mV).
Therefore:
2
RFF ⋅ CFF >
VMULTpk _ max
∆VVFF _ min
−1
4 fL _ min
Always connect RFF and CFF to the pin, the IC does not work properly if the pin is either left
floating or connected directly to ground.
Figure 29. RFF·CFF as a function of 3rd harmonic distortion introduced in the input
current
10
1
f L= 50 Hz
R FF · C FF [s]
0.1
f L= 60 Hz
0.01
0.1
1
10
D3 %
Doc ID 022671 Rev 1
21/33
Application information
6.4
L6564T
THD optimizer circuit
The L6564T is provided with a special circuit that reduces the conduction dead-angle
occurring to the AC input current near the zero-crossings of the line voltage (crossover
distortion). In this way the THD (total harmonic distortion) of the current is considerably
reduced.
A major cause of this distortion is the inability of the system to transfer energy effectively
when the instantaneous line voltage is very low. This effect is magnified by the highfrequency filter capacitor placed after the bridge rectifier, which retains some residual
voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input
current flow to temporarily stop.
To overcome this issue the device forces the PFC pre-regulator to process more energy
near the line voltage zero-crossings as compared to that commanded by the control loop.
This results in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge.
Figure 30 shows the internal block diagram of the THD optimizer circuit.
Figure 30. THD optimizer circuit
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Doc ID 022671 Rev 1
L6564T
Application information
Figure 31. THD optimization: standard TM PFC controller (left side) and L6564T (right side)
Input current
Input current
Rectified mains voltage
Rectified mains voltage
Imains
Input
current
Imains
Input
current
Vdrain
MOSFET's drain
voltage
Vdrain
MOSFET's drain
voltage
Essentially, the circuit artificially increases the ON-time of the power switch with a positive
offset added to the output of the multiplier in the proximity of the line voltage zero-crossings.
This offset is reduced as the instantaneous line voltage increases, so that it becomes
negligible as the line voltage moves toward the top of the sinusoid. Furthermore, the offset is
modulated by the voltage on the VFF pin (see Section 6.3) so as to have little offset at low
line, where energy transfer at zero crossings is typically quite good, and a larger offset at
high line where the energy transfer gets worse.
The effect of the circuit is shown in Figure 31, where the key waveforms of a standard TM
PFC controller are compared to those of this chip.
To take maximum benefit from the THD optimizer circuit, the high-frequency filter capacitor
after the bridge rectifier should be minimized, compatibly with EMI filtering needs. A large
capacitance, in fact, introduces a conduction dead-angle of the AC input current in itself even with an ideal energy transfer by the PFC pre-regulator - therefore reducing the
effectiveness of the optimizer circuit.
6.5
Inductor saturation detection
The boost inductor's hard saturation may be a fatal event for a PFC pre-regulator: the
current up-slope becomes so large (50-100 times steeper, see Figure 32) that during the
current sense propagation delay the current may reach abnormally high values. The voltage
drop caused by this abnormal current on the sense resistor reduces the gate-to-source
voltage, so that the MOSFET may work in the active region and dissipate a huge amount of
power, which leads to a catastrophic failure after few switching cycles.
Doc ID 022671 Rev 1
23/33
Application information
L6564T
However, in some applications such as AC-DC adapters, where the PFC pre-regulator is
turned off at light load for energy saving reasons, even a well-designed boost inductor may
occasionally slightly saturate when the PFC stage is restarted because of a larger load
demand. This happens when the restart occurs at an unfavorable line voltage phase, i.e.
when the output voltage is significantly below the rectified peak voltage. As a result, in the
boost inductor the inrush current coming from the bridge rectifier adds up to the switched
current and, furthermore, there is little or no voltage available for demagnetization.
To cope with a saturated inductor, the L6564T is provided with a second comparator on the
current sense pin (CS, pin 4) that stops the IC if the voltage, normally limited within 1.1 V,
exceeds 1.7 V. After that, the IC is attempted to restart by the internal starter circuitry; the
starter repetition time is twice the nominal value to guarantee lower stress for the inductor
and boost diode. Hence, the system safety is considerably increased.
Figure 32. Effect of boost inductor saturation on the MOSFET current and detection method
24/33
Doc ID 022671 Rev 1
L6564T
6.6
Application information
Power management/housekeeping functions
A communication line with the control IC of the cascaded DC-DC converter can be
established via the disable function included in the PFC_OK pin (see Section 6.2 for more
details). This line is typically used to allow the PWM controller of the cascaded DC-DC
converter to shut down the L6564T in case of light load and to minimize the no-load input
consumption. Should the residual consumption of the chip be an issue, it is also possible to
cut down the supply voltage. The interface circuits are shown in Figure 32. Needless to say,
this operation assumes that the cascaded DC-DC converter stage works as the master and
the PFC stage as the slave or, in other words, that the DC-DC stage starts first, it powers
both controllers and enables/disables the operation of the PFC stage.
Figure 33. Interface circuits that let DC-DC converter's controller IC disable the
L6564T
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Another function available is the brownout protection which is basically a not-latched
shutdown function that is activated when a condition of mains undervoltage is detected. This
condition may cause overheating of the primary power section due to an excess of RMS
current. Brownout can also cause the PFC pre-regulator to function in open loop and this
may be dangerous to the PFC stage itself and the downstream converter, should the input
voltage return abruptly to its rated value. Another problem is the spurious restarts that may
occur during converter power-down and that cause the output voltage of the converter not to
decay to zero monotonically. For these reasons it is usually preferable to shut down the unit
in case of brownout. The brownout threshold is internally fixed at 0.8 V and is sensed on pin
VFF (5) during the voltage falling and an 80 mV threshold hysteresis prevents rebounding at
input voltage turn-off. In Table 5 it is possible to find a summary of all of the above
mentioned working conditions that cause the device to stop operating.
Doc ID 022671 Rev 1
25/33
Application information
Table 5.
26/33
L6564T
Summary of L6564 idle states
Typical IC
Condition
Caused or revealed by
IC behavior
Restart condition
UVLO
Vcc < VccOff
Disabled
Vcc > VccOn
90 µA
Feedback
disconnected
PFC_OK > VPFC_OK_S
and
INV < 1.66 V
Latched
Vcc < Vccrestart then
Vcc > VccOn
180 µA
Standby
PFC_OK < VPFC_OK_D
Stop switching
PFC_OK >
VPFC_OK_E
1.5 mA
AC brownout
VFF < VDIS
Stop switching
RUN > VEN
1.5 mA
OVP
PFC_OK > VPFC_OK_S
Stop Switching
PFC_OK <
VPFC_OK_R
2.2 mA
Low
consumption
COMP < 2.4 V
Burst mode
COMP > 2.4V
2.2 mA
Saturated
boost inductor
Vcs > VCS_th
Doubled Tstart
Auto restart
2.2 mA
Doc ID 022671 Rev 1
consumption
L6564T
Application examples and ideas
7
Application examples and ideas
Figure 34. Demonstration board EVL6564-100W, wide-range mains: electrical schematic
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27/33
Application examples and ideas
L6564T
Figure 35. L6564 100 W TM PFC: compliance
with EN61000-3-2 standard
Meas ured value
Figure 36. L6564 100 W TM PFC: compliance
with JEITA-MITI standard
EN61000-3- 2 class- D limits
Measur ed value
JEITA-MITI Class-Dlim its
10
Harmonic Current [A]
Harmonic Current [A]
1
0.1
0.01
0.001
1
0.1
0.01
0.001
0.0001
0.0001
1
3
5
7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
1
3 5
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
Harmonic Order [n]
Harmonic Order [n]
Figure 37. L6564 100 W TM PFC: input current Figure 38. L6564 100W TM PFC: input current
waveform @230-50 Hz - 100 W load
waveform @100 V-50 Hz - 100 W
load
28/33
Doc ID 022671 Rev 1
L6564T
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 6.
SSO10 mechanical data
Databook (mm.)
Dim.
Min.
Typ.
A
Max.
1.75
A1
0.10
A2
1.25
b
0.31
0.51
c
0.17
0.25
D
4.80
4.90
5
E
5.80
6
6.20
E1
3.80
3.90
4
e
0.25
1
h
0.25
0.50
L
0.40
0.90
K
0°
8°
Doc ID 022671 Rev 1
29/33
Package mechanical data
L6564T
Figure 39. SSO10 package dimensions
8140761 rev. A
30/33
Doc ID 022671 Rev 1
L6564T
9
Ordering codes
Ordering codes
Table 7.
Ordering information
Order codes
Package
L6564TD
Packing
Tube
SSO10
L6564TDTR
Tape and reel
Doc ID 022671 Rev 1
31/33
Revision history
10
L6564T
Revision history
Table 8.
32/33
Document revision history
Date
Revision
18-Jan-2012
1
Changes
Initial release
Doc ID 022671 Rev 1
L6564T
Please Read Carefully:
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www.st.com
Doc ID 022671 Rev 1
33/33
AN3022
Application note
100 W transition-mode PFC pre-regulator with the L6564
Introduction
This application note describes the demonstration board based on the transition-mode PFC
controller L6564 and presents the results of its bench demonstration. The board implements
a 100 W, wide-range mains input, PFC pre-conditioner suitable for ballast, adapters, flat
screen displays, and all SMPS required to meet the IEC61000-3-2 or the JEITA-MITI
regulation.
The L6564 is a current-mode PFC controller operating in transition mode (TM). Available in
an innovative and small package, the SSOP-10, the L6564 offers improved performance
and protection with respect to equivalent 8-pin TM controllers.
Figure 1.
December 2010
EVL6564-100W: L6564 100W TM PFC demonstration board
Doc ID 16106 Rev 2
1/32
www.st.com
Contents
AN3022
Contents
1
Main characteristics and circuit description . . . . . . . . . . . . . . . . . . . . . 4
1.1
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Test results and significant waveforms . . . . . . . . . . . . . . . . . . . . . . . . 10
4
3.1
Harmonic content measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2
Inductor current in TM and L6564 THD optimizer . . . . . . . . . . . . . . . . . . 13
3.3
Voltage feed-forward and brownout functions . . . . . . . . . . . . . . . . . . . . . 15
3.4
PFC_OK pin and feedback failure (open loop) protection . . . . . . . . . . . . 21
Power management and housekeeping functions . . . . . . . . . . . . . . . . 23
4.1
Layout hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
EMI filtering and conducted EMI pre-compliance measurements . . . 26
6
PFC coil specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1
General description and characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4
Winding characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.5
Mechanical aspect and pin numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.6
Unit identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
Doc ID 16106 Rev 2
AN3022
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
EVL6564-100W: L6564 100W TM PFC demonstration board . . . . . . . . . . . . . . . . . . . . . . . 1
EVL6564-100W TM PFC demonstration board: electrical schematic. . . . . . . . . . . . . . . . . . 6
EVL6564-100W TM PFC: compliance to EN61000-3-2 standard. . . . . . . . . . . . . . . . . . . . 10
EVL6564-100W TM PFC: compliance to JEITA-MITI standard . . . . . . . . . . . . . . . . . . . . . 10
EVL6564-100W TM PFC: input current waveform at 230 V - 50 Hz 100 W load . . . . . . . . 11
EVL6564-100W TM PFC: input current waveform at 100 V - 50 Hz 100 W load . . . . . . . . 11
EVL6564-100W TM PFC: power factor vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EVL6564-100W TM PFC: THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
EVL6564-100W TM PFC: efficiency vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EVL6564-100W TM PFC: average efficiency acc. to ES-2. . . . . . . . . . . . . . . . . . . . . . . . . 12
EVL6564-100W TM PFC: static Vout regulation vs. output power . . . . . . . . . . . . . . . . . . . 12
EVL6564-100W TM PFC: Vds & inductor current at 100 Vac - 50 Hz - full load . . . . . . . . 13
EVL6564-100W TM PFC: Vds & inductor current at 100 Vac - 50 Hz - full load (Detail) . . 13
EVL6564-100W TM PFC: Vds & inductor current at 230Vac - 50 Hz - full load . . . . . . . . . 14
EVL6564-100W TM PFC: Vds & inductor current at 230Vac - 50 Hz - full load (Detail). . . 14
EVL6564-100W TM PFC: Vcs & inductor current at 100 Vac - 50 Hz - full load . . . . . . . . 15
EVL6564-100W TM PFC: Vcs & inductor current at 230 Vac - 50 Hz - full load . . . . . . . . 15
L6562A input mains surge 90 Vac to 140 Vac – no VFF input . . . . . . . . . . . . . . . . . . . . . . 16
EVL6564 100W TM PFC: input mains surge 90 Vac to 140 Vac CFF = 1 µF, RFF = 1 MΩ16
L6562A input mains dip 140 Vac to 90 Vac – no VFF input . . . . . . . . . . . . . . . . . . . . . . . . 17
EVL6564-100W TM PFC: Input mains dip 140 Vac to 90 Vac CFF = 1µF, RFF = 1 MΩ. . .17
L6563 input current at 100 Vac-50Hz CFF = 0.47 µF, RFF = 390 kΩ . . . . . . . . . . . . . . . . . . .18
EVL6564-100W TM PFC: input current at 100 Vac-50Hz CFF = 1 µF, RFF = 1 MΩ . . . . . .18
EVL6564-100W startup attempt at 80 Vac - 60 Hz – full load . . . . . . . . . . . . . . . . . . . . . . 19
EVL6564-100W startup with slow input voltage increasing – full load . . . . . . . . . . . . . . . . 20
EVL6564-100W turn-off with slow input voltage decreasing – full load . . . . . . . . . . . . . . . 20
EVL6564-100W startup at 90 Vac -60 Hz – full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EVL6564-100W startup at 265 Vac-50 Hz – full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
EVL6564-100W load transient at 115 Vac - 60 Hz - full load to no load. . . . . . . . . . . . . . . 22
EVL6564-100W open loop at 115 Vac - 60 Hz - full load . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interface circuits that let DC-DC converter’s controller IC disable the L6564 . . . . . . . . . . . 23
EVL6564-100W PCB layout (SMT side view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
EVL6564-100W CE peak measurement at 100Vac - 50Hz Full Load phase . . . . . . . . . . . 26
EVL6564-100W CE peak measurement at 100Vac - 50Hz Full Load neutral . . . . . . . . . . 26
EVL6564-100W CE peak measurement at 230Vac - 50Hz Full Load phase . . . . . . . . . . . 27
EVL6564-100W CE peak measurement at 230Vac - 50Hz Full Load neutral . . . . . . . . . . 27
Electrical diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 16106 Rev 2
3/32
Main characteristics and circuit description
1
AN3022
Main characteristics and circuit description
The main characteristics of the SMPS are:
●
Line voltage range: 90 to 265 Vac
●
Minimum line frequency (fL): 47 Hz
●
Regulated output voltage: 400 V
●
Rated output power: 100 W
●
Maximum 2 fL output voltage ripple: 20 V peak-to-peak
●
Hold-up time: 10 ms (VDROP after hold-up time is 300 V)
●
Minimum switching frequency: 40 kHz
●
Minimum estimated efficiency 92% (at Vin = 90 Vac, Pout = 100 W)
●
Maximum ambient temperature: 50 °C
●
PCB type and size: Single-side, 35 µm, CEM-1, 90 x 83 mm
This demonstration board implements a 100 W power factor correction (PFC) pre-regulator,
continuous power, on a regulated 400 V rail from a wide range mains voltage and provides
for the reduction of the mains harmonics, which allows meeting the European EN61000-3-2
or the Japanese JEITA-MITI standard. The regulated output voltage is typically the input for
the cascaded isolated DC-DC converter that provides the output rails required by the load.
The board is designed to allow full-load operation in still air.
The power stage of the PFC is a conventional boost converter, connected to the output of
the rectifier bridge D1. It is completed by the coil L2, the diode D3 and the capacitor C6. The
boost switch is represented by the power MOSFET Q1. The NTC R1 limits the inrush
current at switch-on. It is connected to the DC rail, in series to the output electrolytic
capacitor, in order to improve the efficiency during low line operation because the RMS
current flowing into the output stage is lower than current flowing into the input stage at the
same input voltage, thus increasing efficiency. The board is equipped with an input EMI filter
necessary to filter the commutation noise coming from the boost stage.
At startup the L6564 is powered by the capacitor C11 that is charged via the resistors R7
and R16. Then the L2 secondary winding and the charge pump circuit (C7, R4, D4 and D5)
generate the Vcc voltage, powering the L6564 during normal operation. The L2 secondary
winding is also connected to the L6564 pin #7 (ZCD) through the resistor R5. Its purpose is
to supply the information that L2 has demagnetized, needed by the internal logic for
triggering a new switching cycle.
The divider R9, R12, R17 and R19 provides the L6564 multiplier with the information of the
instantaneous mains voltage that is used to modulate the peak current of the boost.
The resistors R2, R8, R10 with R13 and R14 are dedicated to sense the output voltage and
send to the L6564 the feedback information necessary to regulate the output voltage. The
components C9, R18 and C8 constitute the error amplifier compensation network necessary
to keep the required loop stability.
The peak current is sensed by resistors R25 and R26 in series to the MOSFET and the
signal is fed into pin #4 (CS) of the L6564. On pin #4 (CS) there is also a small filter
composed of R24 and C15.
The capacitor C13 and the parallel resistor R32 complete an internal peak-holding circuit
that obtains information on the RMS mains voltage. The voltage signal at pin #5, which is a
4/32
Doc ID 16106 Rev 2
AN3022
Main characteristics and circuit description
DC level equal to the peak voltage on pin #3 (MULT), is fed to a second input to the
multiplier for the 1/V2 function necessary to compensate the control loop gain dependence
on the mains voltage. Additionally, the pin #5 (VFF) is internally connected to a comparator
providing brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down
(does not latch) the IC and brings its consumption to a considerably lower level. The L6564
restarts as the voltage at the pin rises above 0.88 V.
The divider R3, R6, R11 and R15 provides the L6564 pin #6 (PFC_OK) with the information
regarding the output voltage level. This information is required by the L6564 output voltage
monitoring and disable functions, used for PFC protection purposes.
If the voltage on pin #6 (PFC_OK) exceeds 2.5 V, the IC stops switching and restarts as the
voltage on the pin falls below 2.4 V, implementing the dynamic OVP and preventing the
output voltage from becoming excessive in case of transients because of the slow response
of the error amplifier. However, if at the same time, the voltage of the INV pin falls below 1.66
V (typ.) that of the pin PFC_OK, a feedback failure is assumed. In this case the device is
latched off. Normal operation can be resumed only by cycling Vcc, bringing its value lower
than 6 V before rising up to the turn-on threshold.
Additionally, if the voltage on pin #6 (PFC_OK) is tied below 0.23 V, the L6564 shuts down.
To restart the L6564, the voltage on pin #6 (PFC_OK) has to increase above 0.27 V. This
function can be used as a remote on/off control input.
To allow interfacing the board with a D2D converter, the connector J3 allows powering the
L6564 with an external Vcc and also controlling the IC operation via pin #6 (PFC_OK).
Doc ID 16106 Rev 2
5/32
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Main characteristics and circuit description
AN3022
Electrical diagram
EVL6564-100W TM PFC demonstration board: electrical schematic
!-V
Bill of material
Table 1.
EVL6564-100W TM PFC bill of material
Doc ID 16106 Rev 2
Des.
Part type/part value
Case/package
Description
C1
470N
DWG
X2 - FLM cap - R46-I 3470--M1-
Arcotronics
C4
470N
DWG
X2 - FLM cap - R46-I 3470--M1-
Arcotronics
C5
470N - 400V
DWG
400V - FLM cap - B32653A4474
Epcos
C6
47µF - 450V
C7
4N7
1206
100V CERCAP - general purpose
AVX
C8
680N
1206
25V CERCAP - general purpose
AVX
C9
68N
0805
50V CERCAP - general purpose
AVX
C10
100N
1206
50V CERCAP - general purpose
AVX
C11
47uF-50V
Dia. 5X10 mm
C12
2N2
1206
50V CERCAP - general purpose
AVX
C13
1uF
0805
25V CERCAP - general purpose
AVX
C15
220p
0805
50V CERCAP - general purpose
AVX
C16
2N2
0805
50V CERCAP - general purpose
AVX
D1
GBU4J
STYLE GBU
D2
1N4005
D3
Dia. 18X31.5 mm 450V - aluminium ELCAP - ED series - 105°C
50V - aluminium ELCAP - YXF series - 105°C
Supplier
Bill of material
7/32
2
Nippon-chemicon
Rubycon
Single phase bridge rectifier
Vishay
DO-41
Rectifier - general purpose
Vishay
STTH2L06
DO-41
Ultrafast high voltage rectifier
D4
LL4148
MINIMELF
D5
BZX79-C18
DO - 35
F1
FUSE 4A
DWG
Fuse T4A - time delay
HS1
HEAT-SINK
DWG
Heat sink for D1& Q1
JPX3
0R0
1206
SMD jumper
J1
MKDS 1,5/ 3-5,08
DWG
PCB term. block, screw conn., pitch 5mm - 3 W.
STMicroelectronics
High speed signal diode
Vishay
Zener diode
Vishay
Wichmann
Phoenix Contact
AN3022
VISHAY
EVL6564-100W TM PFC bill of material (continued)
Doc ID 16106 Rev 2
Part type/part value
Case/package
Description
J2
MKDS 1,5/ 2-5,08
DWG
PCB term. block, screw conn., pitch 5mm - 2 W.
J3
CON3
DWG
PCB term. block, pitch 2.5mm - 3 W.
L1
HF2826-203Y1R5-T01
DWG
Input emi filter - 20mH-1.5A
TDK
L2
SRW2620PQ-X22V102
DWG
PFC inductor - 0.52mH (X08141-01-B)
TDK
Q1
STF7NM50N
TO-220FP
R1
NTC 2R5-S237
DWG
NTC resistor P/N B57237S0259M000
EPCOS
R2
1M0
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R8
1M0
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R10
1M0
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R3
3M3
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R6
3M3
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R4
100R
1206
SMD standard film res - 1/4W - 5% - 250ppm/°C
Vishay
R5
68K
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R7
180K
1206
SMD standard film res - 1/4W - 5% - 250ppm/°C
Vishay
R16
180K
1206
SMD standard film res - 1/4W - 5% - 250ppm/°C
Vishay
R9
2M7
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R12
2M7
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R11
2M2
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R13
62K
0805
SMD standard film res - 1/8W - 1% - 100ppm/°C
Vishay
R14
27K
0805
SMD standard film res - 1/8W - 1% - 100ppm/°C
Vishay
R15
51K
0805
SMD standard film res - 1/8W - 1% - 100ppm/°C
Vishay
R17
1M5
1206
SMD standard film res - 1/4W - 1% - 100ppm/°C
Vishay
R18
82K
0805
SMD standard film res - 1/8W - 5% - 250ppm/°C
Vishay
R19
51K
1206
SMD standard film res - 1/4W - 5% - 250ppm/°C
Vishay
R21
27R
1206
SMD standard film res - 1/4W - 5% - 250ppm/°C
Vishay
N-channel power mosfet
Supplier
Phoenix Contact
Molex
STMicroelectronics
Bill of material
8/32
Des.
AN3022
Table 1.
EVL6564-100W TM PFC bill of material (continued)
Des.
Part type/part value
Case/package
Description
R22
100K
0805
SMD standard film res - 1/8W - 5% - 250ppm/°C
Vishay
R24
220R
PTH
SFR25 AXIAL STAND. FILM RES - 0.4W - 5% - 250ppm/°C
Vishay
R25
0R47
PTH
SFR25 AXIAL STAND. FILM RES - 0.4W - 5% - 250ppm/°C
Vishay
R26
0R68
PTH
SFR25 AXIAL STAND. FILM RES - 0.4W - 5% - 250ppm/°C
Vishay
R30
1K
0805
SMD standard film res - 1/8W - 5% - 250ppm/°C
Vishay
R31
10R
0805
SMD standard film res - 1/8W - 5% - 250ppm/°C
Vishay
R32
1M0
0805
SMD standard film res - 1/8W - 1% - 250ppm/°C
Vishay
U1
L6564D
SSOP-10
Transition-mode PFC controller
Supplier
Bill of material
9/32
Table 1.
STMicroelectronics
Doc ID 16106 Rev 2
AN3022
Test results and significant waveforms
AN3022
3
Test results and significant waveforms
3.1
Harmonic content measurement
One of the main purposes of a PFC pre-conditioner is the correction of input current
distortion, decreasing the harmonic contents below the limits of the relevant regulations.
Therefore, this demonstration board has been tested at full load at both the nominal input
voltage mains according to the European standard EN61000-3-2 Class-D and Japanese
standard JEITA-MITI Class-D.
The circuit is able to reduce the harmonics well below the limits of both regulations from full
load down to light load (measurements are given in Figure 3 and Figure 4). Please note that
all measures and waveforms have been done using a Pi-filter (using a 20 mH common
mode choke and two 470NF-X2 filter capacitors) to filter the noise coming from the circuit.
Figure 3.
EVL6564-100W TM PFC:
compliance to EN61000-3-2
standard
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Figure 4.
(1&ODVV 'OLP LWV
0HDVXUHGYDOXH
-(,7$0,7,&ODVV 'OLP LWV
+DUPRQLF&XUUHQW>[email protected]
+DUPRQLF&XUUHQW>[email protected]
EVL6564-100W TM PFC:
compliance to JEITA-MITI
standard
+DUPRQLF2UGHU>[email protected]
+DUPRQLF2UGHU>[email protected]
!-V
Vin = 230 Vac - 50 Hz, Pout = 100 W
Vin = 100 Vac - 50 Hz, Pout = 100 W
THD = 3.89%, PF = 0.983
THD = 3.21%, PF = 0.999
10/32
Doc ID 16106 Rev 2
!-V
AN3022
Test results and significant waveforms
For user reference, waveforms of the input current and voltage at the nominal input voltage
mains and different load conditions are given in Figure 5 and Figure 6.
Figure 5.
EVL6564-100W TM PFC: input
current waveform at 230 V - 50 Hz
100 W load
Figure 6.
EVL6564-100W TM PFC: input
current waveform at 100 V - 50 Hz
100 W load
CH1: Vout
CH1: Vout
CH2: I_AC
CH2: I_AC
CH3: V bridge
CH3: V bridge
The power factor (PF) and the total harmonic distortion (THD) have been measured too and
the results are given in Figure 7 and Figure 8. As visible, the PF remains close to unity
throughout the input voltage mains and the total harmonic distortion is very low.
Figure 7.
EVL6564-100W TM PFC:
power factor vs. output power
Figure 8.
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4($;=
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EVL6564-100W TM PFC:
THD vs. output power
3)#9DF+]
3)#9DF+]
3RXW :
3RXW :
3RXW :
3RXW :
2XWSXW3RZHU
!-V
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The efficiency, measured according to the ES-2 requirements, is very good at all load and
line conditions (Figure 9). At full load it is always higher than 94%, making this design
suitable for high-efficiency power supplies. The average efficiency, calculated according to
the ES-2 requirements at different nominal mains voltages, is given in Figure 10.
Doc ID 16106 Rev 2
11/32
Test results and significant waveforms
Figure 9.
AN3022
EVL6564-100W TM PFC:
efficiency vs. output power
Figure 10. EVL6564-100W TM PFC:
average efficiency acc. to ES-2
(IILFLHQF\YV2XWSXW3RZHU
$YHUDJH(IILFLHQF\DFFWR(6
$9*(IILFLHQF\>@
(IILFLHQF\>@
(II#9DF+]
(II#9DF+]
3RXW :
3RXW :
9DF+]
9DF+]
(II#9DF+]
3RXW :
9DF+]
3RXW :
2XWSXW3RZHU
!-V
9LQBDF>[email protected]
$&LQSXWYROWDJH
!-V
Figure 11. EVL6564-100W TM PFC: static Vout
regulation vs. output power
2XWSXW9ROWDJHYV2XWSXW3RZHU
2XWSXW9ROWDJH>[email protected]
9RXW#9DF+]
9RXW#9DF+]
9RXW#9DF+]
3RXW :
3RXW :
3RXW :
3RXW :
2XWSXW3RZHU
!-V
The measured output voltage at different line and static load conditions is given in Figure 11.
As visible, the voltage is very stable over the entire input voltage and output load range.
12/32
Doc ID 16106 Rev 2
AN3022
3.2
Test results and significant waveforms
Inductor current in TM and L6564 THD optimizer
Figure 12 through 17 show the waveforms relevant to the inductor current at different
voltage mains. As visible in Figure 12 and Figure 14 the peak inductor current waveform
over a line half-period follows the MULT (pin #3) at both input mains voltage and therefore
the line current is in phase with the input AC voltage, giving low distortion of the current
waveform and high power factor. On both the drain voltage traces, close to the zero-crossing
points of the sine wave, it is possible to note the action of the THD optimizer embedded in
the L6564. It is a circuit that minimizes the conduction dead-angle occurring in the AC input
current near the zero-crossings of the line voltage (crossover distortion). In this way, the
THD (total harmonic distortion) of the current is considerably reduced. A major cause of this
distortion is the inability of the system to transfer energy effectively when the instantaneous
line voltage is very low. This effect is magnified by the high-frequency filter capacitor placed
after the bridge rectifier, which retains some residual voltage that causes the diodes of the
bridge rectifier to be reverse-biased and the input current flow to temporarily stop. To
overcome this issue, the device forces the PFC pre-regulator to process more energy near
the line voltage zero-crossings as compared to that commanded by the control loop. This
results in both minimizing the time interval where energy transfer is lacking and fully
discharging the high-frequency filter capacitor after the bridge. Essentially, the circuit
artificially increases the ON-time of the power switch with a positive offset added to the
output of the multiplier in the proximity of the line voltage zero-crossings. This offset is
reduced as the instantaneous line voltage increases, so that it becomes negligible as the
line voltage moves toward the top of the sinusoid. Furthermore, the offset is modulated by
the voltage on the VFF pin so as to have little offset at low line, where energy transfer at
zero-crossings is typically quite good, and a larger offset at high line where the energy
transfer gets worse. To derive maximum benefit from the THD optimizer circuit, the highfrequency filter capacitors after the bridge rectifier should be minimized, to be compatible
with EMI filtering needs. A large capacitance, in fact, introduces a conduction dead-angle of
the AC input current in itself, thus reducing the effectiveness of the optimizer circuit.
Figure 12. EVL6564-100W TM PFC: Vds &
Figure 13. EVL6564-100W TM PFC: Vds &
inductor current at 100 Vac - 50 Hz inductor current at 100 Vac - 50 Hz full load
full load (Detail)
CH1: Q1 drain voltage
CH1: Q1 drain voltage
CH2: MULT voltage - Pin #3
CH2: MULT voltage - Pin #3
CH4: L2 inductor current
CH4: L2 inductor current
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Test results and significant waveforms
AN3022
In Figure 13 and Figure 15 the detail of the waveforms at the switching frequency allows
measuring the operating frequency and the current peak at the top of the input sine wave
during operation at 100 Vac and 230 Vac. The multiplier waveform has been captured as
reference.
Figure 15. EVL6564-100W TM PFC: Vds &
Figure 14. EVL6564-100W TM PFC: Vds &
inductor current at 230Vac - 50 Hz inductor current at 230Vac - 50 Hz full load
full load (Detail)
CH1: Q1 drain voltage
CH1: Q1 drain voltage
CH2: MULT voltage - Pin #3
CH2: MULT voltage - Pin #3
CH4: L2 inductor current
CH4: L2 inductor current
In Figure 16 and Figure 17 the detail of the waveforms at the switching frequency allows
viewing the operation of the transition mode control. Once the inductor has transferred all
the energy stored, a falling edge on the ZCD pin (pin #5) is detected which triggers a new
on-time by setting the gate drive to high. As soon as the current signal on the CS pin (pin #4)
has reached the level programmed by the internal multiplier circuitry according to the input
mains instantaneous voltage and the error amplifier output level, the gate drive is set low
and MOSFET conduction is stopped. A following off-time transfers the energy stored in the
inductor into the output capacitor and to the load. At the end of the current conduction a new
demagnetization is detected by the ZCD pin that provides for a new on-time of the MOSFET.
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Doc ID 16106 Rev 2
AN3022
Test results and significant waveforms
Figure 16. EVL6564-100W TM PFC: Vcs &
Figure 17. EVL6564-100W TM PFC: Vcs &
inductor current at 100 Vac - 50 Hz inductor current at 230 Vac - 50 Hz full load
full load
CH1: GD - Pin #9
CH1: GD - Pin #9
CH2: ZCD - Pin #7
CH2: ZCD - Pin #7
CH3: CS - Pin #4
CH3: CS - Pin #4
CH4: L2 inductor current
CH4: L2 inductor current
3.3
Voltage feed-forward and brownout functions
The power stage gain of PFC pre-regulators varies with the square of the RMS input
voltage. Because the gain has a single pole characteristic, the crossover frequency fc varies
with the square of the RMS input voltage. This leads to large trade-off in the design. For
example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac means having
fc = 4 Hz at 88 Vac, resulting in a sluggish control dynamics. Additionally, the slow control
loop causes large transient current flow during rapid line or load changes that are limited by
the dynamics of the multiplier output. This limit is considered when selecting the sense
resistor to let the full load power pass under minimum line voltage conditions, with some
margin. However a fixed current limit allows excessive power input at high line, whereas a
fixed power limit requires the current limit to vary inversely with the line voltage.
Voltage feed-forward can compensate for the gain variation with the line voltage and allow
overcoming all of the above-mentioned issues. It consists of deriving a voltage proportional
to the input RMS voltage, feeding this voltage into a squared/divider circuit (1/V2 corrector)
and providing the resulting signal to the multiplier that generates the current reference for
the inner current control loop.
In this way, a change of the line voltage causes an inversely-proportional change of the half
sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the
multiplier, the output is halved and vice versa) so that the current reference is adapted to the
new operating conditions with (ideally) no need for invoking the slow dynamics of the error
amplifier. Additionally, the loop gain is constant throughout the input voltage range, which
improves significantly dynamic behavior at low line and simplifies loop design.
Actually, with other PFCs embedding the voltage feed-forward, deriving a voltage
proportional to the RMS line voltage implies a form of integration, which has its own time
constant. If it is too small, the voltage generated is affected by a considerable amount of
Doc ID 16106 Rev 2
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Test results and significant waveforms
AN3022
ripple at twice the mains frequency that causes distortion of the current reference (resulting
in high THD and poor PF). If it is too large, there is a considerable delay in setting the right
amount of feed-forward, resulting in excessive overshoot and undershoot of the preregulator’s output voltage in response to large line voltage changes. Clearly a trade-off was
required.
The L6564 implements an innovative voltage feed-forward which, with a technique that
makes use of just two external parts, overcomes this time constant trade-off issue whichever
voltage change occurs on the mains (either a surge or drop). A capacitor CFF and a resistor
RFF, both connected from the pin VFF (pin #5) to ground, complete an internal peak-holding
circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin
MULT (pin #3). In this way, in case of a sudden line voltage rise, CFF is rapidly charged
through the low impedance of the internal diode. In case of a line voltage drop, an internal
“mains drop” detector enables a low impedance switch which suddenly discharges CFF
avoiding a long settling time before reaching the new voltage level. Consequently, an
acceptably low steady-state ripple and low current distortion can be achieved without any
considerable undershoot or overshoot on the pre-regulator’s output like in systems with no
feed-forward compensation.
Figure 18. L6562A input mains surge 90 Vac to Figure 19. EVL6564 100W TM PFC: input
mains surge 90 Vac to 140 Vac
140 Vac – no VFF input
CFF = 1 µF, RFF = 1 MΩ
CH1: Vout
CH1: Vout
CH2: MULT (pin #3)
CH2: MULT (pin #3)
CH3: VFF (pin #5)
CH4: I_AC
CH4: I_AC
Figure 19 shows the behavior of the EVL6564-100W demonstration board in case of an
input voltage surge from 90 to 140Vac. In the diagram it is evident that the VFF function
provides for the stability of the output voltage which is not affected by the input voltage
surge. In fact, thanks to the VFF function, the compensation of the input voltage variation is
very fast and the output voltage remains stable at its nominal value. The opposite is
confirmed in Figure 18 which shows the behavior of a PFC using the L6562A and delivering
the same output power. The controller cannot compensate a mains surge and the output
voltage stability is guarantee by the feedback loop only. Unfortunately, as previously stated,
its bandwidth is narrow and thus the output voltage has a significant deviation from the
nominal value. The circuit has the same behavior in case of a mains surge at any input
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Doc ID 16106 Rev 2
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Test results and significant waveforms
voltage, and it is not affected if the input mains surge happens at any point on the input sine
wave.
Figure 21 shows the circuit behavior for a mains dip. As previously described, the internal
circuitry has detected the decrease of the mains voltage and it has activated the CFF
internal fast discharge. As visible, in that case, the output voltage changes but in a few
mains cycles it comes back to the nominal value. The situation is different if we check the
performance of a controller without the VFF function. Figure 20 shows the behavior of a PFC
using the L6562A delivering similar output power. For a mains dip from 140 Vac to 90 Vac,
the output voltage fluctuation is not very different, but the output voltage requires a longer
time to restore the original value.
Testing with a wider voltage variation (e.g. 265 Vac to 90 Vac), the output voltage fluctuation
of a PFC without the voltage feed-forward fast discharging is amplified and it requires more
time to recover its original set value (400 V).
Figure 20. L6562A input mains dip 140 Vac to
90 Vac – no VFF input
Figure 21. EVL6564-100W TM PFC: Input
mains dip 140 Vac to 90 Vac
CFF = 1µF, RFF = 1 MΩ
CH1: Vout
CH1: Vout
CH2: MULT (pin #3)
CH2: MULT (pin #3)
CH3: VFF (pin #5)
CH4: I_AC
CH4: I_AC
Doc ID 16106 Rev 2
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Test results and significant waveforms
AN3022
Comparing Figure 22 and Figure 23 we can see that the input current of Figure 23 has a
better shape and the 3rd harmonic current distortion is not noticeable. This demonstrates
the benefits of the new voltage feed-forward circuit integrated in the L6564, allowing to get a
fast response to mains disturbances but using a quite long VFF time constant provides also
very low THD and high PF at the same time as confirmed by the measurements below the
waveforms.
Figure 22. L6563 input current at 100 Vac-50Hz Figure 23. EVL6564-100W TM PFC: input
CFF = 0.47 µF, RFF = 390 kΩ
current at 100 Vac-50Hz CFF = 1 µF,
RFF = 1 MΩ
THD: 5.15% - 3RD Harmonic: 43 mA
THD: 3.17% - 3RD Harmonic: 30.5 mA
CH2: MULT (pin #3)
CH2: MULT (pin #3)
CH3: VFF (pin #5)
CH3: VFF (pin #5)
CH4: I_AC
CH4: I_AC
Another function integrated in the L6564 is the brownout protection which is basically a nonlatched shutdown function that must be activated when a mains undervoltage condition is
detected. This abnormal condition may cause overheating of the primary power section due
to an excess of RMS current. Brownout can also cause the PFC pre-regulator to work in
open loop and this could be dangerous to the PFC stage itself and the downstream
converter, should the input voltage return abruptly to its rated value. A further problem is the
spurious restarts that may occur during converter power-down which cause the output
voltage of the converter to not decay to zero monotonically. For these reasons it is usually
preferable to shut down the unit in case of brownout.
Brownout thresholds are set internally at 0.88 V (typ.) for enabling and 0.8 V (typ.) for
disabling the L6564. Sensing of the input mains condition is done by an internal comparator
connected to pin VFF (pin #5) which delivers a voltage signal proportional to the input mains.
18/32
Doc ID 16106 Rev 2
AN3022
Test results and significant waveforms
Figure 24. EVL6564-100W startup attempt at
80 Vac - 60 Hz – full load
CH1: PFC output voltage
CH2: Vcc voltage (Pin #10)
CH3: VFF (pin #5)
CH4: gate drive (Pin #9)
Because in the L6564 the brownout thresholds are set internally, the startup and shutdown
thresholds can be adjusted slightly by modifying the resistor values used for the MULT pin.
In Figure 24 a startup tentative below the startup threshold is captured. As shown at startup
the brownout function does not allow the PFC startup even if Vcc has reached the L6564
turn-on threshold.
Figure 25 and Figure 26 show the circuit waveforms during brownout protection. In both
cases the mains voltage were increased or decreased slowly. As visible at turn-on or at turnoff there are no bouncing or starting attempts by the PFC converter.
Doc ID 16106 Rev 2
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Test results and significant waveforms
AN3022
Figure 25. EVL6564-100W startup with slow
Figure 26. EVL6564-100W turn-off with slow
input voltage increasing – full load
input voltage decreasing – full load
CH1: PFC output voltage
CH1: PFC output voltage
CH2: gate drive (Pin #9)
CH2: gate drive (Pin #13)
CH3: VFF (pin #5)
CH3: VFF (pin #5)
CH4: Vcc (pin #10)
Figure 27 and Figure 28 show the waveforms during the startup of the circuit at mains plugin. We can notice that the Vcc voltage rises up to the turn-on threshold, and the L6564 starts
operating. For a short time the energy is supplied by the Vcc capacitor, and then the
auxiliary winding with the charge pump circuit takes over. At the same time, the output
voltage rises from the peak value of the rectified mains to the nominal value of the PFC
output voltage. The good phase margin of the compensation network allows a clean startup,
without any large overshoot.
Figure 27. EVL6564-100W startup at
90 Vac -60 Hz – full load
Figure 28. EVL6564-100W startup at
265 Vac-50 Hz – full load
CH1: PFC output voltage
CH1: PFC Output voltage
CH2: Vcc voltage (Pin #10)
CH2: Vcc voltage (Pin #10)
CH3: VFF (pin #5)
CH3: VFF (pin #5)
CH4: Gate Drive (Pin #9)
CH4: Gate Drive (Pin #9)
20/32
Doc ID 16106 Rev 2
AN3022
3.4
Test results and significant waveforms
PFC_OK pin and feedback failure (open loop) protection
During normal operation, the voltage control loop provides for the output voltage (Vout) of
the PFC pre-regulator close to its nominal value, set by the resistors ratio of the feedback
output divider. In the L6564, a pin of the device (PFC_OK, pin #6) has been dedicated to
monitor the output voltage with a separate resistor divider composed of R3, R4, R11 (high)
and R15 (low), see Figure 1. This divider is selected so that the voltage at the pin reaches
2.5 V if the output voltage exceeds a preset value (Vovp), usually larger than the maximum
Vout that can be expected, also including worst-case load/line transients.
For the EVL6564-100W we have:
Vo = 400 V, Vovp = 434 V.
Select: R3+R4+R11=8.8MΩ;
then: R15 = 8.8 MΩ · 2.5 / (434-2.5) = 51 kΩ.
Once this function is triggered, the gate drive activity is immediately stopped until the
voltage on the pin PFC_OK drops below 2.4 V, see an example in Figure 29.
Notice that both feedback dividers connected to L6564 pin #1 (INV) and pin #6 (PFC_OK)
can be selected without any constraints. The unique criterion is that both dividers have to
sink a current from the output bus which needs to be significantly higher than the current
biasing the error amplifier and PFC_OK comparator.
The OVP function described above is able to handle “normal” overvoltage conditions, i.e.
those resulting from an abrupt load/line change or occurring at startup. In case the
overvoltage is generated by a feedback disconnection, for instance, when one of the upper
resistors of the output divider fails open, an additional circuitry detects the voltage drop of
the pin INV. If the voltage on pin INV is lower than 1.66 V and at the same time the OVP is
active, a feedback failure is assumed. Thus, the gate drive activity is immediately stopped,
the device is shut down, its quiescent consumption is reduced below 180 µA and the
condition is latched as long as the supply voltage of the IC is above the UVLO threshold. To
restart the system it is necessary to recycle the input power, so that the Vcc voltage of the
L6564 goes below 6 V and that one of the PWM controller goes below its UVLO threshold.
Note that this function offers a complete protection against not only feedback loop failures or
erroneous settings, but also against a failure of the protection itself. Either resistor of the
PFC_OK divider failing short or open or a PFC_OK pin floating results in shutting down the
IC and stopping the pre-regulator.
Moreover, the pin PFC_OK doubles its function as a non-latched IC disable. A voltage below
0.23 V shuts down the IC, reducing its consumption below 2 mA. To restart the IC, simply let
the voltage at the pin go above 0.27 V.
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Test results and significant waveforms
AN3022
Figure 29. EVL6564-100W load transient at
Figure 30. EVL6564-100W open loop
115 Vac - 60 Hz - full load to no load
at 115 Vac - 60 Hz - full load
CH1: PFC output voltage
CH1: PFC output voltage
CH2: PFC_OK (Pin #7)
CH2: PFC_OK (Pin #7)
CH3: GD (pin #9)
CH3: GD (pin #9)
CH4: Iout
The event of an open loop is captured in Figure 30, we can notice the protection intervention
latching the operation of the L6564.
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AN3022
4
Power management and housekeeping functions
Power management and housekeeping functions
Unlike similar PFC controllers with more pins, the housekeeping functions of the L6564 are
minimized but still there, and the device, in spite of the low pin count, has some main
functionalities that make it suitable to be implemented in high-end applications.
For example, in order to save power during light load operation or to put the converter in a
safe condition after detecting a failure of the DC-DC converter, a communication line can be
established between the cascade converter and the PFC via the disable function included in
the PFC_OK pin (pin #6). Needless to say, this operation assumes that the cascaded PFC
converter stage works as the master (thanks also to the integrated brownout function) and
the DC-DC stage as the slave or, in other words, that the PFC stage starts first, it powers
both controllers and enables/disables the operation of the downstream converter stage.
Several PWM controllers by STMicroelectronics have integrated some housekeeping
functions for the D2D and offer the possibility to interface directly the L6564 with the
downstream PWM controller via dedicated pins.
Should the residual consumption of the chip be an issue, it is also possible to cut off the
supply voltage. In this case, this operation assumes that the cascaded DC-DC converter
stage works as the master and the PFC stage as the slave or, in other words, that the DCDC stage starts first, it powers both controllers and enables/disables the operation of the
PFC stage.
The EVL6564-100W offers the possibility to test the disable function by connecting it to the
cascaded DC-DC converter using the J3 connector. The PFC_OK pin, Vcc and ground are
available via the series resistors R30 and R31.
Figure 31. Interface circuits that let DC-DC converter’s controller IC disable the
L6564
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,
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,
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,
6CC
6CC?0&#
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Doc ID 16106 Rev 2
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Power management and housekeeping functions
4.1
AN3022
Layout hints
The layout of any converter is a very important phase in the design process needing
attention by the design engineers like any other design phase. Even if it the layout phase
sometimes looks time-consuming, a good layout does indeed save time during the
functional debugging and the qualification phases. Additionally, a power supply circuit with a
correct layout needs smaller EMI filters or less filter stages and which allows consistent cost
savings.
Converters using the L6564 do not need any special or specific layout rule to be followed,
just the general layout rules for any power converter have to be applied carefully. Basic rules
are listed here below which can be used for other PFC circuits having any power level,
working either in transition mode or with a fixed-off time control.
24/32
1.
Keep power and signal RTN separated. Connect the return pins of components
carrying high current such as the input filter, sense resistors, and output capacitor as
close as possible. This point is the RTN star point. A downstream converter must be
connected to this return point.
2.
Minimize the length of the traces relevant to the boost inductor, MOSFET drain, boost
rectifier and output capacitor.
3.
Keep signal components as close as possible to each relevant pin of the L6564.
Specifically, keep the tracks relevant to pin #1 (INV) as short as possible. Components
and traces relevant to the error amplifier have to be placed far from traces and
connections carrying signals with high dV/dt like the MOSFET drain.
4.
Please connect heat sinks to power GND.
5.
Add an external shield to the boost inductor and connect it to power GND.
6.
Please connect the RTN of signal components including the feedback, PFC_OK and
MULT dividers close to the L6564 pin #8 (GND).
7.
Connect a ceramic capacitor (100 - 470 nF) to pin #10 (Vcc) and to pin #8 (GND), close
to the L6564. Connect this point to the RTN star point (see rule1).
Doc ID 16106 Rev 2
AN3022
Power management and housekeeping functions
Figure 32. EVL6564-100W PCB layout (SMT side view)
Doc ID 16106 Rev 2
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EMI filtering and conducted EMI pre-compliance measurements
5
AN3022
EMI filtering and conducted EMI pre-compliance
measurements
The following figures show the peak measurement of the conducted noise at full load and
nominal mains voltages for both mains lines. The limits shown in the diagrams are EN55022
class-B which is the most popular regulation for domestic equipments using a two-wire
mains connection.
It is also useful to remind that typically a PFC produces a significant differential mode noise
with respect to other topologies and therefore in case an additional margin with respect to
the limits is required, we suggest trying to increase the across-the-line (X) capacitors or the
capacitor C5 after the rectifier bridge. This is more effective and cheaper than increasing the
size of the common mode filter coil that in this case would filter the differential mode noise
by the leakage inductance between the two windings only.
In order to recognize if the circuit is affected by common mode or differential mode noise, it
is sufficient to compare the spectrum of phase and neutral line measurements. If the two
measurements are very similar, the noise is almost totally common mode. If there is a
significant difference between the two measurement spectrums, their difference represents
the amount of differential mode noise. Of course to get a reliable comparison the two
measurements have to be done under the same conditions. If the peak measurement is
used (as in the following figures), some countermeasures must be used, like synchronizing
the sweep of the spectrum analyzer with the input voltage. This is necessary as TM PFC
has a switching frequency that is modulated along the sine wave.
Because the differential mode produces the common mode noise by the magnetic field
induced by the current, decreasing the differential mode consequently limits the common
mode.
Figure 33. EVL6564-100W CE peak
Figure 34. EVL6564-100W CE peak
measurement at 100Vac - 50Hz Full
measurement at 100Vac - 50Hz Full
Load phase
Load neutral
26/32
Doc ID 16106 Rev 2
AN3022
EMI filtering and conducted EMI pre-compliance measurements
Figure 35. EVL6564-100W CE peak
Figure 36. EVL6564-100W CE peak
measurement at 230Vac - 50Hz Full
measurement at 230Vac - 50Hz Full
Load phase
Load neutral
As visible in the diagrams, in all test conditions there is a good margin of the measures with
respect to the limits. The measurements have been done in peak detection to speed up the
sweep, otherwise taking a long time. Please note that the harmonic measurements done in
quasi-peak or average as required by the regulation will be much lower because of the
jittering effect of the TM control that cannot be perceived in peak detection.
Doc ID 16106 Rev 2
27/32
PFC coil specifications
AN3022
6
PFC coil specifications
6.1
General description and characteristics
6.2
6.3
●
Applications: consumer, home appliance
●
Transformer: open
●
Coil former: vertical, 6+6 pins
●
Max. temp. rise: 45 °C
●
Max. operating ambient temp.: 60 °C
●
Mains insulation: N.A.
●
Unit finishing: varnish
Electrical characteristics
●
Converter topology: boost, transition mode
●
Core: PQ26/20 – PC44
●
Min. operating frequency: 40 kHz
●
Typical operating frequency: 20 kHz
●
Primary inductance: 520 mH ±10% at 1 kHz – 0.25 V (a)
●
Peak primary current 4.2 APK
●
RMS primary current 1.4 ARMS
Electrical diagram
Figure 37. Electrical diagram
02)-
!58
!-V
a. Measured between pins #5 & #9
28/32
Doc ID 16106 Rev 2
AN3022
6.4
PFC coil specifications
Winding characteristics
Table 2.
Winding characteristics
Pins
Winding
RMS current
Number of turns
Wire type
5-9
Primary (1)
1. 4 ARMS
57.5 - FIT
Multi stranded
#7 x φ0.20 mm
11 - 3
AUX (2)
0.05 ARMS
5.5 - spaced
φ0.28 mm
1. Primary winding external insulation: 2 layers of polyester tape
2. Aux. winding is wound on top of primary winding. External insulation with 2 layers of polyester tape
6.5
Mechanical aspect and pin numbering
●
Maximum height from PCB: 21.5 mm
●
Coil former: vertical, 6+6 pins
●
TDK P/N: BPQ26/20-1112CP
●
Pins #1, 2, 4, 6, 7, 10, 12 are removed. Pin 8 is for polarity key.
–
External copper shield: not insulated, wound around the ferrite core, including the
coil former. It must be well adhered to the ferrite. Height is 8 mm. Connected to pin
#3 by a soldered, solid wire.
Figure 38. Top view
!-V
6.6
Unit identification
●
Manufacturer: TDK
●
Manufacturer P/N: SRW2620PQ-X22V102
Doc ID 16106 Rev 2
29/32
References
7
30/32
AN3022
References
●
“10-pin transition-mode PFC controller” L6564 datasheet
●
“How to design a TM PFC pre-regulator with the L6564” application note AN3009
Doc ID 16106 Rev 2
AN3022
8
Revision history
Revision history
Table 3.
Document revision history
Date
Revision
Changes
18-Nov-2009
1
Initial release
15-Dec-2010
2
Updated: Section 3.4 on page 21
Doc ID 16106 Rev 2
31/32
AN3022
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Doc ID 16106 Rev 2
AN3009
Application note
How to design a transition mode PFC pre-regulator using the L6564
Introduction
The transition mode (TM) technique is widely used for power factor correction in low and
medium power applications, such as lamp ballasts, high-end adapters, flatscreen TVs,
monitors and PC power supplies, and all switched-mode power supplies that must meet
harmonics reduction regulations.
The L6564 is the latest proposal from STMicroelectronics for these types of applications,
which may require a low-cost power factor correction solution.
The L6564 is a current-mode power factor correction (PFC) controller that operates in
transition mode and embeds all the functions needed to control and properly protect a highperformance PFC converter into a very compact 10-pin SSOP-10 package.
Figure 1.
L6564 PFC controller in an SMPS architecture
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Doc ID 16032 Rev 3
1/36
www.st.com
Contents
AN3009
Contents
1
Introduction to the power factor correction (PFC) . . . . . . . . . . . . . . . . . 4
2
Operating the transition mode PFC (boost topology) . . . . . . . . . . . . . . 6
3
Designing a transition mode PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Input specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.3
Designing the power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.4
3.3.1
Rectifier bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.2
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.4
Boost inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.5
Power MOSFET selection and dissipation . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.6
Boost diode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
L6564 biasing circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Design example using the L6564-TM PFC Excel spreadsheet . . . . . . 30
5
EVL6564-100W demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/36
Doc ID 16032 Rev 3
AN3009
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
L6564 PFC controller in an SMPS architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Boost converter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Inductor current waveform and MOSFET timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Switching frequency fixing the line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
θ1 and θ2 depending on input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Representation of capacitive losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Conduction losses and total losses in the STF7NM50N MOSFET for the L6564 TM PFC 18
L6564 internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Open-loop transfer function bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Multiplier characteristics for VFF =1 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Multiplier characteristics for VFF = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Optimum MOSFET activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Excel spreadsheet design specification input table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Other design data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Excel spreadsheet TM PFC schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Excel spreadsheet BOM - 100 W TM PFC based on L6564 . . . . . . . . . . . . . . . . . . . . . . . 32
Wide-range 100 W demonstration board electrical circuit (EVL6564-100W) . . . . . . . . . . . 33
Doc ID 16032 Rev 3
3/36
Introduction to the power factor correction (PFC)
1
AN3009
Introduction to the power factor correction (PFC)
The front-end stage of conventional offline converters, typically consisting of a full-wave
rectifier bridge with a capacitor filter, has an unregulated DC bus from the AC mains. The
filter capacitor must be large enough to have a relatively low ripple superimposed on the DC
level. This means that the instantaneous line voltage is below the voltage on the capacitor
most of the time, thus the rectifiers conduct only for a small portion of each line’s half-cycle.
The current drawn from the mains then becomes a series of narrow pulses whose amplitude
is five to ten times higher than the resulting DC value. Many drawbacks result, such as a
much higher peak and RMS current down from the line, distortion of the AC line voltage,
overcurrents in the neutral line of the three-phase systems and, consequently, poor
utilization of the power system's energy capability. This can be measured in terms of either
total harmonic distortion (THD), as norms provide for, or power factor (PF), intended as the
ratio between the real power (the one transferred to the output) and the apparent power
(RMS line voltage times RMS line current) drawn from the mains, which is more immediate.
A traditional input stage with capacitive filter has a low PF (0.5-0.7) and a high THD
(>100%).
By using switching techniques, a power factor correction (PFC) pre-regulator, located
between the rectifier bridge and the filter capacitor, allows drawing a quasi-sinusoidal
current from the mains, in phase with the line voltage. The power factor becomes very close
to 1 (more than 0.99 is possible) and the previously mentioned drawbacks are eliminated.
Theoretically, any switching topology can be used to achieve a high power factor but, in
practice, the boost topology has become the most popular thanks to the advantages it
offers.
●
Primarily because the circuit requires the fewest external parts (low-cost solution).
●
The boost inductor located between the bridge and the switch causes the input di/dt to
be low, thus minimizing the noise generated at the input and, therefore, the
requirements on the input EMI filter.
●
The switch is source-grounded, therefore easy to drive.
However, a boost topology requires the DC output voltage to be higher than the maximum
expected line peak voltage (400 VDC is a typical value for 230 V or wide-range mains
applications). In addition, there is no isolation between the input and output, thus any line
voltage surge is passed on to the output. Two methods of controlling a PFC pre-regulator
are currently widely used: the fixed-frequency average current mode pulse-width modulation
(FF PWM) and the transition mode pulse-width modulation (TM PWM), the latter having a
fixed ON time and variable frequency. The first method needs a complex control that
requires a sophisticated controller IC (ST's L4981A, with the variant of the frequency
modulation offered by the L4981B) and a considerable component count. The second
method requires a simpler control (implemented by ST's L6564), fewer external parts and is
therefore much more economical. With the first method, the boost inductor works in
continuous conduction mode, while the transition mode makes the inductor work on the
boundary between continuous and discontinuous mode by definition. For a given throughput
power, transition mode operation involves higher peak currents. This, also consistently with
cost considerations, suggests its use in a lower power range (typically up to 250 W), while
the former is recommended for higher power levels. To conclude, FF PWM is not the only
alternative when continuous current mode (CCM) operation is desired. FF PWM modulates
both switch ON and OFF times (their sum is constant by definition), and a given converter
operates in either CCM or DCM (discontinuous current mode), depending on the input
voltage and the load conditions.
4/36
Doc ID 16032 Rev 3
AN3009
Introduction to the power factor correction (PFC)
Exactly the same result can be achieved if the ON time only is modulated and the OFF time
is kept constant, in which case, however, the switching frequency is no longer fixed. This is
referred to as “fixed off time” (FOT) control. Peak current-mode control can still be used.
This application note focuses on transition mode.
Doc ID 16032 Rev 3
5/36
Operating the transition mode PFC (boost topology)
2
AN3009
Operating the transition mode PFC (boost topology)
The operation of the PFC transition mode controlled boost converter can be summarized as
follows.
The AC mains voltage is rectified by a bridge and this rectified voltage is delivered to the
boost converter. This boost converter, using a switching technique, boosts the rectified input
voltage to a regulated DC output voltage (Vo).
The boost converter consists of a boost inductor (L), a controlled power switch (Q), a catch
diode (D), an output capacitor (Co) and, obviously, a control circuitry (Figure 2). The goal is
to shape the input current in a sinusoidal fashion, in phase with the input sinusoidal voltage.
To do this, the L6564 uses the transition mode technique.
Figure 2.
Boost converter circuit
!-V
The error amplifier compares a partition of the output voltage of the boost converter with an
internal reference, generating an error signal proportional to the difference between them. If
the bandwidth of the error amplifier is narrow enough (below 20 Hz), the error signal is a DC
value over a given half-cycle.
The error signal is fed into the multiplier block and multiplied by a partition of the rectified
mains voltage. The result is a rectified sinusoid whose peak amplitude depends on the
mains peak voltage and the value of the error signal.
The output of the multiplier is in turn fed into the (+) input of the current comparator, thus it
represents a sinusoidal reference for the PWM. In fact, when the voltage on the current
sense pin (instantaneous inductor current times the sense resistor) equals the value on the
(+) of the current comparator, the conduction of the MOSFET is terminated. As a
consequence, the peak inductor current is enveloped by a rectified sinusoid. As
demonstrated in Section 3.3.4, transition mode control causes a constant ON time operation
over each line half-cycle.
After the MOSFET has been turned off, the boost inductor discharges its energy into the
load until its current goes to zero. The boost inductor has now run out of energy, the drain
node is floating and the inductor resonates with the total capacitance of the drain. The drain
voltage drops rapidly below the instantaneous line voltage and the signal on the zero current
detector (ZCD) drives the MOSFET on again and another conversion cycle starts.
This low voltage across the MOSFET upon its activation reduces both the switching losses
and the total drain capacitance energy that is dissipated inside the MOSFET.
6/36
Doc ID 16032 Rev 3
AN3009
Operating the transition mode PFC (boost topology)
The resulting inductor current and the timing intervals of the MOSFET are shown in
Figure 3, where it can be observed that, by geometric relationships, the average input
current (the one drawn from the mains) is just one half of the peak inductor current
waveform.
Figure 3.
Inductor current waveform and MOSFET timing
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The system operates not exactly on, but very close to, the boundary between continuous
and discontinuous current mode and that is why this system is called a transition mode PFC.
Besides the simplicity and the few external parts required, this system minimizes the
inductor’s size due to the low inductance value needed. On the other hand, the high current
ripple on the inductor involves high RMS current and high noise on the rectified mains bus,
which needs a heavier EMI filter to be rejected. These drawbacks limit the use of the TM
PFC to lower power range applications.
Doc ID 16032 Rev 3
7/36
Designing a transition mode PFC
AN3009
3
Designing a transition mode PFC
3.1
Input specification
This sections describes a possible design flowchart referred to as a transition mode PFC,
using the L6564. The first part is a detailed specification of the operating conditions of the
circuit that is needed for the following calculation. In this example, a L6564 wide input range
mains PFC circuit has been considered. Some design criteria is also provided.
●
Mains voltage range (Vac rms):
●
Minimum mains frequency
●
Rated output power (W):
VACmin = 90Vac VACmax = 265 Vac (1)
fl = 47 Hz
(2)
Pout = 100 W
(3)
Because the PFC has a boost topology, the regulated output voltage depends strongly on
the maximum AC input voltage. In fact, for correct operation of the boost mechanism the
output voltage must always be higher than the input. As a result, because Vin max is
265.1.414 = 374.7 Vpk, the typical value of the output has been set to 400 Vdc. If the input
voltage is higher, as is typical in ballast applications, the output voltage must be increased
accordingly. As a rule of thumb, the output voltage must be 6 or 7% higher than the
maximum input voltage peak.
●
Regulated DC output voltage (Vdc):
Vout = 400 V
(4)
The target efficiency and power factor are set here to the minimum input voltage and
maximum load. They are used for the following operating condition calculation of the PFC.
Of course, at high input voltages the efficiency is higher.
●
Expected efficiency (%):
η = 94%
(5)
●
Expected power factor:
PF = 0.99
(6)
Because of the narrow-loop voltage bandwidth, the PFC output can face overvoltages at
start-up or when load transients occur.
To avoid excessive output voltages that might overstress the output components and the
load, the L6564 incorporates a device pin (PFC_OK, pin #6) dedicated to monitoring the
output voltage with a separate resistor divider, selected so that the voltage at the pin
reaches 2.5 V if the output voltage exceeds a preset value (VOVP), usually larger than the
maximum Vout that can be expected (including worst-case load/line transients).
8/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
●
Maximum output voltage (Vdc):
VOVP = 430 V
(7)
The mains frequency generates a 2 fL voltage ripple on the output voltage at full load. The
ripple amplitude determines the current flowing into the output capacitor and the ESR.
Additionally, a request for a certain hold-up capability can be sent to the PFC in case mains
dips occur, in which case the output capacitor also has to be dimensioned taking into
account the required minimum voltage value (Vout min) after the hold-up time (tHold) has
elapsed.
●
Maximum output low frequency ripple:
●
Minimum output voltage after line drop (Vdc):
●
Holdup capability (ms):
ΔVout = 20 V
(8)
Vout min = 300 V
(9)
tHold = 10 ms
(10)
The PFC’s minimum switching frequency is one of the main parameters used to dimension
the boost inductor; here the switching frequency is considered at low mains at the peak of
the sinusoid and at full load conditions. As a rule of thumb, the switching frequency must be
higher than the audio bandwidth to prevent audible noise. Additionally, it must not interfere
with the L6564’s minimum internal starter period (reported in the datasheet). On the other
hand, if the minimum frequency is too high, the circuit shows excessive losses at a higher
input voltage and probably skips switching cycles not only at light loads. The typical
minimum frequency range is 20 - 50 kHz for wide-range operation.
●
Minimum switching frequency (kHz):
fsw min = 40 kHz
(11)
To properly select the power components of the PFC and dimension the heatsinks if they
are needed, the maximum operating ambient temperature around the PFC circuitry must be
known. Note that this is not the maximum external operating temperature of the entire
equipment, but rather the local temperature at which the PFC components are working.
●
Maximum ambient temperature (°C):
Doc ID 16032 Rev 3
Tambx = 50°C
(12)
9/36
Designing a transition mode PFC
3.2
AN3009
Operating conditions
The first step is to define the main parameters of the circuit, using the specification points
defined in the previous section.
●
Rated DC output current
Equation 1
Iout =
●
Pout
Vout
Iout =
100 W
= 0.25 A
400 V
Maximum input power
Equation 2
Pin =
●
Pout
η
Pin =
100 W
⋅ 100 = 106.38 W
94
RMS input current
Equation 3
Iin =
●
Pin
VACmin ⋅ PF
Iin =
106.38 W
= 1.19 A
90Vac ⋅ 0.99
Peak inductor current
Equation 4
IL pk = 2 ⋅ 2 ⋅ Iin
IL pk = 2 ⋅ 2 ⋅ 1.19 A = 3.38 A
As shown in Figure 3 on page 7, the inductor current is of a triangular shape at the switching
frequency, and the peak of the triangle is twice its average value. The average value of the
inductor current is exactly the peak of the input sinewave current, and therefore can be
easily calculated as its RMS value can be obtained from Equation 3. To write a complete
inductor specification for the inductor manufacturer, one also must provide the RMS and AC
current, which can both be calculated from Equation 5 and Equation 6, respectively.
●
RMS inductor current
Equation 5
IL rms =
●
2
3
⋅ Iin
IL rms =
2
3
⋅ 1.19 A = 1.38 A
AC inductor current
Equation 6
2
IL ac = IL2rms − Iin
IL ac =
(1.38 )2 − (1.19 A )2
= 0.69 A
The current flowing in the inductor can be split into two parts, depending on the instant of
conduction: during the ON time, the current increases from zero up to the peak value and
circulates into the switch, while during the following OFF time, the current decreases from
the peak down to zero and circulates into the diode. Therefore, a current with a triangular
wave flows into these two components with a peak value equal to the inductor value. It is
also possible, therefore, to calculate the RMS current flowing into the switch and into the
diode, which is necessary to calculate the losses of these two elements.
10/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
●
RMS switch current
Equation 7
ISWrms = IL pk ⋅
●
1 4 ⋅ 2 VAC min
−
⋅
6
9π
Vout
ISWrms = 3.38 A ⋅
1 4 ⋅ 2 90Vac
−
⋅
= 1.18 A
6
9π
400 V
RMS diode current
Equation 8
IDrms = IL pk ⋅
4 ⋅ 2 VAC min
⋅
9π
Vout
IDrms = 3.38 A ⋅
3.3
Designing the power section
3.3.1
Rectifier bridge
4 ⋅ 2 90Vac
⋅
= 0.72 A
9π
400 V
The input rectifier bridge can use any standard, slow recovery, low-cost device. A 600 V
device is normally used to obtain enough margin against mains surges. A negative
temperature coefficient (NTC) resistor limiting the current at turn-on is required to prevent
any overstress on the diode bridge.
The power dissipation of the rectifier bridge can be calculated using Equation 9, Equation 10
and Equation 11. The threshold voltage and dynamic resistance of a single diode of the
bridge can be found in the component datasheet.
Equation 9
Iinrms =
2 ⋅ Iin
=
2
2 ⋅ 1.19 A
= 0.84 A
2
Iin _ avg =
2 ⋅ Iin
=
π
2 ⋅ 1.19 A
= 0.54 A
π
Equation 10
For this application, a GBU4J rectifier bridge has been used. The power dissipated by the
bridge is:
Equation 11
Pbridge = 4 ⋅ R diode ⋅ I 2 inrms + 4 ⋅ Vth ⋅ Iin _ avg
Pbridge = 4 ⋅ 0.04 Ω ⋅ (0.84 A )2 + 4 ⋅ 0.7 V ⋅ 0.54 A = 1.62 W
3.3.2
Input capacitor
The input high-frequency filter capacitor (Cin) has to attenuate the switching noise due to
the high-frequency inductor current ripple (twice the average line current, as shown in
Figure 3). The worst conditions occur on the peak of the minimum rated input voltage. The
maximum high-frequency voltage ripple across Cin is usually imposed between 5% and
20% of the minimum rated input voltage. This is expressed by a coefficient r (= 0.05, 0.2) as
an input design parameter.
Doc ID 16032 Rev 3
11/36
Designing a transition mode PFC
●
AN3009
Ripple voltage coefficient (%):
(13)
r = 0.15
Equation 12
Cin =
Iin
2π ⋅ fsw min ⋅ r ⋅ VAC min
Cin =
1.19 A
= 0.359 μF
2π ⋅ 40 kHz ⋅ 0.15 ⋅ 90 Vac
In real conditions, the input capacitance must be designed taking into account the EMI filter
and a tolerance on the component of about 5% to 10% (typical for polyester capacitors).
A commercial value of Cin = 0.47 µF has been selected. Of course, a larger capacitor
provides a benefit from an EMI point-of-view, but does not benefit the THD, especially at
high mains. Therefore, a compromise must be found between these two parameters. A
good-quality film capacitor for this component must be selected to provide effective filtering.
3.3.3
Output capacitor
The selection of the output bulk capacitor (Co) depends on the DC output voltage (4), the
allowed maximum output voltage (7) and the converter’s output power (3).
The 100/120 Hz (twice the mains frequency) voltage ripple (ΔVout = peak-to-peak ripple
value) is a function of the capacitor impedance and the peak capacitor current.
Equation 13
ΔVout = 2 ⋅ Iout ⋅
1
(2π ⋅ 2fl ⋅ CO )
2
+ ESR2
With a low ESR capacitor the capacitive reactance is dominant, therefore:
Equation 14
CO ≥
Iout
Pout
=
2π ⋅ fl ⋅ ΔVout 2π ⋅ fl ⋅ Vout ⋅ ΔVout
CO ≥
100 W
= 42.5 μF
2 π ⋅ 47 Hz ⋅ 400 V ⋅ 20 V
ΔVout is usually selected in the range of 1.5% of the output voltage. Although ESR does not
normally affect the output ripple, it should be taken into account to calculate the power
losses. The total RMS capacitor ripple current, including mains frequency and switching
frequency components, is:
Equation 15
ICrms = ID 2rms − I2out
ICrms =
(0.72 A )2 − (0.25 A )2
= 0.67 A
If the PFC stage has to guarantee a specified hold-up time, the selection criterion of the
capacitance changes: Co has to deliver the output power for a certain time (tHold) with a
specified maximum dropout voltage (Vout min), that is, the minimum output voltage value
(which takes load regulation and output ripple into account) and is the minimum output
operating voltage before the 'power fail' detection and consequent stopping by the
downstream system supplied by the PFC.
12/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
Equation 16
CO =
(V
out
2 ⋅ Pout ⋅ tHold
− ΔVout
)
2
−
2
Vout
min
CO =
2 ⋅ 100 W ⋅ 10 ms
(400 V − 20 V )2 − (300 V )2
= 36.7 μF
A 20% tolerance on the electrolytic capacitors has to be considered to obtain the correct
dimensioning. As per Equation 14, we have selected for this application a capacitor Co
equal to 47 µF (450 V) so as to maintain a hold-up capability for 12 ms. The actual output
voltage ripple with this capacitor is also calculated. In detail:
Equation 17
(
t hold
CO ⋅ ⎡⎢ Vout − ΔVout
⎣
=
2 ⋅ Pout
)
2
⎤
2
− Vout
min ⎥
⎦
t hold =
[
47 μF ⋅ (400 V − 20 V ) − (300 V )
2 ⋅ 100 W
2
2
] = 14.78 ms
As expected the ripple variation on the output is:
Equation 18
ΔVout =
3.3.4
Iout
2 ⋅ π ⋅ fl ⋅ CO
ΔVout =
0.25 A
= 18.02 V
2 ⋅ π ⋅ 47 Hz ⋅ 47 μF
Boost inductor
The boost inductor determines the working frequency of the converter, thus it is usually
calculated so that the minimum switching frequency is greater than the maximum frequency
of the L6564’s internal starter (typically 150 µs) to ensure correct transition mode operation.
Assuming a unity power factor, it is possible to write:
Equation 19
t on (VAC, ϑ) =
L ⋅ IL pk ⋅ sin(ϑ)
2 ⋅ VAC ⋅ sin(ϑ)
=
L ⋅ IL pk
2 ⋅ VAC
Equation 19 shows that the ON time does not depend on the angle of the mains phase, but
is constant over the entire mains cycle.
Equation 20
t off (VAC, ϑ) =
L ⋅ IL pk ⋅ sin(ϑ)
Vout − 2 ⋅ VAC ⋅ sin(ϑ)
ton and toff are the power MOSFET’s ON and OFF times respectively, ILpk the maximum
peak inductor current in a line cycle and θ the instantaneous line phase in the interval [0,Π]).
Note that the ON time is constant over a line cycle.
As previously said, ILpk is twice the line-frequency peak current (Equation 4), which is
related to the input power and input mains voltage. By substituting this relationship in the
expressions of ton and toff, it is possible to find the instantaneous switching frequency along
a given line cycle.
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Designing a transition mode PFC
AN3009
Equation 21
fsw (VAC, θ) =
(
Ton
VAC 2 ⋅ Vout − 2 ⋅ VAC ⋅ sin(θ)
1
1
=
⋅
+ Toff 2 ⋅ L ⋅ Pin
Vout
)
The switching frequency is minimal at the top of the sinusoid (θ = Π /2 ==> sin θ =1),
maximal at the zero crossings of the line voltage (θ = 1 or Π ==> sin θ =0), where toff = 0.
The absolute minimum frequency fswmin can occur at either the maximum VACmax or the
minimum mains voltage VACmin. The inductor value is therefore defined by the formula:
Equation 22
L(VAC) =
VAC 2 ⋅ (Vout − 2 ⋅ VAC)
2 ⋅ fsw min ⋅ Pin ⋅ Vout
After calculating the values of the inductor at low and high mains – L(VACmin) and
L(VACmax) – the minimum value must be taken into account. It becomes the maximum
inductance value for dimensioning the PFC.
Equation 23
(90Vac )2 ⋅ (400 V −
2 ⋅ 90 Vac)
= 0.642 mH
2 ⋅ 40 kHz ⋅ 106.38 W ⋅ 400 V
L(VAC min ) =
L(VACmax ) =
(265Vac)2 ⋅ (400 V −
2 ⋅ 265Vac)
= 0.515 mH
2 ⋅ 40 kHz ⋅ 106.38 W ⋅ 400 V
For this application, a 0.52 mH boost inductance has been selected.
Figure 4.
Switching frequency fixing the line voltage
&REQUENCYMODULATIONWITHTHE,INEHALFPERIOD
&REQUENCY;K(Z=
3WITCHING&REQ
6!#MIN
3WITCHING&REQ
6!#MAX
T> LINEHALFPERIOD @ !-V
Figure 4 shows the switching frequency versus the θ angle calculated with Equation 22, a
0.52 mH boost inductance and the line voltage fixed at the minimum and maximum values.
The minimum switching frequency can be recalculated for the selected inductance value by
inverting Equation 22 to become:
Equation 24
fsw min (VAC) =
14/36
VAC 2 ⋅ (Vout − 2 ⋅ VAC)
2 ⋅ L ⋅ Pin ⋅ Vout
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
When one compares fswmin(VACmin) and fswmin(VACmax) with L = 0.52 mH, the actual
calculated minimum switching frequency is 40.13 kHz, as expected.
The core size is determined by assuming a peak flux density Bx ≅ 0.25 T (depending on the
ferrite grade selected and relevant specific losses) and by calculating the maximum current
according to Equation 45, as a function of the maximum clamping voltage of the current
sense pin and the value of the sense resistor.
DC and AC copper losses and ferrite losses must also be calculated to determine the
maximum temperature rise of the inductor.
3.3.5
Power MOSFET selection and dissipation
The MOSFET selection involves mainly its RDS(on), which depends on the output power (3),
since the breakdown voltage is fixed by the output voltage only (4), plus the overvoltage
allowed (7) and a safety margin (20%). Therefore, a voltage rating of 500 V
(1.2 · Vout = 480 V) has been selected. With regard to its current rating, as a rule of thumb,
one can select a device with approximately three times the RMS switch current (Equation 7)
but, in any case, the calculation of the power dissipation provides the final confirmation that
the selected device is the right one for the circuit. The heatsink dimensions must also be
taken into consideration. For this L6564 TM PFC application, we have selected a
STF7NM50 MOSFET. The MOSFET's power dissipation depends on the conduction,
switching and capacitive losses.
The conduction losses at maximum load and minimum input voltage are calculated by:
Equation 25
Pcond (VAC) = RDS( on) ⋅ (ISWrms (VAC))
2
Since in datasheets the RDS(on) is normally given at ambient temperature (25 °C), to
correctly calculate the conduction losses at 100°C (typical MOSFET junction working
temperature), a factor of 1.75-2 should be applied. The correct factor can be found in the
device datasheet.
The conduction losses referred to a 1 Ω RDS(on) at ambient temperature as a function of the
input power (pin) and Vac can now be calculated by combining Equation 25 and Equation 7.
Equation 26
⎛
Pin
16 2 ⋅ VAC ⎞⎟
′ (VAC) = 2 ⋅ (ISWrms (VAC)) = 2 ⋅ ⎜
2
Pcond
⋅
−
⋅
⎜ 2 ⋅ VAC ⋅ PF
⎟
3π
Vout
⎝
⎠
2
2
The switching losses in the MOSFET occur only at turn-off because of the TM operation,
and can be basically expressed by:
Equation 27
Pswitch (VAC) = VMOS ⋅ IMOS ⋅ t fall ⋅ fsw (VAC)
Equation 27 represents the crossing between the MOSFET current that decreases linearly
during the fall time and the voltage on the MOSFET drain that increases. In fact, during the
fall time, the current of the boost inductor flows into the parasitic capacitance of the
MOSFET charging it.
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Designing a transition mode PFC
AN3009
For this reason, switching losses also depend on the total drain capacitance. Because the
switching frequency depends on the input line voltage and the phase angle on the sinusoidal
waveform, using Equation 27 the switching losses per 1 µs of current fall time and 1 nF of
total drain capacitance can be written as:
Equation 28
′
Pswitch
(VAC) = IL pk ⋅ Vout ⋅
1
π
π
∫ (sin ϑ)
2
⋅ fsw (VAC, θ) ⋅ dϑ
0
Refer to the MOSFET datasheet to find the value of tfall at turn-off.
At turn-on, the losses are due to the discharge of the total drain capacitance inside the
power MOSFET itself. In general, the capacitive losses are given by:
Equation 29
Pcap (VAC) =
1
⋅ C d ⋅ V 2MOS ⋅ fsw (VAC)
2
where Cd is the total drain capacitance including the MOSFET and any other parasitic
capacitances such as the inductor at the drain node, and where VMOS is the drain voltage at
the MOSFET’s turn-on.
Taking into account the frequency variation with the input line voltage and the phase angle
similar to Equation 29, a detailed description of the capacitive losses per 1 nF of total drain
capacitance can be calculated as:
Equation 30
′ (VAC) =
Pcap
1 1
⋅
2 π
ϑ2
∫ (2
)
2
2VAC − Vout fsw (VAC, ϑ) ⋅dϑ
ϑ1
θ and θ2 depend on the input voltage and are defined below.
Equation 31
⎛ Vout ⎞
⎟⎟
ϑ1 = arcsin⎜⎜
⎝ 2 2VAC ⎠
Equation 32
ϑ2 = π − ϑ1
16/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
θ1 and θ2 depending on input
voltage
Figure 5.
Figure 6.
Representation of capacitive losses
9'5$,1
VLQ- SIN
9LQ
9LQ
9OUT
6
RXW
6!#
9$&
-
- ð
S¥
-
3FDS
=96
DQJOH
W
!-V
!-V
Figure 5 shows the relationship between θ1 and θ2 depending on the input voltage. Figure 6
represents a waveform of the drain voltage. The MOSFET’s activation occurs exactly on the
valley because the inductor has run out of energy and therefore can resonate with the drain
capacitance. Details are provided in the section on the ZCD pin (pin #7). It is clear that for an
input voltage theoretically lower than half of the output voltage, the resonance should ideally
reach zero, achieving a zero voltage operation and therefore avoiding any losses on this
edge. An input voltage corresponding to a positive value of the valley generates capacitive
losses. However, activation of the MOSFET always occurs at the minimum voltage of the
resonance and therefore the losses are minimized.
In practice, it is possible to estimate the total switching and capacitive losses by solving the
integral of the switching frequency depending on sin(θ) on the half-line cycle.
The total losses function of the input mains voltage is the sum of the three previous losses’
functions (Equation 26, Equation 28 and Equation 30 respectively) multiplied by the
MOSFET parameters.
Equation 33
′ (VAC) +
Ploss (VAC) = RDS( on) ⋅ Pcond
t 2fall
′ (VAC) + C d ⋅ Pcap
′ (VAC)
⋅ Psw
Cd
Figure 7 shows the trend of the total losses (derived from Equation 33) as a function of the
input mains voltage for the selected MOSFET STF7NM50N. Capacitive losses are dominant
at high mains voltages and are essentially caused by conduction losses at low and medium
mains voltages.
Doc ID 16032 Rev 3
17/36
Designing a transition mode PFC
Figure 7.
AN3009
Conduction losses and total losses in the STF7NM50N MOSFET for the
L6564 TM PFC
-/3&%44OTALLOSSES
0COND6I
0LOSS6I
0LOSSES;7=
6IN?AC;6RMS=
!-V
From Equation 33 and by using the data relevant to the selected MOSFET and calculating
the losses at VACmin and VACmax, one can observe that the maximum total losses occur at
VACmin. From this number and the maximum ambient temperature (12), the total maximum
thermal resistance required to keep the junction temperature below 125 °C is:
Equation 34
R th =
125 °C − Tambx
P loss (VAC)
R th =
°C
125 °C − 50 °C
= 29
2.58 W
W
If the result of Equation 34 is lower than the junction-to-ambient thermal resistance given in
the MOSFET datasheet for the selected device package, a heatsink must be used.
The STF7NM50N junction-to-ambient thermal resistance in free-air is 62 °C/W, therefore a
heatsink is necessary.
3.3.6
Boost diode selection
Following a similar criterion to the one for the MOSFET, the output rectifier can also be
selected. A minimum breakdown voltage of 1.2·(Vout + ΔVOVP) and current rating higher
than 3·Iout (Equation 1) can be chosen for a rough initial selection of the rectifier. The
correct choice is then confirmed by the thermal calculation: if the diode junction temperature
works within 125 °C, the device has been selected correctly, otherwise a bigger device must
be selected.
For this 100 W application, we have selected a STTH2L06 (600 V, 2 A).
The current values of the rectifier AVG (Equation 1) and RMS (Equation 8), and the
parameter Vth (rectifier threshold voltage) and Rd (dynamic resistance) given in the
datasheet allow the rectifier losses to be calculated.
From the STTH2L06 datasheet the Vth is 0.89 V and Rd is 0.08 Ω.
Equation 35
Pdiode = Vth ⋅ Iout + R d ⋅ ID 2rms
18/36
Pdiode = 0.89 V ⋅ 0.25 A + 0.08 Ω ⋅ (0.72 A ) = 0.26 W
Doc ID 16032 Rev 3
2
AN3009
Designing a transition mode PFC
From (12) and Equation 35, the maximum thermal resistance to keep the junction
temperature below 125 °C is:
Equation 36
R th =
125 °C − Tambx
P diode
R th =
°C
125 °C − 50 °C
= 284
0.26 W
W
Because the calculated Rth is higher than the STTH2L06 junction-to-ambient thermal
resistance, a heatsink is not needed to properly dissipate the heat.
3.4
L6564 biasing circuitry
This section describes the biasing circuitry of the L6564. Figure 8 represents the L6564’s
internal schematic. For more information on the device’s internal functions, refer to the
datasheet.
Figure 8.
L6564 internal schematic
!-V
Pin 1 (INV): this pin is connected both to the inverting input of the E/A and to the OVP
circuitry. A resistive divider has to be connected between the regulated output voltage of the
boost and this pin. The internal reference on the E/A non-inverting input is 2.5 V (typ.). The
PFC output voltage (Vout) is set at its nominal value by the resistor ratio of the feedback
output divider. RoutH and RoutL can then be selected by considering the nominal output
Doc ID 16032 Rev 3
19/36
Designing a transition mode PFC
AN3009
voltage (4) and the desired output power dissipated on the output divider. Following is an
example with a power dissipation of 50 mW.
Equation 37
R outH =
20/36
(VOUT − 2.5V)2
50 mW
R outH =
Doc ID 16032 Rev 3
(400 V − 2.5 V)2
= 3.160 MΩ
50 mW
AN3009
Designing a transition mode PFC
By selecting a commercial value of RoutH equal to 3 MΩ, we get:
Equation 38
R outH 400 V
=
− 1 = 159
R outL
2 .5 V
R outH
V
= out − 1
R outL 2.5 V
Equation 39
R outL =
R outH
159
R outL =
3 MΩ
= 18.8 kΩ
159
We have selected RoutL = 62 kΩ in parallel to 27 kΩ. Note that for RoutH a resistor with a
suitable voltage rating (>400 V) is needed, or else additional in-series resistors must be
used.
Also note that the maximum value of the resistor divider is limited by the L6564’s INV pin
input bias current given in the datasheet. To guarantee correct output voltage regulation, the
current flowing in the resistor divider must be significantly higher than the current flowing
into the pin.
Pin 6 (PFC_OK - feedback failure protection): the PFC_OK pin is dedicated to monitoring
the output voltage by a separate resistor divider. This divider is selected so that the voltage
at the pin reaches 2.5 V (typ.) if the output voltage exceeds a preset value VOVP (7), usually
larger than the maximum Vout that can be expected, and also including worst-case load/line
transients. For a maximum output voltage VOVP of 430 V and imposing a 50 µA current
flowing into the divider, we obtain:
Equation 40
RL =
VREF _ PFC _ OK
Idivider
RL =
2.5 V
= 50 kΩ
50 μA
By selecting a commercial value of 51 kΩ, we then get:
Equation 41
⎞
⎛
VOVP
RH = RL ⋅ ⎜
− 1⎟
⎟
⎜V
⎠
⎝ REF _ PFC _ OK
⎛ 430 V ⎞
RH = 51 kΩ ⋅ ⎜⎜
− 1⎟⎟ = 8.721 MΩ
⎠
⎝ 2 .5 V
By connecting in series two 3.3 MΩ and one 2.2 MΩ resistors, a total value of 8.8 MΩ is
obtained.
Note that both feedback dividers connected to the L6564’s pin #1 (INV) and pin #6
(PFC_OK) can be selected without any constraints. The unique criterion is that both dividers
have to sink a current from the output bus, which needs to be significantly higher than the
current biasing the error amplifier and PFC_OK comparator.
The OVP function described above can handle “normal” overvoltage conditions, that is,
those resulting from an abrupt load/line change or occurring at start-up. If the overvoltage is
generated by a feedback disconnection for instance, when one of the upper resistors of the
output divider fails to open, an additional circuitry detects the voltage drop of pin INV. If the
voltage on pin INV is lower than 1.66 V (typ.) and at same time the OVP is active, a feedback
failure is assumed.
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Designing a transition mode PFC
AN3009
Thus, the activity of the gate driver is immediately stopped, the device is shut down, its
quiescent consumption is reduced to less than 180 µA and the condition is latched for as
long as the supply voltage of the IC remains above the UVLO threshold. To restart the
system, it is necessary to recycle the input power so that the VCC voltage of the L6564 goes
below 6 V and that one of the PWM controllers goes below its UVLO threshold. Note that
this function offers a complete protection against not only feedback loop failures or
erroneous settings, but also a failure of the protection itself. If either one of the PFC_OK
dividers fails to short or open, or a PFC_OK pin is floating, the IC is shut down and the preregulator stopped. Moreover, the PFC_OK pin doubles its function as a not-latched IC
disable: a voltage below 0.23 V shuts down the IC, reducing its consumption below 2 mA. To
restart the IC, simply let the voltage at the pin go above 0.27 V.
Pin 2 (COMP): this pin is the output of the E/A that is fed into one of the two inputs of the
multiplier. A feedback compensation network is placed between this pin and INV (pin #1). It
has to be designed with a narrow bandwidth to prevent the system from rejecting the output
voltage ripple (100 Hz) that would result in a high distortion of the input current waveform.
A simple way of defining the capacitance value is to set the bandwidth (BW) from 20 to 30
Hz. The compensation network can be a simple capacitor, providing a low-frequency pole as
well as a high DC gain. A more complex network, typically a type-II CRC network providing
two poles and a zero, is more suitable for constant power loads like a downstream converter.
If a single capacitor is used it can be dimensioned using the following formulas.
Equation 42
BW =
1
2π ⋅ (R outH // R outL ) ⋅ CCompensation
Equation 43
CCompensation =
1
2π ⋅ (R outH // R outL ) ⋅ BW
For a more complex compensation network calculation refer to [2] and [3] in
Chapter 6: References.
For this 100 W TM PFC, a CRC network providing two poles and a zero has been
implemented with the following values.
C compP = 68 nF
C compS = 680 nF
R compS = 82 kΩ
(14)
The relevant open-loop transfer function and its phase function are reported in Figure 9 and
Figure 10.
22/36
Doc ID 16032 Rev 3
AN3009
Figure 9.
Designing a transition mode PFC
Open-loop transfer function bode
plot
Figure 10. Phase
0HASE&
/PENLOOPTRANSFERFUNCTION
DEG
D"
F;(Z=
F;(Z=
!-V
!-V
The two bode plot charts refer to the PFC operating at 265 Vac and full load. In these
conditions, the crossover frequency is 11.55 Hz and the phase margin is 55 °C. The third
harmonic distortion introduced by the E/A 100 Hz residual ripple is below 3%.
Pin 4 (CS): this pin is the inverting input of the current sense comparator. The L6564
receives the information on the instantaneous inductor current through this pin, provided by
an external sense resistor (Rs) via an RC filter. As this signal crosses the threshold set by
the multiplier output, the PWM latch is reset and the power MOSFET is turned off. The
MOSFET stays in the off state until the PWM latch is set again by the ZCD signal. The pin is
equipped with 150 ns leading-edge blanking to improve noise immunity.
For a 100 W PFC, the sense resistor value (Rs) can be calculated as follows.
Equation 44
Rs <
Vcs min
IL pk
Rs <
1. 0 V
= 0.296 Ω
3.38 A
Where:
●
ILpk is the maximum peak current in the inductor, calculated as shown in Equation 4.
●
Vcsmin equals 1.0 V and is the minimum voltage admitted on the L6564’s current
sense (as per the datasheet).
Because the internal current sense clamping sets the maximum current that can flow in the
inductor, the maximum peak of the inductor current is calculated considering the maximum
voltage Vcsmax admitted on the L6564 (as per the datasheet).
Equation 45
IL pkx =
Vcs max
Rs
IL pkx =
1.16 V
= 4.30 A
0.27 Ω
The calculated ILpkx is the value at which the boost inductor is not saturated and is used to
calculate the inductor’s number of turns and air gap length.
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Designing a transition mode PFC
AN3009
If the boost inductor gets saturated, a second comparison level at 1.7 V detects the
abnormal current value and activates a safety procedure that temporarily stops the
converter and limits the stress of the power components.
The power dissipated in Rs is given by:
Equation 46
2
Ps = R s ⋅ ISWrms
Ps = 0.27 Ω ⋅ (1.18 A ) = 0.37 W
2
According to the results of Equation 45 and Equation 46, two resistors of 0.47 Ω and 0.68 Ω,
each with a power rating of 0.25 W, have been selected.
Pin 3 (MULT): this pin is the second multiplier input. It is connected through a resistive
divider to the rectified mains to obtain a sinusoidal voltage reference. The multiplier can be
described by the relationship:
Equation 47
VCS = VCS _ OFFSET + k m ⋅
(VCOMP − 2.5 V) ⋅ VMULT
2
VFF
Where:
●
VCS (multiplier output) is the reference for the current sense (VCS_OFFSET is its offset).
●
k = 0.45 (typ.) is the multiplier gain.
●
VCOMP is the voltage on pin #2 (E/A output).
●
VMULT is the voltage on pin #3.
●
VFF is the second input to the multiplier for 1/V2 function. It compensates the control
loop gain dependence on the mains voltage. The voltage at this pin is a DC level equal
to the peak voltage on the MULT pin (pin #3).
Figure 12. Multiplier characteristics for
VFF = 3 V
Figure 11. Multiplier characteristics for
VFF =1 V
-ULTIPLIER#HARACTERISTICS
6&&6
-ULTIPLIERCHARACTERISTICS
6&&6
6#/-0
6#/-0
5PPERVOLTAGECLAMP
5PPERVOLTAGE
6
6
6
6
6#3M6
6#36
6
6
6
6
6
6
6
6
6
6-5,4 6
!-V
6-5,46
Figure 11 and Figure 12 show the typical multiplier characteristics.
24/36
Doc ID 16032 Rev 3
!-V
AN3009
Designing a transition mode PFC
The linear operation of the multiplier is guaranteed within the range 0 to 3 V of VMULT and
the range 0 to 1.16 V (typ.) of Vcs, while the minimum guaranteed value of the maximum
slope of the characteristics family (typ.) is given in Equation 48.
Equation 48
dVCS
V
= 1.66
dVMULT
V
The voltage on the MULT pin is also used to derive the information on the RMS mains
voltage for the VFF compensation. The multiplier divider should be calculated by taking into
account the relation with the VFF pin so that the description of the VFF pin comes before the
dimensioning formula.
Pin 5 (voltage feed-forward): the power-stage gain of the PFC pre-regulators varies with the
square of the RMS input voltage. So does the crossover frequency fc of the overall openloop gain because the gain has a single pole characteristic. This leads to large trade-offs in
the design. For example, setting the gain of the error amplifier to get fc = 20 Hz at 264 Vac
means having an fc of about 4 Hz at 88 Vac, resulting in sluggish control dynamics.
Additionally, the slow control loop causes large transient current flows during rapid line or
load changes that are limited by the dynamics of the multiplier output. This limit is
considered when the sense resistor is selected to let the full load power pass under the
minimum line voltage conditions, with some margin. But a fixed current limit allows
excessive power inputs at high lines, whereas a fixed power limit requires the current limit to
vary inversely with the line voltage.
The voltage feed-forward can compensate for the gain variation with the line voltage and
allow overcoming all of the above-mentioned issues. It consists of deriving a voltage
proportional to the input RMS voltage, feeding this voltage into a squarer/divider circuit (1/V2
corrector) and providing the resulting signal to the multiplier that generates the current
reference for the inner current control loop.
In this way, a change in the line voltage causes an inversely proportional change of the half
sine amplitude at the amplifier’s output (if the line voltage doubles, the amplitude of the
multiplier output is halved and vice-versa), so that the current reference is adapted to the
new operating conditions with (ideally) no need for invoking the slow dynamics of the error
amplifier. Additionally, the loop gain is constant throughout the input voltage range, which
significantly improves dynamic behavior at low lines and simplifies loop design.
Actually, with other PFCs embedding the voltage feed-forward function, deriving a voltage
proportional to the RMS line voltage implies a form of integration, which has its own time
constant. If it is too small, the voltage generated is affected by a considerable amount of
ripple at twice the mains frequency, which causes distortion of the current reference
(resulting in high THD and poor PF); if it is too large, there is a considerable delay in setting
the right amount of feed-forward, resulting in excessive overshoot and undershoot of the
pre-regulator's output voltage in response to large line voltage changes. Clearly a trade-off
is required.
The L6564 realizes an innovative voltage feed-forward which, with a technique that makes
use of just two external parts, overcomes this time constant trade-off issue whichever
voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor
RFF, both connected from the pin VFF (pin #5) to ground, complete an internal peak-holding
circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on the
MULT pin (pin #3). In this case, the following value has been selected.
Doc ID 16032 Rev 3
25/36
Designing a transition mode PFC
AN3009
CFF = 1 μF
RFF = 1 MΩ
(15)
In this way, if a sudden rise occurs in the line voltage, CFF is rapidly charged through the low
impedance of the internal diode; if a drop occurs in the line voltage, an internal "mains drop"
detector enables a low impedance switch that suddenly discharges CFF, thus avoiding a long
settling time before reaching the new voltage level. Consequently, an acceptably low steadystate ripple and low current distortion can be achieved without any considerable undershoot
or overshoot on the pre-regulator's output, like in systems with no feed-forward
compensation. This pin is internally connected to a comparator in order to provide the
brownout (AC mains undervoltage) protection. A voltage below 0.8 V shuts down (does not
latch) the IC and brings its consumption to a considerably lower level. The IC restarts when
the voltage at the pin goes above 0.88 V. This information has to be taken into account when
the MULT divider is selected.
The procedure to properly set the operating point of the multiplier is described hereafter.
First, the maximum peak value for VMULT, (VMULTmax) is selected. This value, which
occurs at the maximum mains voltage, should be 3 V or nearly so in wide-range mains, and
less in case of single mains. The sense resistor selected is Rs = 0.27 Ω as described in the
pin #4 paragraph. According to the L6564 datasheet and the linearity setting of the pin, the
maximum voltage accepted on the multiplier input is:
VMULTmax = 3 V
(16)
From (16) the maximum required divider ratio is calculated as:
Equation 49
kp =
VMULT max
2 ⋅ VACmax
=
3.00 V
2 ⋅ 265 Vac
= 8 ⋅ 10 − 3
Assuming a 60 µA current is flowing into the multiplier divider, the lower resistor value can
be calculated as:
Equation 50
RmultL =
VMULT max 3.00 V
=
= 50 kΩ
60 μA
60 μA
A commercial value of 51 kΩ for the lower resistor has been selected. The upper resistor
value can now be calculated as:
Equation 51
RmultH =
1− k p
kp
RmultL =
1 − 8 ⋅ 10 −3
8 ⋅ 10 −3
51 kΩ = 6.319 MΩ
For this application, we have selected RmultH = 6.9 MΩ and RmultL = 51 kΩ. Note that for
RmultH a resistor with a suitable voltage rating (>400 V) is needed, otherwise more in-series
resistors must be used.
The voltage on the multiplier pin with the selected component values is re-calculated when
the minimum line voltage is 0.93 V and the maximum line voltage is 2.74 V. The multiplier
works correctly within its linear region.
26/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
Because the MULT divider also determines the mains input voltage at which the PFC starts
and stops (brownout function), these values are calculated using the actual divider ratio.
Equation 52
0.88 V RmultH + RmultL
⋅
RmultL
2
VSTART =
VSTART =
0.88 V 6.9 MΩ + 51 kΩ
⋅
= 84.4 V
51 kΩ
2
As well as the stop voltage:
Equation 53
VSTOP =
0.80 V RmultH + RmultL
⋅
RmultL
2
VSTOP =
0.80 V 6.9 MΩ + 51 kΩ
⋅
= 77.1 V
51 kΩ
2
The start and stop PFC mains voltages are compatible with the input mains voltage range
(1).
In order to obtain the required start-up and shut-down voltage, a reiteration might be
required, done by selecting the MULT resistors and checking the actual PFC start and stop
mains voltages.
Pin 7 (ZCD): pin #7 is the input of the zero current detector circuit. In transition mode PFC,
the ZCD pin is connected through a limiting resistor to the auxiliary winding of the boost
inductor. The ZCD circuit is triggered by the negative-going edge: when the voltage on the
pin falls below 0.7 V, it sets the PWM latch and thus the MOSFET is turned on. However, to
do so, the circuit must first be armed: prior to falling below 0.7 V, the voltage on pin #7 must
experience a positive-going edge that exceeds 1.4 V (due to the MOSFET's turn-off). The
maximum main-to-auxiliary winding turn ratio (nmax) must ensure that the voltage delivered
to the pin during the MOSFET's OFF time is sufficient to arm the ZCD circuit. A safe margin
of 15% has been added.
Equation 54
n max =
nprimary
n auxiliary
=
Vout − 2 ⋅VACmax
1.4 V ⋅ 1.15
n max =
400 V − 2 ⋅ 265 Vac
= 15.71
1.4 V ⋅ 1.15
If the winding is also used to supply the IC, the above criteria may not be compatible with the
VCC voltage range. To solve this incompatibility, the self-supply network shown in Figure 18
can be used.
The minimum value of the limiting resistor can be found considering the maximum voltage
across the auxiliary winding with a selected turn ratio equal to 10 and assuming a 0.6 mA
current through the pin.
Equation 55
Vout
− VZCDH
n
R1 = aux
0.6 mA
400 V
− 5 .7 V
R1 = 10
= 57.16 kΩ
0.6 mA
Equation 56
R2 =
2 ⋅ VAC max
− VZCDL
n aux
0.6 mA
R2 =
Doc ID 16032 Rev 3
2 ⋅ 265 Vac
−0 V
10
= 62.4 kΩ
0.6 mA
27/36
Designing a transition mode PFC
AN3009
VZCDH at 5.7 V and VZCDL at 0 V are the upper and lower ZCD clamp voltages of the L6564.
Considering the highest value of the two calculations, an RZCD equal to 68 kΩ has been
selected as the limiting resistor.
The actual value can then be tuned by trying to make the activation of the MOSFET occur
right on the valley of the drain voltage (which is resonating because the boost inductor has
run out of energy – as shown in Figure 13).This minimizes the power dissipation at turn-on.
Figure 13. Optimum MOSFET activation
!-V
Pin 8 (GND): this pin acts as the current return for both the signal’s internal circuitry and for
the gate drive current. When layouting the printed circuit board, these two paths should run
separately.
Pin 9 (GD): this pin is the output of the driver. It can drive an external MOSFET with a
600 mA source and a 800 mA sink capability.
The high-level voltage of this pin is clamped at about 12 V so as to avoid excessive gate
voltages in case the pin is supplied with a high Vcc. To avoid undesired switch-ons of the
external MOSFET because of some leakage current when the supply of the L6564 is below
the UVLO threshold, an internal pull-down circuit holds the pin low. The circuit guarantees
1.1 V maximum on the pin (when Isink = 2 mA), with Vcc > VCC_ON. This allows omitting
the "bleeder" resistor connected between the gate and the source of the external MOSFET
used for this purpose.
Pin 10 (Vcc): this pin is the supply of the device. It is externally connected to the start-up
circuit (normally, one resistor is connected to the rectified mains) and to the self-supply
circuit.
Whatever the configuration of the self-supply system, a capacitor must be connected
between this pin and ground.
To start the L6564, the voltage must exceed the start-up threshold (12 V typ.). Below this
value the device does not work and consumes less than 90 µA (typ.) from Vcc. This allows
the use of high-value start-up resistors (in the hundred kΩ), which reduces power
consumption and optimizes system efficiency at low loads, especially in wide-range mains
applications.
When operating, the current consumption (of the device only, not of the gate drive) rises to a
value that depends on the operating conditions but never exceeds 6 mA.
The device keeps on working as long as the supply voltage is over the UVLO threshold
(13 V max). If the Vcc voltage exceeds 22.5 V, an internal Zener diode (rated at 20 mA) is
activated in order to clamp the voltage. Remember that during normal operation, the internal
28/36
Doc ID 16032 Rev 3
AN3009
Designing a transition mode PFC
Zener does not have to clamp the voltage because the power consumption of the device
increases considerably, as does its junction temperature. The suggested operating condition
for safe operation of the device is below the minimum clamping voltage of the pin.
Doc ID 16032 Rev 3
29/36
Design example using the L6564-TM PFC Excel spreadsheet
4
AN3009
Design example using the L6564-TM PFC Excel
spreadsheet
An Excel spreadsheet is provided to allow quick and easy design of a boost PFC preregulator using the STM L6564 controller, operating in transition mode. Figure 14 shows the
first sheet already filled with the input design data used in Chapter 3.
Figure 14. Excel spreadsheet design specification input table
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The tool can generate a complete parts list of the PFC schematic represented in Figure 15,
including the power dissipation calculation of the main components.
30/36
Doc ID 16032 Rev 3
AN3009
Design example using the L6564-TM PFC Excel spreadsheet
Figure 16. Excel spreadsheet TM PFC schematic
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The bill of material shown in Figure 17 is automatically compiled by the Excel spreadsheet.
It summarizes all the selected components as well as some salient data.
Doc ID 16032 Rev 3
31/36
Design example using the L6564-TM PFC Excel spreadsheet
AN3009
Figure 17. Excel spreadsheet BOM - 100 W TM PFC based on L6564
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32/36
Doc ID 16032 Rev 3
!-V
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EVL6564-100W demonstration board
EVL6564-100W demonstration board
Figure 18 shows the schematic of a 100 W, wide-range TM PFC based on the L6564
device. It has been dimensioned using the Excel tool presented in Chapter 4.
Figure 18. Wide-range 100 W demonstration board electrical circuit (EVL6564-100W)
!-V
33/36
References
6
34/36
AN3009
References
1.
L6564 datasheet
2.
“A systematic approach to frequency compensation of the voltage loop in boost PFC
pre regulators”, abstract
3.
AN1089
4.
AN3022
Doc ID 16032 Rev 3
AN3009
7
Revision history
Revision history
Table 1.
Document revision history
Date
Revision
Changes
10-Feb-2010
1
Initial release.
07-May-2010
2
Modified: Figure 10 and 15
22-Oct-2010
3
Modified: Section 3.4 and Equation 40
Doc ID 16032 Rev 3
35/36
AN3009
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Doc ID 16032 Rev 3