SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 • • • • • DW OR NT PACKAGE (TOP VIEW) 3-State I/O-Type Read-Back Inputs Bus-Structured Pinout True Logic Outputs Designed With Nine Bits for Parity Applications Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) 300-mil DIPs OERB 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND description This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q OEQ LE The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable (OEQ) input is high. Read back is provided through the output-enable (OERB) input. When OERB is taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. When OERB is taken high, the output of the data latches is isolated from the D inputs. OERB does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict. The SN74ALS992 is characterized for operation from 0°C to 70°C. logic symbol† OEQ 14 1 OERB 11 CLR LE 1D 13 2 EN3 EN2 R C1 1D 2 2D 3D 4D 5D 6D 7D 8D 9D 23 3 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 logic diagram (positive logic) OEQ OERB CLR LE 1D 14 1 11 13 2 23 1D 1Q C1 R To Eight Other Channels timing diagram Data Bus Input Data tsu Read Back Input Data th LE tsu† tdis OERB tpd tpd Q CLR = H, OEQ = L † This setup time ensures that the read-back circuit will not create a conflict on the input data bus. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (OERB, OEQ, CLR, and LE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to D inputs and to disabled 3-state outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 recommended operating conditions MIN NOM MAX 4.5 5 5.5 VCC VIH Supply voltage VIL Low-level input voltage IOH High level output current High-level IOL Low level output current Low-level tw Pulse duration tsu Setup time th TA Hold time, data after LE↓ 5 Operating free-air temperature 0 High-level input voltage 2 Q – 2.6 D – 0.4 Q 24 D 8 10 CLR low 10 Data before LE↓ 10 Data before OERB↓ 10 V V 0.8 LE high UNIT V mA mA ns ns ns 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS All outputs VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA Q VCC = 4.5 V, D VCC = 4 4.5 5V IOH = – 2.6 mA IOL = 4 mA VOL IOZH IOZL II Q 5V VCC = 4 4.5 Q VCC = 5.5 V, VCC = 5.5 V, Q D inputs All others D inputs‡ VCC = 5 5.5 5V V V 3.2 0.4 0.5 0.25 0.4 IOL = 24 mA VO = 2.7 V 0.35 0.5 VO = 0.4 V VI = 5.5 V IO§ VCC = 5.5 V, VO = 2.25 V Outputs high ICC 55V VCC = 5.5 V, OERB high 20 µA µA 0.1 20 20 – 0.1 – 0.1 – 30 V – 20 0.1 VI = 7 V VI = 0 0.4 4V All others UNIT – 1.2 0.35 VCC = 5 5.5 5V V, IIL MAX 0.25 VI = 2 2.7 7V All others D inputs‡ VCC – 2 2.4 TYP† IOL = 8 mA IOL = 12 mA VCC = 5 5.5 5V V, IIH MIN –112 30 50 Outputs low 50 80 Outputs disabled 35 55 mA µA mA mA mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ For I/O ports (QA thru QH), the parameters IIH and IIL include the off-state output current. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 switching characteristics (see Figure 1) PARAMETER FROM ((INPUT)) TO (OUTPUT) ( ) VCC = 4.5 V to 5.5 V, CL = 50 pF, TA = MIN to MAX† MIN MAX 3 14 4 16 6 20 8 25 Q 6 20 D 8 26 4 21 2 14 4 18 1 14 tPLH tPHL D Q tPLH tPHL LE Q tPHL CLR ten‡ tdis§ OERB D ten‡ tdis§ OEQ Q † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡ ten = tPZH or tPZL § tdis = tPHZ or tPLZ 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns SN74ALS992 9-BIT D-TYPE TRANSPARENT READ-BACK LATCH WITH 3-STATE OUTPUTS SDAS028B – APRIL 1984 – REVISED JANUARY 1995 PARAMETER MEASUREMENT INFORMATION 7V 7V S1 S1 500 Ω 1 kΩ Test Point From Output Under Test CL (see Note A) CL (see Note A) 500 Ω LOAD CIRCUIT FOR Q OUTPUTS 1 kΩ LOAD CIRCUIT FOR D OUTPUTS 3.5 V Timing Input Test Point From Output Under Test 1.3 V 3.5 V High-Level Pulse 1.3 V 1.3 V 0.3 V 0.3 V tw th tsu 3.5 V Data Input 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.3 V 0.3 V 3.5 V Output Control (low-level enabling) 1.3 V tPHL tPLH VOH 1.3 V 1.3 V tPHL Out-of-Phase Output (see Note B) Waveform 1 S1 Closed (see Note C) VOL tPLH VOH 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V 0.3 V tPZL 1.3 V tPLZ 0.3 V In-Phase Output 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V 1.3 V Input 3.5 V Low-Level Pulse [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note C) VOL 0.3 V VOH 1.3 V 0.3 V [0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. When measuring propagation delay times of 3-state outputs, switch S1 is open. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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