AEROFLEX CT2566-FP

CT2566
MIL-STD-1553 to Microprocessor
Interface Unit
Features
A E RO
www.aeroflex.com
C
F
LE
X LA
ISO
9001
E
I NC .
• 78 Pin, 2.1" x 1.87" x .25" PGA type package
• 82 Lead, 2.2" x 1.61 x .18" Flat Package
CIRCUIT TECHNOLOGY
S
Second Source Compatible to the BUS-66300
PGA Version available, (second source to the BUS-66312)
Compatible with MIL-STD-1750 CPUs
Compatible with MOTOROLA, INTEL, and ZILOG CPUs
Compatible with Aeroflex’s CT2565 BC/RT/MT and CT2512 RT
Minimizes CPU overhead
Signal controls for shared memory implementation
Transfers complete messages to shared memory
Provides memory mapped 1553 interface
Packaging – Hermetic Metal
B
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RTIFIED
Description
Aeroflex CT2566 MIL-STD-1553 to Microprocessor Interface Unit simplifies the CPU to 1553 Data
Bus interface. The CT2566 provides an interface by using RAM allowing the CPU to transmit or
receive 1553 traffic simply by accessing the memory. All 1553 message transfers are entirely
memory or I/O mapped. The CT2566 supports 1553 interface devices such as Aeroflex's CT2512
dual RT or the CT2565 dual BC, RT, and MT. The CT2566 operates over the full military -55°C to
+125°C temperature range.
IOEN
BUSREQ
BUSGRNT
BUSACK
CS
OE
WR
CLOCK IN
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
MEMORY
TIMING
CPU
TIMING
EXTEN
EXTLD
CONTENTION
RESOLVER
MEMCS
MEMOE
MEMWR
ADRINC
NBGRNT
BCSTART
TAGEN
EOM
SOM
MICROCODE
CONTROLLER
A15-A00
BLOCK
STATUS
WORD
D15-D00
OPERATION
CONTROL
REGISTERS
CONFIGURATION
REGISTER
START / RESET
REGISTER
INTERRUPT
GENERATOR
INTERRUPT
MASK
REGISTER
MSGERR
TIMEOUT
STATERR
LOOPERR
CHB/CHA
CTLINB/A
CTLOUT B/A
RTU/BC
MT
DBAC
SSBUSY
SSFLAG
SVCREQ
RESET
INT
Figure 1 – Functional Block Diagram
eroflex Circuit Technology – Data Bus Modules For The Future © SCDCT2566 REV B 8/10/99
PARAMETER
Specifications at Nominal Power Supply Voltages
VALUE
UNITS
Logic
IIH (With VIH = 2.7V)
−630
µA
IIL (With VIL = 0.0V)
−700
µA
IOH
4.0 min
mA
IOL
4.0
mA
VIH
2.0
V
VIL
0.8
V
VOH
3.7
V
VOL
0.4
V
12
MHz
5.0±10%
10 typ
V
mA
−55 to +125
−65 to +150
°C
°C
2.1 x 1.87 x 0.25
(53 x 47.5 x 6.4)
2.1 x 1.87 x 0.25
(55.6 x 40.6 x 3.71)
in
(mm)
in
(mm)
1 (28)
1 (28)
oz (g)
oz (g)
Clock
Power Supplies
Voltage
Current Drain
Temperature Range
Operating (Case)
Storage
Physical Characteristics
Size
78 pin DIP
82 pin flatpack
Weight
78 pin DIP
82 pin flatpack
Table 1 – Specifications
buffering architecture is provided to prevent
incomplete or partially updated information from
being transmitted onto the 1553 Data Bus.
The CT2566 requires an external, user supplied
clock.
GENERAL
The CT2566 was designed to perform required
handshaking to the 1553 interface device, storing
or retrieving message(s) from a user supplied
RAM and notifying the CPU that a 1553
transaction has occurred. The CPU uses this
RAM to read the received data as well as to store
messages to be transmitted onto the Bus.
The CT2566 can be used to implement BC, RT,
or MT operation and can be either memory
mapped or I/O mapped to CPU address space.
Registers internal to the CT2566 control its
operation.
The CT2566 can access up to four external,
user supplied registers and can address up to
64K words of RAM. The RAM selected must be a
non-latched static RAM (capable of meeting the
timing constraints for the CT2566). A double
Aeroflex Circuit Technology
COMPATIBLE MICROPROCESSOR TYPES
The CT2566 may be used with most common
microprocessors, including, the Motorola 68000
family, the Intel 8080 family, Zilog Z8000
products,
and
available
MIL-STD-1750
processors.
Interfacing the CT2566 to the 1553 Data Bus
requires external circuitry such as Aeroflex’s
CT2565(BC/RT/MT)
and
ACT4489D
transceivers. Figure 2 shows the interconnection
for these components.
2
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
NAME
I/O
DESCRIPTION
1
SELECT
I
Select. When active, selects CT2566 for operation.
2
RD/WR
I
3
READYD
O
4
EXTEN
O
5
TAGEN
O
6
EOM
I
7
SOM
I
8
STATERR
I
9
ADRINC
I
10
MEM/REG
I
11
CLOCK IN
I
Read/Write. Controls CPU bus data direction.
Ready Data. When active indicates data has been received
from, or is available to the CPU.
External Enable. Output from CT2566 to enable output from
external devices. Same timing as MEMOE.
Tag Enable. Enables an external time tag counter for
transferring the time tag word into memory.
End of Message. Input from 1553 device indicating end of
message.
Start of Message. Input from 1553 device indicating start of
message in RTU mode.
Status Error. Input from 1553 device when status word has
either a bit set or unexpected RT address (in BC mode only).
Address Increment. Sent from 1553 device to increment
address counter following word transfer.
Memory/Register. Input from CPU to select memory or
register data transfer.
Clock input; 50% duty cycle, 12MHz, max.
12
LOOPERR
I
13
BUSREQ
I
14
BUSGRNT
O
15
Not Used
-
16
MEMCS
O
17
OE
I
18
N/C
-
19
NBGRNT
I
20
+ 5 Volt
I
21
D15
I/O
Data Bus Bit 15 (MSB).
22
D13
I/O
Data Bus Bit 13.
23
D11
I/O
Data Bus Bit 11.
24
D09
I/O
Data Bus Bit 9.
25
D07
I/O
Data Bus Bit 7.
26
27
D05
D03
I/O
I/O
Data Bus Bit 5.
Data Bus Bit 3.
Loop Error. Input from 1553 device if short loop BIT fails.
Bus Request. When active, indicates 1553 device requires
use of the address/data bus.
Bus Grant. Handshake output to 1553 device in response to
BUS REQUEST indicating address/data bus available to
1553 device.
Memory Chip Select. Low from CT2566 to enable external
RAM. Used with 4K x 4 RAM type device to read RAM or
used in conjunction with MEMWR to write data into RAM.
Output Enable. Input from 1553 device used to enable
memory on the parallel bus.
Not Used.
Low pulse from 1553 device preceding start of received new
protocol sequence. Used with superseding command to reset
DMA in progress.
Logic power supply.
Table 2 – Pin Functions (78 Pin DIP)
Aeroflex Circuit Technology
3
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
NAME
I/O
DESCRIPTION
28
D01
I/O
Data Bus Bit 1.
Subsystem Flag. Output to 1553 device to set RT subsystem
flag status bit.
Subsystem Busy. Output to 1553 device to set RT subsystem
busy flag.
Output to 1553 device used in conjunction with MT to set
operating mode.
29
SSFLAG
O
30
SSBUSY
O
31
RTU/BC
O
32
A14
O
Address Bit 14.
33
A12
O
Address Bit 12.
34
A10
O
Address Bit 10.
35
A08
O
Address Bit 8.
36
A06
O
Address Bit 6.
37
A04
O
Address Bit 4.
38
A02
I/O
Address Bit 2.
39
A00
I/O
Address Bit 0 (LSB).
40
GND
-
41
STRBD
I
42
IOEN
O
43
EXTLD
O
44
CHB/CHA
45
INT
O
Interrupt. Interrupt pulse line to CPU.
46
BCSTART
O
47
RESET
O
48
MSGERR
I
Bus Controller Start. Outputs to 1553 in initiate BC cycle.
Reset. Output to external device from CT2566 consisting of
the OR condition of CPU reset and CPU Master Clear.
Message Error. Input from 1553 device when an error occurs
in message sequence.
49
CTLIN B/A
I
50
CTLOUT B/A
O
51
TIMEOUT
I
52
MSTRCLR
I
53
BUSACK
I
54
WR
I
55
CS
I
Signal Return.
Strobe Data. Used in conjunction with SELECT to indicate a
data transfer cycle to/from CPU.
Input/Output Enable. Output from CT2566 to enable external
buffers/latches connecting the hybrid to the address/data
bus.
External Load. Used to load data into external device via the
CT2566 data bus. Same timing as MEMWR.
Input from 1553 in RT mode used to indicate received 1553
message came in either Channel A or B.
Input to change active memory map area (0 = area A).
Output from CT2566 selecting which area is to be active (0 =
area A).
Input from 1553 device indicating no response time-out.
Master Clear. Power-on reset from CPU. Resets DMA in
progress and internal registers to logic “0”.
Bus Acknowledge. Input from 1553 device acknowledge
receipt of BUSGRNT.
Write. Input from 1553 device for writing data into memory.
Chip Select. Input from 1553 device that is routed to
MEMCS.
Table 2 – Pin Functions (78 Pin DIP) (Cont.)
Aeroflex Circuit Technology
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SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
NAME
I/O
DESCRIPTION
Memory Output Enable. Output from CT2566 to enable
memory output data.
Memory Write. Output pulse from CT2566 to write data bus
data into memory.
56
MEMOE
O
57
MEMWR
O
58
Not Used
-
59
MT
O
Bus Monitor. Used in conjunction with RTU/BC to set
operating mode.
60
D14
I/O
Data Bus Bit 14.
61
D12
I/O
Data Bus Bit 12.
62
D10
I/O
Data Bus Bit 10.
63
D08
I/O
Data Bus Bit 8.
64
D06
I/O
Data Bus Bit 6.
65
D04
I/O
Data Bus Bit 4.
66
D02
I/O
Data Bus Bit 2.
67
D00
I/O
68
SVCREQ
O
69
DBAC
O
Data Bus Bit 0 (LSB).
Service Request. Used to set service request bit in RT Status
Word.
Dynamic Bus Acceptance. Used to set status bit in RT Status
Word.
70
A15
O
Address Bit 15 (MSB).
71
A13
O
Address Bit 13.
72
A11
O
Address Bit 11.
73
A09
O
Address Bit 9.
74
A07
O
Address Bit 7.
75
A05
O
Address Bit 5.
76
A03
O
Address Bit 3.
77
A01
I/O
Address Bit 1.
78
GND
-
Chassis Ground.
Table 2 – Pin Functions (78 Pin DIP) (Cont.)
PIN NO.
FUNCTION
PIN NO.
FUNCTION
1
N/C
42
N/C
2
SELECT
43
GROUND
3
STRBD
44
CHASSIS GROUND
4
RD/WR
45
A00 (LSB)
5
IOENBL
46
A01
6
READYD
47
A02
7
EXTLD
48
A03
Table 3 – CT2566FP Pin Functions (82 Pin Flat Package)
Aeroflex Circuit Technology
5
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
PIN NO.
FUNCTION
PIN NO.
FUNCTION
8
EXTEN
49
A04
9
CHB/CHA
50
A05
10
TAGEN
51
A06
11
INT
52
A07
12
EOM
53
A08
13
BCSTART
54
A09
14
SOM
55
A10
15
RESET
56
A11
16
STATERR
57
A12
17
MSGERR
58
A13
18
ADRINC
59
A14
19
CTLIN B/A
60
A15
20
MEM/REG
61
RTU/BC
21
CTLOUT B/A
62
DBAC
22
CLOCK IN
63
SSBUSY
23
TIMEOUT
64
SVCREQ
24
LOOPERR
65
SSFLAG
25
MSTRCLR
66
D00
26
BUSYREQ
67
D01
27
BUSACK
68
D02
28
BUSGRNT
69
D03
29
WR
70
D04
30
N/C
71
D05
31
CS
72
D06
32
MEMCS
73
D07
33
MEMOE
74
D08
34
OE
75
D09
35
MEMWR
76
D10
36
Not Used
77
D11
37
N/C
78
D12
38
NBGRNT
79
D13
39
MT
80
D14
40
+5V
81
D15
41
N/C
82
N/C
Table 3 – CT2566FP Pin Functions (82 Pin Flat Package) (Cont.)
Aeroflex Circuit Technology
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SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
MEMORY MANAGEMENT
to ensure that the swapping of the current and
non-current areas doesn’t occur while the CT2566 is
processing a message from the 1553 device. During
message processing, the INCMD is a logic "0" and the
CPU’s map area selection is inhibited. CTLIN B/A will
be automatically latched back into the CT2566 when
INCMD and NODT change to a logic "1".
The RAM used by the CT2566 can be any standard
static memory with a WRITE STROBE pulse width
requirement less than 70ns. The RAM area is broken
down into pointers, look-up tables, and data blocks. All
1553 operation control is accomplished through the
RAM, including fault monitoring and data block
transfers.
For most applications, a 4K x 16 memory is sufficient
to store the number of messages, but the CT2566 can
access up to 64K words.
DESCRIPTOR STACK
The CT2566 uses a Descriptor Stack in BC and RTU
modes. Each stack entry contains four words which
refer to one 1553 message (See Figure 4). The Block
Status Word, shown in Figure 5, indicates the physical
bus which received the message (RTU mode), reports
whether or not an error was detected during message
transfer, and indicates whether the message was
completed (SOM replaced with EOM).
The user-supplied Time-Tag word is loaded at the
start of a message transfer and is updated at the end of
the transfer.
The contents of the fourth word in the Descriptor
Stack depends on the operating mode. In BC mode, it
contains the address of the message data block
containing the 1553 message formatted as shown in
Figure 6. In RTU mode, the word contains the received
1553 Command Word as shown in Figure 7.
A Stack Pointer must be initialized by the CPU. The
Descriptor Stack contains 64, four word entries, and
DOUBLE BUFFERING
A Double Buffering system is available to prevent
partially updated data blocks from being read by the
CPU or transferred onto the 1553 Data Bus. To use
Double Buffering the CPU must divide the RAM into
two areas: “current” and “non-current”. Two Stack
Pointers, Descriptor Stacks, and Look-Up Tables are
required to be used by the CPU.
The 1553 device has access only to the current area
of RAM, and will use the current Descriptor Stack and
Look-Up Table. While the 1553 device is processing
messages using the current area pointers, the CPU
can be setting up the next set of messages in the
non-current area of RAM.
Once an EOM or BCEOM occurs, the CPU can swap
the current and non-current areas by toggling bit 13 of
the Configuration Register (See register section for
description). The 1553 device will then have access to
the new current area. Meanwhile, the CPU can begin
processing the data received during the previous
transfer or can begin setting up the next set of 1553
messages.
BLOCK STATUS WORD
TIME TAG WORD
RESERVED
MESSABE BLOCK ADDRESS
BC DESCRIPTION BLOCK
BUS-66300
50 CTLOUT B/A
INCMD
NODT
12 MHz
D
Q
BLOCK STATUS WORD
LS74
C
TIME TAG WORD
RESERVED
Q
RECEIVED COMMAND WORD
RTU DESCRIPTION BLOCK
49 CTLIN B/A
Figure 4 – Descriptor Stack Entries
Notes:
(1) INCMD is from the BUS-65600 or BUS-65112.
(2) CTLOUT B/A reflects bit 13 of the Configuration Register.
(3) CTLIN B/A is used to select the current area.
automatically wraps around (the 64th entry is followed
by the first entry). The 1553 device uses the current
area Stack Pointer to determine the address of the
Stack entry to be used for the current 1553 message.
The CT2566 automatically increments the current area
Stack Pointer by four upon the completion of each
Figure 3 – Synchronized map switching u
the CT2566
An external circuit (shown in Figure 3) can be added
Aeroflex Circuit Technology
7
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
addition, the CT2566 can access up to four external,
user supplied registers. Possible external register
applications include: defining the RTU address, storing
a CPU Time Tag, and reading a captured Built-In-Test
(BIT) Word from the 1553 interface unit. For further
information, consult factory.
message regardless of whether or not an error was
detected during the processing of that message.
LOOK-UP TABLES
In RTU mode a Look-Up Table is provided to allow
the CT2566 to store messages in distinct areas of RAM
based upon the subaddress of the received command
word. See RTU operation for details.
The CT2566 uses the T/R and the five subaddress
bits to form a pointer into the “current area” Look-Up
Table. The first 32 words of this table are initialized by
the user with the addresses of the data blocks to be
used for receiving data into subaddress 0,1,2,…31.
The next 32 words are initialized by the user with the
address of the data blocks to be used when
transmitting data from subaddress 0,1,2,…31.
Table 2 – Internal Registers Address Definition
CT2566
Address Bits
A2 A1 A0
CT2566 REGISTERS
The CT2566 is controlled through the use of three
internal registers: the Interrupt Mask Register,
Configuration Register, and Start/Reset Register. In
15 14 13 12 11 10
9
8
0
0
0
0
0
1
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
Definition
Interrupt Mask Register
Configuration Register
Not Used
Start/Reset Register (write
only)
External Register
External Register
External Register
External Register
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
CONTROL AREA BIT B/A
MT
RTU/BC
BIT
DEFINITIONS
SUBSYSTEM FLAG
SERVICE REQUEST
BUSY
DB ACCEPT
STOP ON ERROR
CONTROL AREA B/A
RTU/BC/MT
1553 status word bit.
1553 status word bit.
1553 status word bit.
1553 status word bit.
Causes BC to stop at the end of current data block if an error is detected.
Used for double buffering (See Double Buffering).
Operating Mode.
Bit 15 Bit 14
0
0
0
1
1
0
1
1
Mode
BC
MT
RTU
ILLEGAL
Figure 8 – Configuration Register
Aeroflex Circuit Technology
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SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
LOOP TEST FAIL
RESPONSE TIME OUT (BC ONLY)
FORMAT ERROR
STATUS SET (BC ONLY)
ERROR FLAG
CHB/CHA (RTU ONLY)
SOM
EOM
Note: In BC mode Bit 13, CHB/CHA contains a logic "0" regardless of which channel is used.
Figure 5 – Block Status Word
CONFIGURATION
REGISTER
15
13
STACK
POINTERS
DESCRIPTOR
STACKS
DATA
BLOCKS
0
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
RESERVED
MESSAGE
BLOCK ADDR
DATA BLOCK
Note: User may opt to share memory block(s).
DATA BLOCK
Figure 6 – Use of Descriptor Stack – BC Mode
CONFIGURATION
REGISTER
15
13
STACK
POINTERS
DESCRIPTOR
STACKS
LOOK-UP TABLE
(DATA BLOCK ADDR)
DATA
BLOCKS
0
(1)
CURRENT
AREA B/A
BLOCK STATUS WORD
TIME TAG WORD
LOOK-UP
TABLE ADDR (2)
DATA BLOCK
RESERVED
RECEIVED COMMAND
WORD
Note: (1) User may opt to share memory block(s).
(2) See Figure 19.
DATA BLOCK
Figure 7 – Use of Descriptor Stack – RTU Mode
Aeroflex Circuit Technology
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SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
INTERRUPT MASK REGISTER
This register is an eight bit read/write register used to enable the interrupt conditions. All interrupts are enabled
with a logic "1" (See Figure 9).
15
1
4
1
1
1
1
1
3
2
1
0
1
NOT USED
BC EOM
FORMAT ERROR/STATUS SET
NOT USED
EOM
INTERRUPT
DEFINITION
EOM
End of Message. Set by CT2566 (during BC or RTU mode) every time a
1553 message is transferred (regardless of validity).
FORMAT ERROR/
Set by CT2566 for these conditions:
STATUS SET
Loop Test Failure: Last transmitted word did not match received word.
Message Error: Received message contained an address error, one of
eight 1553 status bits set, or 1553 specification violated (parity error,
Manchester error, etc).
Time-Out: Expected transmission was not received during allotted time
Status Set: Received status word contained status bit(s) set or address
error.
Bus Controller End of Message. Set by CT2566 (in BC mode) when all
messages have been transferred.
BC EOM
Figure 9 – Interrupt Mask Register
START/RESET REGISTER
Only two bits of this write only register are used, as illustrated in Figure 10.
15
1
0
NOT USED
CONTROLLER START
RESET
BIT
DEFINITION
RESET
Issued by the CPU to place the CT2566 in the power-on condition;
Configuration, and Interrupt Mask registers are reset to logic “0”.
CONTROLLER START
Issued by the CPU (BC mode) to start message transmission. The CPU
must first load the number of messages to transfer (256, max) in the
message count location of RAM (area A or B). Value is loaded in 1’s
complement (load FFFE to transmit one message). In MT mode it is
used to begin reception of 1553 messages. Issued by CPU in MT mode
to enable monitor operation.
Figure 10 – Start/Reset Register
Aeroflex Circuit Technology
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SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
BC Operation
The BC mode is selected by setting the two MSBs of
the Configuration Register to logic "0". This can be done
by writing directly to the register or by issuing a
MSTRCLR or RESET command. Note that a RESET
will also clear the Interrupt Mask Register.
BC Initialization.
For BC operation, the user initializes the RAM as
shown in Table 3 and follows the steps in Figure 11, BC
Initialization. The CPU loads the data blocks with 1553
messages (See Figure 12). The first word of each data
block must contain the Control Word (shown in Figure
13) for the message. The starting addresses of the data
blocks are placed in the fourth word of the Descriptor
Stack in the order the messages are to be transmitted
(i.e. the address of the first message is loaded into the
fourth location of the Stack, the address of the second
message is placed into the eighth location, etc). Once
the data blocks and the Descriptor Stack have been
initialized, the CPU loads the current area message
count with the number of messages to transfer (load in
1’s complement).
Table 3 - Typical BC Memory Map
(4K memory)]
HEX ADDRESS
FUNCTION
Fixed Areas
0100
0101
0104
0105
Stack Pointer A
Message Count A
Stack Pointer B
Message Count B
User Defined Areas
0108-013F
0140-017F
0180-01BF
01C0-01FF
•
•
0F00-0FFF
Not Used
Data Block 1
Data Block 2
Data Block 3
•
•
Descriptor Stack A
0000-00FF
Descriptor Stack B
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
CONTROL
WORD
BROADCAST
COMMAND
BROADCAST
COMMAND
(NO DATA)
RECEIVE
COMMAND
TRANSMIT
COMMAND
RECEIVE
COMMAND
MODE
COMMAND
MODE
COMMAND
MODE
COMMAND
DATA WORD
1
BROADCAST
COMMAND
LOOPED
BACK BY
CT2565
DATA WORD
1
TRANSMIT
COMMAND
LOOPED
BACK BY
CT2565
TRANSMIT
COMMAND
DATA WORD
MODE
COMMAND
LOOPED
BACK BY
CT2565
MODE
COMMAND
LOOPED
BACK BY
CT2565
DATA WORD
2
DATA WORD
2
STATUS
RECEIVED
TRANSMIT
COMMAND
LOOPED
BACK BY
CT2565
DATA WORD
LOOPED
BACK BY
CT2565
STATUS
WORD
STATUS
WORD
DATA WORD
LAST
DATA WORD
LAST
DATA WORD
1
STATUS
WORD 1
FROM XMTR
STATUS
WORD
DATA WORD
RECEIVED
MODE CODE
WITHOUT
DATA
DATA WORD
LOOPED
BACK BY
CT2565
DATA WORD
LAST
LOOPED
BACK BY
CT2566
DATA WORD
2
DATA WORD
1 RECEIVED
MODE CODE
WITH DATA
RECEIVE
DATA BLOCK
FORMAT
MODE CODE
WITH DATA
TRANSMIT
DATA BLOCK
FORMAT
STATUS
RECEIVE
DATA WORD
LAST
DATA WORD
2 RECEIVED
TRANSMIT
DATA BLOCK
LAST DATA
WORD
RECEIVED
BROADCAST
COMMAND
(NO DATA)
RECEIVE
DATA BLOCK
BROADCAST
COMMAND
WITH DATA
STATUS
WORD 2
FROM
RECEIVER
REMOTE
TERMINAL TO
REMOTE
TERMINAL
DATA BLOCK
Figure 12 – BC Message Data Block Formats
Aeroflex Circuit Technology
11
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
1. Reads the Stack Pointer to get the address of the
current Descriptor Stack Entry.
The CPU selects an internal register by asserting
MEM/REG and the A2 bit to logic "0" (See Table 2).
External registers are selected by asserting MEM/REG
logic "0" and A2 bit to a logic "1". The signals EXTEN
and EXTLD are used to read and write from the
external registers (See Figures 26 to 28).
START
ISSUE RESET COMMAND
Configuration Register
The Configuration Register is an eight bit read/write
register used to define the 1553 operating mode (BC,
MT, or RTU) and the associated RTU status bits. The
four MSBs define the mode of operation; the four LSBs
define the RTU status bits (See Figure 8).
All bits in the Configuration Register (except bit 12)
will be present on the respective CT2566 output pins to
the 1553 device. The MT bit is inverted at the output.
To begin transferring messages onto the bus, the
CPU must issue a Controller Start Command (See
Figure 14). This is done by setting bit 1 of the
Start/Reset Register to a logic "1". An EOM interrupt
will be generated each time a message transfer has
been completed. A BCEOM will be generated once the
specified number of messages has been transferred
(message counter = FFFF).
A Format Error Status Set Interrupt will be generated
at the end of a message if a timeout condition or error
condition was detected. If the STOP ON ERROR bit in
the Configuration Register is set, the CT2566 will stop
bus transactions until a new Controller Start command
is issued by the CPU. These interrupts may be masked
by the CPU through the Interrupt Mask Register.
INITIALIZE STACK POINTER
LOAD MESSAGE COUNTER
LOAD EVERY FOURTH
LOCATION OF STACK WITH
STARTING ADDRESS
LOAD MESSAGES
SET CONFIGURATION
RESISTER TO BC MODE
INITIALIZE INTERRUPT
MASK REGISTER
ISSUE START COMMAND
Figure 11
BC Initialization (under user control)
BC START SEQUENCE
After setting the CONTROLLER START bit in the
Start/Reset Register, the CT2566 takes the following
actions:
1. Reads the Stack Pointer to get the address of the
current Descriptor Stack Entry.
2. Stores an SOM flag in the Block Status Word to
indicate a transfer operation is in progress.
3. Stores the Time Tag if used.
4. Reads the Data Block Address from the fourth
location of the Descriptor Stack and transfers the
Data Block Address into an internal Address
Register.
5. Issues a BCSTART pulse to the associated 1553
device to start the message transfers.
Note that data words are transferred to an from
memory by the associated 1553 interface unit using the
internal Address Register.
15
7
0
NOT USED
BUS CHANNEL A/B
NOT USED
MASK BROADCAST BIT
NOT USED
MODE CODE
BROADCAST
RTU TO RTU
Note: When the BC expects the BROADCAST bit set in the status
word, a logic "1" will mask the status interrupt error flag. A
FORMAT error will be generated if the MASK BROADCAST bit
is not set.
BC EOM Sequence.
Upon completion of a 1553 message (valid or invalid)
the 1553 interface unit issues an EOM pulse to the
CT2566 which takes the following actions:
Aeroflex Circuit Technology
8
Figure 13 – BC Control Word
12
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
*
CONTROLLER START
COMMAND RECEIVED
READS STACK POINTER
LOAD BLOCK STATUS WORD
INTO FIRST WORD OF
DESCRIPTOR STACK ENTRY
(SET SOM BIT IN BLOCK
STATUS WORD)
LOAD TIME TAG INTO
SECOND WORD OF
DESCRIPTOR
STACK ENTRY
DATA BLOCK
TRANSFERRED OK
?
YES
NO
OBTAIN DATA BLOCK
ADDRESS FROM FOURTH WORD
STOP ON
ERROR SET
?
YES
ISSUE BC START TO 1553 DEVICE
NO
MORE MESSAGES
TO SEND
?
NO
READ CONTROL WORD TO
DETERMINE TYPE OF TRANSFER
ISSUE BC EOM
TRANSFER DATA TO/FROM
1553 BUS (NOTE: RAM NOW
CONTROLLED BY INPUT PINS
CS AND OE
STOP
YES
UPDATE BLOCK STATUS WORD
UPDATE TIME TAG
INCREMENT STACK
POINTER BY FOUR.
DECREMENT
MESSAGE COUNT
*
After controller start is issued the subsystem must wait until BCEOM is active
before issuing the next controller start.
Figure 14 – BC Sequence of Operation (Under CT2566 Control)
Aeroflex Circuit Technology
13
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
2. Updates the Block Status Word by resetting the
SOM and setting EOM and any error bits.
3. Updates the Time Tag if used.
4. Increments the contents of the Stack Pointer by
four and increments the Message Counter by
one.
5. Initiates a message transfer beginning with new
Controller Start sequence if more messages are
to be transmitted.
6. Generates a BCEOM interrupt if enabled and no
further messages are to be transmitted.
Note that if an error is received and STOP ON
ERROR is set, the CT2566 completes the current
BCEOM sequence and then stops. The Stack Pointer
will point to the next message to be transmitted.
Table 4 – Typical RTU memory map (4K memory)
HEX ADDRESS
Fixed Areas
0100
0101
0104
0105
0108-013F
0140-017F
01C0-01FF
Descriptor Stack Pointer A
Reserved
Descriptor Stack Pointer B
Reserved
Spare
Look-Up Table A
Look-Up Table B
User Defined Areas
0180-019F
01A0-01BF
0200-021F
0220-023F
0240-025F
0260-027F
•
•
0EE0-0EFF
0000-00FF
0F00-0FFF
RTU Operation
The RTU mode is selected by setting bit 15 of the
Configuration Register to logic "1" and bit 14 to
logic "0".
RTU Initialization
For RTU operation, the user initializes the RAM as
shown in Table 4 and follows the steps shown in Figure
15, RTU Initialization Chart.
Look-Up Tables
The first 32 words of the Look-Up Table are initialized
with the addresses of the data blocks to be used when
received data from subaddress 0, 1, 2,…31. The next
32 table locations should be initialized with the address
of the data blocks to be used when the RTU is
instructed to transmit data from subaddress 0, 1,
2,…31. The data blocks may be any length sufficient to
contain the particular message as long as the data
block does not cross a 256 word boundary. Data blocks
may be shared by Look-Up Tables A and B, if desired
by the user (See Figure 16). The 1553 device can only
access the current Look-Up Table and the current
Descriptor Stack. The CPU selects the current area
through bit 13 of the Configuration Register.
Once in the RTU mode, the CT2566 will store the
command word in the fourth location of the current area
Descriptor Stack. The status of the message will be
recorded in the first location of the stack.
The data associated with the message will be
transferred to/from the data block indicated by the
Look-Up Table entry for that subaddress. If a system
Time Tag is provided by the user the CT2566 will
record the time of the SOM sequence in the second
word of the Stack entry.
When the CT2566 received an EOM pulse from the
1553 device, it resets the SOM bit in the Block Status
Word and sets the EOM bit and any error bits as
necessary. The Time Tag entry will be updated and an
EOM interrupt will be generated by the CPU, if enabled.
Aeroflex Circuit Technology
FUNCTION
Data Block 1
Data Block 2
Data Block 3
Data Block 4
Data Block 5
Data Block 6
•
•
Data Block 107
Descriptor Stack A
Descriptor Stack B
15
8 7 6 5 4
0 0 0 0 0 0 0 0
0
1
CURRENT AREA B/A
(CONFIG. REG BIT 13)
TR (FROM COMMAND
WORD)
RTU SUBADDRESS BITS
(FROM COMMAND WORD)
RTU LOOK-UP TABLE ADDRESS
RTU SOM Sequence
Initiated when 1553 terminal puts a 1553 command
word on D00-D15 and pulses SOM low. The CT2566
saves the command received in an internal register.
Figure 17 illustrates the RTU Sequence of Operation
once a 1553 command word is received. Once the
command word is received, the CT2566 performs the
following steps:
1. Reads the Stack Pointer to get the address of the
current Descriptor Stack Entry.
2. Stores a SOM flag in the Block Status Word to
indicate a transfer operation is in progress.
3. Stores the Time Tag if used.
14
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
4. Stores the Command Word received.
5. Reads a Block address from the Look-Up Table
using the T/R bit and the subaddress from the
Command Word; transfers the Block address into
the address register. Data words are transferred
to/from memory by the associated 1553 interface
unit using the address register.
START
ISSUE RESET COMMAND
RTU EOM Sequence
INITIALIZE STACK POINTER
At the end of a 1553 message (valid or invalid) the
CT2566 received an EOM pulse and then performs the
following:
1. Updates the Block Status Word.
2. Updates the Time Stage if used.
3. Increments the Stack Pointer by four.
4. Generates an Error Interrupt if enabled.
SET UP LOOK-UP TABLE(S)
DATA BLOCK ASSIGNMENTS
SET UP DATA BLOCKS
SET CONFIGURATION
REGISTER TO RTU MODE
1553 COMMAND WORD
RECEIVED
INITIALIZE INTERRUPT
MASK REGISTER
READ STACK POINTER
WAIT FOR 1553 COMMAND
UPDATE DESCRIPTOR STACK
BLOCK STATUS WORD, TIME
TAG AND COMMAND WORD
Figure 15
RTU Initialization (under user control)
READ LOOK-UP TABLE USING
T/R SUBADDRESS CURRENT
AREA BIT B/A
TRANSFER DATA TO/FROM
1553 INTERFACE DEVICE
MESSAGE COMPLETE
?
NO
YES
RECEIVED COMMAND WORD
RTU
WORD
ADDR T/R SUBADD COUNT
UPDATE BLOCK STATUS WORD
AND TIME TAG
INCREMENT STACK POINTER
BY FOUR
GENERATE EOM INTERRUPT AND
ERROR INTERRUPT IF ERROR
CONDITION DETECTED
EXIT
XXXXX
0
00000
XXXXX
USER DEFINED 0140
XXXXX
0
00001
XXXXX
USER DEFINED 0141
XXXXX
0
00010
XXXXX
USER DEFINED 0142
XXXXX
1
11110
XXXXX
USER DEFINED 017E
XXXXX
1
11111
XXXXX
USER DEFINED 017F
}
64
LOCATIONS
Figure 16 – RTU Look-up Table
Figure 17 – RTU Sequence of Operation
(under CT2566 control)
Aeroflex Circuit Technology
LOOK-UP TABLE
15
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
MT Operation
Word. The RAM automatically wraps around (from
location FFFF to location 0000), shown in Figure 20.
Bit 7 of the Identification Word can be reset by the
CPU each time it reads the associated data word into
CPU memory. This provides a simple method of
keeping track of words that have been processed by
the CPU.
The MT mode is selected by setting bit 15 of the
Configuration Register to logic "0" and bit 14 to a
logic "1" along with issuing a Controller Start
Command.
START
15
8 7
1
0
1 1 1
ISSUE RESET COMMAND
GAP TIME
SET TO "1"
CLEAR RAM
ERROR (1 = ERROR, 0 = GOOD STATUS)
COMMAND SYNC
1553 CHANNEL A/B
INITIALIZE STACK POINTER
WORD GAP
SET TO "0"
Note: Each bit of the GAP TIME field
represents .5µs.
SET CONFIGURATION REGISTER
TO MT MODE
Figure 19 – MT Identification Word
ISSUE START COMMAND
Figure 18 – MT Initialize
(under user control)
START COMMAND ISSUED
MT Initialization
For MT operations, the entire RAM is used as the MT
Stack (See Table 5) and the setups shown in Figure 18
are followed. The user instructs the CT2566 where to
store the first received 1553 word by loading the
starting word address in the Stack Pointer. Once a
Controller Start command is issued, the CT2566 will
store this value in the internal Address Register.
The identification Word provides the CPU with
additional information regarding the received 1553
word, its format is shown in Figure 19. This information
allows the user to develop algorithms to restructure the
message transfers. External Logic can be used for
triggering on specific commands or subaddresses. For
further information, consult factory.
The 1553 device will generate an Identification Word
for every word that is transferred across the 1553 Data
Bus. The CT2566 stores the received 1553 word in the
RAM location indicated by the internal Address
Register. The contents of this register are incremented
by one so that it points to the next word in RAM, and
the Identification Word is stored at that location. The
internal Address Register is then incremented by one
again, in preparation for storing the next Identification
Aeroflex Circuit Technology
GET STACK POINTER FROM
WORD 100 IN RAM AND
STORE IN INTERNAL REGISTER
WORD TRANSFERRED
ACROSS 1553 BUS
?
YES
NO
STORE RETREIVED 1553 WORD
IN RAM, INCREMENTS INTERNAL
ADDRESS REGISTER
STORE IDENTIFICATION WORD
IN RAM, INCREMENT INTERNAL
ADDRESS REGISTER
Figure 20 – MT Sequence of Operation
(under CT2566 control)
16
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Table 5 – Typical MT memory map (4K memory)
HEX ADDRESS
FUNCTION
0000
First Received 1553 Word
0001
First Identification Word
0002
Second Received 1553 Word
0003
Second Identification Word
0004
•
0005
•
0006
•
0007
•
0008
•
•
•
•
•
MODE CODES
All mode codes applicable to dual redundant
systems are recognized by the CT2566. Mode
codes can be illegalized by the 1553 BC or
RTU device. Refer to the CT2565 or CT2512
data sheets for more information.
0100
Stack Pointer A (Fixed location)*
0104
Stack Pointer B
•
•
•
•
FFFF
Word stored at FFFF will be followed by
the word stored at 0000.
* The Stack Pointer is loaded into an internal Address
Register upon receipt of a Controller Start command. This
location is overwritten by data once monitor operation
begins.
CT2566 Timing Clock in at 12 MHz
Figures 21 through 37 illustrate the timing for the CT2566 and its operation. All timing definitions are listed in the
tables below and the appropriate definitions are repeated with each diagram.
Delay Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
td3
CPU MEMWR low delay
-
120
ns
td4
CPU MEMOE low delay
-
115
ns
td5
EXTLD low delay
-
130
ns
td6
RESET low delay
-
30
ns
td7
Internal Register delay (read)
-
60
ns
td8
Internal Register delay (write)
-
60
ns
td9
Register Data/Address set-up time
-
40
ns
td10
Register Data/Address hold time
-
0
ns
Aeroflex Circuit Technology
17
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Delay Timing (Cont.)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td11
BC SOM Cycle DMA delay
-
120
ns
td12
INT low delay
-
50
ns
td13
RTU SOM Cycle DMA delay
-
200
ns
td14
1553 Command Word set-up time
60
-
ns
td15
1553 Command Word hold time
60
-
ns
td16
MT SOM Cycle DMA delay
-
120
ns
td17
CS low to MEMCS low delay
-
30
ns
td18
OE low to MEMOE low delay
-
30
ns
td19
WR low to MEMWR low delay
-
30
ns
td20
BUSGRNT high delay
-
25
ns
td21
BUSACK low Address delay
-
45
ns
td22
BUSACK high Address delay
-
25
ns
td23
Address increment delay
-
200
ns
MIN
MAX
UNITS
Pulse Width Timing
SYMBOL
DESCRIPTION
tpw1
READYD pulse width (CPU Handshake)
70
-
ns
tpw2
CPU MEMWR low pulse width
70
-
ns
tpw3
CPU MEMCS low pulse width
70
-
ns
tpw4
EXTLD low pulse width
70
-
ns
tpw5
RESET low pulse width
70
-
ns
tpw6
DMA MEMWR low pulse width
70
-
ns
tpw7
DMA MEMCS low pulse width
70
-
ns
tpw8
BCSTART low pulse width
70
-
ns
tpw9
EOM low pulse width
50
200
ns
tpw10
INT low pulse width
*
tpw9
ns
tpw11
INT low (BCEOM) pulse width
60
-
ns
tpw12
SOM low pulse width
50
200
ns
tpw13
NBGRNT low pulse width
50
200
ns
tpw14
ADRINC low pulse width
50
200
ns
tpw15
MSTRCLR low pulse width
150
-
ns
*The min value of tpw10 equals tpw9 minus 30 ns.
Aeroflex Circuit Technology
18
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
STRBD (41)
See Note
SELECT (1)
td1
IOEN (42)
td2
td7
READYD (3)
tpw1
MEM/REG (10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
SSFLAG, SSBUSY, SVCRQST
DBAC, RTU/BC, MT, CTLIN B/A
DATA VALID
D15-D00
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Reads from Internal Register
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
-
60
ns
tpw1
td7
READYD pulse width (CPU Handshake)
Internal Register delay (read)
Figure 21 – CPU reads from internal register
Aeroflex Circuit Technology
19
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
See Note
STRBD (41)
SELECT (1)
td1
IOEN (42)
td9
td2
tpw1
READYD (3)
MEM/REG (10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
td8
SSFLAG, SSBUSY, SVCRQST
DATA LATCHED
DBAC, RTU/BC, MT, CTLIN B/A
Configuration Register Only
DATA VALID
D15-D00
td10
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Writes to Internal Register
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
tpw1
READYD pulse width (CPU Handshake)
td8
Internal Register delay (write)
-
60
ns
td9
Register Data/Address set-up time
-
40
ns
td10
Register Data/Address hold time
-
0
ns
Figure 22 – CPU writes to internal register
Aeroflex Circuit Technology
20
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
See Note
STRBD (41)
SELECT (1)
td1
IOEN (42)
td2
td9
tpw1
READYD (3)
MEM/REG (10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
EXTEN (4)
D15-D00
DATA FROM EXTERNAL REGISTER
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Reads from External Register Timing
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
-
40
ns
tpw1
td9
READYD pulse width (CPU Handshake)
Register Data/Address set-up time
Figure 23 – CPU reads from external register
Aeroflex Circuit Technology
21
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
See Note
STRBD (41)
SELECT (1)
td2
td1
IOEN (42)
td9
td10
tpw1
READYD (3)
MEM/REG (10)
RD/WR (2)
A02 (38)
VALID
A01 (77)
VALID
A00 (39)
td5
EXTLD (43)
tpw4
CPU DATA
D15-D00
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Writes to External Register
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
tpw1
READYD pulse width (CPU Handshake)
td5
EXTLD low delay
-
130
ns
td9
Register Data/Address set-up time
-
40
ns
td10
Register Data/Address set-up time
-
0
ns
tpw4
EXTLD low pulse width
70
-
ns
Figure 24 – CPU writes to external register
Aeroflex Circuit Technology
22
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
See Note
STRBD (41)
SELECT (1)
IOEN (42)
td2
td1
tpw1
READYD (3)
MEM/REG (10)
RD/WR (2)
MEMCS (16)
MEMOE (56)
td4
A15-A00
RAM ADDRESS VALID
D15-D00
RAM DATA VALID
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Reads from Ram
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
-
115
ns
tpw1
td9
READYD pulse width (CPU Handshake)
CPU MEMOE low delay
Figure 25 – CPU reads from RAM
Aeroflex Circuit Technology
23
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
See Note
STRBD (41)
SELECT (1)
IOEN (42)
td1
td2
tpw1
READYD (3)
MEM/REG (10)
RD/WR (2)
MEMCS (16)
tpw3
td3
MEMWR (57)
tpw2
A15-A00
RAM ADDRESS VALID
D15-D00
RAM DATA VALID
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
CPU Writes To Ram
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
-
120
ns
tpw1
td3
READYD pulse width (CPU Handshake)
CPU MEMWR low delay
tpw2
CPU MEMWR low pulse width
70
-
ns
tpw3
CPU MEMCS low pulse width
70
-
ns
Figure 26 – CPU writes to RAM
Aeroflex Circuit Technology
24
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
BUSREQ (13)
BUSGRNT (14)
td20
BUSACK (53)
A15-A00
td2
td22
MIL-STD-1553 TO CT2566 Handshaking
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td20
BUSGRNT high delay
-
25
ns
td21
BUSACK low Address delay
-
45
ns
td22
BUSACK high Address delay
-
25
ns
MIN
MAX
UNITS
Figure 27 – MIL-STD-1553 to CT2566 Handshaking
CS (55)
td17
MEMCS (16)
OE (17)
td18
MEMOE (56)
WR (54)
td19
MEMWR (57)
MIL-STD-1553 Terminal to Delay
SYMBOL
DESCRIPTION
td17
CS low to MEMCS low delay
-
30
ns
td18
OE low to MEMOE low delay
-
30
ns
td19
WR low to MEMWR low delay
-
30
ns
Figure 28 – MIL-STD-1553 terminal I/O delay
Aeroflex Circuit Technology
25
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
BUSACK (53)
td14
ADRINC (9)
ADDRESS
A15-A00
ADDRESS + 1
td23
CT2566 Address Increment
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
tpw14
ADRINC low pulse width
50
200
ns
td23
Address increment delay
-
200
ns
MIN
MAX
UNITS
-
30
ns
150
-
ns
Figure 29 – CT2566 Unit Address Increment
tpw15
MSTRCLR (52)
See Note
RESET (47)
td6
CT2566 Direct Increment
SYMBOL
td6
tpw15
DESCRIPTION
RESET low delay
MSTRCLR low pulse width
NOTE: The RESET (low) pulse width will be approximately equal to that of MSTRCLR (low).
Figure 30 – CT2566 direct reset
Aeroflex Circuit Technology
26
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12MHz Clock
(Internal)
STRBD (41)
See Note
SELECT (1)
IOEN (42)
td1
td2
READYD (3)
tpw1
MEM/REG 10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
D00 (67)
RESET (47)
tpw5
NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
Programmed CT2566 Reset
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td1
READYD low delay (CPU Handshake)
-
200
ns
td2
IOEN high delay (CPU Handshake)
-
20
ns
70
-
ns
70
-
ns
tpw1
tpw5
READYD pulse width (CPU Handshake)
RESET low pulse width
Figure 31 – Programmed CT2566 reset
Aeroflex Circuit Technology
27
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Aeroflex Circuit Technology
12 MHz Clock
(Internal)
STRBD (41)
SELECT (1)
IOEN (42)
td10
READYD (3)
td9
td11
MEM/REG (10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
D01 (28)
MEMCS (16)
MEMWR (57)
MEMOE (56)
28
TAGEN (5)
tpw8
BCSTART (46)
A15-A00
STACK POINTER
STACK ADDRESS
STACK ADDRESS + 1
STACK ADDRESS + 2
STACK ADDRESS + 3
D15-D00
STACK ADDRESS
BLOCK STATUS WORD
TIME TAG
TRI-STATE
BLOCK ADDRESS
BC SOM Timing (No Contention)
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td9
Register Data/Address set-up time
-
40
ns
td10
Register Data/Address hold time
-
0
ns
td11
BC SOM Cycle DMA delay
-
120
ns
tpw8
BCSTART low pulse width
70
-
ns
Figure 32 – BC SOM timing (no contention)
BC EOM Timing (No Contention)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td9
INT low delay
-
50
ns
tpw9
INT low pulse width
50
200
ns
tpw10
INT low pulse width
*
tpw9
ns
tpw11
INT low delay
60
-
ns
* The min value of tpw10 equals tpw9 minus 30ns.
12 MHz Clock
(Internal)
EOM (6)
tpw9
MEMCS (16)
MEMWR (57)
MEMOE (56)
TAGEN (5)
INT (45)
td12
EOM/Error
tpw10
A15-A00
STACK POINTER
STACK ADDRESS
STACK ADDRESS + 1
STACK ADDRESS + 2
STACK ADDRESS + 3
D15-D00
STACK ADDRESS
BLOCK STATUS WORD
TIME TAG
TRI-STATE
TRI-STATE
Figure 33 – BC EOM timing (no contention)
tpw11
BC
STACK POINTER
STACK POINTER + 1
STACK POINTER + 2
STACK POINTER + 1
STACK ADDRESS + 4
MESSAGE COUNT
TRI-STATE
MESSAGE COUNT + 1
EOM
Figure 33 – BC EOM timing (no contention) con’t
Aeroflex Circuit Technology
29
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Aeroflex Circuit Technology
td13
SOM (7)
tpw12
NBGRNT (19)
tpw13
MEMCS (16)
MEMWR (57)
MEMOE (56)
TAGEN (5)
tpw8
BCSTART (46)
A15-A00
td14
D15-D00
td15
1553 COMMAND
WORD
STACK POINTER
STACK ADDRESS
STACK ADDRESS + 1
STACK ADDRESS + 2
STACK ADDRESS + 3
LOOK-UP ADDRESS
STACK ADDRESS
BLOCK STATUS WORD
TIME TAG
TRI-STATE
COMMAND
BLOCK ADDRESS
30
RTU SOM Timing (No Contention)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
-
200
ns
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
td13
RTU SOM Cycle DMA delay
td14
1553 Command Word set-up time
60
-
ns
td15
1553 Command Word hold time
60
-
ns
tpw8
BCSTART low pulse width
70
-
ns
tpw12
SOM low pulse width
50
200
ns
tpw13
NBGRNT low pulse width
50
200
ns
Figure 34 – RTU SOM (no contention)
Aeroflex Circuit Technology
12 MHz Clock
(Internal)
EOM (6)
tpw9
MEMCS (16)
MEMWR (57)
MEMOE (56)
TAGEN (5)
INT (45)
tpw10
A15-A00
STACK POINTER
STACK ADDRESS
STACK ADDRESS + 1
STACK ADDRESS + 2
STACK ADDRESS + 3
STACK POINTER
D15-D00
STACK ADDRESS
BLOCK STATUS WORD
TIME TAG
TRI-STATE
TRI-STATE
STACK ADDRESS + 4
31
RTU EOM Timing (No Contention)
SYMBOL
DESCRIPTION
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
tpw9
RESET low delay
tpw10
MSTRCLR low pulse width
MIN
MAX
UNITS
50
200
ns
*
tpw9
ns
* The min value of tpw10 equals tpw9 minus 30ns.
Figure 35 – RTU EOM timing (no contention)
12 MHz Clock
(Internal)
STRBD (41)
SELECT (1)
IOEN (42)
READYD (3)
MEM/REG (10)
RD/WR (2)
A02 (38)
A01 (77)
A00 (39)
D01 (28)
td16
MEMCS (16)
MEMOE (56)
BCSTART (46)
tpw6
A15-A00
STACK POINTER
D15-D00
STACK ADDRESS
MT SOM Timing (No Contention)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
td16
MT SOM Cycle DMA delay
-
120
ns
tpw6
BCSTART low pulse width
70
-
ns
Figure 36 – MT SOM timing (no contention)
Aeroflex Circuit Technology
32
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
12 MHz Clock
(Internal)
MEMCS (16)
tpw6
MEMOE (56)
tas1
tpw7
MEMWR (57)
tah2
tas2
tah1
A15-A00
D15-D00
tds2
tdh2
tds1
DMA READ
tdh1
DMA WRITE
DMA Read/Write Timing (SOM/EOM Cycles)
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
tas1
DMA Address set-up time
40
-
ns
tah1
DMA Address hold time
60
-
ns
tds1
DMA Address set-up time
83
-
ns
tdh1
DMA Address hold time
30
-
ns
tas2
DMA Address set-up time
-
45
ns
tah2
DMA Address hold time
0
-
ns
tds2
DMA Address set-up time
-
83
ns
tdh2
DMA Address hold time
0
-
ns
tpw6
DMA MEMWR low pulse width
70
-
ns
tpw7
DMA MEMCS low pulse width
70
-
ns
Figure 37 – DMA Read/Write timing (SOM/EOM cycles)
Aeroflex Circuit Technology
33
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Table 6 – CT2566 Pin Out Description
(DDIP)
Pin
#
1
41
2
42
3
43
4
44
5
45
6
46
7
47
8
48
9
49
10
50
11
51
12
52
13
53
14
54
15
55
16
56
17
57
18
58
19
59
20
SELECT
STRBD
RD/WR
IOEN
READYD
EXTLD
EXTEN
CHB/CHA
TAGEN
INT
EOM
BCSTART
SOM
RESET
STATERR
MSGERR
ADRINC
CTLIN B/A
MEM/REG
CTLOUT B/A
CLOCK IN
TIMEOUT
LOOPERR
MSTRCLR
BUSREQ
BUSACK
BUSGRNT
WR
N/C
CS
MEMCS
MEMOE
OE
MEMWR
N/C
N/C
NBGRNT
MT
+5 Volt
CT2566
MIL-STD-1553
to µPROCESSOR
INTERFACE UNIT
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
SSFLAG
SVCREQ
SSBUSY
DBAC
RTU/BC
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
GND
GND
21
60
22
61
23
62
24
63
25
64
26
65
27
66
28
67
29
68
30
69
31
70
32
71
33
72
34
73
35
74
36
75
37
76
38
77
39
78
40
Function
Pin
#
Function
1
SELECT
40
GND
2
RD/WR
41
STRBD
3
READYD
42
IOEN
4
EXTEN
43
EXTLD
5
TAGEN
44
CHB/CHA
6
EOM
45
INT
7
SOM
46
BCSTART
8
STATERR
47
RESET
9
ADRINC
48
MSGERR
10
MEM/REG
49
CTLIN B/A
11
CLOCK IN
50
CTLOUT B/A
12
LOOPERR
51
TIMEOUT
13
BUSREQ
52
MSTRCLR
14
BUSGRNT
53
BUSACK
15
N/C
54
WR
16
MEMCS
55
CS
17
OE
56
MEMOE
18
N/C
57
MEMWR
19
NBGRNT
58
N/C
20
+ 5 Volt
59
MT
21
D15
60
D14
22
D13
61
D12
23
D11
62
D10
24
D09
63
D08
25
D07
64
D06
26
D05
65
D04
27
D03
66
D02
28
D01
67
D00
29
SSFLAG
68
SVCREQ
30
SSBUSY
69
DBAC
31
RTU/BC
70
A15
32
A14
71
A13
33
A12
72
A11
34
A10
73
A09
35
A08
74
A07
36
A06
75
A05
37
A04
76
A03
38
A02
77
A01
39
A00
78
GND
DDIP Pin Connection Diagram, CT2566 and Pinout
Aeroflex Circuit Technology
34
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Table 7 – CT2566 Pin Out Description
(FP)
Pin
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
N/C
SELECT
STRBD
RD/WR
IOENBL
READYD
EXTLD
EXTEN
CHB/CHA
TAGEN
INT
EOM
BCSTART
SOM
RESET
STATERR
MSGERR
ADRINC
CTLIN B/A
MEM/REG
CTLOUT B/A
CLOCK IN
TIMEOUT
LOOPERR
MSTRCLR
BUSYREQ
BUSACK
BUSGRNT
WR
N/C
CS
MEMCS
MEMOE
OE
MEMWR
N/C
N/C
NBGRNT
MT
+5V
N/C
N/C
CT2566FP
MIL-STD-1553
to µPROCESSOR
INTERFACE UNIT
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
SSFLAG
SVCREQ
SSBUSY
DBAC
RTU/BC
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00 (LSB)
CASE GND
GROUND
N/C
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
Function
Pin
#
Function
1
N/C
42
N/C
2
SELECT
43
GROUND
3
STRBD
44
CASE GND
4
RD/WR
45
A00 (LSB)
5
IOENBL
46
A01
6
READYD
47
A02
7
EXTLD
48
A03
8
EXTEN
49
A04
9
CHB/CHA
50
A05
10
TAGEN
51
A06
11
INT
52
A07
12
EOM
53
A08
13
BCSTART
54
A09
14
SOM
55
A10
15
RESET
56
A11
16
STATERR
57
A12
17
MSGERR
58
A13
18
ADRINC
59
A14
19
CTLIN B/A
60
A15
20
MEM/REG
61
RTU/BC
21
CTLOUT B/A
62
DBAC
22
CLOCK IN
63
SSBUSY
23
TIMEOUT
64
SVCREQ
24
LOOPERR
65
SSFLAG
25
MSTRCLR
66
D00
26
BUSYREQ
67
D01
27
BUSACK
68
D02
28
BUSGRNT
69
D03
29
WR
70
D04
30
N/C
71
D05
31
CS
72
D06
32
MEMCS
73
D07
33
MEMOE
74
D08
34
OE
75
D09
35
MEMWR
76
D10
36
N/C
77
D11
37
N/C
78
D12
38
NBGRNT
79
D13
39
MT
80
D14
40
+5V
81
D15
41
N/C
82
N/C
Flat Package Pin Connection Diagram, CT2566 and Pinout
Aeroflex Circuit Technology
35
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
Plug In Package Outline
2.100
1.870
Lead 1 & ESD
Designator
1.900
.100
.110
Pin 2
Pin 1
.050 Pin 19
TYP
Pin 20
.250
MAX
Pin 59
Pin 41
.018 DIA
TYP
1.650 1.500
Pin 60
Pin 78
Pin 21
Pin 22
.100
TYP
Pin 40
Pin 39
.250
1.800
Flat Package Outline
.050
2.200
MAX
.010
±.002
.015
Pin 42
Pin 82
.180
MAX
1.610
MAX
Lead 1 & ESD
Designator
.400
MIN
.095
(4 Places)
Aeroflex Circuit Technology
Pin 41
2.000
.050 Lead Centers
41 Leads/Side
36
.080
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700
CIRCUIT TECHNOLOGY
Ordering Information
Model Number
CT2566
CT2566-FP
Screening
DESC SMD #
Package
Military Temperature, -55°C to +125°C,
Screened to the individual test methods
of MIL-STD-883
-
Plug in
-
Flat Package
Specifications subject to change without notice
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
www.aeroflex.com/act1.htm
Aeroflex Circuit Technology
Telephone: (516) 694-6700
FAX:
(516) 694-6715
Toll Free Inquiries: (800) THE-1553
E-Mail: [email protected]
37
SCDCT2566 REV B 8/10/99 Plainview NY (516) 694-6700