MT70014 TWO CHANNEL ARINC TRANSMITTER • 8 bit parallel interface • TTL/CMOS compatible I/P • Single 5V supply with low power consumption < 50mW • Full MIL operating range • Automatic parity generation • HIGH/LOW speed programmable independently in each channel VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 1 MT70014 MAXIMUM RATINGS (Above which the useful life may be impaired) Storage Temperature Temperature (Ambient) under Bias Supply Voltage VDD DC Input Voltage Output Current (Single O/P) Output Current (Total O/P) - 65ºC to +150ºC - 55ºC to +125ºC -0.3V to + 7V -0.3 to VDD +0.3V 10mA 20mA ELECTRICAL CHARACTERISTICS over operating range PARAMETER IOH IOL VIH VIL IIL IOZ CI CI/O ICC DESCRIPTION Output High Current Output Low Current Input High Voltage Input Low Voltage Input Load Current Output Leakage Current Input Capacitance I/O Capacitance Supply Current TEST CONDITIONS VOH=2.8V VDD= 4.5V VOL=0.4V MIN 1.0 3.2 2.4 -0.3 TYP VSS 0.4V<VO<VCC Output Disabled Test Frequency = 1.0 MHZ -40 2 7 VCC = MAX. All inputs HIGH, All outputs open. VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 2 MAX UNITS VCC 0.8 0.45 40 2.6 9 1.5 mA mA Volts Volts mA uA pF pF mA MT70014 3. SWITCHING CHARACTERISTICS (For CL = 50pF & RL = 3K ohms) PARAMETER fCLK tP Clock Frequency Min Max Units - 5 MHz ( Serial data bit period for HNL input high ( ( Serial data bit period for HNL input low ( ( (f = f CLK/MHz) 50/f uS 380/f uS tRES NRSET pulse width 200nS tRTC Propagation delay, NRESET falling edge to TXC high - 200nS tRD Propagation delay, NRESET falling edge to data outputs low - 200nS tWL NLD pulse width 200nS - tGL Gap between NLD pulses 400nS - tSU Data set up time 100nS - tH Data hold time 100nS - tLTC Propagation delay, NLD rising edge following last byte load to TXZ low - 400nS tR Output rise time - 50nS tF Output fall time - 50nS tWTE NOT Transmit enable pulse width tTED Propagation delay NOT transmit enable falling edge or NOT Transmission complete falling edge to data output tDTC Last data bit of message to TXC high tM Time of data pulse output (mark time) - 100nS ) ) ) ) tp - 2tp - 200nS tp + 1% 2 VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 3 MT70014 FUNCTIONAL DESCRIPTION The device consists of two independent channels each of which functions as a parallel to serial data converter. The parallel data is loaded via an 8-bit input highway and the serial output is generated in the ARINC format, i.e. 31 bits of data plus one parity bit. The input highway (DIO to D17) is common to both channels as are the reset (NRESET) CLOCK 9clock), positive supply (VDD), and ground (VSS) pins. Each channel has 3 control inputs. Channel 0 has a ‘load’ input (NLDO), a ‘transmit enable’ input (NTXEO), and a ‘high/low speed’ (HNLO) control input. There are 3 outputs per channel. Channel 0 has a ‘data out zeros’ (ZDO) output, a ‘data out ones’ (ODO) output and a ‘transmission complete’ (TXCO) output. Operations for Channel 0 and Channel 1 are identical in all respects. The data to be transmitted by a particular channel is loaded as four 8-bit bytes via the input highway. The four bytes are stored on chip in the order in which they were loaded. Loading is performed by pulsing the (NLDO) input low. The data must then be changed to the value of the next byte and (NLDO) pulsed low again etc. The four bytes are transmitted in the order in which they were loaded. The only exception is the most significant bit of the 4th byte. This bit is ignored and a parity bit is transmitted in its place. The parity bit corresponds to an odd parity check on the first 31 bits, i.e. if the number of ones in the first 31 bits is odd, the parity bit is equal to zero. Data is only accepted if the TXCO output is high. Once byte 4 has been loaded, TXCO is driven low. Data must be valid on the input highway for tsu before and to tH after the (NLDO) rising edge. The clock (CLOCK) input of 5mhz + 1%* is divided down on chip by 50 to give a serial data transmission rate for (HNLO) high or by 380 for (HNLO) low. These rates correspond to the ARINC fast and slow rates respectively. The timing of the two output data lines (ODO) and (ZDO) is shown in Fig.2. A data value of one is signified by a positive pulse output on (ODO) and a zero by a positive pulse on (ZDO). The bit period tp will be 50/f CLK for (HNLO) high and 380/fCLK for (HNLO) low. * ARINC recommends that the transmission rate should not be precisely 100KHZ to avoid interference but any rate within + 1% of these can be used. The overall timing diagram for a complete data transfer is shown in Fig.3. When the last byte has been loaded (TXCO) goes low. This signal is combined with the output of an on chip latch which is set by the (NTXEO) signal to initiate the start of transmission. The latch is reset upon start of transmission. If the (NTXEO) signal is left permanently low the on chip latch is always set and transmission will be initiated by TXCO going low, i.e. as soon as the 4 bytes have been loaded. Hence there is an option between auto-start and controlled-start of transmission. At the end of the transmission TXCO goes high and the device is able to accept new data. The devices can be completely reset by pulsing the (NRESET) line low. This causes both channels to be put into the data load phase of operation. The TXC lines are forced high and all data outputs are forced low. the timing is shown in Fig. 4. INTERFACE DEFINITIONS The device is implemented as a monolithic circuit using CMOS compatible with standard TLL circuitry. A circuit with VOH (min) = 2.7V and VOL (max) = 0.4V will drive all inputs to the device and a standard TTL circuit with IIL (max) = -1.6mA at VI = 0.4V and IIH (max) = 40 uA at VI = 2.4V can be driven by all the outputs of the device. VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 4 MT70014 An on-chip resistor of nominal value 25K ohms is connected between the input pin and VDD. This is intended to pull up the input to a sufficiently high voltage to ensure switching when a standard TTL driver is driving the input. VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 5 MT70014 VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 6 MT70014 VLSI COMPONENTS FOR ARINC 429 DATA TRANSMISSION SYSTEMS 7