AGERE LU3X31T-T64

Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Overview
The LU3X31T-T64 is a fully integrated
10/100 Mbits/s physical layer device with an integrated transceiver. It is provided in a 64-pin TQFP
package with low-power operation and powerdown
modes. Typical applications for this part are CardBus
and PCMCIA Ethernet products. Operating at 3.3 V,
the LU3X31T-T64 is a powerful device for the forward
migration of legacy 10 Mbits/s products and noncompliant (does not have autonegotiation) 100 Mbits/s
devices. The LU3X31T-T64 was designed from the
beginning to conform fully with all pertinent specifications, from the ISO*/IEC 11801 and EIA†/TIA 568
cabling guidelines to ANSI‡ X3.263 TP-PMD to
IEEE § 802.3 Ethernet specifications.
■
100 Mbits/s PLL, combined with the digital adaptive equalizer, robustly handles variations in risefall time, excessive attenuation due to channel
loss, duty-cycle distortion, crosstalk, and baseline
wander
■
Transmit rise-fall time can be manipulated to provide lower emissions, amplitude fully compatible
for proper interoperability
■
Programmable scrambler seed for better FCC
compliancy
■
IEEE 802.3u Clause 28 compliant autonegotiation
for full 10 Mbits/s and 100 Mbits/s control
■
Fully configurable via pins and management
accesses
■
Extended management support with interrupt
capabilities
■
PHY MIB support
■
Symbol mode option
■
Low-power operation: <150 mA max
■
Low autonegotiation power: <30 mA
■
Very low powerdown mode: <5 mA
■
64-pin TQFP package (10 mm x 10 mm x 1.4 mm)
Features
■
Single-chip integrated physical layer and transceiver for 10Base-T and/or 100Base-T functions
■
IEEE 802.3 compatible 10Base-T and 100Base-T
physical layer interface and ANSI X3.263 TP-PMD
compatible transceiver
■
Built-in analog 10 Mbits/s receive filter, eliminating
the need for external filters
■
Built-in 10 Mbits/s transmit filter
■
10 Mbits/s PLL exceeding tolerances for both preamble and data jitter
* ISO is a registered trademark of The International Organization
for Standardization.
† EIA is a registered trademark of The Electronic Industries Association.
‡ ANSI is a registered trademark of The American National Standards Institute, Inc.
§ IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Table of Contents
Contents
Page
Overview................................................................................................................................................................... 1
Features ................................................................................................................................................................... 1
Pin Descriptions........................................................................................................................................................ 6
Functional Description ............................................................................................................................................ 10
Media Independent Interface (MII) ...................................................................................................................... 10
100Base-X Module.............................................................................................................................................. 11
100Base-X Receiver ........................................................................................................................................... 14
100Base-X Link Monitor ...................................................................................................................................... 15
100Base-TX Transceiver..................................................................................................................................... 16
10Base-T Module ................................................................................................................................................ 16
Clock Synthesizer................................................................................................................................................ 18
Autonegotiation ................................................................................................................................................... 18
Reset Operation .................................................................................................................................................. 19
100Base-X PCS Configuration............................................................................................................................ 20
MII Registers .......................................................................................................................................................... 21
dc and ac Specifications......................................................................................................................................... 31
Absolute Maximum Ratings................................................................................................................................. 31
Clock Timing........................................................................................................................................................... 32
Outline Diagram...................................................................................................................................................... 43
64-Pin TQFP ....................................................................................................................................................... 43
Ordering Information............................................................................................................................................... 44
Tables
Page
Table 1. Twisted-Pair Magnetic Interface ................................................................................................................. 5
Table 2. Twisted-Pair Transceiver Control ................................................................................................................ 6
Table 3. MII Interface ............................................................................................................................................... 6
Table 4. PHY Address Configuration ....................................................................................................................... 7
Table 5. 100Base-X PCS Configuration................................................................................................................... 7
Table 6. Autonegotiation Configuration .................................................................................................................... 7
Table 7. LED and Status Outputs ............................................................................................................................ 8
Table 8. Clock and Chip Reset ................................................................................................................................ 9
Table 9. Power and Ground ..................................................................................................................................... 9
Table 10. Symbol Code Scrambler ........................................................................................................................ 13
Table 11. Autonegotiation ...................................................................................................................................... 20
Table 12. MII Management Registers .................................................................................................................... 20
Table 13. Control Register (Register 0h) ............................................................................................................... 21
Table 14. Status Register (Register 1h)................................................................................................................. 23
Table 15. PHY Identifier (Register 2h) ................................................................................................................... 25
Table 16. PHY Identifier (Register 3h) ................................................................................................................... 25
Table 17. Autonegotiation Advertisement (Register 4h) ........................................................................................ 25
Table 18. Autonegotiation Link Partner Ability (Register 5h) ................................................................................. 25
Table 19. Autonegotiation Expansion Register (Register 6h) ................................................................................ 26
Table 20. Receive Error Counter (Register 15h).................................................................................................... 26
Table 21. PHY Control/Status Register (Register 17h).......................................................................................... 27
Table 22. Config 100 Register (Register 18h)........................................................................................................ 28
Table 23. PHY Address Register (Register 19h) ................................................................................................... 29
Table 24. Config 10 Register (Register 1Ah) ......................................................................................................... 29
Table 25. Status 100 Register (Register 1Bh) ....................................................................................................... 30
Table 26. Status 10 Register (Register 1Ch) ......................................................................................................... 30
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Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Table of Contents (continued)
Tables (continued)
Page
Table 27. Interrupt Mask Register (Register 1Dh).................................................................................................. 30
Table 28. Interrupt Status Register (Register 1Eh) ................................................................................................ 31
Table 29. Absolute Maximum Ratings.................................................................................................................... 31
Table 30. Operating Conditions.............................................................................................................................. 31
Table 31. dc Characteristics................................................................................................................................... 32
Table 32. System Clock (Xin) ................................................................................................................................. 32
Table 33. Transmit Clock (Input and Output) .......................................................................................................... 33
Table 34. Management Clock................................................................................................................................. 34
Table 35. MII Receive Timing................................................................................................................................. 35
Table 36. MII Transmit Timing ................................................................................................................................ 36
Table 37. Transmit Timing ...................................................................................................................................... 37
Table 38. Receive Timing....................................................................................................................................... 38
Table 39. Reset and Configuration Timing ............................................................................................................. 39
Table 40. PMD Characteristics............................................................................................................................... 40
Figures
Page
Figure 1. LU3X31T-T64 Block Diagram ................................................................................................................... 4
Figure 2. Pin Diagram .............................................................................................................................................. 5
Figure 3. 100Base-X Data Path ............................................................................................................................. 12
Figure 4. 10Base-T Module Data Path .................................................................................................................. 16
Figure 5. Hardware Reset Configurations.............................................................................................................. 19
Figure 6. System Timing........................................................................................................................................ 32
Figure 7. Transmit Timing (Input and Output) ........................................................................................................ 33
Figure 8. Management Timing ............................................................................................................................... 34
Figure 9. MII Receive Timing ................................................................................................................................. 35
Figure 10. MII Transmit Timing .............................................................................................................................. 36
Figure 11. Transmit Timing .................................................................................................................................... 37
Figure 12. Receive Timing ..................................................................................................................................... 38
Figure 13. Reset and Configuration Timing ........................................................................................................... 39
Figure 14. PMD Timing .......................................................................................................................................... 40
Figure 15. Connection Diagrams (Frequency References).................................................................................... 41
Figure 16. Connection Diagrams (10/100BTX Operation) ..................................................................................... 42
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LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Features (continued)
LEDS
MDIOINTZ
LEDS
MDIO
10/100-TX
MDC
PCS
TXD
TXER
TXCLK
RXD
RXDV
MII
INTERFACE LOGIC
TXEN
MANAGEMENT
INTERFACE
REGISTER/
CONFIG/
CONTROL
10/100-TX
DRIVERS
TPTX±
AUTONEG
RX10
SQUELCH
10/100-RX
PCS
RXER
RXCLK
COL
CLOCK SYNTHESIS
AND RECOVERY
ADAPTIVE EQUALIZER
BASELINE WANDER CORRECTION
TPRX±
CRS
5-6779(F).ar.2
Figure 1. LU3X31T-T64 Block Diagram
4
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
RXVDD2
RXGND2
TPRX–
TPRX+
RXGND1
RXVDD1
CSVDD
CSVDD
CSGND
TXVDD2
TPTX–
TPTX+
TXGND1
TXVDD1
REF100
REF10
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Features (continued)
12
37
VDD4
VDD5
13
36
GND4
GND1
14
35
MDIO
VDD1
15
34
CRS/PHY[3]
MDIOINTZ/PHY[2]
16
33
TXCLK
32
VDD6
PHY[1]
TXD0
38
31
11
30
COL/PHY[4]
100HDEN
TXD1
39
TXD2
10
29
LEDRX
PHY[0]
TXD3
40
28
9
TXER
LEDTX/ACTLED/BPSCR
RSTZ
27
41
TXEN
8
26
LEDCOL/BP4B5B
RESV
GND8
42
25
7
VDD8
LEDFD/10HDEN
EQVDD1
RXCLK
43
24
6
23
LNKLED/BPALIGN
EQGND1
RXD0
44
22
5
RXD1
MDC
TPTXTR
21
45
RXD2
4
20
XTLVDD
AUTONEN
RXD3
46
19
3
RXER
XIN
GND9
RXDV
XOUT
47
18
48
2
17
1
LEDSP/10FDEN
RESV
100FDEN
5-6780(F).br.5
Figure 2. Pin Diagram
Table 1. Twisted-Pair Magnetic Interface
Pin
No.
Pin Name
I/O
Pin Description
53
54
TPTX+
TPTX–
O
61
62
TPRX+
TPRX–
I
Twisted-Pair Transmit Driver Pair. These pins are used to transmit
100Base-T MLT-3 signals on Category 5 UTP cable or 10Base-T
Manchester signals on Category 3 UTP cable.
Twisted-Pair Receive Pair. These pins receive 100Base-T MLT 3 or
10Base-T Manchester data.
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LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Pin Descriptions
Table 2. Twisted-Pair Transceiver Control
Pin
No.
Pin Name
I/O
Pin Description
50
REF100
I
49
REF10
I
5
TPTXTR
I
Reference Resistor for 100 Mbits/s Twisted-Pair Driver. Connect
this pin to ground through a 301 Ω resistor.
Reference Resistor for 10 Mbits/s Twisted-Pair Driver. Connect
this pin to ground through a 4.64 kΩ resistor.
Twisted-Pair Transmitter 3-State. A high on this pin will 3-state the
twisted-pair outputs. Tie to ground in normal operation.
Table 3. MII Interface
Pin
No.
Pin Name
I/O
Pin Description
18
19
20
21
22
23
24
27
28
29
30
31
32
33
34
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
RXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
TXCLK
CRS/PHY[3]
O
O
O
O
O
O
O
I
I
I
I
I
I
O
I/O
39
COL/PHY[4]
I/O
35
45
16
MDIO
MDC
MDIOINTZ/PHY[2]
I/O
I
I/O
Receive Data Valid. Signals the presence of data on RXD[3:0].
Receive Error. Indicates a received coding error has occurred.
Receive Data[3].
Receive Data[2].
Receive Data[1].
Receive Data[0].
Receive Clock.
Transmit Enable. Signals the presence of data on TXD[3:0].
Transmit Error. Indicates a transmit coding error has occurred.
Transmit Data[3].
Transmit Data[2].
Transmit Data[1].
Transmit Data[0].
Transmit Clock.
Carrier Sense/PHY Address[3]. This output pin indicates the carrier
sense condition. See Table 4 for PHY[3] description.
Collision/False Carrier Sense. This output pin indicates collision
condition in normal MII operation and is squelch jabber in 10 Mbits/s
mode. See Table 4 for PHY[4] description.
Management Data I/O. Serial access to device config registers.
Management Data Clock. Clock for R/W of device config registers.
MDIO Interrupt (Active-Low). The MDIO interrupt pin outputs a logic
0 pulse of 40 ns, synchronous to XIN, whenever an unmasked interrupt condition is detected. Refer to management registers 1Dh and
1Eh for interrupt conditions. See Table 4 for PHY[2] description.
Note: Smaller font indicates that the pin has multiple functions.
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Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Pin Descriptions (continued)
Table 4. PHY Address Configuration
Pin
No.
Pin Name
I/O
Pin Description
10
12
16
34
39
PHY[0]
PHY[1]
PHY[2]/MDIOINTZ
PHY[3]/CRS
PHY[4]/COL
I
I
I/O
I/O
I/O
PHY Address[4:0]. These 5 pins are detected during powerup or reset to
initialize the PHY address used for MII management register interface. PHY
address 00h forces the PHY into MII isolate mode. PHY address pins[4:2]
have an internal 40 kΩ pull-down resistor. See Table 3 for MDIOINTZ, CRS,
and COL description.
Note: Smaller font indicates that the pin has multiple functions.
Table 5. 100Base-X PCS Configuration
Pin
No.
Pin Name
I/O
Pin Description
41
BPSCR/LEDTX/
I/O
Bypass Scrambler Mode. A high value on this pin during powerup or reset
will bypass the scramble/descramble operations in 100Base-X data path.
This pin has an internal 40 kΩ pull-down resistor. See Table 7 for LEDTX/
ACTLED description.
Bypass 4B/5B Mode. A high value on this pin during powerup or reset will
bypass the 4B/5B encoder of the PHY. This pin has an internal 40 kΩ pulldown resistor. See Table 7 for LEDCOL description.
Bypass Alignment Mode. A high value on this pin during powerup or reset
will bypass the alignment feature of the PHY. This bypass mode provides a
symbol interface. This pin has an internal 40 kΩ pull-down. See Table 7 for
LNKLED description.
ACTLED
42
BP4B5B/LEDCOL
I/O
44
BPALIGN/LNKLED
I/O
Note: Smaller font indicates that the pin has multiple functions.
Table 6. Autonegotiation Configuration (Refer to Table 11.)
Pin
No.
Pin Name
I/O
Pin Description
4
AUTONEN
I
2
100FDEN
I
11
100HDEN
I
17
10FDEN/LEDSP
I/O
Autonegotiation Enable. A high value on this pin during powerup or reset
will enable autonegotiation; a low value will disable it.
100 Full-Duplex Enable. The logic level of this pin is detected at powerup
or reset to determine whether 100 Mbits/s full-duplex mode is available.
When autonegotiation is enabled, this input sets the ability register bit in
advertisement register 4. When autonegotiation is not enabled, this input
will select the mode of operation.
100 Half-Duplex Enable. The logic level of this pin is detected at powerup
or reset to determine whether 100 Mbits/s half-duplex mode is available.
When autonegotiation is enabled, this input sets the ability register bit in
advertisement register 4. When autonegotiation is not enabled, this input
will select the mode of operation.
10 Full-Duplex Enable. The logic level of this pin is detected at
powerup or reset to determine whether 10 Mbits/s full-duplex mode is available. When autonegotiation is enabled, this input sets the ability register bit
in advertisement register 4. When autonegotiation is not enabled, this input
will select the mode of operation. This pin has an internal 40 kΩ pull-up
resistor. See Table 7 for LEDSP description.
Note: Smaller font indicates that the pin has multiple functions.
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LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Pin Descriptions (continued)
Table 6. Autonegotiation Configuration (Refer to Table 11.) (continued)
Pin
No.
Pin Name
I/O
Pin Description
43
10HDEN/LEDFD
I/O
10 Half-Duplex Enable. The logic level of this pin is detected at powerup or
reset to determine whether 10 Mbits/s half-duplex mode is available. When
autonegotiation is enabled, this input sets the ability register bit in advertisement register 4. When autonegotiation is not enabled, this input will select
the mode of operation. This pin has an internal 40 kΩ pull-up resistor. See
Table 7 for LEDFD description.
Note: Smaller font indicates that the pin has multiple functions.
Table 7. LED and Status Outputs
Pin
No.
Pin Name
I/O
Pin Description
40
LEDRX
I/O
41
LEDTX/ACTLED/
I/O
Receive LED. This output will drive a 10 mA LED if the LU3X31T-T64 is
receiving data from the UTP cable. This pin has an internal 40 kΩ pull-down
resistor. The LED should be connected as logic 0 configuration as shown in
Figure 5, without the 10 kΩ resistor.
Transmit LED or Activity LED. When bit 7 of register 17h is 0, this output
will drive a 10 mA LED if the LU3X31T-T64 is transmitting data. If the control
bit is set, then the LED will be driven whenever receive or transmit activity is
present. This pin has an internal 40 kΩ pull-down. The LED should be connected as LOGIC 0 configuration in Figure 5 without the 10 kΩ resistor. See
Table 5 for BPSCR description.
Link LED. This output will drive a 10 mA LED for as long as a valid link
exists across the cable. Place a 10 kΩ resistor across the LED pins if setting
to nondefault mode, i.e., bypass align mode as shown in Figure 5. See Table
5 for BPALIGN description.
Collision LED. This output will drive a 10 mA LED whenever the LU3X31TT64 senses a collision has occurred. Place a 10 kΩ resistor across the LED
pins if setting to nondefault mode, i.e., bypass 4B/5B mode as shown in Figure 5. See Table 5 for BP4B5B description.
Full-Duplex Status. This output will drive a 10 mA LED when the LU3X31TT64 is in full-duplex mode. Place a 10 kΩ resistor across the LED pins if setting to nondefault mode, i.e., 10HD disable mode as shown in Figure 5. See
Table 6 for 10HDEN description.
Speed Status. This output will drive a 10 mA LED when the LU3X31T-T64
is in 100 Mbits/s mode. Place a 10 kΩ resistor across the LED pins if setting
to nondefault mode, i.e., 10FD disable mode as shown in Figure 5. See
Table 6 for 10FDEN description.
BPSCR
44
LNKLED/BPALIGN
I/O
42
LEDCOL/BP4B5B
I/O
43
LEDFD/10HDEN
I/O
17
LEDSP/10FDEN
I/O
Note: Smaller font indicates that the pin has multiple functions.
8
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Pin Descriptions (continued)
Table 8. Clock and Chip Reset
Pin
No.
Pin Name
I/O
47
XIN
I
48
XOUT
O
9
RSTZ
I
1
8
RESV
—
Pin Description
Crystal Oscillator Input or Clock Input. See Figure 15 for a connection diagram.
Crystal Oscillator Feedback Output. If a single-ended external
clock is connected to XIN pin, then XOUT should be grounded for
minimum power consumption. See Figure 15 for a connection diagram.
Reset (Active-Low). This input must be held low for a minimum of
1 ms to reset the LU3X31T-T64.
Reserved. These pins are unused inputs and should be tied to
ground.
Table 9. Power and Ground
Plane
RX Analog
TX Analog
CS
Digital
Clock
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VCC Pin
Associated Ground Pin
Name
Pin Number
Name
Pin Number
RXVDD1
RXVDD2
TXVDD1
TXVDD2
CSVDD
CSVDD
VDD1
VDD4
VDD5
VDD6
VDD8
—
EQVDD1
XTLVDD
59
64
51
55
57
58
15
37
13
38
25
—
7
46
RXGND1
RXGND2
TXGND1
—
CSGND
—
GND1
GND4
—
—
GND8
GND9
EQGND1
—
60
63
52
—
56
—
14
36
—
—
26
3
6
—
9
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description
The LU3X31T-T64 integrates a 100Base-X physical
sublayer (PHY), a 100Base-TX physical medium
dependent (PMD) transceiver, and a complete 10BaseT module into a single chip for both 10 Mbits/s and
100 Mbits/s Ethernet operation. This device provides
an IEEE 802.3u compliant media independent interface
(MII) to communicate between the physical signaling
and the medium access control (MAC) layers for both
100Base-X and 10Base-T operations. The device is
capable of operating in either full-duplex mode or halfduplex mode in either 10 Mbits/s or 100 Mbits/s operation. Operational modes can be selected by hardware
configuration pins, selected by software settings of
management registers, or determined by the on-chip
autonegotiation logic.
The 10Base-T section of the device consists of the
10 Mbits/s transceiver module with filters and a
Manchester ENDEC module.
The 100Base-X section of the device implements the
following functional blocks:
■
100Base-X physical coding sublayer (PCS)
■
100Base-X physical medium attachment (PMA)
■
Twisted-pair transceiver
The 100Base-X and 10Base-T sections share the following functional blocks:
■
Clock synthesizer module (CSM)
■
MII registers
■
IEEE 802.3u autonegotiation
Each of these functional blocks is described below.
Media Independent Interface (MII)
The LU3X31T-T64 implements an IEEE 802.3u Clause
22 compliant MII as described below.
Interface Signals
Preliminary Data Sheet
July 2000
size data path, TXEN signals the presence of data on
TXD, TXER indicates that a transmit coding error has
occurred, and TXCLK is the transmit clock that synchronizes all the transmit signals. TXCLK is supplied by
the on-chip clock synthesizer.
Receive Data Interface. The MII receive data interface
comprises seven signals: RXD[3:0] are the nibble size
data path, RXDV signals the presence of data on RXD,
RXER indicates a received coding error, and RXCLK is
the receive clock. Depending upon the operation mode,
RXCLK is generated by the clock recovery module of
either the 100Base-X or 10Base-T receiver.
Status Interface. Two status signals, COL and CRS,
are generated in the LU3X31T-T64 to indicate collision
status and carrier sense status to the MAC. COL is
asserted asynchronously whenever LU3X31T-T64 is
transmitting and receiving at the same time in a halfduplex operation mode. In the full-duplex mode, COL is
inactive. CRS is asserted asynchronously whenever
there is activity on either the transmitter or the receiver.
In full-duplex mode, CRS is asserted only when there is
activity on the receiver.
Operation Modes
The LU3X31T-T64 supports three operation modes
and an isolate mode as described below.
100 Mbits/s Mode. For 100 Mbits/s operation, the MII
operates in nibble mode with a clock rate of 25 MHz. In
normal operation, the MII data at RXD[3:0] and
TXD[3:0] are 4 bits wide. In bypass mode (either
BYP_4B5B or BYP_ALIGN option selected), the MII
data takes the form of 5-bit code-groups. The least significant 4 bits appear on TXD[3:0] and RXD[3:0] as
usual, and the most significant bits (TXD[4] and
RXD[4]) appear on the TXER and RXER pins, respectively.
10 Mbits/s Mode. For 10 Mbits/s operation, the TXCLK
and RXCLK operate at 2.5 MHz. The data paths are
always 4 bits wide using TXD[3:0] and RXD[3:0] signal
lines.
Transmit Data Interface. The MII transmit data interface comprises seven signals: TXD[3:0] are the nibble
10
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
Functional Description (continued)
MII Isolate Mode. The LU3X31T-T64 implements an
MII isolate mode that is controlled by bit 10 of the control register (register 0h). The LU3X31T-T64 will set this
bit to one if the PHY address is set to 00000 upon powerup/hardware reset. Otherwise, the LU3X31T-T64 will
initialize this bit to 0. Setting this bit to a 1 will put the
LU3X31T-T64 into isolate mode.
The isolate mode can also be activated by setting the
PHY address (bits 15 through 11 of register 19h) to 0
through the serial management interface, although the
content of the isolate register is not affected by the
modification of PHY address.
The LU3X31T-T64 does not respond to packet data
present at TXD[3:0], TXEN, and TXER inputs and presents a high impedance on the TXCLK, RXCLK, RXDV,
RXER, RXD[3:0], COL, and CRS outputs. The
LU3X31T-T64 will continue to respond to all management transactions.
Serial Management Interface
The serial management interface (SMI) is the part of
the MII that is used to control and monitor status of the
LU3X31T-T64. This mechanism corresponds to the MII
specification for 100Base-X (Clause 22) and supports
registers 0 through 6. Additional vendor-specific registers are implemented within the range of 16 to 31. All
the registers are described in MII Registers on page 21
of this data sheet.
Management Register Access. The SMI consists of
two pins, management data clock (MDC) and management data input/output (MDIO). The LU3X31T-T64 is
designed to support an MDC frequency ranging up to
the IEEE specification of 2.5 MHz. The MDIO line is bidirectional and may be shared by up to 32 devices.
The MDIO pin requires a 1.5 kΩ pull-up resistor which,
during IDLE and turnaround periods, will pull MDIO to
a logic 1 state. Each MII management data frame is
64 bits long. The first 32 bits are preamble consisting of
32 contiguous logic 1 bits on MDIO and 32 corresponding cycles on MDC. Following preamble is the start-offrame field indicated by a <01> pattern. The next field
signals the operation code (OP): <10> indicates READ
from MII management register operation, and <01>
indicates WRITE to MII management register operation. The next two fields are PHY device address and
MII management register address. Both of them are
5 bits wide, and the most significant bit is transferred
first.
During READ operation, a 2-bit turnaround (TA) time
spacing between register address field and data field is
Lucent Technologies Inc.
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
provided for the MDIO to avoid contention. Following
the turnaround time, a 16-bit data stream is read from
or written into the MII management registers of the
LU3X31T-T64.
The LU3X31T-T64 supports a preamble suppression
mode as indicated by a 1 in bit 6 of the basic mode status register (BMSR, address 01h). If the station management entity (i.e., MAC or other management
controller) determines that all PHYs in the system support preamble suppression by returning a 1 in this bit,
then the station management entity need not generate
preamble for each management transaction. The
LU3X31T-T64 requires a single initialization sequence
of 32 bits of preamble following powerup/hardware
reset. This requirement is generally met by the mandatory pull-up resistor on MDIO or the management
access made to determine whether preamble suppression is supported. While the LU3X31T-T64 will respond
to management accesses without preamble, a minimum of one idle bit between management transactions
is required as specified in IEEE 802.3u.
The PHY device address for LU3X31T-T64 is stored in
the PHY address register (register address 19h). It is
initialized by the five I/O pins designated as PHY[4:0]
during powerup or hardware reset and can be changed
afterward by writing into register address 19h.
MDIO Interrupt. The LU3X31T-T64 implements interrupt capability that can be used to notify the management station of certain events. It generates an activehigh interrupt signal on the MDIOINTZ output pin
whenever one of the interrupt status registers (register
address 1Eh) becomes set while its corresponding
interrupt mask register (register address 1Dh) is
unmasked. Reading the interrupt status register (register 1Eh) shows the source of the interrupt and clears
the interrupt output signal.
In addition to the MDIOINTZ pin, the LU3X31T-T64 can
also support the interrupt scheme used by the TI ThunderLAN * MAC. This option can be enabled by setting
bit 11 of register 17h. Whenever this bit is set, the interrupt is signaled through both the MDIOINTZ pin and
embedded in the MDIO signal.
100Base-X Module
The LU3X31T-T64 implements a 100Base-X compliant
PCS and PMA and 100Base-TX compliant TP-PMD as
illustrated in Figure 3. Bypass options for each of the
major functional blocks within the 100Base-X PCS provides flexibility for various applications. 100 Mbits/s
PHY loopback is included for diagnostic purposes.
* TI is a registered trademark and ThunderLAN is a trademark of
Texas Instruments, Inc.
11
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description (continued)
RXCLK
5B/4B
DECODE
RXD[3:0]
BYP-4B5B
DESCRAMBLER
SERIAL
TO
PARALLEL
BYP-SCR
RXER
10/100
TRANSMIT
DRIVER
TPTX±
100BASE-X RECEIVER
100BASE-X TRANSMITTER
TRANSMIT
STATE
MACHINE
BYP-4B5B
BYP-SCR
BYP-ALIGN
MLT-3
STATE
MACHINE
TXD[3:0]
TPRX±
RECEIVE
STATE
MACHINE
RXDV
COL
TXCLK
TXEN
TXER
EQUALIZER
100 Mbit PHY
LOOPBACK PATH
BYP-ALIGN
CRS
CLOCK
RECOVERY
4B/5B
ENCODE
SCRAMBLER
PARALLEL
TO
SERIAL
5-6781(F).ar.2
Figure 3. 100Base-X Data Path
100Base-X Transmitter
The 100Base-X transmitter consists of functional
blocks which convert synchronous 4-bit nibble data, as
provided by the MII, to a 125 Mbits/s serial data
stream. The LU3X31T-T64 implements the 100Base-X
transmit state machine as specified in the IEEE 802.3u
Standard, Clause 24 and comprises the following functional blocks in its data path:
■
Symbol encoder
■
Scrambler block
■
Parallel/serial converter and NRZ/NRZI encoder
block
symbols for transmission. This conversion is required
to allow control symbols to be combined with DATA
symbols. Refer to the table below for 4B to 5B symbol
mapping.
Following onset of the TXEN signal, the 4B/5B symbol
encoder replaces the first two nibbles of the preamble
from the MAC frame with a /J/K code-group pair (11000
10001) start-of-stream delimiter (SSD). The symbol
encoder then replaces subsequent 4B codes with corresponding 5B symbols. Following negation of the
TXEN signal, the encoder substitutes the first two IDLE
symbols with a /T/R code-group pair (01101 00111)
end-of-stream delimiter (ESD) and then continuously
injects IDLE symbols into the transmit data stream until
the next transmit packet is detected.
Symbol Encoder. The symbol encoder converts 4-bit
(4B) nibble data generated by the MAC into 5-bit (5B)
12
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
Assertion of the TXER input while the TXEN input is
also asserted will cause the LU3X31T-T64 to substitute
HALT code-groups for the 5B code derived from data
present at TXD[3:0]. However, the SSD (/J/K) and ESD
(/T/R) will not be substituted with HALT code-groups.
Hence, the assertion of TXER while TXEN is asserted
will result in a frame properly encapsulated with the /J/
K and /T/R delimiters which contains HALT codegroups in place of the DATA code-groups.
The 100 Mbits/s symbol decoder translates all invalid
code groups into 0Eh by default. In case the ACCEPT
HALT register is set (bit 5 of register 18h), the HALT
code-group (00100) is translated into 05h instead.
Table 10. Symbol Code Scrambler
Symbol
Name
5B Code
[4:0]
4B Code
[3:0]
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
V
V
V
V
V
V
V
V
V
V
11110
01001
10100
10101
01010
01011
01110
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
10001
01101
00111
00100
00000
00001
00010
00011
00101
00110
01000
01100
10000
11001
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
undefined
0101
0101
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
undefined
Lucent Technologies Inc.
Interpretation
DATA 0
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
DATA 6
DATA 7
DATA 8
DATA 9
DATA A
DATA B
DATA C
DATA D
DATA E
DATA F
IDLE: interstream fill code
First start-of-stream delimiter
Second start-of-stream delimiter
First end-of-stream delimiter
Second end-of-stream delimiter
HALT: transfer error
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
Invalid code
13
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
Scrambler. For 100Base-TX applications, the scrambler is required to control the radiated emissions at the
media connector and on the twisted-pair cable.
The LU3X31T-T64 implements a data scrambler as
defined by the TP-PMD stream cipher function. The
scrambler uses an 11-bit ciphering linear feedback shift
register (LFSR) with the following recursive linear function:
X[n] = X[n – 11] + X[n – 9] (modulo 2)
The output of the LFSR is combined with the 5B data
from the symbol encoder via an exclusive-OR logic
function. By scrambling the data, the total energy
launched onto the cable is randomly distributed over a
wide frequency range.
A seed value for the scrambler function can be loaded
by setting bit 4 of register 18h. When this bit is set, the
content of bits 10 though 0 of register 19h, which consists of the 5-bit PHY address and a 6-bit user seed,
will be loaded into the LFSR. By specifying unique
seed value for each PHY in a system, the total EMI
energy produced by a repeater application can be
reduced.
Parallel-to-Serial & NRZ-to-NRZI Conversion. After
the transmit data stream is scrambled, the 5-bit codegroup is loaded into a shift register and clocked out with
a 125 MHz clock into a serial bit stream. The serialized
data is further converted from NRZ to NRZI format,
which produces a transition on every logic 1 and no
transition on logic 0.
Collision Detect. During 100 Mbits/s half-duplex operation, a collision condition is indicated if the transmitter
and receiver become active simultaneously. A collision
condition is indicated by the COL pin (pin 39). For fullduplex applications, the COL signal is never asserted.
A collision test register exists at address 0, bit 7.
100Base-X Receiver
The 100Base-X receiver consists of functional blocks
required to recover and condition the 125 Mbits/s
receive data stream. The LU3X31T-T64 implements
the 100Base-X receive state machine diagram as given
in ANSI/IEEE Standard 802.3u, Clause 24. The
125 Mbits/s receive data stream originates from in a
100Base-TX application.
14
Preliminary Data Sheet
July 2000
The receiver block consists of the following functional
blocks:
■
Clock recovery module
■
NRZI/NRZ and serial/parallel decoder
■
Descrambler
■
Symbol alignment block
■
Symbol decoder
■
Collision detect block
■
Carrier sense block
■
Stream decoder block
Clock Recovery. The clock recovery module accepts
125 Mbits/s scrambled NRZI data stream from either
the on-chip 100Base-TX receiver or from an external
100Base-FX transceiver. The LU3X31T-T64 uses an
onboard digital phase-locked loop (PLL) to extract clock
information of the incoming NRZI data, which is then
used to retime the data stream and set data boundaries.
After power-on or reset, the PLL locks to a free-running
25 MHz clock derived from the external clock source.
When initial lock is achieved, the PLL switches to lock
to the data stream, extracts a 125 MHz clock from the
data, and uses it for bit framing of the recovered data.
NRZI-to-NRZ & Serial-to-Parallel Conversion. The
recovered data is converted from NRZI to NRZ and
then to a 5-bit parallel format for the LU3X31T-T64
descrambler. The 5-bit parallel data is not necessarily
aligned to 4B/5B code-group’s boundary.
Data Descrambling. The scrambled data is presented
in groups of 5 bits (quints) to a deciphering circuit that
reverses the data scrambling process performed by the
transmitter. The descrambler acquires synchronization
with the data stream by recognizing IDLE bursts of 40
or more bits and locking its deciphering linear feedback
shift register (LFSR) to the state of the scrambling
LFSR. Upon achieving synchronization, the incoming
data is XORed by the deciphering LFSR and descrambled, again in groups of 5 bits (quints).
In order to maintain synchronization, the descrambler
continuously monitors the validity of the unscrambled
data that it generates. To ensure this, a link state monitor and a hold timer are used to constantly monitor the
synchronization status. Upon synchronization of the
descrambler, the hold timer starts a 722 µs countdown.
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
100Base-X Link Monitor
Upon detection of sufficient IDLE symbols within the
722 µs period, the hold timer will reset and begin a new
countdown. This monitoring operation will continue
indefinitely given a properly operating network connection with good signal integrity. If the link state monitor
does not recognize sufficient unscrambled IDLE symbols within the 722 µs period, the entire descrambler
will be forced out of the current state of synchronization
and reset in order to reacquire synchronization. Register 18h, bit 3, can be used to extend the timer to
2000 µs.
The 100Base-X link monitor function allows the
receiver to ensure that reliable data is being received.
Without reliable data reception, the link monitor will halt
both transmit and receive operations until such time
that a valid link is detected.
The LU3X31T-T64 performs the link integrity test as
outlined in IEEE 100Base-X (Clause 24) link monitor
state diagram. The link status is multiplexed with the
10 Mbits/s link status to form the reportable link status
bit in serial management register 1. This status also
drives the LNKLED pin.
Symbol Alignment. The symbol alignment circuit in
the LU3X31T-T64 determines code word alignment by
recognizing the /J/K delimiter pair. This circuit operates
on unaligned 5-bit data from the descrambler and is
capable of finding /J/K at any of the five possible starting positions within the descrambled data quints. Once
the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary.
When persistent signal energy is detected on the network, the logic moves into a Link-Ready state, after
approximately 500 µs, and waits for an enable from the
autonegotiation module. When received, the link-up
state is entered, and the transmit and receive logic
blocks become active. Should autonegotiation be disabled, the link integrity logic moves immediately to the
link-up state after entering the link-ready state.
Symbol Decoding. The symbol decoder functions as
a look-up table that translates incoming 5B symbols
into 4B nibbles. The symbol decoder first detects the
/J/K symbol pair preceded by IDLE symbols and
replaces the symbol with MAC preamble. All subsequent 5B symbols are converted to the corresponding
4B nibbles for the duration of the entire packet. This
conversion ceases upon the detection of the /T/R symbol pair denoting the end of stream delimiter (ESD).
The translated data is presented on the RXD[3:0] signal lines with RXD[0] representing the least significant
bit of the translated nibble.
Carrier Sense. Carrier sense (CRS) for 100 Mbits/s
operation is asserted upon the detection of two noncontiguous zeros occurring within any 10-bit boundary
of the receive data stream.
Valid Data Signal. The valid data signal (RXDV) indicates that recovered and decoded nibbles are being
presented on the RXD[3:0] outputs synchronous to
RXCLK. RXDV is asserted when the first nibble of
translated /J/K is ready for transfer over the media
independent interface (MII). It remains active until
either the /T/R delimiter is recognized, link test indicates failure, or no signal is detected. On any of these
conditions, RXDV is deasserted.
Receiver Errors. The RXER signal is used to communicate receiver error conditions. While the receiver is in
a state of holding RXDV asserted, the RXER will be
asserted for each code word that does not map to a
valid code-group.
Lucent Technologies Inc.
The carrier sense function is independent of symbol
alignment. For 100 Mbits/s half-duplex operation, CRS
is asserted during either packet transmission or reception. For 100 Mbits/s full-duplex operation, CRS is
asserted only during packet reception. When the IDLE
symbol pair is detected in the receive data stream,
CRS is deasserted.
Bad SSD Detection. A bad start of stream delimiter
(Bad SSD) is an error condition that occurs in the
100Base-X receiver if carrier is detected (CRS
asserted) and a valid /J/K set of code groups (SSD) is
not received.
If this condition is detected, then the LU3X31T-T64 will
assert RXER and present RXD[3:0] = 1110 to the MII
for the cycles that correspond to received 5B codegroups until at least two IDLE code groups are
detected. Once at least two IDLE code groups are
detected, RXER and CRS become deasserted.
15
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description (continued)
100Base-TX Transceiver
LU3X31T-T64 implements a TP-PMD compliant transceiver for 100Base-TX operation. The differential transmit driver is shared by the 10Base-T and 100Base-TX
subsystems. This arrangement results in one device
that uses the same external magnetics for both the
10Base-T and the 100Base-TX transmission with simple RC component connections. The individually waveshaped 10Base-T and 100Base-TX transmit signals
are multiplexed in the transmit output driver.
Transmit Drivers
The LU3X31T-T64 100Base-TX transmit driver implements MLT-3 translation and wave-shaping functions.
The rise/fall time of the output signal is closely controlled to conform to the target range specified in the
ANSI TP-PMD standard.
cable length. The cable length is estimated based on
the incoming signal strength. The equalizer tunes itself
automatically for any cable length to compensate for
amplitude and phase distortions incurred from the
cable.
10Base-T Module
The 10Base-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,
heartbeat, loopback, jabber, waveshaper, and link
integrity functions, as defined in the standard. Figure 4
provides an overview for the 10Base-T module.
The LU3X31T-T64 10Base-T module is comprised of
the following functional blocks:
■
Manchester encoder and decoder
■
Collision detector
■
Link test function
Twisted-Pair Receiver
■
Transmit driver and receiver
For 100Base-TX operation, the incoming signal is
detected by the on-chip twisted-pair receiver that comprises the differential line receiver, an adaptive equalizer, and baseline wander compensation circuits.
■
Serial and parallel interface
■
Jabber and SQE test functions
■
Polarity detection and correction
The LU3X31T-T64 uses an adaptive equalizer which
changes filter frequency response in accordance with
RXCLK
CRS
TPRX±
RECEIVE
FILTER
FILTER
SMART
SQUELCH
CLOCK
RECOVERY
10BASE-T
RECEIVE
PCS
RXDV
RXD[3:0]
COL
10 Mbit PHY
LOOPBACK
PATH
TXEN
TPTX±
10/100
TRANSMIT
DRIVER
WAVE
SHAPER
10BASE-T
TRANSMIT
PCS
TXER
TXD[3:0]
TXCLK
5-6782(F)r3
Figure 4. 10Base-T Module Data Path
16
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
waveform will not be rejected.
Operation Modes
Only after all of these conditions have been satisfied
will a control signal be generated to indicate to the
remainder of the circuitry that valid data is present.
The LU3X31T-T64 10Base-T module is capable of
operating in either half-duplex mode or full-duplex
mode. In half-duplex mode, the LU3X31T-T64 functions
as an IEEE 802.3 compliant transceiver with fully integrated filtering. The COL pin signals collision, and the
CRS is asserted during transmit and receive. In fullduplex mode, the LU3X31T-T64 can simultaneously
transmit and receive data.
Manchester Encoder/Decoder. Data encoding and
transmission begins when the transmit enable input
(TXEN) goes high and continues as long as the transceiver is in good link state. Transmission ends when the
transmit enable input goes low. The last transition
occurs at the center of the bit cell if the last bit is a 1, or
at the boundary of the bit cell if the last bit is 0.
Decoding is accomplished by a differential input
receiver circuit and a phase-locked loop that separates
the Manchester-encoded data stream into clock signals
and NRZ data. The decoder detects the end of a frame
when no more midbit transitions are detected. Within
one and a half bit times after the last bit, carrier sense
is deasserted.
Transmit Driver and Receiver. LU3X31T-T64 integrates all the required signal conditioning functions in
its 10Base-T block such that external filters are not
required. Only an isolation transformer and impedance
matching resistors are needed for the 10Base-T transmit and receive interface. The internal transmit filtering
ensures that all the harmonics in the transmit signal are
attenuated properly.
Smart Squelch. The smart squelch circuit is responsible for determining when valid data is present on the
differential receive. The LU3X31T-T64 implements an
intelligent receive squelch on the TPRX± differential
inputs to ensure that impulse noise on the receive
inputs will not be mistaken for a valid signal. The
squelch circuitry employs a combination of amplitude
and timing measurements (as specified in the IEEE
802.3 10Base-T standard) to determine the validity of
data on the twisted-pair inputs.
The signal at the start of the packet is checked by the
analog squelch circuit, and any pulses not exceeding
the squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first
squelch level is overcome correctly, the opposite
squelch level must then be exceeded within 150 ns.
Finally, the signal must exceed the original squelch
level within a further 150 ns to ensure that the input
Lucent Technologies Inc.
Valid data is considered to be present until the squelch
level has not been generated for a time longer than
200 ns, indicating end of packet. Once good data has
been detected, the squelch levels are reduced to minimize the effect of noise causing premature end of
packet detection. The receive squelch threshold level
can be lowered for use in longer cable applications.
This is achieved by setting bit 11 or register address
1Ah.
Carrier Sense. Carrier sense (CRS) is asserted due to
receive activity once valid data is detected via the
smart squelch function.
For 10 Mbits/s half-duplex operation, CRS is asserted
during either packet transmission or reception.
For 10 Mbits/s full-duplex operation, the CRS is
asserted only on receive activity. CRS is deasserted
following an end of packet.
Collision Detection. For half-duplex operation, a
10Base-T collision is detected when the receive and
transmit channels are active simultaneously. Collisions
are reported by the COL signal. If the ENDEC is transmitting when a collision is detected, the COL signal
remains set for the duration of the collision.
SQE Test Function. Approximately 1 µs after the
transmission of each packet, a signal quality error
(SQE) signal of approximately 10 bit times is generated
(internally) to indicate successful transmission. SQE is
reported as a pulse on the COL signal. This function
can be disabled by setting bit 12 of register 1Ah. The
SQE test function is disabled in full-duplex mode.
Jabber Function. The jabber function monitors the
LU3X31T-T64's output and disables the transmitter if it
attempts to transmit a longer than legal-sized packet. If
TXEN is high for greater than 24 ms, the 10Base-T
transmitter will be disabled and COL will go high.
Once disabled by the jabber function, the transmitter
stays disabled for the entire time that the TXEN signal
is asserted. This signal has to be deasserted for
approximately 256 ms (the unjab time) before the jabber function re-enables the transmit outputs and deasserts COL signal.
The jabber function can be disabled by setting bit 10 of
register 1Ah.
17
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
Link Test Function. A link pulse is used to check the
integrity of the connection with the remote end. If valid
link pulses are not received, the link detector disables
the 10Base-T twisted-pair transmitter, receiver, and collision detection functions.
The link pulse generator produces pulses as defined in
the IEEE 802.3 10Base-T standard. Each link pulse is
nominally 100 ns in duration and is transmitted every
16 ms, in the absence of transmit data.
Preliminary Data Sheet
July 2000
enables bit 12 in register 0. If autonegotiation is
enabled, the negotiation process will commence immediately.
When autonegotiation is enabled, the LU3X31T-T64
transmits the abilities programmed into the autonegotiation advertisement register at address 04h via FLP
bursts. Any combination of 10 Mbits/s, 100 Mbits/s,
half-duplex, and full-duplex modes may be selected.
Autonegotiation controls the exchange of configuration
information. Upon successful autonegotiation, the abilities reported by the link partner are stored in the autonegotiation link partner ability register at address 05h.
Automatic Link Polarity Detection. The LU3X31TT64's 10Base-T Transceiver Module incorporates an
automatic link polarity detection circuit. The inverted
polarity is determined when seven consecutive link
pulses of inverted polarity or three consecutive receive
packets are received with inverted end of packet
pulses. If the input polarity is reversed, the error condition will be automatically corrected and reported in bit
15 of register 1Ch.
The contents of the autonegotiation link partner ability
register are used to automatically configure to the
highest-performance protocol between the local and
far-end nodes. Software can determine which mode
has been configured by autonegotiation by comparing
the contents of register 04h and 05h and then selecting
the technology whose bit is set in both registers of highest priority relative to the following list:
The automatic link polarity detection function can be
disabled by setting bit 3 of register 1Ah.
2. 100Base-TX half duplex
1. 100Base-TX full duplex (highest priority)
3. 10Base-T full duplex
4. 10Base-T half duplex (lowest priority)
Clock Synthesizer
The LU3X31T-T64 implements a clock synthesizer that
generates all the reference clocks needed from a single
external frequency source. The clock source can be a
quartz crystal or a TTL level signal at 25 MHz ±
50 ppm, as shown in Figure 15.
Autonegotiation
The autonegotiation function provides a mechanism for
exchanging configuration information between two
ends of a link segment and automatically selecting the
highest-performance mode of operation supported by
both devices. Fast link pulse (FLP) bursts provide the
signaling used to communicate autonegotiation abilities
between two devices at each end of a link segment. For
further detail regarding autonegotiation, refer to Clause
28 of the IEEE 802.3u specification. The LU3X31T-T64
supports four different Ethernet protocols, so the inclusion of autonegotiation ensures that the highest-performance protocol will be selected based on the ability of
the link partner.
The autonegotiation function within the LU3X31T-T64
can be controlled either by internal register access or
by the use of configuration pins. At powerup and at
device reset, the configuration pins are sampled. If disabled, autonegotiation will not occur until software
18
The basic mode control register (BMCR) at address
00h provides control of enabling, disabling, and restarting of the autonegotiation function. When autonegotiation is disabled, the speed selection bit (bit 13) controls
switching between 10 Mbits/s or 100 Mbits/s operation,
while the duplex mode bit (bit 8) controls switching
between full-duplex operation and half-duplex operation. The speed selection and duplex mode bits have
no effect on the mode of operation when the autonegotiation enable bit (bit 12) is set.
The basic mode status register (BSMR) at address 01h
indicates the set of available abilities for technology
types (bits 15 to 11), autonegotiation ability (bit 3), and
extended register capability (bit 0). These bits are hardwired to indicate the full functionality of the LU3X31TT64. The BMSR also provides status on:
1. Whether autonegotiation is complete (bit 5).
2. Whether the link partner is advertising that a remote
fault has occurred (bit 4).
3. Whether a valid link has been established (bit 2).
The autonegotiation advertisement register at address
04h indicates the autonegotiation abilities to be advertised by the LU3X31T-T64. All available abilities are
transmitted by default, but any ability can be suppressed by writing to this register or configuring external pins.
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Functional Description (continued)
value of 1 until the software reset operation has completed.
The autonegotiation link partner ability register at
address 05h indicates the abilities of the link partner as
indicated by autonegotiation communication. The contents of this register are considered valid when the
autonegotiation complete bit (bit 5, register address
01h) is set.
Both hardware and software reset operations initialize
all registers to their default values. This process
includes re-evaluation of all hardware-configurable
registers.
Reset Operation
Logic levels on several I/O pins are detected during
hardware reset period to determine the initial functionality of LU3X31T-T64. Some of these pins are used as
outputs after the reset operation.
The LU3X31T-T64 can be reset either by hardware or
software. A hardware reset is accomplished by applying
a negative pulse, with a duration of at least 1 ms, to the
RSTZ pin of the LU3X31T-T64 during normal operation.
A software reset is activated by setting the RESET bit in
the basic mode control register (bit 15, register 00h).
This bit is self-clearing and, when set, will return a
Care must be taken to ensure that the configuration
setup will not interfere with normal operation. Dedicated configuration pins can be tied to VCC or ground
directly. Configuration pins multiplexed with logic-level
output functions should be either weakly pulled up or
weakly pulled down through resisters. Configuration
pins multiplexed with LED outputs should be set up
with one of the following circuits shown in Figure 5.
I/O PIN
VCC
10 kΩ
10 kΩ
I/O PIN
LOGIC 1 CONFIGURATION
LOGIC 0 CONFIGURATION
Note: The 10 kΩ resistor is only for nondefault configuration.
5-6783(F).r2
Figure 5. Hardware Reset Configurations
PHY Address
During hardware reset, the logic levels of pins 10, 12, 16, 34, and 39 are latched into bits 4 through 0 of management register at address 19h, respectively. This 5-bit address is used as the PHY address for serial management
interface communication. Note that initializing the PHY address to zero automatically isolates the MII interface.
Autonegotiation and Speed Configuration
The five pins listed in Table 11 configure the speed capability of LU3X31T-T64. The logic state of these pins, at
powerup or reset, are latched into the advertisement register (register address 04h) for autonegotiation purpose.
These pins are also used for evaluating the default value in the base mode control register (register 00h) according
to Table 11.
Lucent Technologies Inc.
19
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Functional Description (continued)
Table 11. Autonegotiation
Configuration Pins at RESET
Registers Initial Value
AUTOEN
Pin 4
100FDEN
Pin 2
(Reg 4.8)
100HDEN
Pin 11
(Reg 4.7)
10FDEN
Pin 17
(Reg 4.6)
10HDEN
Pin 43
(Reg 4.5)
Autonegotiate
Reg 0.12
Speed
Reg 0.13
Duplex
Reg 0.8
0
0
0
0
0
1
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
X
X
X
X
1
X
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
0
100Base-X PCS Configuration
The logic state of BPSCR, BP4B5B, and BPALIGN pins latched into bits 15, 14, and 12 of the Config 100 register at
address 18h during powerup or reset. These registers configure the functionality of 100Base-X PCS (physical coding sublayer) MII registers.
Table 12. MII Management Registers
Address
0h
1h
2h3h
4h
5h
6h
7hFh
15h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
20
Register Name
Control Register
Status Register
PHY Identifier Register
Autonegotiation Advertisement Register
Autonegotiation Link Partner Ability Register
Autonegotiation Expansion Register
IEEE Reserved
Receive Error Counter
PHY Control/Status Register
Config 100 Register
PHY Address Register
Config 10 Register
Status 100 Register
Status 10 Register
Interrupt Mask Register
Interrupt Status Register
Basic/Extended
B
B
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers
Legend:
RO
Read only.
R/W
Read and write capable.
SC
Self-clearing.
LL
Latching low, unlatch on read.
LH
Latching high, unlatch on read.
COR Clear on read.
Table 13. Control Register (Register 0h)
Bit(s)
Name
Description
R/W
Default
15
Reset
R/W
SC
0h
14
Loopback
R/W
0h
13
Speed Selection
R/W
Pin
12
Autonegotiation Enable
1PHY Reset.
0Normal operation.
Setting this bit initiates the software reset
function that resets the entire LU3X31T-T64
device, except for the phase-locked loop circuit. It will relatch in all hardware configuration pin values and set all registers to their
default values. The software reset process
takes 25 µs to complete. This bit, which is
self-clearing, returns a value of 1 until the
reset process is complete.
1Enable loopback mode.
0Disable loopback mode.
This bit controls the PHY loopback operation
that isolates the network transmitter outputs
(TPTX±) and routes the MII transmit data to
the MII receive data path. This function
should only be used when autonegotiation is
disabled (bit 12 = 0). The specific PHY
(10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13 of this
register.
1100 Mbits/s.
010 Mbits/s.
Link speed is selected by this bit or by autonegotiation if bit 12 of this register is set (in
which case, the value of this bit is ignored).
At powerup or reset, this bit will be set unless
AUTONEN, 100FDEN, and 100HDEN pin
are all in logic low state.
1Enable autonegotiation process.
0Disable autonegotiation process.
This bit determines whether the link speed
should be set up by the autonegotiation process. It is set at powerup or reset if the
AUTONEN pin (pin 4) detects a logic 1 input
level.
R/W
Pin
Lucent Technologies Inc.
21
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 13. Control Register (Register 0h) (continued)
Bit(s)
Name
Description
R/W
Default
11
Powerdown
R/W
0h
10
Isolate
R/W
Pin
9
Restart Autonegotiation
R/W, SC
0h
8
Duplex Mode
R/W
Pin
7
Collision Test
R/W
0h
6:0
Reserved
1Powerdown.
0Normal operation.
Setting this bit puts the LU3X31T-T64 into
powerdown mode. During the powerdown
mode, TPTX± and all LED outputs are 3stated, and the MII interface is isolated.
RSTZ is used to clear this bit.
1Isolate PHY from MII.
0Normal operation.
Setting this control bit isolates the
LU3X31T-T64 from the MII, with the exception of the serial management interface.
When this bit is asserted, the LU3X31T-T64
does not respond to TXD[3:0], TXEN, and
TXER inputs, and it presents a high impedance on its TXCLK, RXCLK, RXDV, RXER,
RXD[3:0], COL, and CRS outputs. This bit is
initialized to 0 unless the configuration pins
for the PHY address are set to 00000h during
powerup or reset.
1Restart autonegotiation process.
0Normal operation.
Setting this bit while autonegotiation is
enabled forces a new autonegotiation process to start. This bit is self-clearing and
returns to 0 after the autonegotiation process
is completed.
1Full-duplex mode.
0Half-duplex mode.
If autonegotiation is disabled, this bit determines the duplex mode for the link.
At powerup or reset, this bit is set to 1 if the
AUTONEN pin (pin 4) detects a logic 0 and
either 100FDEN (pin 2) or 10FDEN pin (pin
17) detects a logic 1.
1Enable COL signal test.
0Disable COL signal test.
When set, this bit will cause the COL signal
to be asserted in response to the assertion of
TXEN.
Not used.
RO
0h
22
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 14. Status Register (Register 1h)
Bit(s)
15
14
13
12
11
10
9:7
6
Name
Description
1Capable of 100Base-T4.
0Not capable of 100Base-T4.
This bit is hardwired to 0, indicating that the
LU3X31T-T64 does not support 100Base-T4.
100Base-X Full-duplex
1Capable of 100Base-X full-duplex mode.
0Not capable of 100Base-X full-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 100Base-X fullduplex mode.
100Base-X Half-duplex
1Capable of 100Base-X half-duplex mode.
0Not capable of 100Base-X half-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 100Base-X halfduplex mode.
10 Mbits/s Full-duplex
1Capable of 10 Mbits/s full-duplex mode.
0Not capable of 10 Mbits/s full-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 10Base-T full-duplex
mode.
10 Mbits/s Half-duplex
1Capable of 10 Mbits/s half-duplex mode.
0Not capable of 10 Mbits/s half-duplex
mode.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 supports 10Base-T half-duplex
mode.
100Base-T2
1Capable of 100Base-T2.
0Not capable of 100Base-T2.
This bit is hardwired to 0, indicating that the
LU3X31T-T64 does not support 100Base-T2.
Reserved
Ignore when read.
MF Preamble Suppression 1Accepts management frames with preamble suppressed.
0Will not accept management frames with
preamble suppressed.
This bit is hardwired to 1, indicating that the
LU3X31T-T64 accepts management frame
without preamble. A minimum of 32 preamble bits are required following power-on or
hardware reset. One IDLE bit is required
between any two management transactions
as per IEEE 802.3u specification.
100Base-T4
Lucent Technologies Inc.
R/W
Default
RO
0h
RO
1h
RO
1h
RO
1h
RO
1h
RO
0h
RO
RO
0h
1h
23
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 14. Status Register (Register 1h) (continued)
Bit(s)
Name
Description
R/W
Default
5
Autonegotiation Complete
RO
0h
4
Remote Fault
RO, LH
0h
3
Autonegotiation Ability
RO
1h
2
Link Status
RO,
LL
0h
1
Jabber Detect
RO,
LH
0h
0
Extended Capability
1Autonegotiation process completed.
0Autonegotiation process not completed.
If autonegotiation is enabled, this bit indicates
whether the autonegotiation process has
been completed.
1Remote fault detected.
0Remote fault not detected.
This bit is latched to 1 if the RF bit in the autonegotiation link partner ability register (bit 13,
register address 05h) is set or the receive
channel meets the far-end fault indication
function criteria. It is unlatched when this register is read.
1Capable of autonegotiation.
0Not capable of autonegotiation.
This bit defaults to 1, indicating that the
LU3X31T-T64 is capable of autonegotiation.
1Link is up.
0Link is down.
This bit reflects the current state of the linktest-fail state machine. Loss of a valid link
causes a 0 latched into this bit. It remains 0
until this register is read by the serial management interface.
1Jabber condition detected.
0Jabber condition not detected.
During 10Base-T operation, this bit indicates
the occurrence of a jabber condition. It is
implemented with a latching function so that it
becomes set until it is cleared by a read.
1Extended register set.
0No extended register set.
This bit defaults to 1, indicating that the
LU3X31T-T64 implements extended registers.
RO
1h
24
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 15. PHY Identifier (Register 2h)
Bit(s)
Name
15:0
PHY-ID[31:16]
Description
IEEE address.
R/W
Default
RO
0043h
R/W
Default
RO
RO
RO
011101b
000001b
0001b
Table 16. PHY Identifier (Register 3h)
Bit(s)
Name
15:10
9:4
3:0
PHY-ID[15:10]
PHY-ID[9:4]
PHY-ID[3:0]
Description
IEEE address.
Model No.
Rev. No.
Table 17. Autonegotiation Advertisement (Register 4h)
Bit(s)
Name
Description
R/W
Default
15
Next Page
RO
0h
14
13
Reserved
Remote Fault
RO
R/W
0h
0h
12:10
9
IEEE Reserved
Technology Ability Field for
100Base-T4
RO
RO
0h
0h
8:5
Technology Ability Field
R/W
Pin
4:0
Selector Field
1Capable of next-page function.
0Not capable of next-page function.
This bit defaults to 0, indicating that
LU3X31T-T64 is not next-page capable.
Reserved.
1Remote fault has been detected.
0No remote fault has been detected.
This bit is written by serial management
interface for the purpose of communicating the remote fault condition to the autonegotiation link partner.
These 3 bits default to 0.
This bit defaults to 0, indicating that the
LU3X31T-T64 does not support
100Base-T4.
This 4-bit field contains the advertised
ability of this PHY. At powerup or reset,
the logic level of 100FDEN, 100HDEN,
10FDEN, and 10HDEN pins are latched
into bits 8 through 5, respectively.
These 5 bits are hardwired to 00001h,
indicating that the LU3X31T-T64 supports
IEEE 802.3 CSMA/CD.
RO
01h
Table 18. Autonegotiation Link Partner Ability (Register 5h)
Bit(s)
Name
Description
R/W
Default
15
Next Page
RO
0h
14
Acknowledge
RO
0h
13
Remote Fault
RO
0h
12:5
4:0
Technology Ability Field
Selector Field
1Capable of next-page function.
0Not capable of next-page function.
1Link partner acknowledges reception
of the ability data word.
0Not acknowledged.
1Remote fault has been detected.
0No remote fault has been detected.
Supported technologies.
Encoding definitions.
RO
RO
0h
0h
Lucent Technologies Inc.
25
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 19. Autonegotiation Expansion Register (Register 6h)
Bit(s)
Name
15:5
4
Reserved
Parallel Detection Fault
3
2
1
0
Description
Reserved.
1Fault has been detected.
0No fault detected.
This bit is set if the parallel detection fault
state of the autonegotiation arbitration
state machine is visited during the autonegotiation process. It will remain set until
this register is read.
Link Partner Next-page Able 1Link partner is next-page capable.
0Link partner is not next-page capable.
This bit indicates whether the link partner
is next-page capable. It is meaningful only
when the autonegotiation complete bit (bit
5, register 1) is set.
Next-page Able
1Local device is next-page capable.
0Local device is not next-page capable.
This bit defaults to 0, indicating that the
LU3X31T-T64 is not next-page able.
Page Received
1A new page has been received.
0No new page has been received.
This bit is latched to 1 when a new link
code word page has been received. This
bit is automatically cleared when the
autonegotiation link partner ability register (register 05h) is read by management
interface.
Link Partner Autonegotiatable 1Link partner is autonegotiable.
0Link partner is not autonegotiable.
R/W
Default
RO
RO,
LH
0h
0h
RO
0h
RO
0h
RO,
LH
0h
RO
0h
Table 20. Receive Error Counter (Register 15h)
Bit(s)
Name
Description
R/W
Default
15:0
RX Error Count
Number of receive errors since last reset.
The counter is incremented once for each
packet that has receive error condition
detected. This counter may roll over
depending on value of the CSMODE bit
(bit 13 of register 17h).
RO,
COR
0h
26
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 21. PHY Control/Status Register (Register 17h)
Bit(s)
Name
15:14
13
Reserved
CSMODE
12
11
10
9
8
7
6
5
4
3
2
1
Description
Reserved.
1Counter sticks at FFFFh.
0Counters roll over.
This bit controls the operation of isolate
counter, false carrier counter, and receive
error counters.
TPTXTR
13-state transmit pairs.
0Normal operation.
When this bit is set, the twisted-pair transmitter outputs are 3-stated. Note that the
twisted-pair transmit driver can be 3stated by either this bit or the TPTXTR pin
(pin 5).
ThunderLAN interrupt Enable 1MDIO ThunderLAN interrupt enabled.
0MDIO ThunderLAN interrupt disabled.
This bit enables/disables the TI ThunderLAN interrupt mechanism.
MF Preamble Suppression 1MDIO preamble suppression enabled.
Enable
0MDIO preamble suppression disabled.
LU3X31T-T64 can accept management
frames without preamble as described in
bit 6 of register 1h. This bit allows the user
to enable or disable the preamble suppression function.
Speed Status
1Part is in 100 Mbits/s mode.
0Part is in 10 Mbits/s mode.
This value is not defined during the autonegotiation period.
Duplex Status
1Part is in full-duplex mode.
0Part is in half-duplex mode.
This value is not defined during the autonegotiation period.
Activity LED On
1LEDTX/ACTLED active on both transmit and receive.
0LEDTX/ACTLED active on transmit
only.
LEDRX Off
13-state LEDRX output.
0Normal operation.
LEDTX/ACTLED Off
13-state LEDTX/ACTLED output.
0Normal operation.
LNKLED Off
13-state LNKLED output.
0Normal operation.
LEDCOL Off
13-state LEDCOL output.
0Normal operation.
LEDFD Off
13-state LEDFD output.
0Normal operation.
LEDSP Off
13-state LEDSP output.
0Normal operation.
Lucent Technologies Inc.
R/W
Default
RO
R/W
0h
0h
R/W
0h
R/W
0h
R/W
0h
RO
0h
RO
0h
R/W
0h
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
27
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 21. PHY Control/Status Register (Register 17h) (continued)
Bit(s)
0
Name
Description
LED Pulse Stretching Disable 1LED pulse stretching disabled.
0LED pulse stretching enabled.
When pulse stretching is enabled, all LED
outputs are stretched to 48 ms—72 ms.
R/W
Default
R/W
0
Table 22. Config 100 Register (Register 18h)
Bit(s)
Name
15
BPSCR
14
BP4B5B
13
12
Reserved
BPALIGN
11:10
9
Reserved
Force Good Link 100
8:6
5
Reserved
Accept Halt
4
Load Seed
3
Burst Mode
2:0
Reserved
28
Description
R/W
R/W
1Disable scrambler/descrambler.
0Enable scrambler/descrambler.
This bit is initialized to the logic level of
BPSCR pin (pin 41) at powerup or reset.
R/W
1Disable 4B/5B encoder/decoder.
0Enable 4B/5B encoder/decoder.
This bit is initialized to the logic level of
BP4B5B pin (pin 42) at powerup or reset.
Reserved.
RO
R/W
1Pass unaligned data to MII.
0Pass aligned data to MII.
This bit is initialized to the logic level of
BPALIGN pin (pin 44) at powerup or reset.
Reserved.
RO
1Force good link in 100 Mbits/s mode.
R/W
0Normal operation.
Reserved.
RO
1Passes HALT symbols to the MII.
R/W
0Normal operation.
R/W, SC
1Loads the scrambler seed.
0Normal operation.
Setting this bit loads the user seed stored
in register 19h into the 100Base-X scrambler. The content of this bit returns to 0
after the loading process is completed and
no transmit is active.
1Burst mode.
R/W
0Normal operation.
Setting this bit expands the 722 µs scrambler time-out period to 2,000 µs.
Reserved.
RO
Default
Pin
Pin
0h
Pin
0h
0h
0h
0h
0h
0h
0h
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 23. PHY Address Register (Register 19h)
Bit(s)
Name
Description
R/W
Default
15:11
10:5
Reserved
User Seed
RO
R/W
0h
21h
4:0
PHY Address
Reserved.
User-modifiable seed data. When the
load seed bit (bit 4 of register 18h) is set,
bits 15 through 5 of this register are
loaded into the 100Base-X scrambler.
These 5 bits store the part address used
by the serial management interface. PHY
address of 0 has the special function of
isolating the part from the MII. These bits
are initialized to the logic levels of
PHY[4:0] pins at powerup or reset.
R/W
Pin
Table 24. Config 10 Register (Register 1Ah)
Bit(s)
Name
Description
R/W
Default
15
14
0h
0h
RO
R/W
0h
0h
11
Low Squelch Select
R/W
0h
10
Jabber Disable
R/W
0h
9:7
6
Reserved
Powerdown Mode
RO
R/W
0h
0h
5:4
3
Reserved
Autopolarity Disable
RO
R/W
0h
0h
2:0
Reserved
Reserved.
1Force 10 Mbits/s good link.
0Normal operation.
Reserved.
1Signal quality error test disabled.
0Normal operation.
1Low squelch level selected.
0Normal squelch level selected.
1Jabber function disabled.
0Normal operation.
Reserved.
1—Powers down the LU3X31T-T64 completely. The part comes out of this
mode after a reset is asserted and
deasserted.
0—Normal operation.
Reserved.
1—Disable autopolarity function.
0—Enable autopolarity function.
Reserved.
RO
R/W
13
12
Reserved
Force 10 Mbits/s Good
Link
Reserved
SQE Disable
RO
0h
Lucent Technologies Inc.
29
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
MII Registers (continued)
Table 25. Status 100 Register (Register 1Bh)
Bit(s)
Name
15:14
13
Reserved
PLL Lock Status
12:0
Reserved
Description
Reserved.
1100 Mbits/s PLL locked.
0100 Mbits/s PLL not locked.
Reserved.
R/W
Default
RO
RO
0h
0h
RO
0h
R/W
Default
RO
0h
RO
0h
R/W
Default
RO
R/W
0h
0h
RO
R/W
0h
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
RO
0h
Table 26. Status 10 Register (Register 1Ch)
Bit(s)
Name
15
Polarity
14:0
Reserved
Description
1Polarity of cable is swapped.
0Polarity of cable is correct.
Reserved.
Table 27. Interrupt Mask Register (Register 1Dh)
Bit(s)
15
14
13
12
11
10
9
8
7
6:0
30
Name
Description
Reserved
Reserved.
Receiver Error Counter Full 0Enable interrupt.
1Disable interrupt.
Reserved
Reserved.
Remote Fault
0Enable interrupt.
1Disable interrupt.
Autoneg. Complete
0Enable interrupt.
1Disable interrupt.
Link Up
0Enable interrupt.
1Disable interrupt.
Link Down
0Enable interrupt.
1Disable interrupt.
Data Recovery 100 Lock 0Enable interrupt.
1Disable interrupt.
Up
Data Recovery Lock Down 0Enable interrupt.
1Disable interrupt.
Reserved
Reserved.
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
MII Registers (continued)
Table 28. Interrupt Status Register (Register 1Eh)
Bit(s)
Name
15
14
Reserved
Receiver Error Counter
Full
13
12
11
10
9
8
7
6:0
Description
Reserved.
1Receive error counter has rolled over.
0Receive error counter has not rolled
over.
Reserved
Reserved.
Remote Fault
1Remote fault observed by PHY.
0Remote fault not observed by PHY.
Autonegotiation Com- 1Autonegotiation has completed.
0Autonegotiation has not completed.
plete
Link Up
1Link is up.
0No change on link status.
Link Down
1Link has gone down.
0No change on link status.
Data Recovery 100 Lock 1Data recovery has locked.
0Data recovery is not locked.
Up
Data Recovery 100 Lock 1Data recovery is not locked.
0Data recovery has locked.
Down
Reserved
Reserved.
R/W
Default
RO
RO, LH
0h
0h
RO
RO, LH
0h
0h
RO, LH
0h
RO, LH
0h
RO, LH
0h
RO, LH
0h
RO, LH
0h
RO
0h
dc and ac Specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Table 29. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
TA
Tstg
—
—
—
0
–65
—
–0.5
–0.5
70
150
3.46
5.25
3.46
°C
°C
V
V
V
Ambient Operating Temperature
Storage Temperature
Maximum Supply Voltage
Voltage on MII Input Pins with Respect to Ground
Voltage on Any Other Pin with Respect to Ground
Table 30. Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Operating Supply Voltage
—
3.135
3.3
3.46
V
Power Dissipation*:
100 Mbits/s TX
10 Mbits/s
Autonegotiating
PD
PD
PD
—
—
—
—
—
—
140
150
30
mA
mA
mA
* Power dissipations are specified at 3.3 V and 25 °C. This is the power dissipated by the LU3X31T-T64.
Lucent Technologies Inc.
31
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
dc and ac Specifications (continued)
Table 31. dc Characteristics
Parameter
Symbol
Recommended Power
VDD
VSS
Supply
Supply Current
IDD
100Base-TX
Supply Current
IDD
10Base-TX
Supply Current
IDD
Autonegotiation Mode
Supply Current
IDD
100Base-FX
TTL Input High Voltage
VIH
TTL Input Low Voltage
VIL
TTL Output High-voltage
VOH
MII Pins
TTL Output Low-voltage
VOL
MII Pins
TTL Output High-voltage
VOH2
LED Pins
TTL Output Low-voltage
VOL2
LED Pins
PECL Input High Voltage
VIHPECL
PECL Input Low Voltage
VILPECL
PECL Output High Voltage VOHPECL
PECL Output Low Voltage VOLPECL
Oscillator Input (25 MHz)
XIN
Crystal Freq. Stability
XIN/XOUT
(25 MHz)
Input Capacitance
MII CIN
Conditions
Min
Max
Unit
—
3.0
0.0
—
3.6
0.0
148
V
V
mA
—
156
mA
—
70
mA
—
120
mA
2.0
—
2.4
—
0.8
—
V
V
V
—
0.4
V
3.0
—
V
—
0.3
V
VDD = 3.3 V, VSS = 0.0 V
Full-Duplex Traffic
VDD = 3.3 V, VSS = 0.0 V
Full-Duplex Traffic
VDD = 3.3 V, VSS = 0.0 V
No Link
VDD = 3.3 V, VSS = 0.0 V
Full-Duplex Traffic
VDD = 3.3 V, VSS = 0.0 V
VDD = 3.3 V, VSS = 0.0 V
VDD = 3.3 V, VSS = 0.0 V
IOH = 4 mA
VDD = 3.3 V, VSS = 0.0 V
IOH = 4 mA
VDD = 3.3 V, VSS = 0.0 V
IOH = 10 mA
VDD = 3.3 V, VSS = 0.0 V
IOH = 10 mA
—
—
—
—
—
—
VDD – 1.16 VDD – 0.88
VDD – 1.81 VDD – 1.47
VDD – 1.02
—
—
VDD – 1.62
–50
50
–50
50
—
—
8
V
V
V
V
ppm
ppm
pF
Clock Timing
Table 32. System Clock (Xin)
Symbol
t1
t2
t3
Description
Clock High Pulse Width
Clock Low Pulse Width
Clock Period
t1
Min
Max
Unit
17
17
39.998
23
23
40.002
ns
ns
ns
t2
t3
XIN
5-6784(F)
Figure 6. System Timing
32
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
Table 33. Transmit Clock (Input and Output)
Symbol
t1
t2
t3
t4
Description
TXCLK High Pulse Width (100 Mbits/s)
TXCLK High Pulse Width (10 Mbits/s)
XIN Rise to TXCLK Rise (100 Mbits/s)
XIN Rise to TXCLK Rise (10 Mbits/s)
TXCLK Low Pulse Width (100 Mbits/s)
TXCLK Low Pulse Width (10 Mbits/s)
TXCLK Period (100 Mbits/s)*
TXCLK Period (10 Mbits/s)*
Min
Max
Unit
14
140
14
28
14
140
40
400
26
260
—
—
26
260
40
400
ns
ns
ns
ns
ns
ns
ns
ns
* Specified at ±100 ppm.
t2
t1
t4
t3
TXCLK
XIN
5-6785(F)
Figure 7. Transmit Timing (Input and Output)
Lucent Technologies Inc.
33
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Clock Timing (continued)
Table 34. Management Clock
Symbol
t1
t2
t3
t4
t5
t6
Description
MDC High Pulse Width
MDC Low Pulse Width
MDC Period
MDIO(I) Setup to MDC Rising Edge
MDIO(O) Hold Time from MDC Rising Edge
MDIO(O) Valid from MDC Rising Edge
Min
Max
Unit
200
200
400
10
10
0
—
—
—
—
—
300
ns
ns
ns
ns
ns
ns
t2
t1
t3
MDC
t5
t4
MDIO(I)
t6
MDIO(O)
5-6786(F)
Figure 8. Management Timing
34
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
Table 35. MII Receive Timing
Symbol
Description
Min
Max
Unit
t1
t2
RXER, RXDV, RXD[3:0] Setup to RXCLK Rise
RXER, RXDV, RXD[3:0] Hold After RXCLK
Rise
RXCLK High Pulse Width (100 Mbits/s)
RXCLK High Pulse Width (10 Mbits/s MII)
RXCLK High Pulse Width (10 Mbits/s serial)
RXCLK Low Pulse Width (100 Mbits/s)
RXCLK Low Pulse Width (10 Mbits/s MII)
RXCLK Low Pulse Width (10 Mbits/s serial)
RXCLK Period (100 Mbits/s)
RXCLK Period (10 Mbits/s MII)
RXCLK Period (10 Mbits/s serial)
10
10
—
—
ns
ns
14
140
35
14
140
35
40
400
100
26
260
65
26
260
65
40
400
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
t3
t4
t5
t5
t1
t3
t4
t2
RXCLK
RXER, RXDV,
RXD[3:0]
5-6787(F).c
Figure 9. MII Receive Timing
Lucent Technologies Inc.
35
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Clock Timing (continued)
Table 36. MII Transmit Timing
Symbol
Description
Min
Max
Unit
t1
t2
TXER, TXEN, TXD[3:0] Setup to TXCLK Rise
TXER, TXEN, TXD[3:0] Hold After TXCLK Rise
10
0
—
25
ns
ns
t1
t2
TXCLK
TXER, TXEN,
TXD[3:0]
5-6788(F)
Figure 10. MII Transmit Timing
36
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
Table 37. Transmit Timing
Symbol
t1
t2
t3
t4
Description
TXEN Sampled to CRS High (100 Mbits/s)
TXEN Sampled to CRS High (10 Mbits/s)
TXEN Sampled to CRS Low (100 Mbits/s)
TXEN Sampled to CRS Low (10 Mbits/s)
Transmit Latency (100 Mbits/s)
Transmit Latency (10 Mbits/s)
Sampled TXEN Inactive to End of Frame
(100 Mbits/s)
Sampled TXEN Inactive to End of Frame
(10 Mbits/s)
Min
Max
Unit
0
—
0
—
6
4
—
4
1.5
16
16
14
—
17
bits
bits
bits
bits
bits
bits
bits
—
5
bits
TXCLK
TXEN
t1
t2
CRS
t3
TPTX
t4
PREAMBLE
5-6789(F)
Figure 11. Transmit Timing
Lucent Technologies Inc.
37
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Clock Timing (continued)
Table 38. Receive Timing
Symbol
Description
Min
Max
Unit
t1
Receive Frame to Sampled Edge of RXDV
(100 Mbits/s)
Receive Frame to Sampled Edge of RXDV
(10 Mbits/s)
Receive Frame to CRS High (100 Mbits/s)
Receive Frame to CRS High (10 Mbits/s)
End of Receive Frame to Sampled Edge of
RXDV (100 Mbits/s)
End Receive Frame to Sampled Edge of RXDV
(10 Mbits/s)
End of Receive Frame to CRS Low (100 Mbits/s)
End of Receive Frame to CRS Low (10 Mbits/s)
—
15
bits
—
22
bits
—
—
—
13
5
12
bits
bits
bits
—
4
bits
13
—
24
4.5
bits
bits
t2
t3
t4
RXCLK
t1
RXDV
t2
CRS
t3
t4
TPRX
DATA
5-6790(F)
Figure 12. Receive Timing
38
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
Table 39. Reset and Configuration Timing
Symbol
t1
t2
t3
t4
Description
Power On to Reset High
Reset Pulse Width
Configuration Pin Setup
Configuration Pin Hold
Min
Max
Unit
1.0
1.0
1.0
1.0
—
—
—
—
ms
ms
ms
ms
VCC
t2
t1
RSTZ
t3
t4
CONFIG
5-6791(F)
Figure 13. Reset and Configuration Timing
Lucent Technologies Inc.
39
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Clock Timing (continued)
Table 40. PMD Characteristics
Symbol
t1
t2
t3
Description
TPTX+/TPTX– Rise Time
TPTX+/TPTX– Fall Time
TP Skew
Min
Max
Unit
3.0
3.0
0
5.0
5.0
500
ns
ns
ps
t1
t2
TPTX+
t3
TPTX–
5-6792(F).a
Figure 14. PMD Timing
40
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Clock Timing (continued)
20 pF
25 MHZ ± 50 PPM
XIN
25 MHZ
OSC ±
50 PPM
XIN
XOUT
XOUT
20 pF
GND
25 MHZ CRYSTAL REFERENCE
25 MHZ OSCILLATOR REFERENCE
5-6793(F).Cr.1
Figure 15. Connection Diagrams (Frequency References)
Lucent Technologies Inc.
41
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Clock Timing (continued)
LU3X31T-T64
VCC
DIGITAL VDD
FB
TRANSMIT VDD
0.1 µF
22 µF
FB
RECEIVE VDD
GND
CSVCC
VCC
1Ω
RJ45
4.7 µF
TPTX+
MAGNETIC
TX+
GND
TPTX–
TX–
TRANSMIT
RX+
TPRX+
UNUSED
TPRX–
301 Ω
UNUSED
REF100
RX–
RECEIVE
4.64 kΩ
UNUSED
REF10
RECEIVE GND
TRANSMIT GND
0.1 µF
DIGITAL GND
50 Ω
54 Ω
50 Ω
54 Ω
1000 pF
0.1 µF
75 Ω
0.1 µF
0.1 µF
GND
75 Ω
75 Ω
75 Ω
UNUSED
470 pF 3 kV
CHASSIS GND
GND
5-6794(F).c
Figure 16. Connection Diagrams (10/100BTX Operation)
42
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Outline Diagram
64-Pin TQFP
Dimensions are in millimeters.
12.00 ± 0.20
1.00 REF
10.00 ± 0.20
PIN #1
IDENTIFIER ZONE
64
49
0.25
GAGE PLANE
SEATING PLANE
48
1
0.45/0.75
DETAIL A
10.00
± 0.20
12.00
± 0.20
16
33
0.106/0.200
17
32
0.19/0.27
DETAIL A
DETAIL B
1.40 ± 0.05
0.08
1.60 MAX
M
DETAIL B
SEATING PLANE
0.08
0.50 TYP
0.05/0.15
5-7101(F)
Lucent Technologies Inc.
43
LU3X31T-T64 Single-Port 3 V
10/100 Ethernet Transceiver TX
Preliminary Data Sheet
July 2000
Ordering Information
Device Code
Package
Temperature
Comcode
LU3X31T-T64
64-Pin TQFP
0 °C to 70 °C
108497249
For additional information, contact your Microelectronics Group Account Manager or the following:
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INTERNET:
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E-MAIL:
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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
July 2000
DS00-358LAN (Replaces DS99-346LAN)