AGERE OR3LP26B

Data Sheet
March 2000
ORCA® OR3LP26B Field-Programmable System Chip (FPSC)
Embedded Master/Target PCI Interface
Introduction
Lucent Technologies Microelectronics Group has
developed a solution for designers who need the
many advantages of an FPGA-based design implementation, coupled with the high bandwidth of an
industry-standard PCI interface. The ORCA
OR3LP26B (a member of the Series 3+ FPSC family)
provides a full-featured 33/50/66 MHz, 32-/64-bit PCI
interface, fully designed and tested, in hardware, plus
FPGA logic for user-programmable functions.
PCI Bus Core Highlights
■
Implemented in an ORCA Series 3 OR3L125B
base array, displacing the bottom ten rows of 28
columns.
■
Core is a well-tested ASIC model.
■
Fully compliant to Revision 2.2 of PCI Local Bus
specification.
■
Operates at PCI bus speeds up to 66 MHz on a
32-/64-bit wide bus.
■
Comprises two independent controllers for Master
and Target.
■
Meets/exceeds all requirements for PICMG* Hot
Swap friendly silicon, full Hot Swap model, per the
CompactPCI* Hot Swap specification, PICMG 2.1
R1.0.
■
PCI SIG Hot Plug (R1.0) compliant.
■
Four internal FIFOs individually buffer both directions of both the Master and Target interfaces:
— Both Master FIFOs are 64 bits wide by 32 bits
deep.
— Both Target FIFOs are 64 bits wide by 16 bits
deep.
■
Capable of no-wait-state, full-burst PCI transfers in
either direction, on either the Master or Target
interface. The dual 64-bit data paths extend into
the FPGA logic, permitting full-bandwidth, simultaneous bidirectional data transfers of up to
528 Mbytes/s to be sustained indefinitely.
■
Can be configured to provide either two 64-bit
buses (one in each direction) to be multiplexed
between Master and Target, or four independent
32-bit buses.
■
Provides many hardware options in the PCI core
that are set during FPGA logic configuration.
■
Operates within the requirements of the PCI 5 V
and 3.3 V signaling environments and 3.3 V commercial environmental conditions, allowing the
same device to be used in 5 V or 3.3 V PCI systems.
■
FPGA is reconfigurable via the PCI interface's configuration space (as well as conventionally), allowing the FPGA to be field-updated to meet latebreaking requirements of emerging protocols.
* PICMG and CompactPCI are registered trademarks of the PCI
Industrial Computer Manufacturers Group.
Table 1. ORCA OR3LP26B PCI FPSC Solution—Available FPGA Logic
Device
Usable Gates†
OR3LP26B
60K—120K
Number of Number of Max User Max User
LUTs
Registers
RAM
I/Os
4032
5304
64K
259
Array
Size
Number of
PFUs
18 x 28
504
† The embedded core and interface comprise approximately 85K standard-cell ASIC gates in addition to these usable gates. The usable
gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs. The logic-only
gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per PFU), and 12
gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch, output logic,
CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4
RAM (or 512 gates) per PFU.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Table of Contents
Contents
Page
Introduction ..........................................................................1
PCI Bus Core Highlights ......................................................1
Figures .................................................................................2
Tables ..................................................................................3
FPSC Highlights ...................................................................5
Software Support .................................................................6
Description ...........................................................................7
What Is an FPSC? ............................................................7
FPSC Overview .................................................................7
FPSC Gate Counting ........................................................7
FPGA/Embedded Core Interface ......................................7
ORCA Foundry Development System ..............................7
FPSC Design Kit ...............................................................8
FPGA Logic Overview .......................................................8
PLC Logic ..........................................................................8
PIC Logic ...........................................................................9
System Features ...............................................................9
Routing ..............................................................................9
Configuration .....................................................................9
Boundary Scan ..................................................................9
More Series 3 Information .................................................9
OR3LP26B Overview .........................................................10
Device Layout .................................................................10
PCI Local Bus .................................................................10
OR3LP26B PCI Bus Core Overview ...............................12
PCI Bus Interface ............................................................12
Embedded Core Options/FPGA Configuration ...............13
PCI Bus Core Detailed Description ....................................14
PCI Bus Commands ........................................................14
PCI Protocol Fundamentals ............................................16
FIFO Memories and Control ............................................17
PCI Bus Pin Information ..................................................18
PCI Bus Core Detailed Description Dual Port ....................21
Embedded Core/FPGA Interface Signal Descriptions ....21
Embedded Core/FPGA Interface Signal Locations .........27
Embedded Core Bit Stream Configurable Options .........32
Understanding FIFO Packing/Unpacking ........................33
Embedded Core/FPGA Interface Operation ...................34
Embedded Core/FPGA Interface Operation Summary ...35
Master (FPGA Initiated) Write .........................................36
Master (FPGA Initiated) Read .........................................42
Target (PCI Bus Initiated) Write ......................................49
Target (PCI Bus Initiated) Read ......................................58
PCI Bus Core Detailed Description Quad Port ...................70
Embedded Core/FPGA Interface Signal Descriptions ....70
Embedded Core/FPGA Interface Signal Locations .........76
Embedded Core Bit Stream Configurable Options .........83
Understanding FIFO Packing/Unpacking ........................84
Embedded Core/FPGA Interface Operation ...................86
Embedded Core/FPGA Interface Operation Summary ...87
Master (FPGA Initiated) Write .........................................88
Master (FPGA Initiated) Read .........................................94
Target (PCI Bus Initiated) Write ....................................101
Target (PCI Bus Initiated) Read ....................................110
Configuration Space of the PCI Core ...............................123
PCI Bus Configuration Space Organization ..................123
2
Contents
Page
FPSC Configuration ......................................................... 126
Configuration via PCI Bus ............................................. 126
Readback via PCI interface .......................................... 127
Interaction Among Configuration Modes ...................... 127
Clocking Options at FPGA/Core Boundary ..................... 128
PCI Clock as System Clock .......................................... 128
Local Clock as System Clock ....................................... 128
FPGA Configuration Data Format ................................... 130
Using ORCA Foundry to Generate Configuration
RAM Data ................................................................... 130
FPGA Configuration Data Frame .................................. 130
Bit Stream Error Checking ............................................... 132
FPGA Configuration Modes ............................................. 132
Powerup Sequencing for Series OR3LP26B Device ....... 133
Absolute Maximum Ratings ............................................. 133
Recommended Operating Conditions ............................. 134
Electrical Characteristics ................................................. 135
Timing Characteristics ..................................................... 136
Description .................................................................... 136
Clock Timing ................................................................. 137
Input/Output Buffer Measurement Conditions ................. 148
Output Buffer Characteristics .......................................... 149
Estimating Power Dissipation .......................................... 150
Pin Information ................................................................ 151
Package Compatibility .................................................. 154
Package Thermal Characteristics Summary ................... 178
ΘJA ............................................................................... 178
ψJC ............................................................................... 178
ΘJC ............................................................................... 178
ΘJB ............................................................................... 178
FPGA Maximum Junction Temperature ....................... 178
Package Coplanarity ....................................................... 179
Package Parasitics .......................................................... 180
Package Outline Diagrams .............................................. 181
Terms and Definitions ................................................... 181
352-Pin PBGA .............................................................. 182
680-Pin PBGA .............................................................. 183
Ordering Information ........................................................ 184
Figures
Figure 1. ORCA OR3LP26B PCI FPSC
Block Diagram...............................................................13
Figure 2. Master Write Single (FPGA Bus, Dual-Port).....38
Figure 3. Master Write Single (PCI Bus, 64-Bit) ..............39
Figure 4. Master Write 32-Byte Burst
(FPGA Bus, Dual-Port) .................................................40
Figure 5. Master Write 32-Byte Burst (PCI Bus, 64-Bit) ..41
Figure 6. Master Read Single (FPGA Bus, Dual-Port,
Specified Burst Length, 64-Bit Address).......................44
Figure 7. Master Read Single (PCI Bus, 64-Bit) ..............45
Figure 8. Master Read 32-Byte Burst (FPGA Bus,
Dual-Port, Burst Length, and 64-Bit Address) ..............46
Figure 9. Master Read 32-Byte Burst
(PCI Bus, 64-Bit)...........................................................47
Lucent Technologies Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Table of Contents (continued)
Contents
Page
Figure 10. Target Configuration Write
(PCI Bus, 64-Bit) ...........................................................52
Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...53
Figure 12. Target Write Memory Single
(PCI Bus, 64-Bit) ...........................................................54
Figure 13. Target Write Single (FPGA Bus, Dual-Port)....55
Figure 14. Target Memory Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................56
Figure 15. Target Write Memory 32-Byte Burst
(FPGA Bus, Dual-Port) .................................................57
Figure 16. Target Configuration Read
(PCI Bus, 64-Bit) ...........................................................61
Figure 17. Target I/O Read, Delayed (PCI Bus, 64-Bit) ...62
Figure 18. Target I/O Read, Not Delayed
(PCI Bus, 64-Bit) ...........................................................63
Figure 19. Target Memory Single Read, Delayed
(PCI Bus, 64-Bit) ...........................................................64
Figure 20. Target Read Single (FPGA Bus, Dual-Port)....65
Figure 21. Target Memory Read Single, Not Delayed
(PCI Bus, 64-Bit) ...........................................................66
Figure 22. Target Memory Read 32-Byte Burst, Delayed
(PCI Bus, 64-Bit) ...........................................................67
Figure 23. Target Read Memory 32-Byte Burst
(FPGA, Dual-Port) ........................................................68
Figure 24. Target Read Memory Burst, No Delayed
(PCI Bus, 32-Bit) ...........................................................69
Figure 25. Master Write Single (PCI Bus, 64-Bit) ............90
Figure 26. Master Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................91
Figure 27. Master Write Single Quadword
(FPGA Bus, Quad-Port, 64-Bit Address) ......................92
Figure 28. Master Write 32-Byte Burst
(FPGA Bus, Quad-Port, 64-Bit Address) ......................93
Figure 29. Master Read Single (PCI Bus, 64-Bit) ............96
Figure 30. Master Read Single Quadword (FPGA Bus,
Quad-Port, Specified Burst Length, 32-Bit Address) ....97
Figure 31. Master Read 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................98
Figure 32. Master Read 32-Byte Burst (FPGA Bus,
Quad-Port, Specified Burst Length, 32-Bit Address) ....99
Figure 33. Target Configuration Write
(PCI Bus, 64-Bit) ...........................................................104
Figure 34. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...105
Figure 35. Target Write Memory Single
(PCI Bus, 64-Bit) ...........................................................106
Figure 36. Target Write Single Quadword
(FPGA Bus, Quad-Port, 64-Bit Address) ......................107
Figure 37. Target Memory Write 32-Byte Burst
(PCI Bus, 64-Bit) ...........................................................108
Figure 38. Target Write Memory 32-Byte Burst
(FPGA Bus, Quad-Port, 32-Bit Address) ......................109
Figure 39. Target Configuration Read
(PCI Bus, 64-Bit) ...........................................................113
Figure 40. Target I/O Read, Delayed
(PCI Bus, 64-Bit) ...........................................................114
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Lucent Technologies Inc.
Contents
Page
Figure 41. Target I/O Read, Not Delayed
(PCI Bus, 64-Bit) .......................................................... 115
Figure 42. Target Memory Single Read, Delayed
(PCI Bus, 64-Bit) .......................................................... 116
Figure 43. Target Read Single (FPGA Bus, Quad-Port,
64-Bit Address)............................................................. 117
Figure 44. Target Memory Read Single, Not Delayed
(PCI Bus, 64-Bit) .......................................................... 118
Figure 45. Target Memory Read 32-Byte Burst, Delayed
(PCI Bus, 64-Bit) .......................................................... 119
Figure 46. Target Read Memory 32-Byte Burst
(FPGA Bus, Quad-Port, 32-Bit Address) ...................... 120
Figure 47. Target Read Memory Burst, No Delayed
(PCI Bus, 32-Bit) .......................................................... 121
Figure 48. FPSC Block Diagram and Clock Network ...... 129
Figure 49. Serial Configuration Data Format—
Autoincrement Mode .................................................... 131
Figure 50. Serial Configuration Data Format—
Explicit Mode ................................................................ 131
Figure 51. ExpressCLK to Output Delay ......................... 138
Figure 52. Fast Clock to Output Delay ............................ 139
Figure 53. System Clock to Output Delay ....................... 140
Figure 54. Input to ExpressCLK Setup/Hold Time .......... 141
Figure 55. Input to Fast Clock Setup/Hold Time.............. 142
Figure 56. Input to System Clock Setup/Hold Time ........ 143
Figure 57. ac Test Loads ................................................. 148
Figure 58. Output Buffer Delays ...................................... 148
Figure 59. Input Buffer Delays......................................... 148
Figure 60. Sinklim (TJ = 25 °C, VDD = 3.3 V) ................. 149
Figure 61. Slewlim (TJ = 25 °C, VDD = 3.3 V) ................ 149
Figure 62. Fast (TJ = 25 °C, VDD = 3.3 V)...................... 149
Figure 63. Sinklim (TJ = 125 °C, VDD = 3.0 V) ............... 149
Figure 64. Slewlim (TJ = 125 °C, VDD = 3.0 V) .............. 149
Figure 65. Fast (TJ = 125 °C, VDD = 3.0 V).................... 149
Figure 66. Package Parasitics ......................................... 180
Tables
Table 1. ORCA OR3LP26B PCI FPSC Solution—
Available FPGA Logic................................................... 1
Table 2. PCI Local Bus Data Rates ................................ 10
Table 3. OR3LP26B Array .............................................. 11
Table 4. PCI Bus Command Descriptions ...................... 14
Table 5. Timing Budgets................................................. 17
Table 6. FIFO Flags Provided to FPGA Application ....... 18
Table 7. PCI Bus Pin Descriptions.................................. 18
Table 8. Embedded Core/FPGA Interface Signals ......... 21
Table 9. OR3LP26B FPGA/PCI Core Interface Signal
Locations ...................................................................... 27
Table 10. Bit Definitions on FPGA/PCI Core Interface ... 30
Table 11. Address Cycle Sequences for Various
Operations ................................................................... 31
Table 12. PCI Core Options Settable via FPGA
Configuration RAM Bits ................................................ 32
3
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Table of Contents (continued)
Contents
Page
Table 13. Dual-Port FIFO Packing/Unpacking, Case 1,
PCI Side ...................................................................... 33
Table 14. Dual-Port FIFO Packing/Unpacking, Case 1,
FPGA Side .................................................................. 33
Table 15. Dual-Port FIFO Packing/Unpacking, Case 2,
PCI Side ....................................................................... 33
Table 16. Dual-Port FIFO Packing/Unpacking, Case 2,
FPGA Side .................................................................. 34
Table 17. Index to State Sequence Tables ..................... 35
Table 18. Dual-Port Master Write .................................. 41
Table 19. Dual-Port Master Read, 64-Bit Address
Supplied ....................................................................... 48
Table 20. Dual-Port Master Read, 32-Bit Address
Supplied ...................................................................... 48
Table 21. Dual-Port Target Write ................................... 57
Table 22. Dual-Port Target Read ................................... 69
Table 23. Embedded Core/FPGA Interface Signals ....... 70
Table 24. OR3LP26B FPGA/PCI Core Interface Signal
Locations...................................................................... 76
Table 25. Bit Definitions on FPGA/PCI Core Interface ... 79
Table 26. Address Cycle Sequences for Various
Operations ................................................................... 82
Table 27. PCI Core Options Settable via FPGA
Configuration RAM Bits ................................................ 83
Table 28. Quad-Port FIFO Packing/Unpacking, Case 1,
PCI Side ....................................................................... 84
Table 29. Dual-Port FIFO Packing/Unpacking, Case 1,
FPGA Side .................................................................. 84
Table 30. Quad-Port FIFO Packing/Unpacking, Case 1,
PCI Side ...................................................................... 85
Table 31. Quad-Port FIFO Packing/Unpacking,
Case 1, FPGA Side...................................................... 85
Table 32. Quad-Port FIFO Packing/Unpacking, Case 2,
PCI Side ....................................................................... 85
Table 33. Quad-Port FIFO Packing/Unpacking, Case 1,
FPGA Side ................................................................... 85
Table 34. Holding Registers, Examples of Typical
Operation ..................................................................... 86
Table 35. Index to State Sequence Tables ..................... 87
Table 36. Quad-Port Master Write ................................. 93
Table 37. Quad-Port Master Read, Duplicate Burst
Length and 16-Bit Address........................................... 100
Table 38. Quad-Port Master Read, Specified Burst
Length and 64-Bit Address .......................................... 100
Table 39. Quad-Port Target Write .................................. 109
Table 40. Quad-Port Target Read................................... 122
Table 41. Configuration Space Layout............................ 123
Table 42. Configuration Space Assignment ................... 124
Table 43. Configuration Frame Format and Contents .... 131
Table 44. Configuration Frame Size ............................... 132
Table 45. Configuration Modes....................................... 132
Table 46. Absolute Maximum Ratings ............................ 133
Table 47. Recommended Operating Conditions............. 134
Table 48. Electrical Characteristics ................................ 135
Table 49. Derating for Commercial Devices
(I/O Supply VDD) ......................................................... 136
4
Contents
Page
Table 50. .........................................................................Derating for Commercial Devices (I/O Supply VDD2) ........136
Table 51. ExpressCLK (ECLK) and Fast Clock (fclk)
TimingCharacteristics ...................................................137
Table 52. General-Purpose Clock Timing
Characteristics (Internally Generated Clock) ................138
Table 53. OR3LP26B ExpressCLK to Output
Delay (Pin-to-Pin) .........................................................138
Table 54. OR3LP26B Fast Clock (fclk) to Output
Delay (Pin-to-Pin) .........................................................139
Table 55. OR3LP26B General System Clock (SCLK)
to Output Delay (Pin-to-Pin)..........................................140
Table 56. OR3LP26B Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin) ..................141
Table 57. OR3LP26B Input to Fast Clock
Setup/Hold Time (Pin-to-Pin)........................................142
Table 58. OR3LP26B Input to General System
Clock (SCLK) Setup/Hold Time (Pin-to-Pin) .................143
Table 59. OR3LP26B PCI and FPGA Interface Clock
Operation Frequencies .................................................143
Table 60. OR3LP26B FPGA to PCI, and PCI to FPGA,
Combinatorial Path Delays ...........................................144
Table 61. OR3LP26B FPGA Side Interface
Combinatorial Path Delay Signals ................................144
Table 62. OR3LP26B Interbuf Delays .............................145
Table 63. OR3LP26B FPGA Side Interface Clock to
Output Delays, pciclk Synchronous Signals .................145
Table 64. OR3LP26B FPGA Side Interface Clock to
Output Delays, fclk Synchronous Signals .....................146
Table 65. OR3LP26B FPGA Side Interface Input
Setup Delays, pciclk Synchronous Signals...................147
Table 66. OR3LP26B FPGA Side Interface Input
Setup Delays, fclk Synchronous Signals ......................147
Table 67. PCI Core Internal Power Dissapation .............150
Table 68. FPGA Common-Function Pin Descriptions.....151
Table 69. ORCA OR3LP26B I/Os Summary ..................154
Table 70. Pinout Information ..........................................155
Table 71. ORCA OR3LP26B Plastic Package Thermal
Guidelines.....................................................................178
Table 72. Package Coplanarity .......................................179
Table 73. Package Parasitics ..........................................180
Table 74. Voltage Options ...............................................184
Table 75. Package Options .............................................184
Table 76. ORCA Series 3+ Package Matrix ....................184
Table 77. Embedded Core Type......................................184
Table 78. FPSC Base Array ............................................184
Lucent Technologies Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Highlights (continued)
■
■
Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of accessing its own local Target.
— Capable of acting as the system's configuration
agent by booting up with the Master logic
enabled.
— Supports multiple options for Master bus requests,
to increase PCI bus bandwidth.
— Supports single-cycle I/O space accesses.
— Provides option to delay PCI access until FIFO is
full on Master writes to increase PCI bandwidth.
— Supports programmable latency timer control.
Target:
— Responds legally to all command codes: interrupt
acknowledge, special cycle, and reserved commands ignored; memory read multiple and line
handled as memory read; memory write and
invalidate handled as memory write.
— Implements Target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Method of handling retries is programmable at
FPGA configuration to allow tailoring to different
Target data access latencies.
— Decodes at medium speed.
— Provides option to delay PCI access until FIFO is
full on Target reads to increase PCI bandwidth.
■
Supports dual-address cycles (both as Master and
Target).
■
Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
■
Independent Master and Target clocks can be supplied to the PCI FIFO interface from the FPGA-based
logic.
■
Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
■
PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
Lucent Technologies Inc.
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Parameter
Device Clock = > Out
Device Setup Time
Board Prop. Delay
Board Clock Skew
Total Budget
Load Capacitance
33 MHz
50 MHz
66 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 pF
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
50 pF
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
10 pF
■
Configuration options:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot Plug/Hot Swap capability.
■
Generates interrupts on intan as directed by the
FPGA.
■
PCI I/O output drivers can be programmed for fast or
slew-limited operation.
■
Automatically detects 5 V or 3.3 V PCI bus signaling
environment and provides appropriate I/O signaling,
under 3.3 V commercial conditions.
■
Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary systems.
FPSC Highlights
■
Implemented as an embedded core into the
advanced Series 3+ ORCA FPSC architecture.
■
Allows the user to integrate the core with up to 120K
gates of programmable logic, all in one device, and
provides up to 259 user I/O pins in addition to the
PCI interface pins.
■
FPGA portion retains all of the features of the ORCA
3 FPGA architecture:
— High-performance, cost-effective, 0.25 µm
5-level metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
5
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
FPSC Highlights (continued)
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control,
and device status, as well as for a general-purpose interface to the FPGA. Glueless interface to
i960 † and PowerPC ‡ processors with user-configurable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be combined with FPGA logic to create complex functions, such as digital phase-locked loops (DPLL),
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True internal 3-state, bidirectional buses with simple control provided by the SLIC.
— 32 x 4 RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE §1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
■
High-speed on-chip interface provided between
FPGA logic and embedded core to reduce bottlenecks typically found when interfacing off-chip.
■
Supported in two packages: 352-pin PBGA and
680-pin PBGAM.
Data Sheet
March 2000
Note: This document will conform to the nomenclature
of the PCI Local Bus Specification, as follows:
Term
Meaning
byte
word
DWORD
Quadword
8 bits
16 bits
32 bits
64 bits
Software Support
■
Supported by ORCA Foundry software and thirdparty CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with embedded PCI bus core.
■
PCI core configuration options and simulation
netlists generated by FPSC Configuration Manager
utility in ORCA Foundry software.
■
Preference files provided for timing interface between
PCI bus core and FPGA logic.
* PAL is a trademark of Advanced Micro Devices, Inc.
† i960 is a registered trademark of Intel Corporation.
‡ PowerPC is a registered trademark of International Business
Machines Corporation.
§ IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
6
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TechnologiesInc.
Inc.
Data Sheet
March 2000
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Description
FPGA/Embedded Core Interface
What Is an FPSC?
The interface between the FPGA logic and the embedded core is designed to look like FPGA I/Os from the
FPGA side, simplifying interface signal routing and providing a unified approach with general FPGA design.
Effectively, the FPGA is designed as if signals were
going off of the device to the embedded core, but the
on-chip interface is much faster than going off-chip and
requires less power. All of the delays for the interface
are precharacterized and accounted for in the ORCA
Foundry Development System.
FPSCs, or field-programmable system chips, are
devices that combine field-programmable logic with
ASIC or mask-programmed logic on a single device.
FPSCs provide the time to market and flexibility of
FPGAs, the design effort savings of using soft intellectual property (IP) cores, and the speed, design density,
and economy of ASICs.
FPSC Overview
Lucent’s Series 3+ FPSCs are created from Series 3
ORCA FPGAs. To create a Series 3+ FPSC, several
rows of programmable logic cells (see FPGA Logic
Overview section for FPGA logic details) are removed
from a Series 3 ORCA FPGA, and the area is replaced
with an embedded logic core. Other than replacing
some FPGA gates with ASIC gates, at greater than
10:1 efficiency, none of the FPGA functionality is
changed—all of the Series 3 FPGA capability is
retained: MPI, PCMs, boundary scan, etc. The rows of
programmable logic are replaced at the bottom of the
device, allowing pins on the bottom and sides of the
replaced rows to be used as I/O pins for the embedded
core. The remainder of the device pins retain their
FPGA functionality as do special function FPGA pins
within the embedded core area.
The embedded cores can take many forms and generally come from Lucent Technologies ASIC libraries.
Future offerings will allow customers to supply their
own core functions for the creation of custom FPSCs.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its
embedded core (standard-cell/ASIC gates) and its
FPGA gates. Because FPGA gates are generally
expressed as a usable range with a nominal value, the
total FPSC gate count is sometimes expressed in the
same manner. Standard-cell/ASIC gates are, however,
10 to 25 times more silicon area efficient than FPGA
gates. Therefore, an FPSC with an embedded function
is gate equivalent to an FPGA with a much larger gate
count.
Lucent Technologies Inc.
Lucent Technologies Inc.
Clock spines also can pass across the FPGA/embedded core boundary. This allows for fast, low-skew clocking between the FPGA and the embedded core. Many
of the special signals from the FPGA, such as DONE
and global set/reset, are also available to the embedded core, making it possible to fully integrate the
embedded core with the FPGA as a system.
For even greater system flexibility, FPGA configuration
RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded
core, in turn allowing for greater flexibility. Multiple
embedded core configurations may be designed into a
single device with user-programmable control over
which configurations are implemented, as well as the
capability to change core functionality simply by reconfiguring the device.
ORCA Foundry Development System
The ORCA Foundry Development System is used to
process a design from a netlist to a configured FPSC.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools. The development system
also includes interfaces to, and libraries for, other popular CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPSC. In the design flow, the
user defines the functionality of the FPGA portion of
the FPSC and embedded core settings at two points in
the design flow: at design entry and at the bit stream
generation stage.
7
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Following design entry, the development system’s map,
place, and route tools translate the netlist into a routed
FPSC. A static timing analysis tool is provided to determine device speed and a back-annotated netlist can be
created to allow simulation. Timing and simulation output files from ORCA Foundry are also compatible with
many third-party analysis tools. Its bit stream generator
is then used to generate the configuration data which is
loaded into the FPSC’s internal configuration RAM.
When using the bit stream generator, the user selects
options that affect the functionality of the FPSC. Combined with the front-end tools, ORCA Foundry produces configuration data that implements the various
logic and routing options discussed in this data sheet.
ORCA Series 3 FPGA logic consists of three basic elements: programmable logic cells (PLCs), programmable input/output cells (PICs), and system-level features.
An array of PLCs is surrounded by PICs. Each PLC
contains a programmable function unit (PFU), a supplemental logic and interconnect cell (SLIC), local routing resources, and configuration RAM. Most of the
FPGA logic is performed in the PFU, but decoders,
PAL-like functions, and 3-state buffering can be performed in the SLIC. The PICs provide device inputs
and outputs and can be used to register signals and to
perform input demultiplexing, output multiplexing, and
other functions on two output signals. Some of the
system-level functions include the new microprocessor
interface (MPI) and the programmable clock manager
(PCM).
FPSC Design Kit
PLC Logic
Development is facilitated by an FPSC Design Kit
which, together with ORCA Foundry and third-party
synthesis and simulation engines, provides all software
and documentation required to design and verify an
FPSC implementation. Included in the kit are the FPSC
Configuration Manager, Verilog * and VHDL* gate-level
structural netlists, all necessary synthesis libraries, and
complete online documentation. The kit's software couples with ORCA Foundry under the control of the
ORCA Foundry Control Center (OFCC), providing a
seamless FPSC design environment. More information
can be obtained by visiting the ORCA website or contacting a local sales office, both listed on the last page
of this document.
Each PFU within a PLC contains eight 4-input (16-bit)
look-up tables (LUTs), eight latches/flip-flops (FFs),
and one additional flip-flop that may be used independently or with arithmetic functions.
Description (continued)
FPGA Logic Overview
ORCA Series 3 FPGA logic is a new generation of
SRAM-based FPGA logic built on the successful Series
2 FPGA line from Lucent Technologies Microelectronics Group, with enhancements and innovations geared
toward today’s high-speed designs and tomorrow’s systems on a single chip. Designed from the start to be
synthesis friendly and to reduce place and route times
while maintaining the complete routability of the ORCA
Series 2 devices, the Series 3 more than doubles the
logic available in each logic block and incorporates system-level features that can further reduce logic requirements and increase system speed. ORCA Series 3
devices contain many new patented enhancements
and are offered in a variety of packages, speed grades,
and temperature ranges.
8
The PFU is organized in a twin-quad fashion: two sets
of four LUTs and FFs that can be controlled independently. LUTs may also be combined for use in arithmetic functions using fast-carry chain logic in either
4-bit or 8-bit modes. The carry-out of either mode may
be registered in the ninth FF for pipelining. Each PFU
may also be configured as a synchronous 32 x 4
single- or dual-port RAM or ROM. The FFs (or latches)
may obtain input from LUT outputs or directly from
invertible PFU inputs, or they can be tied high or tied
low. The FFs also have programmable clock polarity,
clock enables, and local set/reset.
The SLIC is connected to PLC routing resources and to
the outputs of the PFU. It contains 3-state, bidirectional
buffers and logic to perform up to a 10-bit AND function
for decoding, or an AND-OR with optional INVERT
(AOI) to perform PAL-like functions. The 3-state drivers
in the SLIC and their direct connections to the PFU outputs make fast, true 3-state buses possible within the
FPGA logic, reducing required routing and allowing for
real-world system performance.
* Verilog and VHDL are registered trademarks of Cadance Design
Systems, Inc.
Lucent
LucentTechnologies
TechnologiesInc.
Inc.
Data Sheet
March 2000
Description (continued)
PIC Logic
The Series 3 PIC addresses the demand for everincreasing system clock speeds. Each PIC contains
four programmable inputs/outputs (PIOs) and routing
resources. On the input side, each PIO contains a fastcapture latch that is clocked by an ExpressCLK. This
latch is followed by a latch/FF that is clocked by a system clock from the internal general clock routing. The
combination provides for very low setup requirements
and zero hold times for signals coming on-chip. It may
also be used to demultiplex an input signal, such as a
multiplexed address/data signal, and register the signals without explicitly building a demultiplexer. Two
input signals are available to the PLC array from each
PIO, and the ORCA Series 2 capability to use any input
pin as a clock or other global input is maintained.
On the output side of each PIO, two outputs from the
PLC array can be routed to each output flip-flop, and
logic can be associated with each I/O pad. The output
logic associated with each pad allows for multiplexing
of output signals and other functions of two output signals.
The output FF, in combination with output signal multiplexing, is particularly useful for registering address
signals to be multiplexed with data, allowing a full clock
cycle for the data to propagate to the output. The I/O
buffer associated with each pad is the same as the
ORCA Series 3 buffer.
System Features
The Series 3 also provides system-level functionality by
means of its dual-use microprocessor interface (MPI)
and its innovative programmable clock manager
(PCM). These functional blocks allow for easy glueless
system interfacing and the capability to adjust to varying conditions in today’s high-speed systems. Since
these and all other Series 3 features are available in
every Series 3+ FPSC, they can also interface to the
embedded core providing for easier system integration.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
ExpressCLKs may be glitchlessly and independently
enabled and disabled with a programmable control signal using the new StopCLK feature. The improved PIC
routing resources are now similar to the patented intraPLC routing resources and provide great flexibility in
moving signals to and from the PIOs. This flexibility
translates into an improved capability to route designs
at the required speeds when the I/O signals have been
locked to specific pins.
Configuration
The FPGA logic’s functionality is determined by internal
configuration RAM. The FPGA logic’s internal initialization/configuration circuitry loads the configuration data
at powerup or under system control. The RAM is
loaded by using one of several configuration modes,
including serial EEPROM, the microprocessor interface, or the embedded function core.
Boundary Scan
Boundary scan is implemented in the OR3LP26B
device as with any of the OR3LXXB family of parts. The
PCI core side of the device contains the same boundary-scan registers. After performing a boundary-scan
test, it is highly recommended that the device be reset
through the PCI rstn pin. This reset will clear out any
PCI core internal registers that may have been set during the boundary-scan tests.
More Series 3 Information
For more information on Series 3 FPGAs, please refer
to the Series 3 FPGA data sheet, available on the
ORCA worldwide website or by contacting Lucent
Technologies as directed on the back of this data
sheet.
Routing
The abundant routing resources of ORCA Series 3
FPGA logic are organized to route signals individually
or as buses with related control signals. Clocks are
routed on a low-skew, high-speed distribution network
and may be sourced from PLC logic, externally from
any I/O pad, or from the very fast ExpressCLK pins.
Lucent Technologies Inc.
Lucent Technologies Inc.
9
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
OR3LP26B Overview
Device Layout
The OR3LP26B FPSC provides a PCI local bus core
(with FIFOs) combined with FPGA logic. The device is
based on a 2.5 V OR3L125B FPGA. The OR3L125B
has a 28 x 28 array of programmable logic cells (PLCs).
For the OR3LP26B, the bottom ten rows of PLCs in the
array were replaced with the embedded PCI bus core.
Table 3 shows a schematic view of the OR3LP26B. The
upper portion of the device is an 18 x 28 array of PLCs
surrounded on the left, top, and right by programmable
input/output cells (PICs). At the bottom of the PLC
array are the core interface cells (CICs) connecting to
the embedded core region. The embedded core region
contains the PCI bus functionality of the device. It is
surrounded on the left, bottom, and right by PCI bus
dedicated I/Os as well as power and special function
FPGA pins. Also shown are the interquad routing
blocks (hIQ, vIQ) present in the Series 3 FPGA
devices. System-level functions (located in the corners
of the PLC array), routing resources, and configuration
RAM are not shown in Figure 1.
Data Sheet
March 2000
Table 2. PCI Local Bus Data Rates
Clock
Frequency
(MHz)
Data Path
Width (bits)
Peak Data Rate
(Mbytes)
33
33
66
66
32
64
32
64
132
264
264
528
The PCI bus is electrically specified so that no glue
logic is required to interface to the bus—PCI devices
interface directly to the PCI bus. Other features include
registers for device and subsystem identification and
autoconfiguration, support for 64-bit addressing, and
multi-Master capability that allows any PCI bus Master
access to any PCI bus Target.
PCI Local Bus
PCI local bus, or simply, PCI bus, has become an
industry-standard interface protocol for use in applications ranging from desktop PC busing to high-bandwidth backplanes in networking and communications
equipment. The PCI bus specification* provides for
both 5 V and 3.3 V signaling environments. The interface clock speed is specified in the range from dc to
66 MHz with detailed specifications at 33 MHz and
66 MHz as well as recommendations for 50 MHz operation. Data paths are defined as either 32-bit or 64-bit.
These data path and frequency combinations allow for
the peak data transfer rates described in Table 2.
* PCI Local Bus Specification Rev. 2.2, PCI SIG, December 18,
1998.
10
Lucent
LucentTechnologies
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
OR3LP26B Overview (continued)
Table 3. OR3LP26B Array
PT5
PT6
PT7
PT8
PT9
PT10
PT11
PT12
PT13
PT14
PT15
PT16
PT17
PT18
PT19
PT20
PT21
PT22
PT23
PT24
PT25
PT26
PT27
PT28
PL1
R1
C1
R1
C2
R1
C3
R1
C4
R1
C5
R1
C6
R1
C7
R1
C8
R1
C9
R1
C10
R1
C11
R1
C12
R1
C13
R1
C14
R1
C15
R1
C16
R1
C17
R1
C18
R1
C19
R1
C20
R1
C21
R1
C22
R1
C23
R1
C24
R1
C25
R1
C26
R1
C27
R1
C28
PL2
R2
C1
R2
C2
R2
C3
R2
C4
R2
C5
R2
C6
R2
C7
R2
C8
R2
C9
R2
C10
R2
C11
R2
C12
R2
C13
R2
C14
R2
C15
R2
C16
R2
C17
R2
C18
R2
C19
R2
C20
R2
C21
R2
C22
R2
C23
R2
C24
R2
C25
R2
C26
R2
C27
R2
C28
PL3
R3
C1
R3
C2
R3
C3
R3
C4
R3
C5
R3
C6
R3
C7
R3
C8
R3
C9
R3
C10
R3
C11
R3
C12
R3
C13
R3
C14
R3
C15
R3
C16
R3
C17
R3
C18
R3
C19
R3
C20
R3
C21
R3
C22
R3
C23
R3
C24
R3
C25
R3
C26
R3
C27
R3
C28
PR3
PL4
R4
C1
R4
C2
R4
C3
R4
C4
R4
C5
R4
C6
R4
C7
R4
C8
R4
C9
R4
C10
R4
C11
R4
C12
R4
C13
R4
C14
R4
C15
R4
C16
R4
C17
R4
C18
R4
C19
R4
C20
R4
C21
R4
C22
R4
C23
R4
C24
R4
C25
R4
C26
R4
C27
R4
C28
PR4
PL5
R5
C1
R5
C2
R5
C3
R5
C4
R5
C5
R5
C6
R5
C7
R5
C8
R5
C9
R5
C10
R5
C11
R5
C12
R5
C13
R5
C14
R5
C15
R5
C16
R5
C17
R5
C18
R5
C19
R5
C20
R5
C21
R5
C22
R5
C23
R5
C24
R5
C25
R5
C26
R5
C27
R5
C28
PR5
PL6
R6
C1
R6
C2
R6
C3
R6
C4
R6
C5
R6
C6
R6
C7
R6
C8
R6
C9
R6
C10
R6
C11
R6
C12
R6
C13
R6
C14
R6
C15
R6
C16
R6
C17
R6
C18
R6
C19
R6
C20
R6
C21
R6
C22
R6
C23
R6
C24
R6
C25
R6
C26
R6
C27
R6
C28
PR6
PL7
R7
C1
R7
C2
R7
C3
R7
C4
R7
C5
R7
C6
R7
C7
R7
C8
R7
C9
R7
C10
R7
C11
R7
C12
R7
C13
R7
C14
R7
C15
R7
C16
R7
C17
R7
C18
R7
C19
R7
C20
R7
C21
R7
C22
R7
C23
R7
C24
R7
C25
R7
C26
R7
C27
R7
C28
PR7
PL8
R8
C1
R8
C2
R8
C3
R8
C4
R8
C5
R8
C6
R8
C7
R8
C8
R8
C9
R8
C10
R8
C11
R8
C12
R8
C13
R8
C14
R8
C15
R8
C16
R8
C17
R8
C18
R8
C19
R8
C20
R8
C21
R8
C22
R8
C23
R8
C24
R8
C25
R8
C26
R8
C27
R8
C28
PR8
PL9
R9
C1
R9
C2
R9
C3
R9
C4
R9
C5
R9
C6
R9
C7
R9
C8
R9
C9
R9
C10
R9
C11
R9
C12
R9
C13
R9
C14
R9
C15
R9
C16
R9
C17
R9
C18
R9
C19
R9
C20
R9
C21
R9
C22
R9
C23
R9
C24
R9
C25
R9
C26
R9
C27
R9
C28
PR9
R10
C1
R10
C2
R10
C3
R10
C4
R10
C5
R10
C6
R10
C7
R10
C8
R10
C9
R10
C10
R10
C11
R10
C12
R10
C13
R10
C14
R10
C15
R10
C16
R10
C17
R10
C18
R10
C19
R10
C20
R10
C21
R10
C22
R10
C23
R10
C24
R10
C25
R10
C26
R10
C27
R10
C28
PR10
R11
C1
R11
C2
R11
C3
R11
C4
R11
C5
R11
C6
R11
C7
R11
C8
R11
C9
R11
C10
R11
C11
R11
C12
R11
C13
R11
C14
R11
C15
R11
C16
R11
C17
R11
C18
R11
C19
R11
C20
R11
C21
R11
C22
R11
C23
R11
C24
R11
C25
R11
C26
R11
C27
R11
C28
PR11
R12
C1
R12
C2
R12
C3
R12
C4
R12
C5
R12
C6
R12
C7
R12
C8
R12
C9
R12
C10
R12
C11
R12
C12
R12
C13
R12
C14
R12
C15
R12
C16
R12
C17
R12
C18
R12
C19
R12
C20
R12
C21
R12
C22
R12
C23
R12
C24
R12
C25
R12
C26
R12
C27
R12
C28
PR12
R13
C1
R13
C2
R13
C3
R13
C4
R13
C5
R13
C6
R13
C7
R13
C8
R13
C9
R13
C10
R13
C11
R13
C12
R13
C13
R13
C14
R13
C15
R13
C16
R13
C17
R13
C18
R13
C19
R13
C20
R13
C21
R13
C22
R13
C23
R13
C24
R13
C25
R13
C26
R13
C27
R13
C28
PR13
R14
C1
R14
C2
R14
C3
R14
C4
R14
C5
R14
C6
R14
C7
R14
C8
R14
C9
R14
C10
R14
C11
R14
C12
R14
C13
R14
C14
R14
C15
R14
C16
R14
C17
R14
C18
R14
C19
R14
C20
R14
C21
R14
C22
R14
C23
R14
C24
R14
C25
R14
C26
R14
C27
R14
C28
PR14
R15
C1
R15
C2
R15
C3
R15
C4
R15
C5
R15
C6
R15
C7
R15
C8
R15
C9
R15
C10
R15
C11
R15
C12
R15
C13
R15
C14
R15
C15
R15
C16
R15
C17
R15
C18
R15
C19
R15
C20
R15
C21
R15
C22
R15
C23
R15
C24
R15
C25
R15
C26
R15
C27
R15
C28
PR15
R16
C1
R16
C2
R16
C3
R16
C4
R16
C5
R16
C6
R16
C7
R16
C8
R16
C9
R16
C10
R16
C11
R16
C12
R16
C13
R16
C14
R16
C15
R16
C16
R16
C17
R16
C18
R16
C19
R16
C20
R16
C21
R16
C22
R16
C23
R16
C24
R16
C25
R16
C26
R16
C27
R16
C28
PR16
R17
C1
R17
C2
R17
C3
R17
C4
R17
C5
R17
C6
R17
C7
R17
C8
R17
C9
R17
C10
R17
C11
R17
C12
R17
C13
R17
C14
R17
C15
R17
C16
R17
C17
R17
C18
R17
C19
R17
C20
R17
C21
R17
C22
R17
C23
R17
C24
R17
C25
R17
C26
R17
C27
R17
C28
PR17
PR18
PL18
PL17
PL16
PL15
PL14
PL13
PL12
PL11
PL10
PT4
R18
C1
R18
C2
R18
C3
R18
C4
R18
C5
R18
C6
R18
C7
R18
C8
R18
C9
R18
C10
R18
C11
R18
C12
R18
C13
R18
C14
R18
C15
R18
C16
R18
C17
R18
C18
R18
C19
R18
C20
R18
C21
R18
C22
R18
C23
R18
C24
R18
C25
R18
C26
R18
C27
R18
C28
ASB1
ASB2
ASB3
ASB4
ASB5
ASB6
ASB7
ASB8
ASB9
ASB10
ASB11
ASB12
ASB13
ASB14
ASB15
ASB16
ASB17
ASB18
ASB19
ASB20
ASB21
ASB22
ASB23
ASB24
ASB25
ASB26
ASB27
ASB28
EMBEDDED CORE AREA
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
Lucent Technologies Inc.
Lucent Technologies Inc.
IIII IIII IIII IIII IIII IIII IIII IIII IIII
III
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT3
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT2
PR2
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
PT1
PR1
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII IIII
IIII IIII IIII IIII
11
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
OR3LP26B Overview (continued)
PCI Bus Interface
OR3LP26B PCI Bus Core Overview
The OR3LP26B PCI bus interface is compliant to Revision 2.2 of the PCI Local Bus specification. It is capable
of no-wait-state, full-burst operation at all of the
rate/data width combinations described in Table 2 as
well as at a 50 MHz specification that provides a speed
increase over the 33 MHz specification and a larger
bus loading capability than the 66 MHz specification.
The OR3LP26B operates in either the 3.3 V or 5 V PCI
signaling environment and is automatically configured
for the appropriate environment by a PCI bus vio pin.
The OR3LP26B embedded core comprises a PCI bus
interface with independent Master and Target controllers, FIFO memories and control logic for data buffering, a dual-/quad-port interface to the FPGA logic
which performs data packing and multiplexing, and
logic to support embedded core and FPGA configuration. Each of these areas is briefly described in the following paragraphs. A detailed description of all of the
features and functionality of the OR3LP26B embedded
core is provided in the next section.
12
Independent Master and Target controllers are provided for use in systems requiring Master/Target or Target only operation. Six 32-bit base address registers
(BARs) are provided for choosing the address space of
the PCI device, and these six registers can be combined in pairs to produce 64-bit BARs. Dual address
cycles are supported in both 32-bit and 64-bit addressing modes. The BARs work in either the I/O or the
memory space of the device, and can be configured as
prefetchable or nonprefetchable.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
OR3LP26B Overview (continued)
Independent data paths exist for the Master and Target controllers. This allows for separate operation of Master
and Target functions, and the capability for a Master to talk to a Target on the same device.
In dual-port mode, the Master and Target controllers share two 64-bit data paths, one in each direction, between
the FIFOs and the FPGA logic. This provides for full-rate transfers in both 32- and 64-bit PCI bus operation.
Quad-port mode provides two 32-bit data paths for each controller: one in each direction. This mode allows for
simultaneous reads and writes on either the Master or Target controller.
Diagrams for dual-port and quad-port operation are shown in Figure 1.
113 USER I/O PADS
113 USER I/O PADS
73
USER
I/O PADS
73
USER
I/O PADS
OR3T SERIES FPGA
18 ROWS x 28 COLUMNS
32
32
32
73
USER
I/O PADS
32
TARGET
64-bit x
16 DEEP
FIFO
MASTER
64-bit x
32 DEEP
FIFO
64
64
DATA CONTROL
AND
MULTIPLEXING
DATA CONTROL
AND
MULTIPLEXING
TARGET
64-bit x
16 DEEP
FIFO
73
USER
I/O PADS
OR3T SERIES FPGA
18 ROWS x 28 COLUMNS
MASTER
64-bit x
32 DEEP
FIFO
TARGET
64-bit x
16 DEEP
FIFO
TARGET
64-bit x
16 DEEP
FIFO
MASTER
64-bit x
32 DEEP
FIFO
PCI
MASTER/TARGET
INTERFACE
PCI
MASTER/TARGET
INTERFACE
PCI
BUS
PCI
BUS
MASTER
64-bit x
32 DEEP
FIFO
5-6368(F).e
Note: User I/O pin count includes three ExpressCLK pins.
Figure 1. ORCA OR3LP26B PCI FPSC Block Diagram
Embedded Core Options/FPGA Configuration
In addition to the Series 3 FPGA configuration modes (less Master parallel), the OR3LP26B can also be configured
via the PCI bus. Configuration as discussed here has two meanings. There is configuration of the FPGA logic, and
there is configuration of the options available in the embedded core. Both are accomplished through the FPGA
configuration process (some PCI configuration options may also be set via registers within the PCI bus core).
Readback of FPGA and PCI core options is also possible using the PCI bus or Series 3 FPGA readback modes.
The PCI bus core will be functional in the default PCI bus configuration space, as defined in the PCI bus 2.2 specification, prior to an initial configuration of the FPGA logic or the embedded core options.
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13
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description
The following sections describe the operation of the embedded core PCI bus interface.
PCI Bus Commands
The PCI core supports all commands required by the PCI specification. The following table describes each command. Subsequent sections will describe the protocols in which the commands are used.
Table 4. PCI Bus Command Descriptions
Command
Command
Code
(Binary)
Master
Generates
Target
Accepts
—
—
—
—
0010
Interrupt
Acknowledge
Special
Cycle
I/O Read
√
√
0011
I/O Write
√
√
0100
0101
0110
(reserved)
(reserved)
Memory
Read
—
—
—
—
√
√
0000
0001
14
Description
Only implemented as Master by agents that interface to the system CPU and as Target by agents that incorporate the system
interrupt controller.
Target ignores, per PCI Specification section 3.6.2.
Fully implemented.
Target: Bursting is prevented by disconnecting with data on the
first data phase. If signal deltrn is asserted low, I/O (and memory)
reads are handled as delayed transactions; no wait-states are
generated. If signal deltrn is deasserted high, the unit waits for the
data from the FPGA application, inserting wait-states (up to the
maximum allowed, after which a retry is issued).
Master: Bursting is allowed, and no wait-states are generated.
Fully implemented.
Target: Bursting is prevented by disconnecting with data on the
first data phase. If signal deltrn is asserted low, I/O writes are
handled as delayed transactions; no wait-states are generated.
Master: Bursting is allowed, and no wait-states are generated.
Target ignores, per PCI Specification section 3.1.1.
Target ignores, per PCI Specification section 3.1.1.
Fully implemented.
Target: Bursting is allowed. If signal deltrn is asserted low, memory (and I/O) reads are handled as delayed transactions. If signal
deltrn is deasserted high, the unit waits for the data from the
FPGA application, inserting wait-states (up to the maximum
allowed, after which a retry is issued). If signal trburstpendn is
asserted low and the Target Read FIFO is empty, wait-states are
inserted (up to the maximum allowed, after which a retry is
issued).
Master: Bursting is allowed, and no wait-states are generated.
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description (continued)
Table 4. PCI Bus Command Descriptions (continued)
Command
Command
Code
(Binary)
Master
Generates
Target
Accepts
0111
Memory
Write
√
√
1000
1001
1010
(reserved)
(reserved)
Configuration Read
—
—
—
—
√
√
1011
Configuration Write
√
√
1100
Memory
Read
Multiple
√
√
1101
Dual
Access
Cycle
Memory
Read Line
√
√
√
√
Memory
Write and
Invalidate
√
√
1110
1111
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Description
Fully implemented.
Target: Writes are posted, bursting is allowed, and no wait-states
are generated.
Master: Bursting is allowed, and no wait-states are generated.
Target ignores, per PCI Specification section 3.1.1.
Target ignores, per PCI Specification section 3.1.1.
Fully implemented.
Target: Bursting is disallowed, and no wait-states are generated.
Target disconnects with data on first data word. The FPGA portion
of the device is not involved in Target configuration transactions.
Master: Bursting is allowed, and no wait-states are generated.
Fully implemented.
Target: Bursting is disallowed, and no wait-states are generated.
Target disconnects with data on first data word. The FPGA portion
of the device is not involved in Target configuration transactions.
Master: Bursting is allowed, and no wait-states are generated.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (0110); the user’s FPGA
logic is responsible for ensuring that the Master operation meets
the special requirement that the read request ends on a cacheline
boundary.
Fully implemented. Per PCI Specification section 3.9, the PCI core
will automatically convert a 64-bit address to a 32-bit address if
the upper 32 bits are all zeros.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (0110); the user’s FPGA
logic is responsible for ensuring that the Master operation meets
the special requirement that the read request continues to the next
cacheline boundary.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory write (0111); the user’s FPGA
logic is responsible for ensuring that the Master operation meets
the special requirement that writes of complete cachelines, with all
byte enables, are performed.
15
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description
Device Selection (devseln)
(continued)
The target is responsible for responding to a master’s
request by asserting the PCI bus signal devseln.
devseln may be asserted one, two, or three clocks
after the address phrase of a transaction, corresponding to fast, medium, or slow decode, respectively. The
PCI core’s target is capable of preforming a mediumspeed decode response. The decode response speed
has a significant impact on the overall latency and
bandwidth of nonburst PCI transactions, but its impact
decreases greatly for burst transactions, particularly for
burst lengths of the size of the PCI core’s FIFOs.
PCI Protocol Fundamentals
Basic Transfer Control
The following paragraphs describe various aspects of
the PCI protocol and the way they are handled by the
PCI core.
Addressing. The PCI Specification defines three types
of address spaces. The first, configuration address
space, is a physical address of space and is intended
as a means for powerup software to identify agents and
configure them before other address spaces have allocated. The second, I/O address space, is intended for
mapping control functions. Control function page sizes
in configuration space should be no more than
256 bytes. The third, memory address space, is
intended for bulk data transfer. It has features to facilitate this, such as special commands for cache implementation, large page sizes, and mechanisms for
prefetching. The PCI core handles all three address
space types as both a Master and a Target.
Byte Alignment. On all write operations (configuration,
I/O, and memory space, and including the memory
write and invalidate instruction), for both the PCI core’s
Master and Target functions, byte enables are fully
implemented from/to the FPGA interface. Note, however, that even though the PCI core implements the
ability to control byte enables for the memory write and
invalidate instruction, the PCI Specification requires
that this instruction assert all byte enables, and this is
the FPGA application’s responsibility. On read operations, the utility of byte enables is more dubious since
the data must be enroute from the PCI bus from Target
to Master, at the time that the corresponding byte
enables are enroute on the PCI bus Master to Target
(unless wait-states are inserted). The PCI core, therefore, does not implement byte enable control for Master
or Target reads. Byte enables on master read operations are always asserted, and target ignores the byte
enables that are sent, in accordance with PCI Specification requirements.
16
Address/Data Stepping
Stepping is an optional feature added to the PCI Specification to accommodate agents whose bus drive capability is insufficient to handle large groups of signals
changing state in one clock cycle. Continuous stepping
allows weak drivers multiple cycles for signal transition.
Discrete stepping partitions the bus into two or more
groups of bits that transition on successive clock
cycles. However, stepping exacts a heavy toll on performance, cutting maximum bandwidth by at least 50%
and increasing latency. The PCI core is designed for
maximum throughput with high-performance buffers, so
stepping is unnecessary and not implemented. The
wait cycle control, bit 7 of the command register, is
therefore hardwired to a zero.
Reset Operation
The PCI bus contains a signal, rstn, that performs a
PCI reset function. When the reset occurs, all state
machines in the ASIC are placed in their idle state, the
configuration space BARs are reset to their mask values, and the command registers are reset. The reset
does not reset the FPGA logic. The PCI reset signal is
fed from the ASIC to the FPGA logic to be used by the
designer.
Interrupt Acknowledge
The interrupt acknowledge command is a read by the
system CPU implicitly addressed to the system interrupt controller. Other agents, including the PCI core,
are not required to implement this instruction; the PCI
core’s Master does not generate it and its Target
ignores it.
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PCI Bus Core Detailed Description
(continued)
Arbitration Parking
The PCI Specification requires that all master agents
properly handle bus parking, which means that when
that agent receives an asserted gntn without the agent
having asserted reqn, the agent still must drive signal
par and buses AD and c_ben. The PCI core meets this
requirement.
Parity
The PCI core implements all required and optional features, including the following:
■
Master generates parity on all addresses placed on
the bus.
■
Sending agent generates parity on all data placed on
the bus.
■
Target calculates parity on all addresses received
from the bus.
■
Receiving agent calculates parity on all data
received from the bus.
■
The detected parity error bit in the status register is
set whenever an agent calculates corrupted parity.
■
The signal perrn is generated whenever an agent
calculates corrupted parity and the parity error
response bit is set in the command register.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
value. In this case, the total budget increases from
15 ns (66 MHz) to 20 ns (50 MHz).
Table 5. Timing Budgets
Timing Element 33 MHz 50 MHz 66 MHz
Cycle Time
Valid Output
Delay
Propagation
Time
Input Setup Time
Clock Skew
Unit
30.0
11.0
20.0
7.5
15.0
6.0
ns
ns
10.0
6.5
5.0
ns
7.0
2.0
4.5
1.5
3.0
1.0
ns
ns
64-Bit Addressing
The PCI core fully supports 64-bit addressing, whether
or not the PCI core is configured to utilize the 64-bit
data extension. When the PCI core is a 64-bit target
being addressed by 64-bit master, the PCI core will
decode the address one cycle faster so that dualaddress operation will have no performance impact;
see PCI Specification section 3.9 for details.
Section 3.9 of the PCI Specification also states that a
Master that supports 64-bit addressing must nevertheless generate requests utilizing a single address
instead of a dual address when the upper 32 bits are all
zeros. This shortens the request time by one cycle
when communicating with 32-bit Targets. It is the FPGA
application’s responsibility to ensure that this requirement is met.
66 MHz Operation
The PCI core is fully compliant to PCI Specification
requirements at all clock rates up to 66 MHz. All
33 MHz requirements are also met.
Timing Budget
The PCI core’s timing budget is summarized in Table 5.
Note that the 66 MHz timing requirements only allow
5 ns for signal propagation (TPROP), as compared to
10 ns at 33 MHz. The effect of the reduction is to also
reduce the number of agents that the bus can support,
although the actual number is not specified in the PCI
Specification and is dependent on the design of the
hardware components. The four components of the
timing budget are TVAL (valid output delay), TPROP
(propagation time), TSU (input setup time), and TSKEW
(clock skew); of these, only TVAL and TSU are controlled
by the PCI component, and TPROP and TSKEW are system parameters. Table 5 includes a third column (also
shown in the PCI Specification). This column indicates
the performance attainable if all 66 MHz requirements
are met except TPROP = 10 ns, which is the 33 MHz
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FIFO Memories and Control
The OR3LP26B embedded core contains four FIFO
memories and supporting control logic. Two FIFOs are
for the master interface data and two for the target
interface data. These FIFOs are always configured to
operate in 64-bit mode and also carry byte enable bits
on a per-byte basis (e.g., the 64-bit FIFO actually carries 64 bits of data and 8 byte enable bits for a total of
72 bits). During 32-bit transactions, the FPSC will pack
the data to fully utilize the memories. All FIFOs have
four flags: Full, Almost Full (Full-4), Empty, and Almost
Empty (Empty+4). (See Table 6.) The FPGA application is provided with the Full/Empty signal and Almost
Full/Empty signal associated with the FPGA side of the
FIFO. In addition, the FPGA application is provided
with the PCI side's Full/Empty signal (but not the
Almost Full/Empty signal), to enable checking for operation completion. Clocking for the FPGA side of all
FIFOs is flexible, with options for different clocks for the
Master and Target FIFOs, sourced by the FPGA logic,
or by the PCI bus clock.
17
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description (continued)
Table 6. FIFO Flags Provided to FPGA Application
Write Operation
Master Operation
Target Operation
Read Operation
FPGA Side
PCI Side
FPGA Side
PCI Side
mw_fulln
mw_afulln
tw_emptyn
tw_aemptyn
mw_emptyn
mr_emptyn
mr_aemptyn
tr_fulln
tr_afulln
mr_fulln
tw_fulln
tr_emptyn
PCI Bus Pin Information
This section describes signals on the PCI bus interface and at the embedded core/FPGA interface. Some signal
definitions change name and location based on the mode of operation. Modes of operation are described following
the signal descriptions. PCI bus signal package pin locations can be found in Table 70.
Table 7. PCI Bus Pin Descriptions
I/O
Description
clk
I
rstn
I
Clock. Provides timing for all transactions on the PCI bus and is an input to the
OR3LP26B device. All PCI signals, except rstn and intan, are sampled on the rising edge of clk, and all other PCI bus timing parameters are defined with respect to
this edge. The signal clk operates up to 66 MHz, and the minimum frequency is dc.
Reset. An active-low signal used to reset the entire PCI bus. rstn is asynchronous
to clk. During rstn, all PCI output signals are 3-stated.
Symbol
System Pins
Address and Data Pins
ad[31:0]
I/O
Address and Data. Multiplexed on the same PCI pins. A PCI bus transaction consists of an address phase followed by one or more data phases.
During data phases, ad[7:0] contain the least significant byte and ad[31:24] contain the most significant byte. During memory commands, the ad[31:2] lines specify the address and ad[1:0] specify the type of bursting sequence to use. The table
below outlines the bursting sequence based on the values of ad[1:0].
18
c_ben[3:0]
I/O
par
I/O
ad[1:0] Bursting sequence.
00 Linear incrementing.
01 Disconnect after first transfer.
10 Disconnect after first transfer.
11 Disconnect after first transfer.
Bus Command and Byte Enables. Active-low signals multiplexed on the same
PCI pins. During the address phase of a transaction, c_ben[3:0] define the bus
command. During the data phase, c_ben[3:0] are used as byte enables. The byte
enables are valid for the entire data phase and determine which byte lanes carry
meaningful data.
Parity. Specifies even parity across ad[31:0] and c_ben[3:0]. par is stable and
valid one clock after the address phase. For data phases, par is stable and valid
one clock after irdyn is asserted on a write transaction or trdyn is asserted on a
read transaction. Once par is valid, it remains valid until one clock after the completion of the current data phase. The Master drives par for address and write data
phases; the Target drives par for read data phases.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description (continued)
Table 7. PCI Bus Pin Descriptions (continued)
Symbol
I/O
Description
Interface Control Pins
framen
I/O
Cycle Frame. An active-low signal driven by the current Master to indicate the
beginning and duration of an access. The signal framen is asserted to indicate a
bus transaction is beginning. While framen is asserted, data transfers continue.
When framen is deasserted, the transaction is in the final phase or has completed.
Initiator Ready. An active-low signal indicating the bus Master’s ability to complete
irdyn
I/O
the current data phase of the transaction. The signal irdyn is used in conjunction
with trdyn. A data phase is completed on any clock cycle during which both irdyn
and trdyn are asserted. During a write, irdyn indicates that valid data is present on
ad[31:0]. During a read, it indicates the Master is prepared to accept data. Wait
cycles are inserted until both irdyn and trdyn are asserted together.
Target Ready. An active-low signal asserted to indicate the readiness of the TarI/O
trdyn
get’s agent to complete the current data phase of the transaction. The signal trdyn
is used in conjunction with irdyn. A data phase is completed on any clock where
both trdyn and irdyn are sampled active. During reads, trdyn indicates that valid
data is present on ad[31:0] lines. During write cycles, trdyn indicates that the Target is prepared to accept data.
STOPn. Indicates that the current Target is requesting the Master to stop the curI/O
stopn
rent transaction.
Initialization Device Select. Used as a chip select during PCI configuration read
idsel
I
and write transactions. Generally, the user ties idsel to one of the upper 24 address
lines, ad[31:8].
Device Select. An active-low input indicating that a device on the bus has been
devseln
I/O
selected. As an output, it indicates that the driving device has decoded its address
as the Target of the current access.
Arbitration Pins (for Bus Master Only)
Request. An active-low signal that indicates to the arbiter that the asserting agent
reqn
O
desires use of the bus. In the OR3LP26B, this signal is asserted when the
OR3LP26B Master controller needs access to the PCI bus.
Grant. An active-low signal that indicates to the OR3LP26B that access to the PCI
gntn
I
bus has been granted.
Error Reporting Pins
Parity Error. An active-low signal for the reporting of data parity errors during all
perrn
I/O
PCI transactions except a special cycle. The perrn pin is a sustained 3-state signal
and must be driven active by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration of perrn is one clock for
each data phase that a data parity error is detected. If sequential data phases each
have a data parity error, the perrn signal will be asserted for more than a single
clock. perrn is driven high for one clock before being 3-stated. The signal perrn is
not asserted until it has claimed the access by asserting devseln and completed a
data phase.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description (continued)
Table 7. PCI Bus Pin Descriptions (continued)
Symbol
I/O
Description
serrn
O
System Error. An active-low open drain signal pulsed by agents to report errors
other than parity. serrn is sampled every clk edge, so any agent asserting serrn
must ensure it is valid for at least one clock period. The OR3LP26B asserts serrn if
a Master abort sequence is asserted when the Master controller is accessing the
PCI bus.
O
PCI Interrupt. The OR3LP26B asserts this active-low open drain signal when it
requests an interrupt from the PCI compliant interrupt controller.
Interrupt Pins
intan
64-Bit Bus Extension Pins
64-Bit Address and Data. These signals provide the upper 32 bits of address and
ad[63:32]
I/O
data when in PCI 64-bit operation. During an address phase (when using the DAC
command and when req64n is asserted), these address bits are transferred. During a data phase, the data is valid when req64n and ack64n are both asserted.
Otherwise, these bits are 3-stated.
Byte Enables. These are the upper four, active-low, bus command and byte
c_ben[7:4]
I/O
enables when in PCI 64-bit operation. During an address phase (when using the
DAC command and when req64n is asserted), the bus command is transferred.
During a data phase, these bits are the active-low byte enables for data bits 64:32.
Otherwise, these bits are 3-stated.
Request 64-Bit Transfer. This active-low signal is asserted by the current bus
req64n
I/O
Master to indicate that it desires to transfer data using 64 bits. The signal req64n
has the same meaning as framen for 32-bit transfers.
Acknowledge 64-Bit Transfer. The Target drives this signal low to indicate that it
ack64n
I/O
has decoded its own address as the Target of the current access and that it can do
64-bit transfers. The signal ack64n has the same timing as devseln in 32-bit transfers.
Upper Double-Word Parity. The even parity bit that covers ad[63:32] and
par64
I/O
c_ben[7:4]. PAR64 is valid one clock after the initial address phase when req64n is
asserted and the DAC command is indicated on c_ben[7:4]. It is also valid the
clock cycle after the second address phase of a DAC command when req64n is
asserted.
Hot Swap Function Pins
enumn
O
Active-low open drain signal that notifies the system host that the card has been
freshly inserted or is about to be extracted. The system host can then either install
(for insertion) or quiesce (for extraction) the card’s driver to adjust for the change in
system configuration.
ledn
O
Active-low open-drain signal that drives a blue LED, indicating that removal of the
card is permitted. This signal is asserted low whenever the LED ON/OFF (LOO) bit
in the hot swap control and status register (HSSCR) is asserted high.
ejectsw
I
Active-high signal that indicates that the card’s ejector handle is unseated. This signals that the operator has freshly inserted the card, or will extract the card when the
blue LED illuminates. If not used, tie high or low.
PCI Bus Signaling Environment Voltage. This input indicates to the PCI core the
vio
I
signaling environment being employed on the PCI bus. The input is tied to the
appropriate voltage supply (either 5.0 V or 3.3 V).
20
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port
Pages 21—69 will refer to the dual-port mode of the OR3LP26B device. For quad-port mode, please refer to pages
70—122.
Embedded Core/FPGA Interface Signal Descriptions
In Table 8, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers
to a signal flowing out of the FPGA logic (into the embedded core).
Table 8. Embedded Core/FPGA Interface Signals
Symbol
I/O
Description
Data FIFO Signals
datafmfpga[63:0]
datafmfpgax[7:0]
O
datatofpga[63:0]
datatofpgax[7:0]
I
Main data bus into the master write FIFO and target read FIFO. Refer to Table 10 on
page 30 for bus usage and bit descriptions.
These signals must be synchronous to fclk.
Main data bus out of the master read FIFO and target write FIFO. Refer to Table 10
on page 30 for bus usage and bit descriptions.
These signals are synchronous to fclk.
Master General Signals
fpga_mbusyn
O
Symbol
I/O
Description
maenn
O
ma_fulln
I
mstatecntr[2:0]
I
mfifoclrn
O
Master Command/Address/Burst Length Enable. This is an active-low signal and
is used to enable registering commands, burst length, and start address into the Master address register of the PCI core. On each rising edge of the clock that this signal
is sampled low, command, burst length, and address will be registered.
This signal must be synchronous to fclk.
Master Address Register Full Flag. This active-low signal indicates that the Master
address register is full and no more addresses can be registered.
This signal is synchronous to fclk.
Internal State Counter. Used for Master reads and writes. Details of the Master state
machine operation can be found in tables at the end of each operation section.
This signal is synchronous to fclk.
Master FIFO Clear. This active-low signal is asserted by the FPGA Master to clear all
Master FIFOs.
This signal must be synchronous to fclk.
FPGA Master Is Busy. This signal is used in modes currently not implemented in the
core. Tie off this signal to a 1.
fpga_msyserror
FPGA Master Cycle Aborted by PCI Target. The PCI Master controller in the PCI
I
core asserts this active-high as an indication that the current cycle to the PCI bus has
been aborted. This signal is synchronous to fclk.
mcfgshiftenn
O mcfgshiftenn is an active-low signal that determines the data that is output by the PCI
pci_mcfg_stat
I
core onto signal pci_mcfg_stat:
mcfgshiftenn = 1: pci_mcfg_stat = wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
mcfgshiftenn = 0: pci_mcfg_stat = each bit below, one at a time on successive pciclk rising edges (unmasked), reset when
mcfgshiftenn = 1;
Status bits:
Data parity error detected, Target abort received, and
Master abort received.
Both signals are synchronous to fclk.
Master FIFO Address and Command Register Control Signals
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21
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 8. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Master Logic Ready. This active-high signal indicates that the Master logic
interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Master FIFO clears.
This signal is synchronous to fclk.
Master
Command Code. Command code for the current Master read/write
mcmd[3:0]
O operation. Refer to Table 10 on page 30.
This signal must be synchronous to fclk.
Master Write Data FIFO Signals
mwdataenn
O Master Write FIFO Data Enable. This active-low signal enables the registering
of bus datafmfpga during Master write operations into the PCI core Master
write data FIFOs on the rising edge of the Master FIFO clock signal. The signal
mwdataenn should not be asserted when the Master write data FIFOs are full,
or data may be lost.
This signal must be synchronous to fclk.
mwpcihold
O Master Write PCI Bus Hold. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to
fill the FIFO. The transaction will begin when mwpcihold is deasserted or the
FIFO becomes full. When asserted, mwpcihold must be held low for a minimum of two pciclk periods.
This signal must be synchronous to pcilk.
Master Write Data FIFO Full Flag. This active-low signal indicates that the
mw_fulln
I
Master write data FIFOs are full.
This signal is synchronous to fclk.
Master Write Data FIFO Almost Full Flag. This active-low signal indicates that
mw_afulln
I
only four more empty locations remain in the Master write data FIFOs.
This signal is synchronous to fclk.
Master
Write Data FIFO Empty Flag. This active-low signal indicates that the
mw_emptyn
I
Master write data FIFO is empty. Refer to Master write description on signal
usage.
This signal is synchronous to pciclk.
mwlastcycn
O Master Write Last Data Cycle. This active-low signal has two functions:
a. It is asserted low to indicate that the accompanying 32/64 bits of Master read
or write address information is the final portion being sent. It can also be
asserted prior to any address portion being sent, indicating that the previous
address is to be used.
b. It is asserted low to indicate that the accompanying master write data is the
final data for this operation. When more than one cycle is required to transfer
a complete data word, this signal is only valid on the last cycle.
This signal must be synchronous to fclk.
Master Read Data FIFO Signals
mrdataenn
O Master Read FIFO Data Output Enable. This active-low signal enables the
data from the PCI core Master read data FIFOs onto bus datatofpga during
Master read operations on the rising edge of the Master FIFO clock signal. Valid
data will be read from the FIFO whenever it is not empty.
This signal must be synchronous to fclk.
Master
Read Data FIFO Empty. This active-low signal indicates that the Masmr_emptyn
I
ter read data FIFOs of the PCI core are empty.
This signal is synchronous to fclk.
m_ready
22
I
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 8. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
mr_aemptyn
I
mr_fulln
I
fpga_mstopburstn
O
mrlastcycn
I
Master Read Data FIFO Almost Empty. This active-low signal indicates that
only four more data locations are available to be read from the Master read data
FIFOs of the PCI core.
This signal is synchronous to fclk.
Master Read Data FIFO Full Flag. This active-low signal indicates that the
Master read data FIFO is full. Refer to Master read description on signal usage.
This signal is synchronous to pciclk.
Stop Burst Reads. This active-low signal is used by the FPGA Master to terminate burst reads before completion. When asserted, it must stay asserted for a
minimum of two pciclk periods. When asserted, fpga_mstopburstn must stay
asserted until ma_fulln goes inactive (high).
This signal must be synchronous to pciclk.
Master Read Last Data Cycle. This active-low signal is asserted to indicate
that the accompanying Master read data is the final data for this operation.
When more than one cycle is required to transfer a complete data word, this
signal is only valid on the last cycle (1 fclk period).
This signal is synchronous to fclk.
Target General Signals
disctimerexpn
I
fpga_tabort
O
fpga_tretryn
O
deltrn
O
tcfgshiftenn
pci_tcfg_stat
O
I
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Discard Timer Expired. This active-low signal, when asserted, indicates that
the discard timer has expired and the core will now treat the retried delayed
transaction as a new transaction. The discard timer is a 15-bit counter which
starts its count when a delayed transaction is started.
This signal is synchronous to fclk.
Target Abort. This active-high signal is asserted by the FPGA Target application to abort all future PCI cycles. Once asserted, this signal needs to remain
asserted for a minimum of two pciclk cycles.
This signal must be synchronous to pciclk.
Assert Retry. This active-low signal is asserted by an FPGA Target to the PCI
core to send a retry to the PCI bus. Once asserted, this signal needs to remain
asserted for a minimum of two pciclk cycles.
This signal must be synchronous to pciclk.
Target Delayed Transaction. Used for Target I/O write (page 50) and Target
read operations (page 59). Target memory writes are always posted. Once
asserted, this signal needs to remain asserted for a minimum of two pciclk
cycles.
This signal must be synchronous to pciclk.
tcfgshiftenn is an active-low signal that determines the data that is output by
the PCI core onto signal pci_tcfg_stat:
tcfgshiftenn = 1: pci_tcfg_stat = wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
tcfgshiftenn = 0: pci_tcfg_stat = each bit below, one at a time on successive pciclk rising edges (unmasked), reset when
tcfgshiftenn = 1;
Status bits:
Target abort signaled, system error signaled,
and parity error detected.
Both signals are synchronous to fclk.
23
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 8. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Target FIFO Address and Command Register Control Signals
tfifoclrn
O Target FIFO Clear. This active-low signal is asserted by the FPGA Target to
clear all Target FIFOs.
This signal must be synchronous to fclk.
Target Request from PCI. This active-low signal is synchronous to the Target
treqn
I
FIFO clock signal. The PCI core asserts treqn as an indication to the Target
that a transfer request (either read or write) is pending to the target. As long as
there are valid target addresses present in the address FIFO, the treqn signal
will continue to be active.
This signal is synchronous to fclk.
Target
Logic Ready. This active-high signal indicates that the Target logic intert_ready
I
facing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Target FIFO clears.
This signal is synchronous to fclk.
taenn
O Target Address and Command Register Output Enable. This active-low signal enables PCI addresses to be read from the Target address register of the
PCI core, and PCI commands to be read from the Target command register.
The PCI core will only execute enough address cycles to transfer the address
within the matched page (higher-order bits are not stripped).
This signal must be synchronous to fclk.
Target Command Code. This bus provides the command code for a new Tartcmd[3:0]
I
get operation, and is valid when the FPGA senses treqn active-low.
Because it is synchronous to pciclk, it must be qualified with treqn.
Base Address Register Number. This bus indicates which of the six BARs
bar[2:0]
I
matched the address for the current Target operation, and is valid when the
FPGA senses treqn active-low. The three 64-bit BARs are designated as numbers 0, 2, and 4.
Because it is synchronous to pciclk, it must be qualified with treqn.
Internal State Counter. Used for target reads and writes. Details of the target
tstatecntr[2:0]
I
state machine operation can be found in tables at the end of each operation
section.
This signal is synchronous to fclk.
Target Write Data FIFO Signals
twdataenn
O Target Write FIFO Data Enable. This active-low signal enables data from the
PCI core Target write data FIFOs onto bus datatofpga during Target write operations on the rising edge of the Target FIFO clock signal. Valid data will be read
from the FIFO whenever it is not empty.
This signal must be synchronous to fclk.
Target Write FIFO Empty. This signal active indicates that the Target write
tw_emptyn
I
FIFO is empty.
This signal is synchronous to fclk.
Target Write FIFO Almost Empty. This active-low signal indicates that only
tw_aemptyn
I
four more empty locations are available in the Target write FIFOs.
This signal is synchronous to fclk.
Target Write Data FIFO Full Flag. This active-low signal indicates that the tartw_fulln
I
get write data FIFO is full. Refer to target write description on signal usage.
This signal is synchronous to pciclk.
24
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 8. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Target Write Last Data Cycle. This active-low signal has two functions:
a. It is asserted low to indicate that the accompanying 32/64 bits of Target read or
write address information is the final portion being sent. It can also be asserted
prior to any address portion being sent, indicating that the previous address is
to be used.
b. It is asserted low to indicate that the accompanying Target write data is the final
data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle.
This signal is synchronous to fclk.
Target Read Data FIFO Signals
twburstpendn
O Target Write Burst Data Availability Pending Flag. This active-low signal
directs the PCI core not to immediately disconnect when the Target write FIFO
becomes full, but rather to insert PCI bus wait-states (up to the maximum allowed,
and then disconnect). Once asserted, this signal needs to remain asserted for a
minimum of two pciclk periods.
This signal must be synchronous to pciclk.
trdataenn
O Target Read FIFO Data Enable. This active-low signal enables the registering of
bus datafmfpga during Target read operations into the PCI core Target read data
FIFOs on the rising edge of the Target FIFO clock signal. The signal trdataenn
should not be asserted when the Target read data FIFOs are full, or data may be
lost.
This signal must be synchronous to fclk.
Target Read FIFO Full. This signal is active-low and synchronous to the rising
tr_fulln
I
edge of the Target FIFO clock signal. The PCI core asserts this signal to indicate
that the Target read FIFOs are full and that no more data can be clocked in.
This signal is synchronous to fclk.
Target Read FIFO Almost Full. This active-low signal indicates that the Target
tr_afulln
I
read FIFO has only four more empty locations available in the FIFOs.
This signal is synchronous to fclk.
Target Read Data FIFO Empty Flag. This active-low signal indicates that the tartr_emptyn
I
get read data FIFO is empty. Refer to target read description on signal usage.
This signal is synchronous to pciclk.
trpcihold
O Target Read PCI Bus Hold. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to fill
the FIFO. The transaction will begin when trpcihold is deasserted or the FIFO
becomes full. Once asserted, this signal needs to remain asserted for a minimum
of two pciclk periods.
This signal must be synchronous to pciclk.
Target Read Last Data Cycle. This active-low signal is asserted to indicate that
trlastcycn
I
the accompanying Target read data is the final data for this operation. When more
than one cycle is required to transfer a complete data word, this signal is only
valid on the last cycle. During a read burst, trlastcycn may remain inactive for
longer than it is required to complete the data transfer. If this occurs, the FPGA
Target should continue to write data into the Target read FIFOs unless the incremented address crosses the address decode space of the FPGA Target. The
address should be incremented by a double word as long as trlastcycn is inactive.
This signal is synchronous to fclk.
twlastcycn
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25
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 8. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
trburstpendn
O
Target Read Burst Data Availability Pending Flag. This active-low signal
directs the PCI core not to immediately disconnect when the Target read FIFO
becomes empty, but rather to insert PCI bus wait-states (up to the maximum
allowed, and then disconnect). Once asserted, this signal needs to remain
asserted for a minimum of two pciclk periods.
This signal must be synchronous to pciclk.
Miscellaneous Signals
pci_intan
O
fclk1
fclk2
O
O
pciclk
I
pci_rstn
I
fpga_syserror
O
pci_64bit
I
fifo_sel
O
PCI Interrupt Request. This active-low signal is used to generate a PCI bus
interrupt and is forwarded by the PCI core as intan onto the PCI bus. Once
asserted, this signal needs to remain asserted for a minimum of two pciclk
cycles.
This signal must be synchronous to pciclk.
FPGA Clock 1 and 2. Clocks for use by the PCI core for Master and Target
FIFOs. When the PCI clock domain extends into the FPGA, the FPGA may
reroute the PCI clock back into fclk1 or fclk2. External or user-defined clocks may
also be used. The signals fclk1 and fclk2 must be the same clock in dual-port
mode.
PCI Clock. The signal pciclk is synchronous to clk and may be used by the
FPGA logic.
PCI Reset for Use by the FPGA Logic. This active-low signal indicates that a
PCI bus reset was received from the PCI bus (rstn).
System Error. This active-high signal is used by the FPGA to generate a system
error on the PCI bus. This is passed to the PCI bus as serrn.
This signal must be synchronous to pciclk.
PCI Bus in 64-Bit Mode. This active-high signal indicates that the PCI core
detected that it is connected as a 64-bit agent to the PCI bus. This is the result of
detecting PCI signal req64n as active (low) on the inactive-going (rising) edge of
PCI signal rstn. Note that this does not imply that any particular transaction is
64-bit, since each transaction is individually negotiated using PCI signals req64n
and ack64n.
This signal is synchronous to pciclk.
FIFO Select. An active-high signal that is valid in the dual-port modes to select
either Master read data (fifo_sel = 0) or Target write data (fifo_sel = 1).
This signal must be synchronous to fclk.
26
Description
Lucent
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Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Embedded Core/FPGA Interface Signal Locations
Table 9 lists the physical locations of all signals on the PCI core/FPGA interface. Separate names are provided for
dual-port and quad-port bus signals, since their functionality is port mode dependent.
Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB1A
ASB1B
ASB1C
ASB1D
ASB2A
ASB2B
ASB2C
ASB2D
ASB3A
ASB3B
ASB3C
ASB3D
ASB4A
ASB4B
ASB4C
ASB4D
ASB5A
ASB5B
ASB5C
ASB5D
ASB6A
ASB6B
ASB6C
ASB6D
ASB7A
ASB7B
ASB7C
ASB7D
ASB8A
ASB8B
ASB8C
ASB8D
ASB9A
ASB9B
ASB9C
ASB9D
CKTOASB9
pci_rstn
pci_64bit
(unused)
(unused)
datatofpga31
datatofpga30
datatofpga29
datatofpga28
datatofpga27
datatofpga26
datatofpga25
datatofpga24
datatofpga23
datatofpga22
datatofpga21
datatofpga20
datatofpga19
datatofpga18
datatofpga17
datatofpga16
datatofpgax3
datatofpgax2
datatofpgax1
datatofpgax0
datatofpga15
datatofpga14
datatofpga13
datatofpga12
datatofpga11
datatofpga10
datatofpga9
datatofpga8
datatofpga7
datatofpga6
datatofpga5
datatofpga4
(unused)
pci_intan
(unused)
fpga_syserror
fpga_mbusyn
datafmfpga31
datafmfpga30
datafmfpga29
datafmfpga28
datafmfpga27
datafmfpga26
datafmfpga25
datafmfpga24
datafmfpga23
datafmfpga22
datafmfpga21
datafmfpga20
datafmfpga19
datafmfpga18
datafmfpga17
datafmfpga16
datafmfpgax3
datafmfpgax2
datafmfpgax1
datafmfpgax0
datafmfpga15
datafmfpga14
datafmfpga13
datafmfpga12
datafmfpga11
datafmfpga10
datafmfpga9
datafmfpga8
datafmfpga7
datafmfpga6
datafmfpga5
datafmfpga4
fclk1
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27
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations (continued)
28
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB10A
ASB10B
ASB10C
ASB10D
ASB11A
ASB11B
ASB11C
ASB11D
ASB12A
ASB12B
ASB12C
ASB12D
ASB13A
ASB13B
ASB13C
ASB13D
ASB14A
ASB14B
ASB14C
ASB14D
CKFMASB14
ASB15A
ASB15B
ASB15C
ASB15D
ASB16A
ASB16B
ASB16C
ASB16D
ASB17A
ASB17B
ASB17C
ASB17D
ASB18A
ASB18B
ASB18C
ASB18D
ASB19A
ASB19B
ASB19C
ASB19D
CKTOASB19
ASB20A
datatofpga3
datatofpga2
datatofpga1
datatofpga0
tstatecntr0
tstatecntr1
tstatecntr2
pci_tcfg_stat
tcmd0
tcmd1
tcmd2
tcmd3
bar0
bar1
bar2
disctimerexpn
treqn
twlastcycn
tw_emptyn
tw_aemptyn
pciclk
t_ready
trlastcycn
tr_fulln
tr_afulln
tw_fulln
tr_emptyn
mw_emptyn
mr_fulln
ma_fulln
mw_fulln
mw_afulln
m_ready
mrlastcycn
mr_emptyn
mr_aemptyn
fpga_msyserror
datatofpga32
datatofpga33
datatofpga34
datatofpga35
(unused)
datatofpga36
datafmfpga3
datafmfpga2
datafmfpga1
datafmfpga0
(unused)
(unused)
(unused)
tcfgshiftenn
(unused)
(unused)
(unused)
twburstpendn
trburstpendn
fpga_tabort
fpga_tretryn
deltrn
taenn
twdataenn
fifo_sel
(unused)
(unused)
tfifoclrN
trdataenn
(unused)
(unused)
trpcihold
mwpcihold
fpga_mstopburstn
(unused)
maenn
mwdataenn
mwlastcycn
mrdataenn
mcmd0
mcmd1
mcmd2
mcmd3
datafmfpga32
datafmfpga33
datafmfpga34
datafmfpga35
fclk2
datafmfpga36
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 9. OR3LP26B FPGA/PCI Core Interface Signal Locations (continued)
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB20B
ASB20C
ASB20D
ASB21A
ASB21B
ASB21C
ASB21D
ASB22A
ASB22B
ASB22C
ASB22D
ASB23A
ASB23B
ASB23C
ASB23D
ASB24A
ASB24B
ASB24C
ASB24D
ASB25A
ASB25B
ASB25C
ASB25D
ASB26A
ASB26B
ASB26C
ASB26D
ASB27A
ASB27B
ASB27C
ASB27D
ASB28A
ASB28B
ASB28C
ASB28D
datatofpga37
datatofpga38
datatofpga39
datatofpga40
datatofpga41
datatofpga42
datatofpga43
datatofpga44
datatofpga45
datatofpga46
datatofpga47
datatofpgax4
datatofpgax5
datatofpgax6
datatofpgax7
datatofpga48
datatofpga49
datatofpga50
datatofpga51
datatofpga52
datatofpga53
datatofpga54
datatofpga55
datatofpga56
datatofpga57
datatofpga58
datatofpga59
datatofpga60
datatofpga61
datatofpga62
datatofpga63
mstatecntr0
mstatecntr1
mstatecntr2
pci_mcfg_stat
datafmfpga37
datafmfpga38
datafmfpga39
datafmfpga40
datafmfpga41
datafmfpga42
datafmfpga43
datafmfpga44
datafmfpga45
datafmfpga46
datafmfpga47
datafmfpgax4
datafmfpgax5
datafmfpgax6
datafmfpgax7
datafmfpga48
datafmfpga49
datafmfpga50
datafmfpga51
datafmfpga52
datafmfpga53
datafmfpga54
datafmfpga55
datafmfpga56
datafmfpga57
datafmfpga58
datafmfpga59
datafmfpga60
datafmfpga61
datafmfpga62
datafmfpga63
mfifoclrn
(unused)
(unused)
mcfgshiftenn
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29
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 10. Bit Definitions on FPGA/PCI Core Interface
Bits
Name
A. Dual-Port Master Write, Command and Address
datafmfpgax[7:3]
datafmfpgax[2]
datafmfpgax[1:0]
datafmfpga[63:32]
—
DA
—
A3 & A2
datafmfpga[31:0]
mcmd[3:0]
A1 & A0
mcmd
B. Dual-Port Master Write, Data
datafmfpgax[7:0]
datafmfpga[63:0]
BE7—BE0
D7—D0
datafmfpgax[7:3]
datafmfpgax[2]
datafmfpgax[1:0]
datafmfpga[63:56]
datafmfpga[55:50]
datafmfpga[49:32]
datafmfpga[31:0]
—
DA
—
mrd_benn
—
BL
A1 & A0
mcmd[3:0]
mcmd
D. Dual-Port Master Read (64-Bit Address Cycle)
—
A3 & A2
A1 & A0
—
E. Dual-Port Master Read, Data
datatofpgax[7:0]
datatofpga[63:0]
mstatecntr = 0
Unused
Dual address indicator (active-high)
Unused
Address words 3 and 2 (if DA = 1; else must set
all bits to 0s)
Address words 1 and 0
Master command opcode*
mstatecntr = 4
C. Dual-Port Master Read (Burst Length Cycle)
datafmfpgax[7:0]
datafmfpga[63:32]
datafmfpga[31:0]
mcmd[3:0]
Description
Byte enables (active-low)
Data bytes 7 to 0
mstatecntr = 0
Unused
Dual address indicator (active-high)
Unused
Byte enables (active-low)
Unused
Burst length (in Quadwords)
Address words 1 and 0 (set to all 0s if 64-bit
address required—A1 & A0 supplied in next
cycle)
Master command opcode*
mstatecntr = 1
Unused
Address words 3 and 2
Address words 1 and 0
Unused
mstatecntr = 4
—
D7—D0
Unused
Data bytes 7 to 0
* Command Codes (codes correspond to PCI bus command codes):
0000 Not Used (interrupt acknowledge not implemented)
0001 Not Used (special cycle not implemented)
0010 I/O Read
0011 I/O Write
0100 Reserved (per PCI specification)
0101 Reserved (per PCI specification)
0110 Memory Read
0111 Memory Write
1000 Reserved (per PCI specification)
1001 Reserved (per PCI specification)
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Not Used (dual address operation is indicated via separate signal)
1110 Memory Read Line
1111 Memory Write and Invalidate
30
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 10. Bit Definitions on FPGA/PCI Core Interface (continued)
Bits
Name
Description
F. Dual-Port Target Write & Read, Command and Address
datatofpgax[7:4]
datatofpgax[3]
datatofpgax[2]
datatofpgax[1:0]
datatofpga[63:32]
datatofpga[31:0]
tcmd[3:0]
—
Burst_I
DA
—
A3 & A2
A1 & A0
tcmd
tstatecntr = 0
Unused
Burst indication (active-high)
Dual address indicator (active-high)
Unused
Address words 3 and 2
Address words 1 and 0
Target command opcode*
G. Dual-Port Target Write, Data
tstatecntr = 4
datatofpgax[7:0]
datatofpga[63:0]
BE7—BE0
D7—D0
Byte enables (active-low)
Data bytes 7 to 0
H. Dual-Port Target Read, Data
tstatecntr = 4
datafmfpgax[7:0]
datafmfpga[63:0]
—
D7—D0
Unused
Data bytes 7 to 0
* Command Codes (codes correspond to PCI bus command codes):
0000 Not Used (interrupt acknowledge not implemented)
0001 Not Used (special cycle not implemented)
0010 I/O Read
0011 I/O Write
0100 Reserved (per PCI specification)
0101 Reserved (per PCI specification)
0110 Memory Read
0111 Memory Write
1000 Reserved (per PCI specification)
1001 Reserved (per PCI specification)
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Not Used (dual address operation is indicated via separate signal)
1110 Memory Read Line
1111 Memory Write and Invalidate
Table 11. Address Cycle Sequences for Various Operations
Operation
Master Write
Master Read
Target Write
Target Read
Address
Mode
Supplied
Address
New Burst
Length
Address Cycle
Sequence
(Once Only)
Data Cycle
Sequence
(Repeats)
SA
DA
SA
DA
SA
DA
SA
DA
31:0
63:0
31:0
63:0
31:0
63:0
31:0
63:0
NA
NA
C
C
NA
NA
NA
NA
A
A
NA
D
F
F
F
F
B
B
E
E
G
G
H
H
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Embedded Core Bit Stream Configurable Options
Table 12 lists all optional functionality in the PCI core that can be defined via bits in the FPGA configuration RAM.
The table also lists the settings available for each feature. Each of these options is configured using the FPSC
Design Kit software.
Table 12. PCI Core Options Settable via FPGA Configuration RAM Bits
Address in
Configuration Space
Revision ID
Class Code
Bus Master Support
Report: Data Parity Error Detected
Report: Target Abort Signaled
Report: Target Abort Received
Report: Master Abort Received
Report: System Error Signaled
Report: Parity Error Detected
(nonmaskable)
Latency Timer Initial Value
Base Address Register (BAR) Area 1
Base Address Register (BAR) Area 2
Base Address Register (BAR) Area 3
Subsystem Vendor ID
Subsystem ID
Minimum Grant (Min_Gnt)
Maximum Latency (Max_Lat)
Port Mode
08
Any 8-bit value.
09—0B
Any 24-bit value.
Command register bit 2 Four options.
■ Initially disabled, read-only.
■ Initially disabled, read/write.
■ Initially enabled, read-only.
Status register bit 8
Include or exclude in decode for pci_mcfg_stat.
Status register bit 11
Include or exclude in decode for pci_tcfg_stat.
Status register bit 12
Include or exclude in decode for pci_mcfg_stat.
Status register bit 13
Include or exclude in decode for pci_mcfg_stat.
Status register bit 14
Include or exclude in decode for pci_tcfg_stat.
Status register bit 15
Include or exclude in decode for pci_tcfg_stat.
OD
10—17
18—1F
20—27
2C—2D
2E—2F
3E
3F
Target Address Comparator
—
—
—
—
—
Target Maximum Intial Latency
—
I/O Mode
Master FIFO Interface Clock
Target FIFO Interface Clock
32
Optional Settings
Any 8-bit value divisible by 8.
■ One or two 32-bit BARs or one 64-bit BAR, or none
(i.e., unprogrammed).
■ If 64-bit BAR, must be memory; page size can be from
24 to 264 bytes.
■ 32-bit BARs can be memory or I/O.
2
32 bytes.
■ If 32-bit I/O BAR, page size can be from 2 to 2
20 or 232
■ If 32-bit memory BAR, address space can be 2
bytes, page size can be 24 to the maximum (220 or 232)
bytes.
■ If memory, can be prefetchable or nonprefetchable.
Same as for BAR area 1.
Same as for BAR area 1.
Any 16-bit value.
Any 16-bit value.
Any 8-bit value.
Any 8-bit value.
Dual port or quad port.
Fast or slew-limited PCI output buffers.
fclk1 or fclk2.
fclk1 or fclk2.
Enabled or disabled; when enabled, PCI core will not
transfer most significant byte(s) of Target address if they
match previous Target operation's address and require
additional bus cycle(s).
Normal (16) or extended (32); note that only normal
latency complies with PCI Specification. Extended latency
may be specified in proprietary systems where bandwidth
requirements override fairness considerations.
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Dual Port (continued)
Understanding FIFO Packing/Unpacking
In dual-port mode, the interface from the core to the FPGA is always 64 bits wide. However, data packing through
the FIFOs will differ depending on whether the transfers on the PCI bus are 32 bits or 64 bits. The following discussions pertain to target write or master read operations where data will be read from the FIFOs.
■
64-bit Transfers: Since the FIFOs are always in 64-bit mode, the data will flow through without any repacking.
Keep in mind that 64-bit transfers must start on a Quadword aligned address (AD2 = 0).
■
32-bit Transfers: The FIFOs are always in 64-bit mode, so depending upon what address the transfer begins,
the data coming out of the FIFOs will be packed differently. The following two cases provide examples with different starting addresses and word counts. Case 1 is also true for Master read operations.
Case 1: Target write burst, 32-bit. Even 32-bit starting address, and even number of 32-bit words transferred on the
PCI bus.
Table 13. Dual-Port FIFO Packing/Unpacking, Case 1, PCI Side
PCI Address
PCI Data
PCI Byte Enables
(Active-Low)
00001000
(00001004)
(00001008)
(0000100C)
(00001010)
(00001014)
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
32-bit Word6
0000
0000
0000
0000
0000
0000
Table 14. Dual-Port FIFO Packing/Unpacking, Case 1, FPGA Side
Master Write FIFO Slot
FIFO Data Bits 63:32
FIFO Data Bits 31:0
datatofpga[63:0]
1
2
3
32-bit Word2
32-bit Word4
32-bit Word6
32-bit Word1
32-bit Word3
32-bit Word5
FIFO Byte Enables
(Active-Low)
datatofpgax[7:0]
00000000
00000000
00000000
Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.
Dummy words are unknown data words in the FIFOs with their byte enables disabled.
Case 2: Target write burst, 32-bit. Even 32-bit starting address, odd number of 32-bit words transferred on the PCI
bus.
Table 15. Dual-Port FIFO Packing/Unpacking, Case 2, PCI Side
PCI Address
PCI Data
PCI Byte Enables
(Active-Low)
00001000
(00001004)
(00001008)
(0000100C)
(00001010)
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
0000
0000
0000
0000
0000
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 16. Dual-Port FIFO Packing/Unpacking, Case 2, FPGA Side
Master Write FIFO Slot
FIFO Data Bits 63:32
FIFO Data Bits 31:0
datatofpga[63:0]
1
2
3
32-bit Word2
32-bit Word4
Dummy Word
32-bit Word1
32-bit Word3
32-bit Word5
FIFO Byte Enables
(Active-Low)
datatofpgax[7:0]
00000000
00000000
FFFF0000
Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.
Dummy words are unknown data words in the FIFOs with their byte enables disabled.
Embedded Core/FPGA Interface Operation
Target Address Holding Register and BAR Number Indicator
The PCI core provides two features that reduce overhead on setup of Target transfers.
First, the PCI core’s Target control logic detects the page size of the base address register (BAR) that matched the
current PCI address, and only transfers the address bytes necessary to send the page address, and not the virtual
address of the page, to the FPGA application. The bar bus is synchronous to pciclk, so it must be qualified with
treqn.
Second, the PCI core utilizes an optional address holding register so that only the least significant portion of the
address that is different from the previous address is sent to the FPGA application. Utilization of this feature usually
reduces the amount of address that must be transferred, but may require that the FPGA application build a copy of
the holding register in order to reconstruct the address. For this reason, this feature is optional and can be disabled
via a bit in the FPGA configuration manager.
Interrupt Request and System Error Generation
Two additional signals are available on the user side interface to request an interrupt on intan (pci_intan) and force
a system error on the PCI serrn pin (fpga_syserror). The pci_intan signal may be asserted low at any time. It is
not directly tied to any bus cycle. The fpga_syserror, as well, may be asserted high at any time. The serrn signal
will be subsequently asserted low during the next PCI transaction to this device. In generating pci_intan and
fpga_syserror, keep in mind that both signals need to be synchronous to pciclk.
Working in 32-bit and 64-bit Modes
The OR3LP26B works equally well in 32-bit and 64-bit PCI systems. In a 64-bit system, it is required that, during
reset, the host assert req64n low indicating that the bus width is 64 bits. The core will evaluate this signal at reset,
and automatically configure itself in either 32-bit or 64-bit mode. When configured in 32-bit mode, the core will
3-state all upper PCI bus pins and apply a weak pull-up.
32-Bit Transfers in a 64-bit System
Although designed as a 64-bit interface, the OR3LP26B also works efficiently in 32-bit mode. For single 32-bit
transfers, the core will perform a 32-bit PCI transfer. For burst transactions, the core will attempt 64-bit transfers,
and then back down to 32-bit mode if ack64n was not received. In general, the core will perform the PCI bus transaction that is most efficient on the bus.
34
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Dual Port (continued)
Embedded Core/FPGA Interface Operation Summary
The following sections describe the FIFO bus operation, which is the interface between the embedded core and the
FPGA logic. Several configurations are possible for the FIFO bus, and the signal definitions can change for different modes. Tables are provided to define the modes, the signal definitions, and the states of each operation for
each mode.
Table 17 is an index to the state tables and timing figures provided for each of the operational modes of the FPGA
interface to the PCI core. Each of these operations is detailed on the pages shown in the table.
Table 17. Index to State Sequence Tables
Master/
Target
PCI Bus
Mode
Transaction Type
Master
Write
Config, Memory, I/O
Read
Config, Memory, I/O
Write
Config
I/O
Memory, I/O
Memory
Config
I/O
Target
Read
Memory
Single/Burst and
Delayed/Not Delayed
PCI Bus Timing
Figure Number
Nonburst
Burst
Nonburst
Burst
Nonburst
Delayed
Nonburst, Not Delayed
Burst
Nonburst
Delayed
Not Delayed
Nonburst
Nonburst Delayed
Burst
Burst Delayed
Figure 3
Figure 5
Figure 7
Figure 9
Figure 10
Figure 11
Figure 12
Figure 14
Figure 16
Figure 17
Figure 18
Figure 21
Figure 19
Figure 24
Figure 22
State Table
Table 18
Table 19*
Table 20†
Table 21
FPGA Bus
Timing Figure
Number
Figure 2
Figure 4
Figure 6
Figure 8
‡
Figure 13
Figure 15
Table 22
‡
Figure 20
Figure 23
* 64-bit address supplied.
† 32-bit address supplied.
‡ The FPGA interface does not participate in Target configuration operations.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Dual
Port (continued)
Master (FPGA Initiated) Write
Operation Setup
In order to initiate a PCI Master write operation, the
FPGA application must supply the required information
in the specific order prescribed in Table 18. A master
command word and address must be accompanied by
assertion of the enable maenn. The definition of the
Master command word is shown in Table 10. The
FPGA application can use the value returned on bus
mstatecntr, the Master write counter’s present value,
to determine the counter’s next state, using the state
diagram for the particular operation being executed.
The counter’s next state must be determined because
the FPGA application must supply the data to the PCI
core that corresponds to the counter value being sent
from the core to the FPGA.
Data Sheet
March 2000
The FPGA application begins supplying the write data
by deasserting maenn and asserting mwdataenn. On
every cycle that mwdataenn is asserted, the PCI core
clocks data and its associated byte enables into the
Master write FIFO (64 deep by 36 bits wide in 32-bit
PCI mode; 32 deep by 72 bits wide in 64-bit PCI mode)
via bus datafmfpga.
FIFO Full/Almost Full
When the Master write FIFO contains four or fewer
empty locations, the PCI core asserts mw_afulln, the
almost full indicator. This allows some latency to exist
in the FPGA’s response without risking overfilling the
FIFO. When all locations in the Master write FIFO are
full, the PCI core asserts mw_fulln, the FIFO full indicator. Since data can be simultaneously written to and
read from the Master write FIFO, both mw_afulln and
mw_fulln can change states in either direction multiple
times in the course of a burst transfer.
FIFO Empty
Master State Counter
The PCI core provides a state counter,
mstatecntr[2:0], that informs the FPGA of the current
state of the PCI core's Master state counter. This state
counter determines what data is currently being provided by the PCI core or expected from the FPGA
application. This state counter transitions from one
state to another in a predictable fashion, and thus, it is
not strictly necessary to transmit its value to the FPGA.
Nonetheless, the value on bus mstatecntr can be used
to minimize FPGA logic or verify proper operation.
The data provided by the PCI core to the FPGA application on bus datatofpga is accompanied by a value
on bus mstatecntr. This value can be directly used by
the FPGA application to determine the proper use of
that data. This eliminates the need for logic in the
FPGA to duplicate this state counters in this case.
The data required from the FPGA application by the
PCI core on bus datafmfpga is also defined by the
value on bus mstatecntr. However, the state counter
value is being sent to the FPGA in the same cycle that
the data must be sent from the FPGA. Therefore, the
FPGA application must build its own copy of the state
counter value in this case. The value provided by the
PCI core can be used as the previous value, or it can
be used to verify the proper operation of the FPGA
application's logic.
In addition to the full and almost full signals that report
when the Master write FIFO is currently unable to
receive data from the FPGA application, the PCI core
also provides the FIFO's empty signal. During a master
write burst transaction, the master write FIFO may go
empty, especially if the user side application is slow at
filling the FIFO. When this condition occurs, the master
will insert wait-states continuously until another word
(or the last word) is written into the FIFO and will not
terminate the transaction. On the target side, if the target is ready to accept more data, it will have trdyn
asserted which will disable it from terminating the
transaction as well. This can create a deadlock condition on the PCI bus. If the user application cannot supply any more data, and wishes to terminate the burst,
additional FPGA logic must be incorporated to detect
and accomplish the termination. The way to terminate
the transaction is to provide one last piece of data
(either real data or a dummy data word with all byte
enables disabled) along with mwlastcycn asserted.
Table 10 lists the values of the state counter mstatecntr and the appropriate accompanying data.
Data Transfer
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Data Sheet
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PCI Bus Core Detailed Description Dual
Port (continued)
Designing a Deadlock Timer
This design example is a method by which the user
application can detect the deadlock condition and terminate the burst transaction. Since the mw_emptyn
signal is on the pciclk clock domain, it must be resynchronized to the fclk domain. To accomplish this, double register mw_emptyn with fclk driven registers. The
mw_emptyn signal is fed as a clock enable and a synchronous clear to a counter, driven by fclk. The
counter's length may be designed to guarantee a certain time-out latency on the PCI bus. When the FIFO is
not empty (mw_emptyn = 1), the counter will stay
cleared. When the FIFO has been empty for an
extended period of time, the counter will count and
eventually overflow. This overflow indication can be
used to write one dummy word into the FIFO with the
byte enables disabled along with the mwlastcycn bit
asserted. The transaction will complete, and the core
will go back into an idle state.
Bursting
Instead of using a burst length, the Master write operation relies on mwlastcycn to inform the PCI core on a
cycle-by-cycle basis when additional burst data is to
follow. This allows the FPGA application to maintain
control over the length of the Master write burst for as
long as possible, but may require the FPGA application
to implement a burst length counter if needed. When
executing a burst Master write, a deasserted mwlastcycn must accompany every data element except the
last element on bus datafmfpga. The signal mwlastcycn must remain asserted throughout a nonburst
Master write, since the last data phase is the only data
phase. The maximum burst length is limited only by the
latency timer. To initiate a burst, the starting address
must be aligned to a 64-byte boundary. If ad[2] is a 1, a
single transfer will be executed.
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Embedded Master/Target PCI Interface
Termination
Once initiated, Master write operations will repeat on
the PCI bus until either one of the following occurs:
1. All data is sent.
2. An abort occurs (either Master or Target).
3. The PCI bus’s reset signal (rstn) is asserted.
If a PCI transaction is terminated with a retry or disconnect before all data has been written, the PCI core will
initiate another Master write operation, continuing from
that point.
Reset
The FPGA application can apply the PCI core’s reset
signal mfifoclrn to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The mfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the m_ready signal will go low. After the
reset signal is deasserted high, m_ready will continue
to be low for 8—10 clock periods. The FPGA application should not continue normal operation until
m_ready is asserted high.
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that control and provide status to the FPGA application. The
signal pci_mcfg_stat provides the status, and mcfgshiftenn controls what information the status line provides. The pci_mcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
mcfgshiftenn = 1. When high, pci_mcfg_stat provides the wired-OR of the three status lines. If
pci_mcfg_stat gets set to a 1, indicating an error, then
the FPGA application may set mcfgshiftenn = 0 to
determine individual status. Once low, the
pci_mcfg_stat signal will output data parity error
detected on the first clock, target abort received on the
second clock, and master abort received on the third
clock.
37
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Master Write, Nonburst Transaction
Figure 2 (FPGA bus) and Figure 3 (PCI bus) show the timing of a Master write, nonburst transaction. In Figure 2,
the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the
command word and the address on bus datafmfpga. On the next clock, maenn is deasserted and the one Quadword of data is provided on bus datafmfpga along with assertion of the Master write data enable (mwdataenn).
Since the protocol for providing start-up data is fixed for a specific operation, the FPGA application can be preprogrammed with the sequence, or can use the value of the Master state counter (mstatecntr) to assist in determination of the next required data word of information. The PCI core knows that this is a nonburst operation because the
FPGA application asserts the Master write burst signal (mwlastcycn). This completes the setup for this operation.
Execution begins on the PCI bus, as shown in Figure 3.
T0
T1
T2
T3
T4
fclk
ma_fulln
X
0
mstatecntr
4
mcmd
X
CMD
datafmfpga
X
ADRS
0
X
D0
X
maenn
mwdataenn
mwlastcycn
mw_fulln
mw_afulln
mwpcihold
5-88831(F).a
Figure 2. Master Write Single (FPGA Bus, Dual-Port)
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PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
clk
framen
ad
ADRS
DATA
c_ben
CMD
BEs
irdyn
devseln
trdyn
stopn
5-8847(F).a
Figure 3. Master Write Single (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Dual Port (continued)
Master Write, Burst Transaction
Figure 4 (FPGA bus) and Figure 5 (PCI bus) show the timing of a four Quadword Master write burst transaction.
Operation is similar to that in the previous Master write, nonburst transaction, but extra data is supplied by the
FPGA application. In Figure 4, the transaction is initiated by the FPGA application asserting Master address enable
(maenn), while providing the command word and address on bus datafmfpga. On the second through fifth clocks,
maenn is deasserted, the Master write data enable (mwdataenn) is asserted, and four Quadwords of data are
provided on bus datafmfpga. Since the protocol for providing start-up data is fixed for a specific operation, the
FPGA application can be preprogrammed with the sequence, or can use the value of the Master state counter
(mstatecntr) to assist in determination of the next required Quadword of information. The PCI core knows that this
is a burst operation because the FPGA application deasserts the Master write burst signal (mwlastcycn) during all
but the final data transfer cycle. Execution begins on the PCI bus, as shown in Figure 5. If the Master write PCI bus
hold signal (mwpcihold) is inactive, PCI bus activity will begin when the Master write FIFO goes nonempty; otherwise, the PCI bus activity will wait until all data is loaded, as in this case, or the FIFO goes full. Execution begins on
the PCI bus, as shown in Figure 5.
T0
T1
T2
T3
T4
T5
T6
T7
fclk
ma_fulln
X
0
mstatecntr
4
mcmd
X
CMD
datafmfpga
X
ADRS
0
X
D0
D1
D2
D3
X
maenn
mwdataenn
mwlastcycn
mw_fulln
mw_afulln
mwpcihold
5-8832(F).a
Figure 4. Master Write 32-Byte Burst (FPGA Bus, Dual-Port)
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Data Sheet
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PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
clk
framen
ad
ADRS
D0
D1
c_ben
CMD
BE0
BE1
D2
BE2
D3
BE3
irdyn
devseln
trdyn
stopn
5-8848(F).a
Figure 5. Master Write 32-Byte Burst (PCI Bus, 64-Bit)
Table 18. Dual-Port Master Write
mstatecntr
Next State of
mstatecntr
Description
Bus
mwlastcycn
maenn
mwdataenn
0
0
0
4
Idle
Address[63:0]
1
0
1
0
1
1
4
4 or 0
Data[63:0], be[7:0]
—
datafmfpgax[7:0]
datafmfpga[63:0]
datafmfpgax[7:0]
datafmfpga[63:0]
0*
1
0
* mwlastcycn is only 0 during the last data Quadword sent.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Dual
Port (continued)
Master (FPGA Initiated) Read
Operation Setup
In order to initiate a PCI Master read operation, the
FPGA application must supply the required information
in the specific order prescribed in Table 19 through
Table 20. The command word, burst length, and
address must be accompanied by assertion of the
enable maenn. The definition of the Master command
word was previously described in Table 10. The FPGA
application can use the value returned on bus mstatecntr, the Master state counter’s present value, to determine the counter’s next state, using the state diagram
for the particular operation being executed. The
counter’s next state must be determined because the
FPGA application must supply the data to the PCI core
that corresponds to the counter value being sent from
the core to the FPGA.
Data Transfer
The FPGA application begins receiving the read data
by deasserting maenn and asserting mrdataenn. On
every cycle that mrdataenn is asserted, the PCI core
clocks data from the Master read FIFO (64 deep by
36 bits wide in 32-bit PCI mode; 32 deep by 72 bits
wide in 64-bit PCI mode) to the FPGA application via
bus datatofpga.
FIFO Empty/Almost Empty
When the Master read FIFO contains four or fewer data
elements, the PCI core asserts mr_aemptyn, the
almost empty indicator. This allows some latency to
exist in the FPGA’s response without risking overreading the FIFO. When all locations in the Master write
FIFO are empty, the PCI core asserts mr_empty, the
FIFO empty indicator. Since data can be simultaneously written to and read from the Master read FIFO,
both mr_aemptyn and mr_emptyn can change states
in either direction multiple times in the course of a burst
data transfer.
FIFO Full
In addition to the empty and almost empty signals that
report when the Master read FIFO is currently unable
to supply data to the FPGA application, the PCI core
also provides the FIFO's full signal. During a master
read burst transaction, the master read FIFO may go
full, especially if the user side application is slow at
unloading the FIFO. When this condition occurs, the
42
Data Sheet
March 2000
master will insert wait-states continuously until another
word is read from the FIFO, or the word count is
exhausted. On the target side, if the target is ready to
send more data, it will have trdyn asserted which will
disable it from terminating the transaction as well. This
can create a deadlock condition on the PCI bus. If the
user application cannot unload any more data, and
wishes to terminate the burst, additional FPGA logic
must be incorporated to detect and accomplish the termination. Two operations must occur to terminate the
current transaction. First, the fpga_mstopburstn signal must be asserted indicating to the core the master
request to terminate. Second, one additional word of
data must be read from the FIFO (only if the FIFO is
full). The signal fpga_mstopburstn needs to stay
asserted low until the ma_fulln flag is asserted low
indicating that the transaction has been terminated and
cleared.
Designing a Deadlock Timer
This design example is a method by which the user
application can detect this condition and terminate the
burst transaction. Since the mr_fulln and
fpga_mstopburstn signals are on the pciclk clock
domain, the deadlock counter will run on the pciclk
clock. The mr_fulln signal is fed as a clock enable and
a synchronous clear to a counter, driven by pciclk. The
counter's length may be designed to guarantee a certain time-out latency on the PCI bus. When the FIFO is
not full (mr_fulln = 1), the counter will stay cleared.
When the FIFO has been full for an extended period of
time, the counter will count and eventually overflow.
This overflow indication can be used to set the
fpga_mstopburstn signal indicating a request to stop
the burst. The overflow signal is then detected and synchronized onto the fclk domain to be used to read one
additional word from the FIFO. The transaction will
complete, and the core will go back into an idle state.
Bursting
The PCI core uses the burst count supplied during
operation setup to determine the Master read operation’s burst length (unlike the Master write, which uses
signal mwlastcycn). The burst length of 18 bits allows
bursts of up to 218–1 quad words to be specified. To initiate a burst, the starting address must be aligned to a
64-byte boundary, and all of the byte enables must be
enabled. If ad[2] is a 1, a single transfer will executed.
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Data Sheet
March 2000
PCI Bus Core Detailed Description Dual
Port (continued)
Master Read Byte Enables
During master reads, byte enables are always supplied
by the Master to the Target, even though on reads the
data is flowing in the opposite direction. Thus, the byte
enables cannot be buffered in a FIFO alongside the
corresponding data. Also, the byte enables must be
presented on the bus by the Master at the same time
that the data is being presented on the bus by the Target (unless the Target uses trdyn to insert wait-states),
and so the data provided by the Target cannot depend
on the byte enables (once again, without wait-states).
Termination
Once initiated, Master read operations will repeat on
the PCI bus until either one of the following occurs:
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that control and provide status to the FPGA application. The
signal pci_mcfg_stat provides the status, and mcfgshiftenn controls what information the status line provides. The pci_mcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
mcfgshiftenn = 1. When high, pci_mcfg_stat provides the wired-OR of the three status lines. If
pci_mcfg_stat gets set to a 1, indicating an error, then
the FPGA application may set mcfgshiftenn = 0 to
determine individual status. Once low, the
pci_mcfg_stat signal will output data parity error
detected on the first clock, target abort received on the
second clock, and master abort received on the third
clock.
1. All data is received.
2. An abort occurs (either Master or Target).
3. The fpga_mstopburstn signal is asserted.
4. The PCI bus’ reset signal (rstn) is asserted.
If a PCI transaction is terminated with a retry or disconnect before all data has been received, the PCI core
will initiate another Master read operation, continuing
from that point.
Reset
The FPGA application can apply the PCI core’s reset
signal mfifoclrn to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The mfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the m_ready signal will go low. After the
reset signal is deasserted high, m_ready will continue
to be low for 8—10 clock periods. The FPGA application should not continue normal operation until
m_ready is asserted high.
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43
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Master Read, Nonburst Transaction
Figure 6 (FPGA bus) and Figure 7 (PCI bus) show the timing of a single Quadword Master read. In Figure 6, the
transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the
command, burst length, and lower DWORD address on bus datafmfpga. On the next clock, the FPGA application
provides the upper DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn
are deasserted. PCI bus activity now begins as shown in Figure 7. Once data is transferred on the PCI bus and
mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and one Quadword of data is transferred on bus datatofpga.
T0
T1
T2
T3
T4
TN
TN+1
TN+2
TN+3
fclk
ma_fulln
X
mstatecntr
0
1
mcmd
X
CMD
datafmfpga
X
BRST
datatofpga
X
4
4
X
ADRS
0
X
X
X
X
DATA
maenn
mrdataenn
mwlastcycn
mrlastcycn
mr_emptyn
mr_aemptyn
5-8833(F).a
Figure 6. Master Read Single (FPGA Bus, Dual-Port, Specified Burst Length, 64-Bit Address)
44
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
clk
framen
ad
c_ben
ADRS
CMD
DATA
BEs
irdyn
devseln
trdyn
stopn
5-8849(F).a
Figure 7. Master Read Single (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Master Read, Burst Transaction
Figure 8 (FPGA bus dual port) and Figure 9 (PCI bus) show the timing of a four Quadword Master read burst. Operation is similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA
application. In Figure 8, the transaction is initiated by the FPGA application asserting Master address enable
(maenn), while providing the command, burst length, and lower DWORD address on bus datafmfpga. On the next
clock, the FPGA application provides the upper DWORD address and asserts mwlastcycn. On the third cycle,
both maenn and mwlastcycn are deasserted. PCI bus activity now begins as shown in Figure 9. Once data is
transferred on the PCI bus and mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and four
Quadwords of data are transferred on bus datatofpga.
T0
T1
T2
T3
T4
TN
TN+1
TN+2
TN+3
TN+4
TN+5
TN+6
fclk
ma_fulln
X
0
mstatecntr
1
mcmd
X
CMD
datafmfpga
X
BRST
datatofpga
X
4
4
X
ADRS
0
X
X
X
X
D0
D1
D2
D3
X
maenn
mrdataenn
mwlastcycn
mrlastcycn
mr_emptyn
mr_aemptyn
5-8834(F).a
Figure 8. Master Read 32-Byte Burst (FPGA Bus, Dual-Port, Burst Length, and 64-Bit Address)
46
Lucent
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
clk
framen
ad
ADRS
c_ben
CMD
D0
BE0
D1
BE1
D2
BE2
D3
BE3
irdyn
trdyn
stopn
5-8850(F).a
Figure 9. Master Read 32-Byte Burst (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Table 19. Dual-Port Master Read, 64-Bit Address Supplied
mstatecntr
Next State
of
mstatecntr
0
0
0
1
1
4
4
4 or 0
Description
Bus
maenn
mwlastcycn
mrlastcycn
mrdataenn
Idle
BE[7:0], Burst
Length
Address[63:0]
Data[63:0]
—
datafmfpgax[7:0]
datafmfpga[63:0]
datafmfpga[63:0]
datatofpga[63:0]
1
0
1
1
1
1
1
1
0
1
0
1
1
0*
1
0
maenn
mwlastcycn
mrlastcycn
mrdataenn
1
0
1
0
1
1
1
1
1
1
0*
0
* mrlastcycn is 0 during the last Quadword transferred.
Table 20. Dual-Port Master Read, 32-Bit Address Supplied
mstatecntr
Next State
of
mstatecntr
0
0
0
4
4
4 or 0
Description
Bus
Idle
—
BE[7:0], Burst datafmfpgax[7:0]
Length,
datafmfpga[63:0]
Address[31:0]
Data[63:0]
datatofpga[63:0]
* mrlastcycn is 0 during the last Quadword transferred.
48
Lucent
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Data Sheet
March 2000
PCI Bus Core Detailed Description Dual
Port (continued)
Target (PCI Bus Initiated) Write
Operation Setup
The FPGA application waits for Target request, treqn,
from the PCI core to become active, indicating a Target
operation, either read or write. It then asserts Target
address enable, taenn, to clock out the command and
its address. Table 21 describes the specific order of
operation for a Target write transaction.
Bursts can be of any length, but will disconnect when
any of the following conditions occur:
■
tw_fulln is asserted low, and twburstpendn is deasserted high.
■
The maximum number of wait-states has been
inserted.
■
The BAR boundary has been crossed.
Target State Counter
The PCI core provides a state counter, tstatecntr[2:0],
that informs the FPGA of the current state of the PCI
core's Target state counter. This state counter determines what data is currently being provided by the PCI
core or expected from the FPGA application. This state
counter transitions from one state to another in a predictable fashion, and thus, it is not strictly necessary to
transmit its value to the FPGA. Nonetheless, the value
on bus tstatecntr can be used to minimize FPGA logic
or verify proper operation.
The data provided by the PCI core to the FPGA application on bus datatofpga is accompanied by a value
on bus tstatecntr. This value can be directly used by
the FPGA application to determine the proper use of
that data. This eliminates the need for logic in the
FPGA to duplicate these state counters in this case.
The data required from the FPGA application by the
PCI core on bus datafmfpga is also defined by the
value on bus tstatecntr. However, the state counter
value is being sent to the FPGA in the same cycle that
the data must be sent from the FPGA. Therefore, the
FPGA application must build its own copy of the state
counter value in this case. The value provided by the
PCI core can be used as the previous value, or it can
be used to verify the proper operation of the FPGA
application's logic.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Transfer
For a Target write data transfer, the FPGA application
begins receiving the supplied data by deasserting
taenn and asserting twdataenn. On every cycle that
twdataenn is asserted, the FPGA application clocks
data out of the PCI core’s Target write FIFO (32 deep
by 36 bits wide in 32-bit PCI mode; 16 deep by 72 bits
wide in 64-bit PCI mode) via bus datatofpga.
FIFO Empty/Almost Empty
Data to be written is buffered in the Target write FIFO
(32 deep by 36 bits wide in 32-bit PCI mode; 16 deep
by 72 bits wide in 64-bit PCI mode). When this FIFO
contains four or fewer data elements, the PCI core
asserts tw_aempty, the FIFO almost empty indicator.
This allows some latency to exist in the FPGA’s
response without risking overreading the FIFO. When
the PCI core has read all data out of the Target write
FIFO, the PCI core asserts tw_emptyn, the FIFO
empty indicator. Since data can be simultaneously written to and read from the Target write FIFO, both
tw_aemptyn and tw_emptyn can change states in
either direction multiple times in the course of a burst
data transfer.
FIFO Full
In addition to the empty and almost empty signals that
report when the Target write FIFO is currently unable to
supply data to the FPGA application, the PCI core also
provides the FIFO's full signal. If the FIFO does go full,
the core will do one of two things. If twburstpendn is
deasserted high, the target will disconnect. If twburstpendn is asserted low, the target will assert up to eight
wait-states and then disconnect if still full. The FIFO full
flag is not generally used in user designs. If it is, however, keep in mind that it is synchronous to pciclk.
Bursting
Signal twlastcycn tells the FPGA application whether
the current write is a burst. The FPGA application continues to unload data from the FIFO as long as twlastcycn is inactive. The bursting will continue until either
twlastcycn is received, the FIFO becomes full, or the
BAR boundary is crossed. There is no fixed maximum
transfer word count.
Table 10 lists the values of the state counter tstatecntr
and the appropriate accompanying data.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Dual
Port (continued)
Nondelayed Transactions
Target memory and I/O write operations may work in a
nondelayed transaction mode. Once the PCI core Target determines that it is the intended recipient, it
asserts devseln and trdyn and begins loading data
into the Target write FIFO. After the core accepts the
data element that fills the FIFO, the next data element
will cause a disconnect without data. The operation is
then complete on the PCI bus; even if the FPGA partially empties the Target write FIFO, no Target write
transaction, even a continuation of the previous burst,
will be accepted until the FIFO is emptied. The next
Target write operation will be considered a new transaction.
Delayed Transactions
Target I/O write operations may also be handled as
delayed transactions by asserting deltrn. The signal
deltrn was designed to be a static signal. This signal
should be tied off high or low depending upon whether
the FPGA application wishes to run delayed transactions. When asserting deltrn low, the PCI core will execute delayed transactions for I/O writes as well as all
target reads. In delayed transaction mode, the operation is not accepted on the first request. Instead, on the
first request, the PCI core records the command,
address, and first data word (32 or 64 bits) along with
its byte enables (4 or 8 bits). The first command and
address are put in the Target address FIFO, and the
data word and byte enables are put in the Target write
FIFO. The request is terminated in a retry, and the
FPGA application is informed as usual that a Target
request is pending via the assertion of treqn. Masters
are required to repeat requests terminated in retry until
data is moved (see PCI Specification section
3.3.3.2.2). The transaction status at this time is DWR
(delayed write request—see PCI Specification section
3.3.3.3.6), and subsequent requests will be terminated
in retry. When the FPGA application reads the FIFO
and empties it, the transaction status changes to DWC
(delayed write completion), and the next Target I/O
50
Data Sheet
March 2000
write that matches the stored command, address, data,
and byte enables will be accepted with a disconnect
with data, completing the transaction and clearing the
Target address and Target write FIFOs. Internal to the
ASIC, there is also a 15-bit time-out timer (known as
the discard timer). During a delayed I/O write transaction, this counter will begin counting. If the same master does not come back within 215 – 1 pciclk's to
complete the write, this timer will expire, resetting the
target state machines and setting a user side signal
(disctimerexp = 1). From this point forward, any master performing a write (including the original master
coming back to complete the transfer) will be treated as
a new transaction. If monitoring this signal, keep in
mind that disctimerexp is synchronous to pciclk and
asserts high for one clock period.
Termination
Nondelayed write transaction completion occurs when
the last item remaining in the Target write FIFO has
been read by the FPGA application (although the
actual PCI bus transaction may have completed much
earlier). Delayed write transaction completion occurs
when the I/O write results in a disconnect with data.
The PCI core signals end of transaction to the FPGA
application by deasserting treqn.
Reset
The FPGA application can apply the PCI core’s reset
signal tfifoclrn to place the core’s target logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The tfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the t_ready signal will go low. After the reset
signal is deasserted high, t_ready will continue to be
low for 8—10 clock periods. The FPGA application
should not continue normal operation until t_ready is
asserted high.
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Data Sheet
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PCI Bus Core Detailed Description Dual
Port (continued)
Understanding and Using the pci_tcfg_stat Status
Signals
On the Target interface, there are two signals that control and provide status to the FPGA application. The
signal pci_tcfg_stat provides the status and tcfgshiftenn controls what information the status line provides. The pci_tcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
tcfgshiftenn = 1. When high, pci_tcfg_stat provides
the wired-OR of the three status lines. If pci_tcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set tcfgshiftenn = 0 to determine individual status. Once low, the pci_tcfg_stat signal will
output target abort signaled on the first clock, system
error signaled on the second clock, and parity error
detected on the third clock.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Initiating PCI Target Retries
In contrast to target abort, many applications may
require to assert PCI target retries. In general, this may
be asserted for times when the FPGA application is
temporarily busy and unavailable to service PCI
requests. The interface signal, fpga_tretryn, is used
for this purpose. From the PCI core's point of view, it
needs to know whether to perform a target retry at the
very beginning of a transaction, so it is not possible to
have a transaction started and then assert the
fpga_tretryn signal. The signal fpga_tretryn needs to
be asserted before the transaction begins, and it was
not designed to be toggled on and off from transaction
to transaction. Once an FPGA application determines
that it wants to apply a target retry to any master that
accesses it, it would assert the fpga_tretryn signal
low. All future target accesses will be terminated in a
retry (disconnect without data). On the FPGA application side, no activity will occur. In generating this signal,
keep in mind that this signal needs to be synchronous
to pciclk.
Initiating Target Aborts
There may be a need in an application to initiate a target abort condition on the PCI bus. In general, this is
asserted for only the most severe cases. The interface
signal, fpga_tabort, is used for this purpose. From the
PCI core's point of view, it needs to know whether to
perform a target abort at the very beginning of a transaction, so it is not possible to have a transaction
started, and then assert the fpga_tabort signal. The
signal fpga_tabort needs to be asserted before the
transaction begins, and it was not designed to be toggled on and off from transaction to transaction. Once
an FPGA application determines that it wants to apply
a target abort to any master that accesses it, it would
assert the fpga_tabort signal high. All future target
accesses will be terminated in an abort. In generating
this signal, keep in mind that this signal needs to be
synchronous to pciclk.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Write to Configuration Space Transaction
Figure 10 shows the timing on the PCI interface for a Target write to configuration space. Accesses of configuration
space occur without any involvement of the FPGA interface. All configuration space accesses are disconnected
with data on the first data word and are thus restricted from bursting. Address decode speed is medium, and the
PCI core signals that it is ready to receive the data by asserting trdyn one cycle after devseln is asserted.
T0
T1
T2
T3
T4
T5
T6
clk
framen
ad
X
ADDRESS
DATA
X
c_ben
X
CMD
BYTE ENABLES
X
idsel
X
X
irdyn
devseln
trdyn
stopn
5-8851(F).a
Figure 10. Target Configuration Write (PCI Bus, 64-Bit)
52
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Write I/O, Delayed Transaction
Figure 11 (PCI bus) and Figure 13 (FPGA bus) show the timing for a Target I/O write operation that is handled as a
delayed transaction; that is, the operation completes on the local (FPGA) bus before completing on the PCI bus.
The FPGA application indicates its desire to do this by asserting signal deltrn. In Figure 11, three transactions are
shown: the first is the initial write that latches the command, address, data, and byte enables in the PCI core. The
core's Target logic then issues a retry, obligating the remote Master to continue to issue that identical request until
data is moved. Meanwhile, the information is relayed to the FPGA interface via the address and data FIFOs, triggering the FPGA interface exchange discussed below and shown in Figure 13. All subsequent read or write
requests to memory, I/O, or configuration space will result in retries, as shown in the second transaction of Figure
11. The third transaction is the final transaction that completes the transfer of data. Although the data was actually
latched and forwarded to the FPGA from the first transaction, it is not until the FPGA acknowledges that it has
received the data, by emptying the Target write FIFO, that the PCI core acknowledges to the remote Master that it
has received the data by performing a disconnect with data. The timing on this third transaction is identical to the
timing of the first except that trdyn accompanies stopn to indicate the disconnect with data.
The timing on the FPGA interface (Figure 13) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of target request (treqn), together with the new command on bus
datatofpga. The FPGA application responds by asserting target address enable (taenn) and accepting the command and subsequent address on bus datatofpga. This is followed by deassertion of taenn, assertion of Target
write data enable (twdataenn), and the receiving of the data on bus datatofpga. Although only 32 bits of data are
being transferred, the FPGA application must accept 64 bits of data (two clock cycles) because the FIFOs are
operating in 64-bit mode.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0
Tc1
Tc2 Tc3 Tc4
Tc5
Tc6
clk
framen
ad[31:0]
X
ADRS
DATA
X
X
ADRS
DATA
X
X
ADRS
DATA
X
c/be[3:0]n
X
CMD
BEs
X
X
CMD
BEs
X
X
CMD
BEs
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
COMMAND, AND WRITE DATA LATCHED AS A
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE WRITE COMPLETION NOT RECEIVED.
TRANSACTION #3: DISCONNECTED WITH DATA
BECAUSE WRITE COMPLETION RECEIVED.
DELAYED WRITE REQUEST.
5-7372(F).a
Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Write Nonburst Transaction
Figure 12 (PCI bus) and Figure 13 (FPGA bus) show the timing on the PCI and FPGA interfaces, respectively, for a
Target memory nonburst write transaction. The timing on the PCI interface (Figure 12) is similar to that of an I/O
write except that, since bursts to memory space are allowed, the signal stopn is not asserted. The FPGA interface
timing is as shown in Figure 13, and is the same as the timing for memory and I/O write transactions.
T0
T1
T2
T3
T4
T5
clk
framen
ad
c_ben
X
ADDRESS
DATA
X
X
CMD
BYTE ENABLES
X
irdyn
devseln
trdyn
stopn
5-8854(F).a
Figure 12. Target Write Memory Single (PCI Bus, 64-Bit)
54
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
fclk
t_ready
treqn
tstatecntr
0
4
tcmd
X
CMD
datatofpga
X
ADRS
0
X
DATA
X
taenn
twdataenn
twlastcycn
tw_emptyn
tw_aemptyn
5-8835(F).a
Figure 13. Target Write Single (FPGA Bus, Dual-Port)
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55
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Write Memory Burst Transaction
Figure 14 (PCI bus) and Figure 15 (FPGA bus) show the timing for a Target memory write burst of four Quadwords.
The timing on the PCI interface (Figure 14) is typical for a medium-speed decode Target. Note that trdyn is
asserted at the earliest possible time, which is concurrent with assertion of devseln. In the example of a four Quadword burst, the FIFO is not filled, so execution continues to completion. This would also be the case for a burst of
any length when the FPGA application is capable of unloading the FIFO as fast as the PCI interface is loading it. If
the Target write FIFO becomes full, the PCI core Target will disconnect without data on the first data word it cannot
accept.
The timing on the FPGA interface (Figure 15) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of target request (treqn), together with the new command on bus
tcmd. The FPGA application responds by asserting target address enable (taenn) and accepting the address on
bus datatofpga. This is followed by deassertion of taenn, assertion of Target write data enable (twdataenn), and
the receiving of the data on bus datatofpga. The FPGA application is informed that the last 64-bit data is being
presented when Target write burst (twlastcycn) is asserted.
T0
T1
T2
T3
T4
T5
T6
T7
T8
clk
framen
ad
X
ADDRESS
D0
D1
D2
D3
c_ben
X
CMD
BE0
BE1
BE2
BE3
irdyn
devseln
trdyn
stopn
5-8855(F).a
Figure 14. Target Memory Write 32-Byte Burst (PCI Bus, 64-Bit)
56
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
fclk
t_ready
treqn
0
tstatecntr
4
tcmd
X
CMD
datatofpga
X
ADRS
0
X
D0
D1
D2
D3
X
taenn
twdataenn
twlastcycn
tw_emptyn
tw_aemptyn
5-8836(F).a
Figure 15. Target Write Memory 32-Byte Burst (FPGA Bus, Dual-Port)
Table 21. Dual-Port Target Write
tstatecntr
Next State
of
tstatecntr
Description
Bus
treqn
twlastcycn
taenn
0
0
0
4
Idle
Address[63:0]
1
0
1
0
1
0
4
4 or 0
Data[63:0], BE[7:0]
—
datatofpgax[7:0]
datatofpga[63:0]
datatofpgax[7:0]
datatofpga[63:0]
1*
0†
1
* treqn is deasserted high on the last data Quadword.
† twlastcycn is asserted low on the last data Quadword.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Dual
Port (continued)
Target (PCI Bus Initiated) Read
The Target read operation presents unique demands
on the PCI core because only in the Target read operation does the PCI core request data that is needed to
complete the transaction after the PCI transaction has
already begun on the PCI bus. Target latency rules
require that the data be acquired quickly or that the Target terminate the transaction with a retry/disconnect.
Also, once the transfer process is underway, the Target
does not know how much more data will be requested,
yet the Target must prefetch data so that it will be available if needed. Special signals and protocols are
described below to efficiently deal with these unique
demands.
Operation Setup
The FPGA application waits for Target request, treqn,
from the PCI core to be active, indicating a Target operation, either read or write. It then asserts address
enable, taenn, to clock out the command and its
address. Table 22 describes the specific order of operation for a Target read transaction.
Data Transfer
For a target read data transaction, the FPGA application begins supplying the requested data by deasserting taenn and asserting trdataenn. On every cycle that
trdataenn is asserted, the FPGA application clocks
data into the PCI core’s Target read FIFO (32 deep by
36 bits wide in 32-bit PCI mode; 16 deep by 72 bits
wide in 64-bit PCI mode) via bus datafmfpga. Since
the Target read FIFO will always be empty at the start
of a transaction, the first Target read request to a specific address will result in a retry, initiating a delayed
transaction (if signal trburstpendn is deasserted high)
or PCI bus wait-states (if signal trburstpendn is
asserted low).
Data Sheet
March 2000
FIFO Full/Almost Full
When the Target read FIFO contains four or fewer
empty locations, the PCI core asserts tr_afulln, the
almost full indicator. This allows some latency to exist
in the FPGA’s response without risking overfilling the
FIFO. When all locations in the Target read FIFO are
full, the PCI core asserts tr_fulln, the full indicator.
Since the data can be simultaneously written to and
read from the Target read FIFO, both tr_afulln and
tr_fulln can change states in either direction multiple
times in the course of a burst data transfer.
FIFO Empty
In addition to the full and almost full signals that report
when the Target read FIFO is currently unable to
receive data from the FPGA application, the PCI core
also provides the FIFO's empty signal. If the FIFO does
go empty, the core will do one of two things. If twburstpendn is deasserted high, the target will disconnect. If
twburstpendn is asserted low, the target will assert up
to eight wait-states and then disconnect if still empty.
The FIFO empty flag is not generally used in user
designs. If it is, however, keep in mind that it is synchronous to pciclk.
Bursting
Signal trlastcycn tells the FPGA application whether
the current read is a burst. One data element must be
supplied regardless of this signal’s state. The FPGA
application continues to supply data elements (contingent on the full bits) as long as trlastcycn is inactive.
Note that this may result in the discarding of unused
data elements supplied in excess of the PCI transaction’s needs. Burst transfers are done either as continuous data phases if read data continues to be available
in the read data FIFO, or as a series of transfers terminated as disconnects without data. Bursts will continue
until either trlastcycn is received, the BAR boundary is
crossed, or a 218 physical page address is crossed.
The signal trpcihold can be asserted to hold off activation of the nonempty condition. While trpcihold is
active, the Target read FIFO empty flag will not change
to the nonempty state until it is full, but then will remain
in the nonempty state until that FIFO truly becomes
empty. Use of this signal can result in more efficient utilization of PCI bus bandwidth by causing a full buffer
contents to be burst, without wait-states, whenever the
PCI bus is claimed. This is explained in the Delayed
Transactions section.
58
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Data Sheet
March 2000
PCI Bus Core Detailed Description Dual
Port (continued)
Delayed Transactions
Delayed transactions can be executed by assesting
deltrn low. When deltrn is asserted low, the PCI core
Target read logic will issue a retry whenever no Target
read operation is already pending. When this signal is
inactive-high, it will instead generate wait-states, and
continue to do so until either the FIFO becomes not
empty, when it will transmit the data, or until the maximum initial latency value (16 or 32 clock cycles) has
been reached. This signal should be inactive when
minimum latency is desired on the initial data word, at
the expense of overall PCI bus efficiency. Whereas disable delayed transactions affects the transaction’s
behavior on the initial data word, signal trburstpendn
affects behavior when the Target read FIFO empties.
When trburstpendn is inactive, a disconnect without
data results from an attempt to read from an empty
FIFO. With trburstpendn active, the PCI core will wait
for data from the FIFO by inserting wait-states (up to
the maximum subsequent latency value of 8, at which
time a disconnect without data will be generated).
Asserting trburstpendn will minimize latency for this
transaction’s data at the expense of overall PCI bus
efficiency. trburstpendn must remain static throughout
a Target read transaction.
Delayed transactions are very similar to a target retry
except that the address is actually stored in the core.
Delayed transactions are usually implemented in systems where the user side interface cannot supply the
first piece of data in 16 clock cycles. An example of this
may be that the user interface is connected to another
bus system. On a PCI target read, the user interface
must arbitrate for the user bus and get the necessary
data. Delayed transaction mode is used when the deltrn bit is asserted low. This bit is not a dynamic bit. It
must be set ahead of a transaction occurring. It is not
recommended to switch between delayed and nondelayed transactions dynamically.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
When deltrn is low, a master read request is terminated in a target retry. On the user interface side, the
address is stored in the target address FIFO, and treqn
is asserted low. All future master requests are terminated in a retry until the address is read out of the
FIFO, data is loaded into the FIFO, and the same
request comes back to complete the transaction. In
generating this signal, keep in mind that this signal
needs to be synchronous to pciclk.
Another option the designer has using delayed transactions is to use the signal trpcihold. The signal trpcihold should be used when the user side interface is
slow loading requested data, and the designer wishes
to utilize the PCI in the most efficient manner. Without
this signal, an external master will request data and
hold onto the PCI bus until either it has received it or it
gets terminated by latency timers, etc. A more efficient
method to utilize the PCI bus is to assert trpcihold,
load the FIFOs, and then deassert it. While the trpcihold signal is asserted, the core thinks that the FIFOs
stay empty even though they are slowly filling with data.
Requests from an external master are terminated in
retries. When the trpcihold signal is deasserted (or the
FIFO becomes full), the core will allow an external
master to come in, the data will be burst across the PCI
bus as fast as the master will allow, and the transaction
will end. In generating trpcihold, keep in mind that this
signal needs to be synchronous to pciclk.
Termination
Normal transaction completion occurs immediately
upon completion of the PCI bus transfer, even if extra
data remains in the Target read FIFO. When the PCI
transaction ends either normally, or as retry, disconnect, or Target abort, the PCI core signals end of transaction to the FPGA application by deasserting treqn.
When treqn deasserts, the FPGA application must
immediately deassert trdataenn.
59
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Dual
Port (continued)
Reset
The FPGA application can apply the PCI core’s reset
signal tfifoclrn to place the core’s target logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The tfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the t_ready signal will go low. After the reset
signal is deasserted high, t_ready will continue to be
low for 8—10 clock periods. The FPGA application
should not continue normal operation until t_ready is
asserted high.
Understanding and Using the pci_tcfg_stat Status
Signals
Data Sheet
March 2000
Initiating Target Aborts
There may be a need in an application to initiate a target abort condition on the PCI bus. In general, this is
asserted for only the most severe cases. The interface
signal, fpga_tabort, is used for this purpose. From the
PCI core's point of view, it needs to know whether to
perform a target abort at the very beginning of a transaction, so it is not possible to have a transaction
started, and then assert the fpga_tabort signal. The
signal fpga_tabort needs to be asserted before the
transaction begins, and it was designed to be toggled
on and off from transaction to transaction. Once an
FPGA application determines that it wants to apply a
target abort to any master that accesses it, it would
assert the fpga_tabort signal high. All future target
accesses will be terminated in an abort. In generating
this signal, keep in mind that this signal needs to be
synchronous to pciclk.
On the Target interface, there are two signals that control and provide status to the FPGA application. The
signal pci_tcfg_stat provides the status, and tcfgshiftenn controls what information the status line provides. The pci_tcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
tcfgshiftenn = 1. When high, pci_tcfg_stat provides
the wired-OR of the three status lines. If pci_tcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set tcfgshiftenn = 0 to determine individual status. Once low, the pci_tcfg_stat signal will
output target abort signaled on the first clock, system
error signaled on the second clock, and parity error
detected on the third clock.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read from Configuration Space
Figure 16 shows the timing on the PCI interface for a Target read from configuration space. Accesses of configuration space occur without any involvement of the FPGA interface. All configuration space accesses are disconnected with data on the first data word, and are thus restricted from bursting. Address decode speed is medium,
and the PCI core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is
asserted.
T0
T1
T2
T3
T4
T5
T6
clk
framen
ad
X
ADDRESS
c_ben
X
CMD
idsel
X
X
DATA
X
BYTE ENABLES
X
X
irdyn
devseln
trdyn
stopn
5-8856(F).a
Figure 16. Target Configuration Read (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read I/O, Delayed Transaction
Figure 17 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target I/O read that is handled as a delayed
transaction. In other words, the operation completes on the local (FPGA) bus before completing on the PCI bus.
The FPGA application indicates its desire to do this by driving the delayed transaction signal deltrn active-low. In
Figure 17, three transactions are shown: the first is the initial read that latches the command, address, and byte
enables. The PCI core’s Target logic then issues a retry, obligating the remote Master to continue to issue that identical request until data is moved. Meanwhile, the latched information is relayed to the FPGA interface via the
address FIFO, triggering the FPGA interface exchange discussed below and in Figure 20. All subsequent read or
write requests to memory or I/O space will result in retries, as shown in the second transaction of Figure 17. The
third transaction is the final transaction that completes the transfer of data. The timing on this third transaction is
identical to the timing of the first except that trdyn accompanies stopn to indicate the disconnect with data.
The timing on the FPGA interface (Figure 20) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of Target request (treqn), together with the new command on bus datatofpga. The FPGA application responds by asserting Target address enable (taenn) and accepting the command and
subsequent address on bus datatofpga, after which taenn is deasserted. The FPGA application then accesses
the requested data, asserts Target read data enable (trdataenn), and transmits the data on bus datafmfpga. This
is a nonburst transaction; therefore, Target read burst (trlastcycn) is kept asserted.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BEs
X
X
ADRS
X
X
CMD
BEs
X
X
ADRS
X
CMD
X
DATA
BEs
X
irdyn
evseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
DELAYED READ REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: DISCONNECTED WITH DATA
BECAUSE READ OPERATION COMPLETED.
5-8858(F).a
Figure 17. Target I/O Read, Delayed (PCI Bus, 64-Bit)
62
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read I/O, No Delayed Transaction
Figure 18 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target I/O read that is handled as an immediate execution; that is, the operation completes on the PCI bus immediately and then is presented to the FPGA via
the FPGA interface. The FPGA application indicates its desire to do this by deasserting signal deltrn. The PCI core
Target terminates the I/O read request by disconnecting with data on the first data word, thus disallowing bursting.
The PCI interface timing shown in Figure 18 is identical to the timing of the third (final) transaction of Target I/O
read, delayed transaction (Figure 17), which shows a Target I/O read with delayed transaction. Also, the FPGA
interface timing is as shown in Figure 20, regardless of whether delayed transactions are enabled.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
clk
framen
ad
X
ADDRESS
c_ben
X
CMD
X
BYTE ENABLES
X
DATA
BYTE ENABLES
X
X
irdyn
devseln
trdyn
stopn
5-8857(F).a
Figure 18. Target I/O Read, Not Delayed (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read Memory, Nonburst, Delayed Transaction
Figure 19 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target memory nonburst read handled as a
delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn. The timing on
the PCI interface (Figure 19) is similar to that of an I/O read (Figure 17) except that stop is not asserted here to
cause disconnect with data, but rather the operation is free to continue since it is allowed to complete on the source
(PCI) bus before it completes on the destination (FPGA) bus. The FPGA interface timing is as shown in Figure 20
and is the same as the timing in the I/O accesses of Target I/O read, delayed transaction and Target I/O read, no
delayed transaction.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BEs
X
X
ADRS
X
X
CMD
BEs
X
X
ADRS
X
CMD
X
DATA
BEs
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: NORMAL COMPLETION
BECAUSE READ OPERATION COMPLETED.
DELAYED READ REQUEST.
5-8860(F).a
Figure 19. Target Memory Single Read, Delayed (PCI Bus, 64-Bit)
64
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
fclk
t_ready
treqn
tstatecntr
0
4
0
tcmd
X
CMD
X
datatofpga
X
ADRS
X
datafmfpga
X
DATA
X
taenn
trdataenn
twlastcycn
trlastcycn
tr_fulln
tr_afulln
5-8837(F).a
Figure 20. Target Read Single (FPGA Bus, Dual-Port)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read Memory, Nonburst, No Delayed Transaction
Figure 21 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target memory nonburst read handled as an
immediate (nondelayed) transaction. The FPGA application indicates its desire to do this by deasserting signal deltrn. The timing on the PCI interface is shown in Figure 21. Here the PCI core accepts the transaction without issuing a retry but does not immediately assert trdyn. Wait-states are inserted until the requested data is placed in the
Target read FIFO, at which time trdyn is asserted and the data is returned. If the FPGA application cannot fetch the
data within the initial/subsequent latency time, the PCI core issues a retry or disconnect without data. The FPGA
interface timing is as shown in Figure 20, and is the same as the timing in the accesses of Target I/O read, delayed
transaction, Target I/O read, no delayed transaction, and Target read memory nonburst, delayed transaction.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
clk
framen
ad
X
ADDRESS
c_ben
X
CMD: MEM RD
X
BYTE ENABLES
X
DATA
X
BYTE ENABLES
X
irdyn
devseln
trdyn
stopn
5-8859(F).a
Figure 21. Target Memory Read Single, Not Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read Memory Burst, Delayed Transaction
Figure 22 (PCI bus) and Figure 23 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn.
On the PCI interface (Figure 22), three transactions are shown. In the first, the PCI core responds to the request
after determining that the address matches one of its BARs by asserting devseln. However, since delayed transaction has been specified by the FPGA application by asserting signal deltrn, the PCI core issues a retry. The PCI
core now waits for the FPGA application to load the Target read FIFO; until this occurs, all memory and I/O
accesses result in retries as exemplified by the second transaction in Figure 22. After the required data is loaded
(either the first data word or a complete FIFO contents, depending on whether the Target read PCI bus hold signal
trpcihold is deasserted or asserted, respectively), the actual data transfer will occur as shown in the third transaction in Figure 22. The FPGA interface timing is as shown in Figure 23. This is similar to the timing for a Target nonburst read as shown in Figure 20 except that multiple data cycles are required as long as trlastcycn is inactivehigh.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BE0
X
X
ADRS
X CMD
X
BE0
X
X
ADRS
X
CMD
X
D0
BE0
D1 D2
D3
BE1 BE2 BE3
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
DELAYED READ REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: NORMAL COMPLETION
BECAUSE READ OPERATION COMPLETED.
5-8862fF).a
Figure 22. Target Memory Read 32-Byte Burst, Delayed (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
fclk
t_ready
treqn
tstatecntr
0
4
0
tcmd
X
CMD
X
datatofpga
X
ADRS
X
datafmfpga
X
D0
D1
D2
D3
X
taenn
trdataenn
twlastcycn
trlastcycn
tr_fulln
tr_afulln
5-8838(F).a
Figure 23. Target Read Memory 32-Byte Burst (FPGA, Dual-Port)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual Port (continued)
Target Read Memory Burst, No Delayed Transaction
Figure 24 (PCI bus) and Figure 23 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a nondelayed transaction. Figure 24 shows the timing on the PCI interface is similar to that of an I/O
read (Figure 18) except that stop is not asserted here to cause disconnect with data, but rather the operation is free
to continue since it is allowed to complete on the source (PCI) bus before it completes on the destination (FPGA)
bus.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
Tn4
Tn5
Tn6
clk
framen
ad
X
ADRS
c_ben
X
CMD
X
X
BE0
D0
D1
BE0
D2
BE1
D3
BE2
X
BE3
irdyn
devseln
trdyn
stopn
5-8861(F).a
Figure 24. Target Read Memory Burst, No Delayed (PCI Bus, 32-Bit)
Table 22. Dual-Port Target Read
tstatecntr
Next State
of
Description
tstatecntr
0
0
0
4
4
4 or 0
Idle
Address[63:
0]
Data[63:0]
Bus
treqn
trdataenn twlastcycn taenn
trlastcycn
—
datatofpgax[7:0]
datatofpga[63:0]
datafmfpga[63:0]
1
0
1
1
1
1
1
0
1
0
1*
0
0†
1
1
* treqn is deasserted high on the last data Quadword.
† twlastcycn is asserted low on the last data Quadword.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port
Pages 70—122 will refer to the quad-port mode of the OR3LP26B device. For dual-port mode, please refer to
pages 21—69.
Embedded Core/FPGA Interface Signal Descriptions
In Table 23, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers
to a signal flowing out of the FPGA logic (into the embedded core).
Table 23. Embedded Core/FPGA Interface Signals
Symbol
I/O
Master Data FIFO Signals
mwdata[35:0]
O
Description
Main data bus into the master write FIFO. Refer to Table 25 on page 79 for bus
usage and bit descriptions.
These signals must be synchronous to fclk.
Main data bus out of the master read FIFO. Refer to Table 25 on page 79 for bus
usage and bit descriptions.
These signals are synchronous to fclk.
mrdata[35:0]
I
Master General Signals
fpga_mbusyn
O
Symbol
I/O
Description
maenn
O
ma_fulln
I
mstatecntr[2:0]
I
mfifoclrn
O
Master Command/Address/Burst Length Enable. This is an active-low signal
and is used to enable registering commands, burst length, and start address into
the Master address register of the PCI core. On each rising edge of the clock that
this signal is sampled low, command, burst length, and address will be registered.
This signal must be synchronous to fclk.
Master Address Register Full Flag. This active-low signal indicates that the Master address register is full and no more addresses can be registered.
This signal is synchronous to fclk.
Internal State Counter. Used for Master reads and writes. Details of the Master
state machine operation can be found in tables at the end of each operation section.
This signal is synchronous to fclk.
Master FIFO Clear. This active-low signal is asserted by the FPGA Master to clear
all Master FIFOs.
This signal must be synchronous to fclk.
FPGA Master Is Busy. This signal is used in modes currently not implemented in
the core. Tie off this signal to a 1.
FPGA Master Cycle Aborted by PCI Target. The PCI Master controller in the PCI
fpga_msyserror
I
core asserts this active-high as an indication that the current cycle to the PCI bus
has been aborted. This signal is synchronous to fclk.
mcfgshiftenn
O mcfgshiftenn is an active-low signal that determines the data that is output by the
pci_mcfg_stat
I
PCI core onto signal pci_mcfg_stat:
mcfgshiftenn = 1: pci_mcfg_stat = wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
mcfgshiftenn = 0: pci_mcfg_stat = each bit below, one at a time on successive pciclk rising edges (unmasked), reset when
mcfgshiftenn = 1;
Status bits:
Data parity error detected, Target abort received, and
Master abort received.
Both signals are synchronous to fclk.
Master FIFO Address and Command Register Control Signals
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Table 23. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Master Logic Ready. This active-high signal indicates that the Master logic
interfacing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Master FIFO clears.
This signal is synchronous to fclk.
Master Command Code. Command code for the current Master read/write
mcmd[3:0]
O operation. Refer to Table 25 on page 79.
This signal must be synchronous to fclk.
Master Write Data FIFO Signals
mwdataenn
O Master Write FIFO Data Enable. This active-low signal enables the registering
of bus datafmfpga during Master write operations into the PCI core Master
write data FIFOs on the rising edge of the Master FIFO clock signal. The signal
mwdataenn should not be asserted when the Master write data FIFOs are full,
or data may be lost.
This signal must be synchronous to fclk.
mwpcihold
O Master Write PCI Bus Hold. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to
fill the FIFO. The transaction will begin when mwpcihold is deasserted or the
FIFO becomes full. When asserted, mwpcihold must be held low for a minimum of two pciclk periods.
This signal must be synchronous to pciclk.
Master Write Data FIFO Full Flag. This active-low signal indicates that the
mw_fulln
I
Master write data FIFOs are full.
This signal is synchronous to fclk.
Master Write Data FIFO Almost Full Flag. This active-low signal indicates that
mw_afulln
I
only four more empty locations remain in the Master write data FIFOs.
This signal is synchronous to fclk.
Master Write Data FIFO Empty Flag. This active-low signal indicates that the
mw_emptyn
I
Master write data FIFO is empty. Refer to Master write description on signal
usage.
This signal is synchronous to pciclk.
mwlastcycn
O Master Write Last Data Cycle. This active-low signal has two functions:
a. It is asserted low to indicate that the accompanying 32/64 bits of Master read
or write address information is the final portion being sent. It can also be
asserted prior to any address portion being sent, indicating that the previous
address is to be used.
b. It is asserted low to indicate that the accompanying master write data is the
final data for this operation. When more than one cycle is required to transfer
a complete data word, this signal is only valid on the last cycle.
This signal must be synchronous to fclk.
Master Read Data FIFO Signals
mrdataenn
O Master Read FIFO Data Output Enable. This active-low signal enables the
data from the PCI core Master read data FIFOs onto bus datatofpga during
Master read operations on the rising edge of the Master FIFO clock signal. Valid
data will be read from the FIFO whenever it is not empty.
This signal must be synchronous to fclk.
Master Read Data FIFO Empty. This active-low signal indicates that the Masmr_emptyn
I
ter read data FIFOs of the PCI core are empty.
This signal is synchronous to fclk.
m_ready
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I
71
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 23. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
mr_aemptyn
I
mr_fulln
I
fpga_mstopburstn
O
mrlastcycn
I
Master Read Data FIFO Almost Empty. This active-low signal indicates that
only four more data locations are available to be read from the Master read data
FIFOs of the PCI core.
This signal is synchronous to fclk.
Master Read Data FIFO Full Flag. This active-low signal indicates that the
Master read data FIFO is full. Refer to Master read description on signal usage.
This signal is synchronous to pciclk.
Stop Burst Reads. This active-low signal is used by the FPGA Master to terminate burst reads before completion. When asserted, it must stay asserted for a
minimum of two pciclk periods. When asserted, fpga_mstopburstn must stay
asserted until ma_fulln goes inactive (high).
This signal must be synchronous to pciclk.
Master Read Last Data Cycle. This active-low signal is asserted to indicate
that the accompanying Master read data is the final data for this operation.
When more than one cycle is required to transfer a complete data word, this
signal is only valid on the last cycle (1 fclk period).
This signal is synchronous to fclk.
Target General Signals
disctimerexpn
72
I
fpga_tabort
O
fpga_tretryn
O
deltrn
O
tcfgshiftenn
pci_tcfg_stat
O
I
Discard Timer Expired. This active-low signal, when asserted, indicates that
the discard timer has expired and the core will now treat the retried delayed
transaction as a new transaction. The discard timer is a 15-bit counter which
starts its count when a delayed transaction is started.
This signal is synchronous to fclk.
Target Abort. This active-high signal is asserted by the FPGA Target application to abort all future PCI cycles. Once asserted, this signal needs to remain
asserted for a minimum of two pciclk cycles.
This signal must be synchronous to pciclk.
Assert Retry. This active-low signal is asserted by an FPGA Target to the PCI
core to send a retry to the PCI bus. Once asserted, this signal needs to remain
asserted for a minimum of two pciclk cycles.
This signal must be synchronous to pciclk.
Target Delayed Transaction. Used for Target I/O write (page 102) and Target
read operations (page 111). Target memory writes are always posted. Once
asserted, this signal needs to remain asserted for a minimum of two pciclk
cycles.
This signal must be synchronous to pciclk.
tcfgshiftenn is an active-low signal that determines the data that is output by
the PCI core onto signal pci_tcfg_stat:
tcfgshiftenn = 1: pci_tcfg_stat = wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
tcfgshiftenn = 0: pci_tcfg_stat = each bit below, one at a time on successive pciclk rising edges (unmasked), reset when
tcfgshiftenn = 1;
Status bits:
Target abort signaled, system error signaled,
and parity error detected.
Both signals are synchronous to fclk.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 23. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Target Data FIFO Signals
twdata[35:0]
I
Description
Target side data bus into the FPGA from the target write FIFOs.
These signals are synchronous to fclk.
trdata[35:0]
O Target side data bus out of the FPGA into the target read FIFOs.
These signals must be synchronous to fclk.
Target FIFO Address and Command Register Control Signals
tfifoclrn
O Target FIFO Clear. This active-low signal is asserted by the FPGA Target to
clear all Target FIFOs.
This signal must be synchronous to fclk.
Target Request from PCI. This active-low signal is synchronous to the Target
treqn
I
FIFO clock signal. The PCI core asserts treqn as an indication to the Target
that a transfer request (either read or write) is pending to the target. As long as
there are valid target addresses present in the address FIFO, the treqn signal
will continue to be active.
This signal is synchronous to fclk.
Target Logic Ready. This active-high signal indicates that the Target logic intert_ready
I
facing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Target FIFO clears.
This signal is synchronous to fclk.
taenn
O Target Address and Command Register Output Enable. This active-low signal enables PCI addresses to be read from the Target address register of the
PCI core, and PCI commands to be read from the Target command register.
The PCI core will only execute enough address cycles to transfer the address
within the matched page (higher-order bits are not stripped).
This signal must be synchronous to fclk.
Target Command Code. This bus provides the command code for a new Tartcmd[3:0]
I
get operation, and is valid when the FPGA senses treqn active-low.
Because it is synchronous to pciclk, it must be qualified with treqn.
Base Address Register Number. This bus indicates which of the six BARs
bar[2:0]
I
matched the address for the current Target operation, and is valid when the
FPGA senses treqn active-low. The three 64-bit BARs are designated as numbers 0, 2, and 4.
Because it is synchronous to pciclk, it must be qualified with treqn.
Internal State Counter. Used for target reads and writes. Details of the target
tstatecntr[2:0]
I
state machine operation can be found in tables at the end of each operation
section.
This signal is synchronous to fclk.
Target Write Data FIFO Signals
twdataenn
O Target Write FIFO Data Enable. This active-low signal enables data from the
PCI core Target write data FIFOs onto bus datatofpga during Target write operations on the rising edge of the Target FIFO clock signal. Valid data will be read
from the FIFO whenever it is not empty.
This signal must be synchronous to fclk.
Target Write FIFO Empty. This signal active indicates that the Target write
tw_emptyn
I
FIFO is empty.
This signal is synchronous to fclk.
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73
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 23. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
Target Write FIFO Almost Empty. This active-low signal indicates that only four
more empty locations are available in the Target write FIFOs.
This signal is synchronous to fclk.
Target Write Data FIFO Full Flag. This active-low signal indicates that the target
tw_fulln
I
write data FIFO is full. Refer to target write description on signal usage.
This signal is synchronous to pciclk.
Target Write Last Data Cycle. This active-low signal has two functions:
twlastcycn
I
a. It is asserted low to indicate that the accompanying 32/64 bits of Target read or
write address information is the final portion being sent. It can also be asserted
prior to any address portion being sent, indicating that the previous address is
to be used.
b. It is asserted low to indicate that the accompanying Target write data is the final
data for this operation. When more than one cycle is required to transfer a complete data word, this signal is only valid on the last cycle.
This signal is synchronous to fclk.
Target
Write Burst Data Availability Pending Flag. This active-low signal
twburstpendn
O
directs the PCI core not to immediately disconnect when the Target write FIFO
becomes full, but rather to insert PCI bus wait-states (up to the maximum allowed,
and then disconnect). Once asserted, this signal needs to remain asserted for a
minimum or two pciclk periods.
This signal must be synchronous to pciclk.
Target Read Data FIFO Signals
trdataenn
O Target Read FIFO Data Enable. This active-low signal enables the registering of
bus datafmfpga during Target read operations into the PCI core Target read data
FIFOs on the rising edge of the Target FIFO clock signal. The signal trdataenn
should not be asserted when the Target read data FIFOs are full, or data may be
lost.
This signal must be synchronous to fclk.
Target Read FIFO Full. This signal is active-low and synchronous to the rising
tr_fulln
I
edge of the Target FIFO clock signal. The PCI core asserts this signal to indicate
that the Target read FIFOs are full and that no more data can be clocked in.
This signal is synchronous to fclk.
Target Read FIFO Almost Full. This active-low signal indicates that the Target
tr_afulln
I
read FIFO has only four more empty locations available in the FIFOs.
This signal is synchronous to fclk.
Target Read Data FIFO Empty Flag. This active-low signal indicates that the tartr_emptyn
I
get read data FIFO is empty. Refer to target read description on signal usage.
This signal is synchronous to pciclk.
trpcihold
O Target Read PCI Bus Hold. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to fill
the FIFO. The transaction will begin when trpcihold is deasserted or the FIFO
becomes full. Once asserted, this signal needs to remain asserted for a minimum
or two pciclk periods.
This signal must be synchronous to pciclk.
tw_aemptyn
74
I
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 23. Embedded Core/FPGA Interface Signals (continued)
Symbol
I/O
Description
trlastcycn
I
trburstpendn
O
Target Read Last Data Cycle. This active-low signal is asserted to indicate that
the accompanying Target read data is the final data for this operation. When more
than one cycle is required to transfer a complete data word, this signal is only
valid on the last cycle. During a read burst, trlastcycn may remain inactive for
longer than it is required to complete the data transfer. If this occurs, the FPGA
Target should continue to write data into the Target read FIFOs unless the incremented address crosses the address decode space of the FPGA Target. The
address should be incremented by a double word as long as trlastcycn is inactive.
This signal is synchronous to fclk.
Target Read Burst Data Availability Pending Flag. This active-low signal
directs the PCI core not to immediately disconnect when the Target read FIFO
becomes empty, but rather to insert PCI bus wait-states (up to the maximum
allowed, and then disconnect). Once asserted, this signal needs to remain
asserted for a minimum or two pciclk periods.
This signal must be synchronous to pciclk.
Miscellaneous Signals
pci_intan
O
fclk1
fclk2
O
O
pciclk
I
pci_rstn
I
fpga_syserror
O
pci_64bit
I
fifo_sel
O
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PCI Interrupt Request. This active-low signal is used to generate a PCI bus
interrupt and is forwarded by the PCI core as intan onto the PCI bus. Once
asserted, this signal needs to remain asserted for a minimum of two pciclk
cycles.
This signal must be synchronous to pciclk.
FPGA Clock 1 and 2. Clocks for use by the PCI core for Master and Target
FIFOs. When the PCI clock domain extends into the FPGA, the FPGA may
reroute the PCI clock back into fclk1 or fclk2. External or user-defined clocks may
also be used. The signals fclk1 and fclk2 must be the same clock in dual-port
mode.
PCI Clock. The signal pciclk is synchronous to clk and may be used by the
FPGA logic.
PCI Reset for Use by the FPGA Logic. This active-low signal indicates that a
PCI bus reset was received from the PCI bus (rstn).
System Error. This active-high signal is used by the FPGA to generate a system
error on the PCI bus. This is passed to the PCI bus as serrn.
This signal must be synchronous to pciclk.
PCI Bus in 64-Bit Mode. This active-high signal indicates that the PCI core
detected that it is connected as a 64-bit agent to the PCI bus. This is the result of
detecting PCI signal req64n as active (low) on the inactive-going (rising) edge of
PCI signal rstn. Note that this does not imply that any particular transaction is
64-bit, since each transaction is individually negotiated using PCI signals req64n
and ack64n.
This signal is synchronous to pciclk.
FIFO Select. An active-high signal that is valid in the dual-port modes to select
either Master read data (fifo_sel = 0) or Target write data (fifo_sel = 1).
This signal must be synchronous to fclk.
75
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Embedded Core/FPGA Interface Signal Locations
Table 24 lists the physical locations of all signals on the PCI core/FPGA interface. Separate names are provided for
dual-port and quad-port bus signals, since their functionality is port mode dependent.
Table 24. OR3LP26B FPGA/PCI Core Interface Signal Locations
76
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB1A
ASB1B
ASB1C
ASB1D
ASB2A
ASB2B
ASB2C
ASB2D
ASB3A
ASB3B
ASB3C
ASB3D
ASB4A
ASB4B
ASB4C
ASB4D
ASB5A
ASB5B
ASB5C
ASB5D
ASB6A
ASB6B
ASB6C
ASB6D
ASB7A
ASB7B
ASB7C
ASB7D
ASB8A
ASB8B
ASB8C
ASB8D
ASB9A
ASB9B
ASB9C
ASB9D
CKTOASB9
ASB10A
pci_rstn
pci_64bit
(unused)
(unused)
twdata31
twdata30
twdata29
twdata28
twdata27
twdata26
twdata25
twdata24
twdata23
twdata22
twdata21
twdata20
twdata19
twdata18
twdata17
twdata16
twdata35
twdata34
twdata33
twdata32
twdata15
twdata14
twdata13
twdata12
twdata11
twdata10
twdata9
twdata8
twdata7
twdata6
twdata5
twdata4
(unused)
twdata3
pci_intan
(unused)
fpga_syserror
fpga_mbusyn
trdata31
trdata30
trdata29
trdata28
trdata27
trdata26
trdata25
trdata24
trdata23
trdata22
trdata21
trdata20
trdata19
trdata18
trdata17
trdata16
trdata35
trdata34
trdata33
trdata32
trdata15
trdata14
trdata13
trdata12
trdata11
trdata10
trdata9
trdata8
trdata7
trdata6
trdata5
trdata4
fclk1
trdata3
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 24. OR3LP26B FPGA/PCI Core Interface Signal Locations (continued)
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB10B
ASB10C
ASB10D
ASB11A
twdata2
twdata1
twdata0
tstatecntr0
trdata2
trdata1
trdata0
(unused)
ASB11B
tstatecntr1
(unused)
ASB11C
tstatecntr2
ASB11D
ASB12A
pci_tcfg_stat
tcmd0
(unused)
tcfgshiftenn
ASB12B
tcmd1
(unused)
ASB12C
tcmd2
(unused)
ASB12D
twburstpendn
ASB13A
tcmd3
bar0
ASB13B
ASB13C
ASB13D
bar1
bar2
disctimerexpn
ASB14A
treqn
ASB14B
twlastcycn
taenn
twdataenn
ASB14C
tw_emptyn
fifo_sel
ASB14D
(unused)
CKFMASB14
tw_aemptyn
pciclk
ASB15A
t_ready
ASB15B
trlastcycn
tfifoclrn
trdataenn
ASB15C
tr_fulln
(unused)
ASB15D
(unused)
ASB16A
tr_afulln
tw_fulln
ASB16B
ASB16C
ASB16D
tr_emptyn
mw_emptyn
mr_fulln
ASB17A
ASB17B
ASB17C
ASB17D
ASB18A
ASB18B
ASB18C
ASB18D
ASB19A
ASB19B
ma_fulln
mw_fulln
mw_afulln
m_ready
mrlastcycn
mr_emptyn
mr_aemptyn
fpga_msyserror
mrdata0
mrdata1
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(unused)
trburstpendn
fpga_tabort
fpga_tretryn
deltrn
(unused)
trpcihold
mwpcihold
fpga_mstopburstn
(unused)
maenn
mwdataenn
mwlastcycn
mrdataenn
mcmd0
mcmd1
mcmd2
mcmd3
mwdata0
mwdata1
77
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 24. OR3LP26B FPGA/PCI Core Interface Signal Locations (continued)
PCI Core/FPGA Interface Site
FPGA Input Signal Name
FPGA Output Signal Name
ASB19C
ASB19D
CKTOASB19
mrdata2
mrdata3
mwdata2
mwdata3
fclk2
ASB20A
ASB20B
ASB20C
ASB20D
ASB21A
ASB21B
ASB21C
ASB21D
ASB22A
ASB22B
ASB22C
ASB22D
ASB23A
ASB23B
ASB23C
ASB23D
ASB24A
ASB24B
ASB24C
ASB24D
ASB25A
ASB25B
ASB25C
ASB25D
ASB26A
ASB26B
ASB26C
ASB26D
ASB27A
ASB27B
ASB27C
ASB27D
ASB28A
ASB28B
78
(unused)
mrdata4
mrdata5
mrdata6
mrdata7
mrdata8
mrdata9
mrdata10
mrdata11
mrdata12
mrdata13
mrdata14
mrdata15
mrdata32
mrdata33
mrdata34
mrdata35
mrdata16
mrdata17
mrdata18
mrdata19
mrdata20
mrdata21
mrdata22
mrdata23
mrdata24
mrdata25
mrdata26
mrdata27
mrdata28
mrdata29
mrdata30
mrdata31
mstatecntr0
mstatecntr1
ASB28C
mstatecntr2
ASB28D
pci_mcfg_stat
mwdata4
mwdata5
mwdata6
mwdata7
mwdata8
mwdata9
mwdata10
mwdata11
mwdata12
mwdata13
mwdata14
mwdata15
mwdata32
mwdata33
mwdata34
mwdata35
mwdata16
mwdata17
mwdata18
mwdata19
mwdata20
mwdata21
mwdata22
mwdata23
mwdata24
mwdata25
mwdata26
mwdata27
mwdata28
mwdata29
mwdata30
mwdata31
mfifoclrn
(unused)
(unused)
mcfgshiftenn
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 25. Bit Definitions on FPGA/PCI Core Interface
Bits
Name
A. Quad-Port Master Write (Lower Address Cycle)
mwdata[35]
HR
mwdata[34]
mwdata[33:32]
mwdata[31:0]
mcmd[3:0]
DA
—
A1 & A0
mcmd
B. Quad-Port Master Write (Upper Address Cycle)
mwdata[35:32]
mwdata[31:0]
mcmd[3:0]
—
A3 & A2
—
C. Quad-Port Master Write, Lower Data DWORD
mwdata[35:32]
mwdata[31:0]
BE3—BE0
D3—D0
D. Quad-Port Master Write, Upper Data DWORD
mwdata[35:32]
mwdata[31:0]
BE7—BE4
D7—D4
E. Quad-Port Master Read (16-Bit Address Cycle)
mwdata[35]
HR
mwdata[34]
mwdata[33]
DA
SPL = 1
mwdata[32]
mwdata[31:24]
mwdata[23:16]
—
MRd_BenN
—
Description
mstatecntr = 0
Holding address register selector:
0 = select HR0
1 = select HR1
Dual address indicator (active-high)
Unused
Address words 1 and 0
Master command opcode*
mstatecntr = 1
Unused
Address words 3 and 2
Unused
mstatecntr = 4
Byte enables (active-low)
Data bytes 3 to 0
mstatecntr = 5
Byte enables (active-low)
Data bytes 7 to 4
mstatecntr = 0
Holding address register selector:
0 = select HR0
1 = select HR1
Dual address indicator (active-high)
Burst length source
0 = use new burst length
1 = use burst length of previous operation, and
only 16-bit address is supplied
Unused
Byte enables (active-low)
Unused
* Command Codes (codes correspond to PCI bus command codes):
0000 Not Used (interrupt acknowledge not implemented)
0001 Not Used (special cycle not implemented)
0010 I/O Read
0011 I/O Write
0100 Reserved (per PCI specification)
0101 Reserved (per PCI specification)
0110 Memory Read
0111 Memory Write
1000 Reserved (per PCI specification)
1001 Reserved (per PCI specification)
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Not Used (dual address operation is indicated via separate signal)
1110 Memory Read Line
1111 Memory Write and Invalidate
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79
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 25. Bit Definitions on FPGA/PCI Core Interface (continued)
Bits
Name
Description
mwdata[15:0]
mcmd[3:0]
A0
mcmd
Address word 0
Master command opcode*
F. Quad-Port Master Read (Burst Length Cycle)
mwdata[35]
HR
mwdata[34]
mwdata[33]
DA
SPL = 0
mwdata[32]
mwdata[31:24]
mwdata[23:18]
mwdata[17:0]
mcmd[3:0]
—
MRd_BenN
—
BL
mcmd
G. Quad-Port Master Read (Lower Address Cycle)
mwdata[35:32]
mwdata[31:0]
mcmd[3:0]
—
A1 & A0
—
H. Quad-Port Master Read (Upper Address Cycle)
mwdata[35:32]
mwdata[31:0]
mcmd[3:0]
—
A3 & A2
—
I. Quad-Port Master Read, Lower Data DWORD
mrdata[35:32]
mrdata[31:0]
—
D3—D0
J. Quad-Port Master Read, Upper Data DWORD
mrdata[35:32]
mrdata[31:0]
—
D7—D4
mstatecntr = 0
Holding address register selector:
0 = select HR0
1 = select HR1
Dual address indicator (active-high)
Burst length source
0 = use new burst length
1 = use burst length of previous operation
Unused
Byte enables (active-low)
Unused
Burst length (In Quadwords)
Master command opcode*
mstatecntr = 1
Unused
Address words 1 and 0
Unused
mstatecntr = 2
Unused
Address words 3 and 2
Unused
mstatecntr = 4
Unused
Data bytes 3 to 0
mstatecntr = 5
Unused
Data bytes 7 to 4
* Command Codes (codes correspond to PCI bus command codes):
0000 Not Used (interrupt acknowledge not implemented)
0001 Not Used (special cycle not implemented)
0010 I/O Read
0011 I/O Write
0100 Reserved (per PCI specification)
0101 Reserved (per PCI specification)
0110 Memory Read
0111 Memory Write
1000 Reserved (per PCI specification)
1001 Reserved (per PCI specification)
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Not Used (dual address operation is indicated via separate signal)
1110 Memory Read Line
1111 Memory Write and Invalidate
80
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TechnologiesInc.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 25. Bit Definitions on FPGA/PCI Core Interface (continued)
Bits
Name
Description
K. Quad-Port Target Write & Read (Lower Address Cycle)
twdata[35]
twdata[34]
twdata[33:32]
twdata[31:0]
tcmd[3:0]
Burst_I
DA
—
A1 & A0
tcmd
tstatecntr = 0
Burst indication (active-high)
Dual address indicator (active-high)
Unused
Address words 1 and 0
Target command opcode*
L. Quad-Port Target Write & Read (Upper Address Cycle)
twdata[35:32]
twdata[31:0]
tcmd[3:0]
—
A3 & A2
—
tstatecntr = 1
Unused
Address words 3 and 2
Unused
M. Quad-Port Target Write, Lower Data DWORD
twdata[35:32]
twdata[31:0]
BE3—BE0
D3—D0
tstatecntr = 4
Byte enables (active-low)
Data bytes 3 to 0
N. Quad-Port Target Write, Upper Data DWORD
twdata[35:32]
twdata[31:0]
BE7—BE4
D7—D4
tstatecntr = 5
Byte enables (active-low)
Data bytes 7 to 4
O. Quad-Port Target Read, Lower Data DWORD
trdata[35:32]
trdata[31:0]
—
D3—D0
tstatecntr = 4
Unused
Data bytes 3 to 0
P. Quad-Port Target Read, Upper Data DWORD
trdata[35:32]
trdata[31:0]
—
D7—D4
tstatecntr = 5
Unused
Data bytes 7 to 4
* Command Codes (codes correspond to PCI bus command codes):
0000 Not Used (interrupt acknowledge not implemented)
0001 Not Used (special cycle not implemented)
0010 I/O Read
0011 I/O Write
0100 Reserved (per PCI specification)
0101 Reserved (per PCI specification)
0110 Memory Read
0111 Memory Write
1000 Reserved (per PCI specification)
1001 Reserved (per PCI specification)
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Not Used (dual address operation is indicated via separate signal)
1110 Memory Read Line
1111 Memory Write and Invalidate
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 26. Address Cycle Sequences for Various Operations
Operation
Master Write
Master Read
Target Write
Target Read
82
Address
Mode
Supplied
Address
New Burst
Length
Address Cycle
Sequence
(Once Only)
Data Cycle
Sequence
(Repeats)
SA/DA
DA
SA/DA
SA/DA
SA/DA
DA
SA/DA
DA
SA/DA
DA
31:0
63:0
15:0
(none)
31:0
63:0
31:0
63:0
31:0
63:0
NA
NA
No
Yes
Yes
Yes
NA
NA
NA
NA
A
A, B
E
F
F, G
F, G, H
K
K, L
K
K, L
CD
CD
I, J
I, J
I, J
I, J
M, N
M, N
O, P
O, P
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Embedded Core Bit Stream Configurable Options
Table 27 lists all optional functionality in the PCI core that can be defined via bits in the FPGA configuration RAM.
The table also lists the settings available for each feature. Each of these options is configured using the FPSC
Design Kit software.
Table 27. PCI Core Options Settable via FPGA Configuration RAM Bits
Address in
Configuration Space
Revision ID
Class Code
Bus Master Support
Report: Data Parity Error Detected
Report: Target Abort Signaled
Report: Target Abort Received
Report: Master Abort Received
Report: System Error Signaled
Report: Parity Error Detected
(nonmaskable)
Latency Timer Initial Value
Base Address Register (BAR) Area 1
Base Address Register (BAR) Area 2
Base Address Register (BAR) Area 3
Subsystem Vendor ID
Subsystem ID
Minimum Grant (Min_Gnt)
Maximum Latency (Max_Lat)
Port Mode
08
Any 8-bit value.
09—0B
Any 24-bit value.
Command register bit 2 Four options.
■ Initially disabled, read-only.
■ Initially disabled, read/write.
■ Initially enabled, read-only.
Status register bit 8
Include or exclude in decode for pci_mcfg_stat.
Status register bit 11
Include or exclude in decode for pci_tcfg_stat.
Status register bit 12
Include or exclude in decode for pci_mcfg_stat.
Status register bit 13
Include or exclude in decode for pci_mcfg_stat.
Status register bit 14
Include or exclude in decode for pci_tcfg_stat.
Status register bit 15
Include or exclude in decode for pci_tcfg_stat.
OD
10—17
18—1F
20—27
2C—2D
2E—2F
3E
3F
Target Address Comparator
—
—
—
—
—
Target Maximum Intial Latency
—
I/O Mode
Master FIFO Interface Clock
Target FIFO Interface Clock
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Optional Settings
Any 8-bit value divisible by 8.
■ One or two 32-bit BARs or one 64-bit BAR, or none
(i.e., unprogrammed).
■ If 64-bit BAR, must be memory; page size can be from
24 to 264 bytes.
■ 32-bit BARs can be memory or I/O.
2
32 bytes.
■ If 32-bit I/O BAR, page size can be from 2 to 2
20 or 232
■ If 32-bit memory BAR, address space can be 2
bytes, page size can be 24 to the maximum (220 or 232)
bytes.
■ If memory, can be prefetchable or nonprefetchable.
Same as for BAR area 1.
Same as for BAR area 1.
Any 16-bit value.
Any 16-bit value.
Any 8-bit value.
Any 8-bit value.
Dual port or quad port.
Fast or slew-limited PCI output buffers.
fclk1 or fclk2.
fclk1 or fclk2.
Enabled or disabled; when enabled, PCI core will not
transfer most significant byte(s) of Target address if they
match previous Target operation's address and require
additional bus cycle(s).
Normal (16) or extended (32); note that only normal
latency complies with PCI Specification. Extended latency
may be specified in proprietary systems where bandwidth
requirements override fairness considerations.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Understanding FIFO Packing/Unpacking
In quad-port mode, the interface from the core to the FPGA is always 32 bits wide. However, data packing through
the FIFOs will differ depending on whether the transfers on the PCI bus are 32 bits or 64 bits. The following discussions pertain to target write or master read operations where data will be read from the FIFOs.
■
64-bit transfers: Since the FIFOs are always in 64-bit mode, the data will flow through without any repacking.
Keep in mind that 64-bit transfers must start on a Quadword aligned address (AD2 = 0). Case 1 provides an
example of how the data is read out of the read side of the FIFO.
Case 1: Master read burst, 64-bit. Quadword aligned starting address, even number of 64-bit words transferred on
the PCI bus.
Table 28. Quad-Port FIFO Packing/Unpacking, Case 1, PCI Side
PCI Address
PCI Data
PCI Byte Enables
(Active-Low)
00001000
(00001008)
(00001010)
(00001018)
(00001020)
(00001028)
64-bit Word1
64-bit Word2
64-bit Word3
64-bit Word4
64-bit Word5
64-bit Word6
00000000
00000000
00000000
00000000
00000000
00000000
Table 29. Dual-Port FIFO Packing/Unpacking, Case 1, FPGA Side
Master Write FIFO Slot
1
1
2
2
3
3
4
4
5
5
6
6
FIFO Data Bits [31:0]
FIFO Byte Enables
(Active-Low)
twdata[31:0]
64-bit Word1 [31:0]
64-bit Word1 [63:32]
64-bit Word2 [31:0]
64-bit Word2 [63:32]
64-bit Word3 [31:0]
64-bit Word3 [63:32]
64-bit Word4 [31:0]
64-bit Word4 [63:32]
64-bit Word5 [31:0]
64-bit Word5 [63:32]
64-bit Word6 [31:0]
64-bit Word6 [63:32]
twdata[35:32]
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.
Dummy words are unknown data words in the FIFOs with their byte enables disabled.
■
32-bit transfers: The FIFOs are always in 64-bit mode, so depending upon what address the transfer begins, the
data coming out of the FIFOs will be packed differently. The following two cases provide examples with different
starting addresses and word counts. Case 1 is also true for Master read operations.
Case 1: Target write burst, 32-bit. Quadword aligned starting address, even number of 32-bit words transferred on
the PCI bus.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 30. Quad-Port FIFO Packing/Unpacking, Case 1, PCI Side
PCI Address
PCI Data
PCI Byte Enables
(Active-Low)
00001000
(00001004)
(00001008)
(00001010)
(00001014)
(00001018)
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
32-bit Word6
0000
0000
0000
0000
0000
0000
Table 31. Quad-Port FIFO Packing/Unpacking, Case 1, FPGA Side
Master Write FIFO Slot
1
1
2
2
3
3
FIFO Data Bits [31:0]
FIFO Byte Enables
(Active-Low)
twdata[31:0]
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
32-bit Word6
twdata[35:32]
0000
0000
0000
0000
0000
0000
Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.
Dummy words are unknown data words in the FIFOs with their byte enables disabled.
Case 2: Target write burst, 32-bit. Quadword aligned starting address, odd number of 32-bit words transferred on
the PCI bus.
Table 32. Quad-Port FIFO Packing/Unpacking, Case 2, PCI Side
PCI Address
PCI Data
PCI Byte Enables
(Active-Low)
00001000
(00001004)
(00001008)
(00001010)
(00001014)
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
0000
0000
0000
0000
0000
Table 33. Quad-Port FIFO Packing/Unpacking, Case 1, FPGA Side
Master Write FIFO Slot
1
1
2
2
3
3
FIFO Data Bits [31:0]
FIFO Byte Enables
(Active-Low)
twdata[31:0]
32-bit Word1
32-bit Word2
32-bit Word3
32-bit Word4
32-bit Word5
Dummy Word
twdata[35:32]
0000
0000
0000
0000
0000
FFFF
Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.
Dummy words are unknown data words in the FIFOs with their byte enables disabled.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Embedded Core/FPGA Interface Operation
Dual Master Address Holding Registers
The PCI core utilizes a pair of address holding registers to reduce latency when setting up repeated Master transfers to or from the same address. Every Master operation has associated with it one of the two holding registers, as
specified by the holding register selector signal (as described in Table 25). Each address holding register records
the full previous address, allowing some, all, or none of that recorded address to be used to build the next address
associated with that holding register. This can save up to two cycles for quad-port mode. The holding register
optionally supplies the most significant portion, or all, or none, of the address. The amount supplied by the holding
register is determined by the timing of the signal mwlastcycn, which accompanies the last portion of data, or
accompanies the command word when the holding register supplies the entire address. Table 34 below gives
examples in quad-port, 64-bit addressing mode, of typical operation using the holding registers, illustrating the
above rules.
The two holding registers can be assigned one to read and one to write, thus providing two unrelated areas for the
two functions. Another useful application is to dedicate one register to a fixed address such as the beginning of a
buffer, the data port of a FIFO or a mailbox register. This especially increases effective bandwidth on shorter bursts.
Table 34. Holding Registers, Examples of Typical Operation
Address on Bus
mwdata
AU
AL
1111-1111 2222-2222
Last
Cycle
Valid
With
Holding
Register
Select
Holding Register 0
Initial Value
Holding Register 1
Initial Value
AU
AL
AU
AL
Master Read/Write
Address
AU
AL
AU
0
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
1111-1111 2222-2222
3333-3333
AL
0
1111-1111 2222-2222
xxxx-xxxx
xxxx-xxxx
1111-1111 3333-3333
4444-4444 5555-5555
AU
1
1111-1111 3333-3333
xxxx-xxxx
xxxx-xxxx
4444-4444 5555-5555
—
—
—
Cmd
0
1111-1111 3333-3333 4444-4444 5555-5555 1111-1111 3333-3333
—
6666-6666
AL
0
1111-1111 3333-3333 4444-4444 5555-5555 1111-1111 6666-6666
—
—
Cmd
1
1111-1111 6666-6666 4444-4444 5555-5555 4444-4444 5555-5555
—
7777-7777
AL
1
1111-1111 6666-6666 4444-4444 5555-5555 4444-4444 7777-7777
8888-8888 9999-9999
AU
0
1111-1111 6666-6666 4444-4444 7777-7777 8888-8888 9999-9999
Target Address Holding Register and BAR Number Indicator
The PCI core provides two features that reduce overhead on setup of Target transfers in quad-port 64-bit addressing mode.
First, the PCI core’s Target control logic detects the page size of the base address register (BAR) that matched the
current PCI address, and only transfers the address bytes necessary to send the page address, and not the virtual
address of the page, to the FPGA application. The bar bus is synchronous to the pciclk, so it must be qualified with
treq which is on the fclk clock domain.
Second, the PCI core utilizes an optional address holding register so that only the least significant portion of the
address that is different from the previous address is sent to the FPGA application. Utilization of this feature usually
reduces the amount of address that must be transferred, but may require that the FPGA application build a copy of
the holding register in order to reconstruct the address. For this reason, this feature is optional and can be disabled
via a bit in the FPGA configuration manager.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Interrupt Request and System Error Generation
Two additional signals are available on the user side interface to request an interrupt on intan (pci_intan) and
force a system error on the PCI serrn pin (fpga_syserror). The pci_intan signal may be asserted low at any time.
It is not directly tied to any bus cycle. The fpga_syserror, as well, may be asserted high at any time. The serrn will
be subsequently asserted low during the next PCI transaction to this device. In generating pci_intan and
fpga_syserror, keep in mind that both signals need to be synchronous to pciclk.
Working in 32- and 64-bit Modes
The OR3LP26B works equally well in 32-bit and 64-bit PCI systems. In a 64-bit system, it is required that, during
reset, the host assert req64n low indicating that the bus width is 64 bits. The core will evaluate this signal at reset,
and automatically configure itself in either 32-bit or 64-bit mode. When configured in 32-bit mode, the core will 3state all upper PCI bus pins and apply a weak pull-up.
32-bit Transfers in a 64-bit System
Although designed as a 64-bit interface, the OR3LP26B also works efficiently in 32-bit mode. For single 32-bit
transfers, the core will perform a 32-bit PCI transfer. For burst transactions, the core will attempt 64-bit transfers,
and then back down to 32-bit mode if ack64n was not received. In general, the core will perform the PCI bus transaction that is most efficient on the bus.
Embedded Core/FPGA Interface Operation Summary
The following sections describe the FIFO bus operation, which is the interface between the embedded core and the
FPGA logic. Several configurations are possible for the FIFO bus, and the signal definitions can change for different modes. Tables are provided to define the modes, the signal definitions, and the states of each operation for
each mode.
Table 35 is an index to the state tables and timing figures provided for each of the operational modes of the FPGA
interface to the PCI core. Each of these operations is detailed on the pages shown in the table.
Table 35. Index to State Sequence Tables
Master/
Target
Master
Target
PCI Bus
Transaction Type
Mode
Write
Config,
Memory, I/O
Read
Config,
Memory, I/O
Write
Config
I/O
Memory, I/O
Memory
Config
I/O
Read
Memory
Single/Burst and Delayed/
Not Delayed
Nonburst
Burst
Nonburst
Burst
Nonburst
Delayed
Nonburst, Not Delayed
Burst
Nonburst
Delayed
Not Delayed
Nonburst
Nonburst Delayed
Burst
Burst Delayed
PCI Bus Timing
State Table
Figure Number
Figure 25
Figure 26
Figure 29
Figure 31
Figure 33
Figure 34
Figure 35
Figure 37
Figure 39
Figure 40
Figure 41
Figure 44
Figure 42
Figure 47
Figure 45
Table 36
Table 37*†
Table 38‡
Table 39
FPGA Bus Timing
Figure Number
Figure 27
Figure 28
Figure 30
Figure 32
§
Figure 36
Figure 38
Table 40
§
Figure 43
Figure 46
* Duplicate burst length and 16-bit address.
† 64-bit address supplied.
‡ 32-bit address supplied.
§ The FPGA interface does not participate in Target configuration operations.
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PCI Bus Core Detailed Description
Quad Port (continued)
Master (FPGA Initiated) Write
Operation Setup
Data Sheet
March 2000
Data Transfer
The FPGA application begins supplying the write data
by deasserting maenn and asserting mwdataenn. On
every cycle that mwdataenn is asserted, the PCI core
clocks data and its associated byte enables into the
Master write FIFO (64 deep by 36 bits wide in 32-bit
PCI mode; 32 deep by 72 bits wide in 64-bit PCI mode)
via bus mwdata.
In order to initiate a PCI Master write operation, the
FPGA application must supply the required information
in the specific order prescribed in Table 36. A master
command word and address must be accompanied by
assertion of the enable maenn. The definition of the
Master command word is shown in Table 25. The
FPGA application can use the value returned on bus
mstatecntr, the Master write counter’s present value,
to determine the counter’s next state, using the state
diagram for the particular operation being executed.
The counter’s next state must be determined because
the FPGA application must supply the data to the PCI
core that corresponds to the counter value being sent
from the core to the FPGA.
When the Master write FIFO contains four or fewer
empty locations, the PCI core asserts mw_afulln, the
almost full indicator. This allows some latency to exist
in the FPGA’s response without risking overfilling the
FIFO. When all locations in the Master write FIFO are
full, the PCI core asserts mw_fulln, the FIFO full indicator. Since data can be simultaneously written to and
read from the Master write FIFO, both mw_afulln and
mw_fulln can change states in either direction multiple
times in the course of a burst transfer.
Master State Counter
FIFO Empty
The PCI core provides a state counter,
mstatecntr[2:0], that informs the FPGA of the current
state of the PCI core's Master state counter. This state
counter determines what data is currently being provided by the PCI core or expected from the FPGA
application. This state counter transitions from one
state to another in a predictable fashion, and thus, it is
not strictly necessary to transmit its value to the FPGA.
Nonetheless, the value on bus mstatecntr can be used
to minimize FPGA logic or verify proper operation.
In addition to the full and almost full signals that report
when the Master write FIFO is currently unable to
receive data from the FPGA application, the PCI core
also provides the FIFO's empty signal. During a master
write burst transaction, the master write FIFO may go
empty, especially if the user side application is slow at
filling the FIFO. When this condition occurs, the master
will insert wait-states continuously until another word
(or the last word) is written into the FIFO and will not
terminate the transaction. On the target side, if the target is ready to accept more data, it will have trdyn
asserted which will disable it from terminating the
transaction as well. This can create a deadlock condition on the PCI bus. If the user application cannot supply any more data, and wishes to terminate the burst,
additional FPGA logic must be incorporated to detect
and accomplish the termination. The way to terminate
the transaction is to provide one last piece of data
(either real data or a dummy data word with all byte
enables disabled) along with mwlastcycn asserted.
The data provided by the PCI core to the FPGA application on bus mrdata is accompanied by a value on bus
mstatecntr. This value can be directly used by the
FPGA application to determine the proper use of that
data. This eliminates the need for logic in the FPGA to
duplicate this state counters in this case.
The data required from the FPGA application by the
PCI core on bus mwdata is also defined by the value
on bus mstatecntr. However, the state counter value is
being sent to the FPGA in the same cycle that the data
must be sent from the FPGA. Therefore, the FPGA
application must build its own copy of the state counter
value in this case. The value provided by the PCI core
can be used as the previous value, or it can be used to
verify the proper operation of the FPGA application's
logic.
FIFO Full/Almost Full
Table 25 lists the values of the state counter mstatecntr and the appropriate accompanying data.
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Data Sheet
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PCI Bus Core Detailed Description
Quad Port (continued)
Designing a Deadlock Timer
This design example is a method by which the user
application can detect the deadlock condition and terminate the burst transaction. Since the mw_emptyn
signal is on the pciclk clock domain, it must be resynchronized to the fclk domain. To accomplish this, double register mw_emptyn with fclk driven registers. The
mw_emptyn signal is fed as a clock enable and a synchronous clear to a counter, driven by fclk. The
counter's length may be designed to guarantee a certain time-out latency on the PCI bus. When the FIFO is
not empty (mw_emptyn = 1), the counter will stay
cleared. When the FIFO has been empty for an
extended period of time, the counter will count and
eventually overflow. This overflow indication can be
used to write one dummy word into the FIFO with the
byte enables disabled along with the mwlastcycn bit
asserted. The transaction will complete, and the core
will go back into an idle state.
Bursting
Instead of using a burst length, the Master write operation relies on mwlastcycn to inform the PCI core on a
cycle-by-cycle basis when additional burst data is to
follow. This allows the FPGA application to maintain
control over the length of the Master write burst for as
long as possible, but may require the FPGA application
to implement a burst length counter if needed. When
executing a burst Master write, a deasserted mwlastcycn must accompany every data element except the
last element on bus mwdata. The signal mwlastcycn
must remain asserted throughout a nonburst Master
write, since the last data phase is the only data phase.
The maximum burst length is limited only by the latency
timer. To initiate a burst, the starting address must be
aligned to a 64-byte boundary. If ad[2] is a 1, a single
transfer will be executed.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Reset
The FPGA application can apply the PCI core’s reset
signal mfifoclrn to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The mfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the m_ready signal will go low. After the
reset signal is deasserted high, m_ready will continue
to be low for 8—10 clock periods. The FPGA application should not continue normal operation until
m_ready is asserted high.
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that control and provide status to the FPGA application. The
signal pci_mcfg_stat provides the status, and mcfgshiftenn controls what information the status line provides. The pci_mcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
mcfgshiftenn = 1. When high, pci_mcfg_stat provides the wired-OR of the three status lines. If
pci_mcfg_stat gets set to a 1, indicating an error, then
the FPGA application may set mcfgshiftenn = 0 to
determine individual status. Once low, the
pci_mcfg_stat signal will output data parity error
detected on the first clock, target abort on received the
second clock, and master abort received on the third
clock.
Termination
Once initiated, Master write operations will repeat on
the PCI bus until one of the following occurs:
1. All data is sent.
2. An abort occurs (either Master or Target).
3. The PCI bus’s reset signal (rstn) is asserted.
If a PCI transaction is terminated with a retry or disconnect before all data has been written, the PCI core will
initiate another Master write operation, continuing from
that point.
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Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Master Write, Nonburst Transaction
Figure 27 (FPGA bus) and Figure 25 (PCI bus) show the timing of a Master write, nonburst transaction. In Figure
27, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing
the command word and the lower DWORD address on bus mwdata. On the next clock, for 64-bit address mode,
the upper DWORD address is provided on bus mwdata while asserting wmlastcycn. On the next clock, maenn is
deasserted and the one DWORD of data is provided on bus mwdata along with assertion of the Master write data
enable (mwdataenn). The forth clock provided the second DWORD of data an assertion of mwlastcycn. Since the
protocol for providing start-up data is fixed for a specific operation, the FPGA application can be preprogrammed
with the sequence, or can use the value of the Master state counter (mstatecntr) to assist in determination of the
next required data word of information. This completes the setup for this operation. Execution begins on the PCI
bus, as shown in Figure 25.
T0
T1
T2
T3
T4
clk
framen
ad
ADRS
DATA
c_ben
CMD
BEs
irdyn
devseln
trdyn
stopn
5-8847F).a
Figure 25. Master Write Single (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Master Write, Burst Transaction
Figure 28 (FPGA bus) and Figure 26 (PCI bus) show the timing of a 4-Quadword Master write burst transaction.
Operation is similar to that in the previous Master write, nonburst transaction, but extra data is supplied by the
FPGA application. In Figure 28, the transaction is initiated by the FPGA application asserting Master address
enable (maenn), while providing the command word and the lower DWORD address on bus mwdata. On the second clock, for 64-bit addressing, the upper DWORD address is supplied along with mwlastcycn. On the third
through tenth clocks, maenn is deasserted, the Master write data enable (mwdataenn) is asserted, and eight
DWORDs of data are provided on bus mwdata. On the tenth clock, mwlastcycn is asserted along with the last
DWORD of data. Since the protocol for providing start-up data is fixed for a specific operation, the FPGA application can be preprogrammed with the sequence, or can use the value of the Master state counter (mstatecntr) to
assist in determination of the next required DWORD of information. The PCI core knows that this is a burst operation because the FPGA application deasserts the Master write burst signal (mwlastcycn) during all but the final
data transfer cycle. Execution begins on the PCI bus, as shown in Figure 26. If the Master write PCI bus hold signal
(mwpcihold) is inactive, PCI bus activity will begin when the Master write FIFO goes nonempty; otherwise, the PCI
bus activity will wait until all data is loaded, as in this case, or the FIFO goes full. Execution begins on the PCI bus,
as shown in Figure 26.
T0
T1
T2
T3
T4
T5
T6
T7
clk
framen
ad
ADRS
D0
D1
c_ben
CMD
BE0
BE1
D2
BE2
D3
BE3
irdyn
devseln
trdyn
stopn
5-8848(F).a
Figure 26. Master Write 32-Byte Burst (PCI Bus, 64-Bit)
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Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
1
4
5
T6
fclk
m_ready
ma_fulln
X
mstatecntr
0
mcmd
X
CMD
mwdata
X
ADRS-L
0
X
ADRS-U
D0
D1
X
maenn
mwdataenn
mwlastcycn
mw_fulln
mw_afulln
mwpcihold
5-8839(F).a
Figure 27. Master Write Single Quadword (FPGA Bus, Quad-Port, 64-Bit Address)
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
fclk
m_ready
ma_fulln
X
mstatecntr
0
1
mcmd
X
CMD
mwdata
X
ADRS-L ADRS-U
4
5
4
5
4
5
4
5
0
X
D0
D1
D2
D3
D4
D5
D6
D7
X
maenn
mwdataenn
mwlastcycn
mw_fulln
mw_afulln
mwpcihold
5-8840(F).a
Figure 28. Master Write 32-Byte Burst (FPGA Bus, Quad-Port, 64-Bit Address)
Table 36. Quad-Port Master Write
mstatecntr
Next State of
mstatecntr
0
0
1
4
0
1
4
5 or 0
5
4 or 0
Description
Bus
maenn
mwdataenn
mwlastcycn
Idle
Address[31:0]
Address[63:32]
Data[31:0],
BE[3:0]
Data[63:32],
BE[7:4]
—
mwdata[35:0]
mwdata[35:0]
mwdata[35:0]
1
0
0
1
1
1
1
0
1
1
0
1
mwdata[35:0]
1
0
0*
* mwlastcycn is only 0 during the last data DWORD sent.
Notes:
For 32-bit addressing, state 1 is absent.
For 32-bit data, state 5 is absent.
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PCI Bus Core Detailed Description
Quad Port (continued)
Master (FPGA Initiated) Read
Operation Setup
In order to initiate a PCI Master read operation, the
FPGA application must supply the required information
in the specific order prescribed in Table 38. The command word, burst length (if supplied), and address
must be accompanied by assertion of the enable
maenn. The definition of the Master command word
was previously described in Table 25. The FPGA application can use the value returned on bus mstatecntr,
the Master state counter’s present value, to determine
the counter’s next state, using the state diagram for the
particular operation being executed. The counter’s next
state must be determined because the FPGA application must supply the data to the PCI core that corresponds to the counter value being sent from the core to
the FPGA.
Data Transfer
The FPGA application begins receiving the read data
by deasserting maenn and asserting mrdataenn. On
every cycle that mrdataenn is asserted, the PCI core
clocks data from the Master read FIFO (64 deep by
36 bits wide in 32-bit PCI mode; 32 deep by 72 bits
wide in 64-bit PCI mode) to the FPGA application via
bus mrdata.
FIFO Empty/Almost Empty
When the Master read FIFO contains four or fewer data
elements, the PCI core asserts mr_aemptyn, the
almost empty indicator. This allows some latency to
exist in the FPGA’s response without risking overreading the FIFO. When all locations in the Master write
FIFO are empty, the PCI core asserts mr_empty, the
FIFO empty indicator. Since data can be simultaneously written to and read from the Master read FIFO,
both mr_aemptyn and mr_emptyn can change states
in either direction multiple times in the course of a burst
data transfer.
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Data Sheet
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FIFO Full
In addition to the empty and almost empty signals that
report when the Master read FIFO is currently unable
to supply data to the FPGA application, the PCI core
also provides the FIFO's full signal. During a master
read burst transaction, the master read FIFO may go
full, especially if the user side application is slow at
unloading the FIFO. When this condition occurs, the
master will insert wait-states continuously until another
word is read from the FIFO, or the word count is
exhausted. On the target side, if the target is ready to
send more data, it will have trdyn asserted which will
disable it from terminating the transaction as well. This
can create a deadlock condition on the PCI bus. If the
user application cannot unload any more data, and
wishes to terminate the burst, additional FPGA logic
must be incorporated to detect and accomplish the termination. Two operations must occur to terminate the
current transaction. First, the fpga_mstopburstn signal must be asserted indicating to the core the master
request to terminate. Second, one additional word of
data must be read from the FIFO (only if the FIFO is
full). The signal fpga_mstopburstn needs to stay
asserted low until the ma_fulln flag is asserted low
indicating that the transaction has been terminated and
cleared.
Designing a Deadlock Timer
This design example is a method by which the user
application can detect this condition and terminate the
burst transaction. Since the mr_fulln and
fpga_mstopburstn signals are on the pciclk clock
domain, the deadlock counter will run on the pciclk
clock. The mr_fulln signal is fed as a clock enable and
a synchronous clear to a counter, driven by pciclk. The
counter's length may be designed to guarantee a certain time-out latency on the PCI bus. When the FIFO is
not full (mr_fulln = 1), the counter will stay cleared.
When the FIFO has been full for an extended period of
time, the counter will count and eventually overflow.
This overflow indication can be used to set the
fpga_mstopburstn signal indicating a request to stop
the burst. The overflow signal is then detected and synchronized onto the fclk domain to be used to read one
additional word from the FIFO. The transaction will
complete, and the core will go back into an idle state.
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PCI Bus Core Detailed Description
Quad Port (continued)
Bursting
The PCI core uses the burst count supplied during
operation setup to determine the Master read operation’s burst length (unlike the Master write, which uses
signal mwlastcycn). The burst length of 18 bits allows
bursts of up to 218 – 1 quad words to be specified. To
initiate a burst, the starting address must be aligned to
a 64-byte boundary. If ad[2] is a 1, a single transfer will
be executed.
Master Read Byte Enables
During master reads, byte enables are always supplied
by the Master to the Target, even though on reads the
data is flowing in the opposite direction. Thus, the byte
enables cannot be buffered in a FIFO alongside the
corresponding data. Also, the byte enables must be
presented on the bus by the Master at the same time
that the data is being presented on the bus by the Target (unless the Target uses trdyn to insert wait-states),
and so the data provided by the Target cannot depend
on the byte enables (once again, without wait-states).
Termination
Once initiated, Master read operations will repeat on
the PCI bus until the following occurs:
1. All data is received.
2. An abort occurs (either Master or Target).
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Reset
The FPGA application can apply the PCI core’s reset
signal mfifoclrn to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The mfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the m_ready signal will go low. After the
reset signal is deasserted high, m_ready will continue
to be low for 8—10 clock periods. The FPGA application should not continue normal operation until
m_ready is asserted high.
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that control and provide status to the FPGA application.
pci_mcfg_stat provides the status, and mcfgshiftenn
controls what information the status line provides. The
pci_mcfg_stat signal is always active and duplicates
the status contained in configuration status register at
location offset 0x04, bits 24, 28, and 29. To use this
status output, the FPGA application must keep mcfgshiftenn = 1. When high, pci_mcfg_stat provides the
wired-OR of the three status lines. If pci_mcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set mcfgshiftenn = 0 to determine
individual status. Once low, the pci_mcfg_stat signal
will output data parity error detected on the first clock,
target abort received on the second clock, and master
abort received on the third clock.
3. The fpga_mstopburstn signal is asserted.
4. The PCI bus’ reset signal (resetn) is asserted.
If a PCI transaction is terminated with a retry or disconnect before all data has been received, the PCI core
will initiate another Master read operation, continuing
from that point.
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PCI Bus Core Detailed Description Quad Port (continued)
Master Read, Nonburst Transaction
Figure 30 (FPGA bus) and Figure 29 (PCI bus) show the timing of a single Quadword Master read. In Figure 30,
the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the
command and burst length on bus mwdata. On the next clock, the FPGA application provides the DWORD
address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI bus
activity now begins as shown in Figure 29. Once data is transferred on the PCI bus and mr_emptyn is deasserted
high, the FPGA application asserts mrdataenn and two DWORDs of data are transferred on bus mrdata.
T0
T1
T2
T3
T4
T5
clk
framen
ad
c_ben
ADRS
CMD
DATA
BEs
irdyn
devseln
trdyn
stopn
5-8849(F).a
Figure 29. Master Read Single (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
TN
TN+1
TN+2
TN+3
TN+4
fclk
m_ready
ma_fulln
X
mstatecntr
0
1
mcmd
0
CMD
mwdata
X
BRST
mrdata
X
4
4
0
ADRS
5
0
D1
X
0
X
X
X
D0
maenn
mrdataenn
mwlastcycn
mrlastcycn
mr_emptyn
mr_aemptyn
5-8841(F).a
Figure 30. Master Read Single Quadword (FPGA Bus, Quad-Port, Specified Burst Length, 32-Bit Address)
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Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Master Read, Burst Transaction
Figure 32 (FPGA bus) and Figure 31 (PCI bus) show the timing of a four Quadword Master read burst. Operation is
similar to that in the Master read, nonburst transaction, but extra data words are supplied by the FPGA application.
In Figure 32, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while
providing the command and burst length on bus mwdata. On the next clock, the FPGA application provides the
DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI
bus activity now begins as shown in Figure 31. Once data is transferred on the PCI bus and mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and eight DWORDs of data are transferred on bus mrdata.
T0
T1
T2
T3
T4
T5
T6
T7
T8
clk
framen
ad
ADRS
c_ben
CMD
D0
BE0
D1
BE1
D2
BE2
D3
BE3
irdyn
trdyn
stopn
5-8850(F).a
Figure 31. Master Read 32-Byte Burst (PCI Bus, 64-Bit)
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Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
TN
TN+1 TN+2 TN+3 TN+4 TN+5 TN+6 TN+7 TN+8 TN+9 TN+10
fclk
m_ready
ma_fulln
X
mstatecntr
0
1
mcmd
X
CMD
mwdata
X
BRST ADRS
mrdata
X
4
4
5
4
X
5
4
5
4
5
0
D3
D4
D5
D6
D7
X
X
X
X
D0
D1
D2
maenn
mrdataenn
mwlastcycn
mrlastcycn
mr_emptyn
mr_aemptyn
5-8842(F).a
Figure 32. Master Read 32-Byte Burst (FPGA Bus, Quad-Port, Specified Burst Length, 32-Bit Address)
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Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Table 37. Quad-Port Master Read, Duplicate Burst Length and 16-Bit Address
mstatecntr
Next State
of
mstatecntr
0
0
0
4
4
5
5 or 0
4 or 0
Description
Bus
Idle
—
BE[7:0],
mwdata[35:0]
Address[15:0]
Data[31:0]
mrdata[31:0]
Data[63:32]
mrdata[31:0]
maenn
mwlastcycn mrlastcycn mrdataenn
1
0
1
0
1
1
1
1
1
1
1
1
1
0*
0
0
* mrlastcycn is 0 on the last data DWORD transfer.
Table 38. Quad-Port Master Read, Specified Burst Length and 64-Bit Address
mstatecntr
Next State
of
mstatecntr
0
0
0
1 or 4
1
2
4
5
2 or 4
4
5 or 0
4 or 0
Description
Bus
maenn
mwlastcycn mrlastcycn mrdataenn
Idle
BE[7:0], Burst
Length
Address[31:0]
Address[63:32]
Data[31:0]
Data[63:32]
—
mwdata[35:0]
1
0
1
1
1
1
1
1
mwdata[31:0]
mwdata[31:0]
mrdata[31:0]
mrdata[31:0]
0
0
1
1
1
0
1
1
1
1
1
0*
1
1
0
0
* mrlastcycn is 0 on the last data DWORD transfer.
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PCI Bus Core Detailed Description
Quad Port (continued)
Target (PCI Bus Initiated) Write
Operation Setup
The FPGA application waits for Target request, treqn,
from the PCI core to become active, indicating a Target
operation, either read or write. It then asserts Target
address enable, taenn, to clock out the command and
its address. Table 39 describes the specific order of
operation for a Target write transaction.
Bursts can be of any length, but will disconnect when
any of the following conditions occur:
■
tw_fulln is asserted low, and twburstpendn is deasserted high.
■
The maximum number of wait-states has been
inserted.
■
The BAR boundary has been crossed.
Target State Counter
The PCI core provides a state counter, tstatecntr[2:0],
that informs the FPGA of the current state of the PCI
core's Target state counter. This state counter determines what data is currently being provided by the PCI
core or expected from the FPGA application. This state
counter transitions from one state to another in a predictable fashion, and thus, it is not strictly necessary to
transmit its value to the FPGA. Nonetheless, the value
on bus tstatecntr can be used to minimize FPGA logic
or verify proper operation.
The data provided by the PCI core to the FPGA application on bus twdata is accompanied by a value on
bus tstatecntr. This value can be directly used by the
FPGA application to determine the proper use of that
data. This eliminates the need for logic in the FPGA to
duplicate these state counters in this case.
The data required from the FPGA application by the
PCI core on bus trdata is also defined by the value on
bus tstatecntr. However, the state counter value is
being sent to the FPGA in the same cycle that the data
must be sent from the FPGA. Therefore, the FPGA
application must build its own copy of the state counter
value in this case. The value provided by the PCI core
can be used as the previous value, or it can be used to
verify the proper operation of the FPGA application's
logic.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Transfer
For a Target write data transfer, the FPGA application
begins receiving the supplied data by deasserting
taenn and asserting twdataenn. On every cycle that
twdataenn is asserted, the FPGA application clocks
data out of the PCI core’s Target write FIFO (32 deep
by 36 bits wide in 32-bit PCI mode; 16 deep by 72 bits
wide in 64-bit PCI mode) via bus twdata.
FIFO Empty/Almost Empty
Data to be written is buffered in the Target write FIFO
(32 deep by 36 bits wide in 32-bit PCI mode; 16 deep
by 72 bits wide in 64-bit PCI mode). When this FIFO
contains four or fewer data elements, the PCI core
asserts tw_aempty, the FIFO almost empty indicator.
This allows some latency to exist in the FPGA’s
response without risking overreading the FIFO. When
the PCI core has read all data out of the Target write
FIFO, the PCI core asserts tw_emptyn, the FIFO
empty indicator. Since data can be simultaneously written to and read from the Target write FIFO, both
tw_aemptyn and tw_emptyn can change states in
either direction multiple times in the course of a burst
data transfer.
FIFO Full
In addition to the empty and almost empty signals that
report when the Target write FIFO is currently unable to
supply data to the FPGA application, the PCI core also
provides the FIFO's full signal. If the FIFO does go full,
the core will do one of two things. If twburstpendn is
deasserted high, the target will disconnect. If twburstpendn is asserted low, the target will assert up to eight
wait-states and then disconnect if still full. The FIFO full
flag is not generally used in user designs. If it is, however, keep in mind that it is synchronous to pciclk.
Bursting
Signal twlastcycn tells the FPGA application whether
the current write is a burst. The FPGA application continues to unload data from the FIFO as long as twlastcycn is inactive. The bursting will continue until either
twlastcycn is received, the FIFO becomes full, or the
BAR boundary is crossed. There is no fixed maximum
transfer word count.
Table 25 lists the values of the state counter tstatecntr
and the appropriate accompanying data.
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PCI Bus Core Detailed Description
Quad Port (continued)
Nondelayed Transactions
Target memory and I/O write operations may work in a
nondelayed transaction mode. Once the PCI core Target determines that it is the intended recipient, it
asserts devseln and trdyn and begins loading data
into the Target write FIFO. After the core accepts the
data element that fills the FIFO, the next data element
will cause a disconnect without data. The operation is
then complete on the PCI bus; even if the FPGA partially empties the Target write FIFO, no Target write
transaction, even a continuation of the previous burst,
will be accepted until the FIFO is emptied. The next
Target write operation will be considered a new transaction.
Delayed Transactions
Target I/O write operations may also be handled as
delayed transactions by asserting deltrn. The signal
deltrn was designed to be a static signal. This signal
should be tied off high or low depending upon whether
the FPGA application wishes to run delayed transactions. When asserting deltrn low, the PCI core will execute delayed transactions for I/O writes as well as all
target reads. In delayed transaction mode, the operation is not accepted on the first request. Instead, on the
first request, the PCI core records the command,
address, and first data word (32 or 64 bits) along with
its byte enables (4 or 8 bits). The first command and
address are put in the Target address FIFO, and the
data word and byte enables are put in the Target write
FIFO. The request is terminated in a retry, and the
FPGA application is informed as usual that a Target
request is pending via the assertion of treqn. Masters
are required to repeat requests terminated in retry until
data is moved (see PCI Specification section
3.3.3.2.2). The transaction status at this time is DWR
(delayed write request—see PCI Specification section
3.3.3.3.6), and subsequent requests will be terminated
in retry. When the FPGA application reads the FIFO
and empties it, the transaction status changes to DWC
(delayed write completion), and the next Target I/O
write that matches the stored command, address, data,
and byte enables will be accepted with a disconnect
with data, completing the transaction and clearing the
Target address and Target write FIFOs. Internal to the
ASIC, there is also a 15-bit time-out timer (known as
the discard timer). During a delayed I/O write transaction, this counter will begin counting. If the same master does not come back within 215 – 1 pciclk's to
complete the write, this timer will expire, resetting the
target state machines and setting a user side signal
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Data Sheet
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(disctimerexp = 1). From this point forward, any master performing a write (including the original master
coming back to complete the transfer) will be treated as
a new transaction. If monitoring this signal, keep in
mind that disctimerexp is synchronous to pciclk and
asserts high for one clock period.
Termination
Nondelayed write transaction completion occurs when
the last item remaining in the Target write FIFO has
been read by the FPGA application (although the
actual PCI bus transaction may have completed much
earlier). Delayed write transaction completion occurs
when the I/O write results in a disconnect with data.
The PCI core signals end of transaction to the FPGA
application by deasserting treqn.
Reset
The FPGA application can apply the PCI core’s reset
signal tfifoclrn to place the core’s target logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The tfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the t_ready signal will go low. After the reset
signal is deasserted high, t_ready will continue to be
low for 8—10 clock periods. The FPGA application
should not continue normal operation until t_ready is
asserted high.
Understanding and Using the pci_tcfg_stat Status
Signals
On the Target interface, there are two signals that control and provide status to the FPGA application. The
signal pci_tcfg_stat provides the status and tcfgshiftenn controls what information the status line provides. The pci_tcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
tcfgshiftenn = 1. When high, pci_tcfg_stat provides
the wired-OR of the three status lines. If pci_tcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set tcfgshiftenn = 0 to determine individual status. Once low, the pci_tcfg_stat signal will
output target abort signaled on the first clock, system
error signaled on the second clock, and parity error
detected on the third clock.
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PCI Bus Core Detailed Description
Quad Port (continued)
Initiating Target Aborts
There may be a need in an application to initiate a target abort condition on the PCI bus. In general, this is
asserted for only the most severe cases. The interface
signal, fpga_tabort, is used for this purpose. From the
PCI core's point of view, it needs to know whether to
perform a target abort at the very beginning of a transaction, so it is not possible to have a transaction
started, and then assert the fpga_tabort signal. The
signal fpga_tabort needs to be asserted before the
transaction begins, and it was not designed to be toggled on and off from transaction to transaction. Once
an FPGA application determines that it wants to apply
a target abort to any master that accesses it, it would
assert the fpga_tabort signal high. All future target
accesses will be terminated in an abort. In generating
this signal, keep in mind that this signal needs to be
synchronous to pciclk.
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Initiating PCI Target Retries
In contrast to target abort, many applications may
require to assert PCI target retries. In general, this may
be asserted for times when the FPGA application is
temporarily busy and unavailable to service PCI
requests. The interface signal, fpga_tretryn, is used
for this purpose. From the PCI core's point of view, it
needs to know whether to perform a target retry at the
very beginning of a transaction, so it is not possible to
have a transaction started and then assert the
fpga_tretryn signal. The signal fpga_tretryn needs to
be asserted before the transaction begins, and it was
not designed to be toggled on and off from transaction
to transaction. Once an FPGA application determines
that it wants to apply a target retry to any master that
accesses it, it would assert the fpga_tretryn signal
low. All future target accesses will be terminated in a
retry (disconnect without data). On the FPGA application side, no activity will occur. In generating this signal,
keep in mind that this signal needs to be synchronous
to pciclk.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Write to Configuration Space Transaction
Figure 33 shows the timing on the PCI interface for a Target write to configuration space. Accesses of configuration
space occur without any involvement of the FPGA interface. All configuration space accesses are disconnected
with data on the first data word and are thus restricted from bursting. Address decode speed is medium, and the
PCI core signals that it is ready to receive the data by asserting trdyn one cycle after devseln is asserted.
T0
T1
T2
T3
T4
T5
T6
clk
framen
ad
X
ADDRESS
DATA
X
c_ben
X
CMD
BYTE ENABLES
X
idsel
X
X
irdyn
devseln
trdyn
stopn
5-8851(F).a
Figure 33. Target Configuration Write (PCI Bus, 64-Bit)
104
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Write I/O, Delayed Transaction
Figure 34 (PCI bus) and Figure 36 (FPGA bus) show the timing for a Target I/O write operation that is handled as a
delayed transaction; that is, the operation completes on the local (FPGA) bus before completing on the PCI bus.
The FPGA application indicates its desire to do this by asserting signal deltrn. In Figure 34, three transactions are
shown: the first is the initial write that latches the command, address, data, and byte enables in the PCI core. The
core's Target logic then issues a retry, obligating the remote Master to continue to issue that identical request until
data is moved. Meanwhile, the information is relayed to the FPGA interface via the address and data FIFOs, triggering the FPGA interface exchange discussed below and shown in Figure 36. All subsequent read or write
requests to memory, I/O, or configuration space will result in retries, as shown in the second transaction of Figure
34. The third transaction is the final transaction that completes the transfer of data. Although the data was actually
latched and forwarded to the FPGA from the first transaction, it is not until the FPGA acknowledges that it has
received the data, by emptying the Target write FIFO, that the PCI core acknowledges to the remote Master that it
has received the data by performing a disconnect with data. The timing on this third transaction is identical to the
timing of the first except that trdyn accompanies stopn to indicate the disconnect with data.
The timing on the FPGA interface (Figure 36) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of target request (treqn), together with the new command on bus twdata.
The FPGA application responds by asserting target address enable (taenn) and accepting the command and subsequent lower DWORD address on bus twdata. On the next clock, the upper DWORD address is received along
with twlastcycn. This is followed by deassertion of taenn, assertion of Target write data enable (twdataenn), and
the receiving of the data on bus twdata.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0
Tc1
Tc2 Tc3 Tc4
Tc5
Tc6
clk
framen
ad[31:0]
X
ADRS
DATA
X
X
ADRS
DATA
X
X
ADRS
DATA
X
c/be[3:0]n
X
CMD
BEs
X
X
CMD
BEs
X
X
CMD
BEs
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
COMMAND, AND WRITE DATA LATCHED AS A
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE WRITE COMPLETION NOT RECEIVED.
TRANSACTION #3: DISCONNECTED WITH DATA
BECAUSE WRITE COMPLETION RECEIVED.
DELAYED WRITE REQUEST.
5-7372(F).a
Figure 34. Target I/O Write, Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Write Nonburst Transaction
Figure 35 (PCI bus) and Figure 36 (FPGA bus) show the timing on the PCI and FPGA interfaces, respectively, for a
Target memory nonburst write transaction. The timing on the PCI interface (Figure 35) is similar to that of an I/O
write except that, since bursts to memory space are allowed, the signal stopn is not asserted. The FPGA interface
timing is as shown in Figure 36, and is the same as the timing for memory and I/O write transactions.
T0
T1
T2
T3
T4
T5
clk
framen
ad
c_ben
X
ADDRESS
DATA
X
X
CMD
BYTE ENABLES
X
irdyn
devseln
trdyn
stopn
5-8854(F).a
Figure 35. Target Write Memory Single (PCI Bus, 64-Bit)
106
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
T6
4
5
0
D1
X
fclk
t_ready
treqn
0
tstatecntr
tcmd
X
CMD
twdata
X
ADRS-L
X
ADRS-U
D0
taenn
twdataenn
twlastcycn
tw_emptyn
tw_aemptyn
5-8843(F).a
Figure 36. Target Write Single Quadword (FPGA Bus, Quad-Port, 64-Bit Address)
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Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Target Write Memory Burst Transaction
Figure 37 (PCI bus) and Figure 38 (FPGA bus) show the timing for a Target memory write burst of four Quadwords.
The timing on the PCI interface (Figure 37) is typical for a medium-speed decode Target. Note that trdyn is
asserted at the earliest possible time, which is concurrent with assertion of devseln. In the example of a four Quadword burst, the FIFO is not filled, so execution continues to completion. This would also be the case for a burst of
any length when the FPGA application is capable of unloading the FIFO as fast as the PCI interface is loading it. If
the Target write FIFO becomes full, the PCI core Target will disconnect without data on the first data word it cannot
accept.
The timing on the FPGA interface (Figure 37) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of target request (treqn), together with the new command on bus tcmd. The
FPGA application responds by asserting target address enable (taenn) and accepting the address on bus twdata.
This is followed by deassertion of taenn, assertion of Target write data enable (twdataenn), and the receiving of
the data on bus twdata. The FPGA application is informed that the last 32 bits of data is being presented when Target write burst (twlastcycn) is asserted.
T0
T1
T2
T3
T4
T5
T6
T7
T8
clk
framen
ad
X
ADDRESS
D0
D1
D2
D3
c_ben
X
CMD
BE0
BE1
BE2
BE3
irdyn
devseln
trdyn
stopn
5-8855(F)
Figure 37. Target Memory Write 32-Byte Burst (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
4
5
4
5
4
5
4
5
0
D5
D6
D7
X
T12
fclk
t_ready
treqn
tstatecntr
0
tcmd
X
CMD
twdata
X
ADRS
X
D0
D1
D2
D3
D4
taenn
twdataenn
twlastcycn
tw_emptyn
tw_aemptyn
5-8844(F).a
Figure 38. Target Write Memory 32-Byte Burst (FPGA Bus, Quad-Port, 32-Bit Address)
Table 39. Quad-Port Target Write
tstatecntr
Next State of
tstatecntr
0
0
1
4
0
1 or 4
4
5 or 0
5
4 or 0
Description
Bus
treqn
twlastcycn
taenn
Idle
Address[31:0]
Address[63:32]
Data[31:0],
BE[3:0]
Data[63:32],
BE[7:4]
—
twdata[35:0]
twdata[32:0]
twdata[35:0]
1
0
0
0
1
1
0
1
1
0
0
1
twdata[35:0]
1†
0*
1
* treqn is deasserted high on the last data DWORD.
† twlastcycn is asserted low on the last data DWORD.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port (continued)
Target (PCI Bus Initiated) Read
The Target read operation presents unique demands
on the PCI core because only in the Target read operation does the PCI core request data that is needed to
complete the transaction after the PCI transaction has
already begun on the PCI bus. Target latency rules
require that the data be acquired quickly or that the Target terminate the transaction with a retry/disconnect.
Also, once the transfer process is underway, the Target
does not know how much more data will be requested,
yet the Target must prefetch data so that it will be available if needed. Special signals and protocols are
described below to efficiently deal with these unique
demands.
Operation Setup
The FPGA application waits for Target request, treqn,
from the PCI core to be active, indicating a Target operation, either read or write. It then asserts address
enable, taenn, to clock out the command and its
address. Table 40 describes the specific order of operation for a Target read transaction.
Bursts can be of any length, but will disconnect when
either of the following conditions occur:
■
tr_emptyn is asserted low.
■
The BAR boundary has been crossed.
Data Transfer
For a target read data transaction, the FPGA application begins supplying the requested data by deasserting taenn and asserting trdataenn. On every cycle that
trdataenn is asserted, the FPGA application clocks
data into the PCI core’s Target read FIFO (32 deep by
36 bits wide in 32-bit PCI mode; 16 deep by
72 bits wide in 64-bit PCI mode) via bus trdata. Since
the Target read FIFO will always be empty at the start
of a transaction, the first Target read request to a specific address will result in a retry, initiating a delayed
transaction (if signal trburstpendn is
deasserted high) or PCI bus wait-states (if signal
trburstpendn is asserted low).
Data Sheet
March 2000
lization of PCI bus bandwidth by causing a full buffer
contents to be burst, without wait-states, whenever the
PCI bus is claimed. This is explained in the Delayed
Transactions section.
FIFO Full/Almost Full
When the Target read FIFO contains four or fewer
empty locations, the PCI core asserts tr_afulln, the
almost full indicator. This allows some latency to exist
in the FPGA’s response without risking overfilling the
FIFO. When all locations in the Target read FIFO are
full, the PCI core asserts tr_fulln, the full indicator.
Since the data can be simultaneously written to and
read from the Target read FIFO, both tr_afulln and
tr_fulln can change states in either direction multiple
times in the course of a burst data transfer.
FIFO Empty
In addition to the full and almost full signals that report
when the Target read FIFO is currently unable to
receive data from the FPGA application, the PCI core
also provides the FIFO's empty signal. If the FIFO does
go empty, the core will do one of two things. If twburstpendn is deasserted high, the target will disconnect. If
twburstpendn is asserted low, the target will assert up
to eight wait-states and then disconnect if still empty.
The FIFO empty flag is not generally used in user
designs. If it is, however, keep in mind that it is synchronous to pciclk.
Bursting
Signal trlastcycn tells the FPGA application whether
the current read is a burst. One data element must be
supplied regardless of this signal’s state. The FPGA
application continues to supply data elements (contingent on the full bits) as long as trlastcycn is inactive.
Note that this may result in the discarding of unused
data elements supplied in excess of the PCI transaction’s needs. Burst transfers are done either as continuous data phases if read data continues to be available
in the read data FIFO, or as a series of transfers terminated as disconnects without data. Bursts will continue
until either trlastcycn is received, the BAR boundary is
crossed, or a 218 physical page address is crossed.
The signal trpcihold can be asserted to hold off activation of the nonempty condition. While trpcihold is
active, the Target read FIFO empty flag will not change
to the nonempty state until it is full, but then will remain
in the nonempty state until that FIFO truly becomes
empty. Use of this signal can result in more efficient uti110
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Data Sheet
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PCI Bus Core Detailed Description
Quad Port (continued)
Delayed Transactions
Delayed transactions can be executed by asserting
deltrn low. When deltrn is asserted low, the PCI core
Target read logic will issue a retry whenever no Target
read operation is already pending. When this signal is
inactive-high, it will instead generate wait-states, and
continue to do so until either the FIFO becomes not
empty, when it will transmit the data, or until the maximum initial latency value (16 or 32 clock cycles) has
been reached. This signal should be inactive when
minimum latency is desired on the initial data word, at
the expense of overall PCI bus efficiency. Whereas disable delayed transactions affects the transaction’s
behavior on the initial data word, signal trburstpendn
affects behavior when the Target read FIFO empties.
When trburstpendn is inactive, a disconnect without
data results from an attempt to read from an empty
FIFO. With trburstpendn active, the PCI core will wait
for data from the FIFO by inserting wait-states (up to
the maximum subsequent latency value of 8, at which
time a disconnect without data will be generated).
Asserting trburstpendn will minimize latency for this
transaction’s data at the expense of overall PCI bus
efficiency. trburstpendn must remain static throughout
a Target read transaction.
Delayed transactions are very similar to a target retry
except that the address is actually stored in the core.
Delayed transactions are usually implemented in systems where the user side interface cannot supply the
first piece of data in 16 clock cycles. An example of this
may be that the user interface is connected to another
bus system. On a PCI target read, the user interface
must arbitrate for the user bus and get the necessary
data. Delayed transaction mode is used when the deltrn bit is asserted low. This bit is not a dynamic bit. It
must be set ahead of a transaction occurring. It is not
recommended to switch between delayed and nondelayed transactions dynamically.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
slow loading requested data, and the designer wishes
to utilize the PCI in the most efficient manner. Without
this signal, an external master will request data and
hold onto the PCI bus until either it has received it or it
gets terminated by latency timers, etc. A more efficient
method to utilize the PCI bus is to assert trpcihold,
load the FIFOs, and then deassert it. While the trpcihold signal is asserted, the core thinks that the FIFOs
stay empty even though they are slowly filling with data.
Requests from an external master are terminated in
retries. When the trpcihold signal is deasserted (or the
FIFO becomes full), the core will allow an external
master to come in, the data will be burst across the PCI
bus as fast as the master will allow, and the transaction
will end. In generating trpcihold, keep in mind that this
signal needs to be synchronous to pciclk.
Termination
Normal transaction completion occurs immediately
upon completion of the PCI bus transfer, even if extra
data remains in the Target read FIFO. When the PCI
transaction ends either normally, or as retry, disconnect, or Target abort, the PCI core signals end of transaction to the FPGA application by deasserting treqn.
When treqn deasserts, the FPGA application must
immediately deassert trdataenn.
Reset
The FPGA application can apply the PCI core’s reset
signal tfifoclrn to place the core’s target logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The tfifoclrn signal is synchronous with fclk and must
be asserted for a minimum of three clock periods. During reset, the t_ready signal will go low. After the reset
signal is deasserted high, t_ready will continue to be
low for 8—10 clock periods. The FPGA application
should not continue normal operation until t_ready is
asserted high.
When deltrn is low, a master read request is terminated in a target retry. On the user interface side, the
address is stored in the target address FIFO, and treqn
is asserted low. All future master requests are terminated in a retry until the address is read out of the
FIFO, data is loaded into the FIFO, and the same
request comes back to complete the transaction. In
generating this signal, keep in mind that this signal
needs to be synchronous to pciclk.
Another option the designer has using delayed transactions is to use the signal trpcihold. The signal trpcihold should be used when the user side interface is
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port (continued)
Understanding and Using the pci_tcfg_stat Status
Signals
On the Target interface, there are two signals that control and provide status to the FPGA application. The
signal pci_tcfg_stat provides the status, and tcfgshiftenn controls what information the status line provides. The pci_tcfg_stat signal is always active and
duplicates the status contained in configuration status
register at location offset 0x04, bits 24, 28, and 29. To
use this status output, the FPGA application must keep
tcfgshiftenn = 1. When high, pci_tcfg_stat provides
the wired-OR of the three status lines. If pci_tcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set tcfgshiftenn = 0 to determine individual status. Once low, the pci_tcfg_stat signal will
output target abort signaled on the first clock, system
error signaled on the second clock, and parity error
detected on the third clock.
112
Data Sheet
March 2000
Initiating Target Aborts
There may be a need in an application to initiate a target abort condition on the PCI bus. In general, this is
asserted for only the most severe cases. The interface
signal, fpga_tabort, is used for this purpose. From the
PCI core's point of view, it needs to know whether to
perform a target abort at the very beginning of a transaction, so it is not possible to have a transaction
started, and then assert the fpga_tabort signal. The
signal fpga_tabort needs to be asserted before the
transaction begins, and it was designed to be toggled
on and off from transaction to transaction. Once an
FPGA application determines that it wants to apply a
target abort to any master that accesses it, it would
assert the fpga_tabort signal high. All future target
accesses will be terminated in an abort. In generating
this signal, keep in mind that this signal needs to be
synchronous to pciclk.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Target Read from Configuration Space
Figure 39 shows the timing on the PCI interface for a Target read from configuration space. Accesses of configuration space occur without any involvement of the FPGA interface. All configuration space accesses are disconnected with data on the first data word, and are thus restricted from bursting. Address decode speed is medium,
and the PCI core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is
asserted.
T0
T1
T2
T3
T4
T5
T6
clk
framen
ad
X
ADDRESS
c_ben
X
CMD
idsel
X
X
DATA
X
BYTE ENABLES
X
X
irdyn
devseln
trdyn
stopn
5-8856(F).a
Figure 39. Target Configuration Read (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Read I/O, Delayed Transaction
Figure 40 (PCI bus) and Figure 43 (FPGA bus) show the timing for a Target I/O read that is handled as a delayed
transaction. In other words, the operation completes on the local (FPGA) bus before completing on the PCI bus.
The FPGA application indicates its desire to do this by driving the delayed transaction signal deltrn active-low. In
Figure 40, three transactions are shown: the first is the initial read that latches the command, address, and byte
enables. The PCI core’s Target logic then issues a retry, obligating the remote Master to continue to issue that identical request until data is moved. Meanwhile, the latched information is relayed to the FPGA interface via the
address FIFO, triggering the FPGA interface exchange discussed below and in Figure 43. All subsequent read or
write requests to memory or I/O space will result in retries, as shown in the second transaction of Figure 40. The
third transaction is the final transaction that completes the transfer of data. The timing on this third transaction is
identical to the timing of the first except that trdyn accompanies stopn to indicate the disconnect with data.
The timing on the FPGA interface (Figure 40) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of Target request (treqn), together with the new command on bus twdata.
The FPGA application responds by asserting Target address enable (taenn) and accepting the command and
lower DWORD address on bus twdata, after which taenn is deasserted. On the next clock, the upper DWORD
address is transferred. The FPGA application then accesses the requested data, asserts Target read data enable
(trdataenn), and transmits the data on bus trdata.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BEs
X
X
ADRS
X
X
CMD
BEs
X
X
ADRS
X
CMD
X
DATA
BEs
X
irdyn
evseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
DELAYED READ REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: DISCONNECTED WITH DATA
BECAUSE READ OPERATION COMPLETED.
5-8858(F).a
Figure 40. Target I/O Read, Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Read I/O, No Delayed Transaction
Figure 41 (PCI bus) and Figure 43 (FPGA bus) show the timing for a Target I/O read that is handled as an immediate execution; that is, the operation completes on the PCI bus immediately and then is presented to the FPGA via
the FPGA interface. The FPGA application indicates its desire to do this by deasserting signal deltrn. The PCI core
Target terminates the I/O read request by disconnecting with data on the first data word, thus disallowing bursting.
The PCI interface timing shown in Figure 41 is identical to the timing of the third (final) transaction of Target I/O
read, delayed transaction (Figure 40), which shows a Target I/O read with delayed transaction. Also, the FPGA
interface timing is as shown in Figure 43, regardless of whether delayed transactions are enabled.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
clk
framen
ad
X
ADDRESS
c_ben
X
CMD
X
BYTE ENABLES
X
DATA
BYTE ENABLES
X
X
irdyn
devseln
trdyn
stopn
5-8857(F).a
Figure 41. Target I/O Read, Not Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Read Memory, Nonburst, Delayed Transaction
Figure 42 (PCI bus) and Figure 43 (FPGA bus) show the timing for a Target memory nonburst read handled as a
delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn. The timing on
the PCI interface (Figure 42) is similar to that of an I/O read (Figure 40) except that stop is not asserted here to
cause disconnect with data, but rather the operation is free to continue since it is allowed to complete on the source
(PCI) bus before it completes on the destination (FPGA) bus. The FPGA interface timing is as shown in Figure 43
and is the same as the timing in the I/O accesses of Target I/O read, delayed transaction and Target I/O read, no
delayed transaction.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BEs
X
X
ADRS
X
X
CMD
BEs
X
X
ADRS
X
CMD
X
DATA
BEs
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: NORMAL COMPLETION
BECAUSE READ OPERATION COMPLETED.
DELAYED READ REQUEST.
5-8860(F).a
Figure 42. Target Memory Single Read, Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
4
5
T6
fclk
t_ready
treqn
tstatecntr
0
tcmd
X
CMD
twdata
X
ADRS-L
trdata
X
0
X
ADRS-U
X
D0
D1
X
taenn
trdataenn
twlastcycn
trlastcycn
tr_fulln
tr_afulln
5-8845(F).a
Figure 43. Target Read Single (FPGA Bus, Quad-Port, 64-Bit Address)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
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PCI Bus Core Detailed Description Quad Port (continued)
Target Read Memory, Nonburst, No Delayed Transaction
Figure 44 (PCI bus) and Figure 43 (FPGA bus) show the timing for a Target memory nonburst read handled as an
immediate (nondelayed) transaction. The FPGA application indicates its desire to do this by deasserting signal deltrn. The timing on the PCI interface is shown in Figure 44. Here the PCI core accepts the transaction without issuing a retry but does not immediately assert trdyn. Wait-states are inserted until the requested data is placed in the
Target read FIFO, at which time trdyn is asserted and the data is returned. If the FPGA application cannot fetch the
data within the initial/subsequent latency time, the PCI core issues a retry or disconnect without data. The FPGA
interface timing is as shown in Figure 43, and is the same as the timing in the accesses of Target I/O read, delayed
transaction, Target I/O read, no delayed transaction, and Target read memory nonburst, delayed transaction.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
clk
framen
ad
X
ADDRESS
c_ben
X
CMD: MEM RD
X
BYTE ENABLES
X
DATA
X
BYTE ENABLES
X
irdyn
devseln
trdyn
stopn
5-8859(F).a
Figure 44. Target Memory Read Single, Not Delayed (PCI Bus, 64-Bit)
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Read Memory Burst, Delayed Transaction
Figure 45 (PCI bus) and Figure 46 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a delayed transaction. The FPGA application indicates its desire to do this by asserting signal deltrn.
On the PCI interface (Figure 45), three transactions are shown. In the first, the PCI core responds to the request
after determining that the address matches one of its BARs by asserting devseln. However, since delayed transaction has been specified by the FPGA application by asserting signal deltrn, the PCI core issues a retry. The PCI
core now waits for the FPGA application to load the Target read FIFO; until this occurs, all memory and I/O
accesses result in retries as exemplified by the second transaction in Figure 45. After the required data is loaded
(either the first data word or a complete FIFO contents, depending on whether the Target read PCI bus hold signal
trpcihold is deasserted or asserted, respectively), the actual data transfer will occur as shown in the third transaction in Figure 45. The FPGA interface timing is as shown in Figure 46. This is similar to the timing for a Target nonburst read as shown in Figure 43 except that multiple data cycles are required as long as trlastcycn is inactivehigh.
Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 Tb7 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9
clk
framen
ad
X
ADRS
X
c_ben
X
CMD
BE0
X
X
ADRS
X CMD
X
BE0
X
X
ADRS
X
CMD
X
D0
BE0
D1 D2
D3
BE1 BE2 BE3
X
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
AND COMMAND LATCHED AS A
DELAYED READ REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE READ OPERATION NOT COMPLETED.
TRANSACTION #3: NORMAL COMPLETION
BECAUSE READ OPERATION COMPLETED.
5-8862(F).a
Figure 45. Target Memory Read 32-Byte Burst, Delayed (PCI Bus, 64-Bit)
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
4
5
4
5
4
5
4
5
T11
fclk
t_ready
treqn
0
tstatecntr
tcmd
X
CMD
X
twdata
X
ADRS
X
trdata
X
D0
D1
D2
D3
D4
D5
D6
D7
0
X
taenn
trdataenn
twlastcycn
trlastcycn
tr_fulln
tr_afulln
5-8846(F).a
Figure 46. Target Read Memory 32-Byte Burst (FPGA Bus, Quad-Port, 32-Bit Address)
120
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Target Read Memory Burst, No Delayed Transaction
Figure 47 (PCI bus) and Figure 46 (FPGA bus) show the timing for a Target memory burst read of four Quadwords
handled as a nondelayed transaction. Figure 47 shows the timing on the PCI interface is similar to that of an I/O
read (Figure 40) except that stop is not asserted here to cause disconnect with data, but rather the operation is free
to continue since it is allowed to complete on the source (PCI) bus before it completes on the destination (FPGA)
bus.
T0
T1
T2
T3
Tn0
Tn1
Tn2
Tn3
Tn4
Tn5
Tn6
clk
framen
ad
X
ADRS
c_ben
X
CMD
X
BE0
X
D0
BE0
D1
D2
BE1
D3
BE2
X
BE3
irdyn
devseln
trdyn
stopn
5-8861(F).a
Figure 47. Target Read Memory Burst, No Delayed (PCI Bus, 32-Bit)
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121
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Quad Port (continued)
Table 40. Quad-Port Target Read
tstatecntr
Next
State of
tstatecntr
Description
0
0
0
1 or 4
Idle
Address[31:0]
1
4
5
4
5 or 0
4 or 0
Bus
—
datatofpgax[7:0]
datatofpga[63:0]
Address[63:32] datatofpga[63:0]
Data[31:0]
datafmfpga[31:0]
Data[63:32]
datafmfpga[31:0]
treqn taenn trdataenn twlastcycn trlastcycn
1
0
1
0
1
1
1
1
1
1
0
0
1*
0
1
1
1
0
0
1
1
0†
0
1
1
* treqn is deasserted high on the last data DWORD.
† twlastcycn is asserted low on the last data DWORD.
122
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Configuration Space of the PCI Core
The following section describes the configuration space of the PCI core. This includes the layout and organization
as called out in the PCI Specification as well as details specific to the PCI core’s implementation. Note that the
term configuration has two meanings: in the FPGA context, it refers to the programming of the FPGA’s SRAM to
define its functionality, and in the PCI context, it refers to the process of initializing the personality of the PCI agent
residing at a specific location or card slot via a data space that is physically addressed. The PCI’s configuration
space is being discussed here.
PCI Bus Configuration Space Organization
Table 41 shows the layout of the PCI core’s configuration space. The header type is 00 hex (non-PCI-to-PCI
bridge). All required and many optional features are implemented. Note that the defined space extends beyond 3F
hex, and includes provisions for hot swap and FPGA configuration via the PCI bus. Table 42 further details the content and function of each register in the PCI configuration space.
Table 41. Configuration Space Layout
31
16 15
Device ID
Status
0
Vendor ID
Command
Class Code
Header Type
Latency Timer
Base Address Registers
BIST
Revision ID
Cache Line Size
Cardbus CIS Pointer
Subsystem ID
Max_Lat
Reserved
Reserved
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Subsystem Vendor ID
Expansion ROM Base Address
Reserved
Cap_Ptr
Min_Gnt
Interrupt Pin
Interrupt Line
FPGA Configuration Command-Status Register
FPGA Configuration Data Register
Scratch Register
Reserved
HS_CSR
Next Item
Capability ID
Reserved
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
3Ch
40h
44h
48c
40c
48h
54h
thru
FFh
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Configuration Space of the PCI Core (continued)
Table 42. Configuration Space Assignment
Bytes
Width
Bit
00—01
02—03
04—05
16
16
16
—
—
0
1
2
3
4
5
6
7
8
9
15—10
06—07
08
09—0B
0C
0D
0E
0F
10—27
28—2B
2C—2D
2E—2F
30—33
34
35—37
38—3B
16
8
24
8
8
8
8
192
32
16
16
32
8
24
32
4—0
5
6
7
8
10—9
11
12
13
14
15
—
—
—
7—3
2—0
—
—
—
—
—
—
—
—
—
—
Description
Vendor ID
Device ID
Command:
Enable I/O Space
Enable Memory Space
Enable Bus Master
Enable Special Cycle
Enable Mem Wr & Inv
Enable VGA Palette Snoop
Enable Par Err Response
Enable Stepping
Enable SERRn
Enable Fast Back-to-Back
Reserved
Status:
Reserved
66 MHz Capable
UDF Supported
Fast Back-to-Back
Data PERRn Detected
devseln Timing
Target Abort Signaled
Target Abort Received
Master Abort Received
System Error Signaled
Parity Error Detected
Revision ID
Class Code
Cache Line Size
Latency Timer:
Programmable Portion
Granularity = 8 clks
Header Type
BIST
BAR
Cardbus CIS Pointer
Subsystem Vendor ID
Subsystem ID
Expansion ROM Base Address
(Capabilities Pointer)
(Reserved)
(Reserved)
Read/Write
Initial Value
Read Only
Read Only
11C1h (Lucent)
5401h (OR3LP26B)
Read/Write
Read/Write
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read Only
Read/Write
Read/Write
Read Only
0
0
*
0
0
0
0
0
0
0
zeros
Read Only
Read Only
Read Only
Read Only
zeros
1
0
1
0
01b (medium)
0
0
0
0
0
*
*
zeros
†
Read Only
†
†
†
†
†‡
Read Only
Read Only
Read Only
Read/Write
Read Only
Read Only
Read Only
§
Read Only
Read Only
Read Only
Read Only
—
Read Only
Read Only
zeros
zeros
00h
zeros
*
zeros
zeros
*
zeros
50h
zeros
zeros
* These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration bit stream.
† These exhibit special behavior per the PCI Specification:
— Reads behave normally.
— Writing a 1 clears the bit to zero.
— Writing a 0 has no effect on the bit.
‡ This bit is set when the device detects any type of parity error from its own master or target.
§ Bytes 10—27 hex contain the base address registers (BARs).
— Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes
10—17, 18—1F, or 20—27 hex.
— Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI core’s behavior is not affected
by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is marked as
nonprefetchable (this is not a violation, since the nonprefetchable bit only says that data can’t be discarded once it has been sent over the
PCI bus; nevertheless, caution must be exercised when this bit is reset).
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Configuration Space of the PCI Core (continued)
Table 42. Configuration Space Assignment (continued)
Bytes
Width
Bit
3C
3D
3E
3F
40—41
9
8
8
8
16
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
42—43
44—47
48-4B
4C
50
51
52
16
32
32
32
8
8
7
6
5
4
3
2
1
0
Description
Interrupt Line
Interrupt Pin
Min_Gnt
Max_Lat
FPGA Config. Command-Status Register:
Gsr
PCI Core Global Set/Reset
ConfigFPGA Enable FPGA Config.
RdCfgN
Enable Readback
PrgmN
Reset FPGA Config. Logic
FastSlowN
Fast/Slow Config. Clock
BitErr_1
Error Signal from FPGA
BitErr_0
Error Signal from FPGA
CfgBusy
Cfg Not In Idle State
RdBkNext
Readback Handshake
PciRegVld
Configuration Handshake
SRFull
Shift Reg Full
SREmpty
Shift Reg Empty
HndShkErr
Handshake Error
InitN
FPGA’s INITN
Done
FPGA’s DONE
Mode
PCI Core Mode
(Reserved)
FPGA Config. Data Register
Scratch Register
Reserved for Manufacturing Testing
Capability ID
Next Item
Hot Swap Control Status Register:
INS
ENUMn Status - Insertion
EXT
ENUMn Status - Extraction
Reserved
Reserved
LOO
Reserved
EIM
ENUMn Signal Mark
Reserved
Read/Write
Initial Value
Read/Write
Read Only
Read Only
Read Only
zeros
01h (INTAn)
*
*
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
0
0
1
1
0
0
0
0
0
0
0
0
0
**
**
0
zeros
zeros
zeros
Footnote 7
06h (Hot Plug)
00h (Last item)
††
Read Only
Read Only
‡‡
‡‡
Read Only
Read Only
Read/Write
Read Only
Read/Write
Read Only
1
0
0
0
0
0
0
0
* These values are intended to be custom assigned, per the intended application, by assigning constants via the FPGA configuration bit
stream.
† These exhibit special behavior per the PCI Specification:
— Reads behave normally.
— Writing a 1 clears the bit to zero.
— Writing a 0 has no effect on the bit.
‡ This bit is set when the device detects any type of parity error from its own master or target.
§ Bytes 10—27 hex contain the base address registers (BARs).
— Any legal combination of memory and I/O BARs is permitted, as long as 64-bit BARs are naturally aligned, that is, they occupy bytes
10—17, 18—1F, or 20—27 hex.
— Memory BARs may be marked as prefetchable/nonprefetchable by setting/resetting bit 3; however, the PCI core’s behavior is not affected
by this setting. In particular, the Target read operation may discard unused FIFO read-ahead data even though the data space is marked
as nonprefetchable (this is not a violation, since the nonprefetchable bit only says that data can’t be discarded once it has been sent over
the PCI bus; nevertheless, caution must be exercised when this bit is reset).
** These signals are tied to the FPGA signal of the same name and are not initialized.
†† This 32-bit register is used during manufacturing test. Writes are not allowed; reads are allowed and cause no side effects, but the value
returned is undefined.
‡‡ These exhibit special behavior per the CompactPCI Hot Swap Specification:
— Reads behave normally.
— Writing a 1 clears the bit to zero.
— Writing a 0 has no effect on the bit.
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125
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
FPSC Configuration
Configuration via PCI Bus
The OR3LP26B FPSC provides the designer many
configuration options. In addition to all the configuration
options provided in the standard Series 3 architecture
(except Master parallel mode) including configuration
via the microprocessor and boundary-scan (JTAG)
interfaces, the OR3LP26B PCI FPSC also allows configuration via the PCI interface. With this capability,
many configuration schemes can be implemented. For
example, a generic FPSC configuration can be loaded
via a serial configuration PROM and updated via the
PCI bus or the microprocessor interface. The FPSC
can also be reprogrammed in the field, or the configuration can be dynamically modified to perform different
tasks.
The OR3LP26B is configured using locations 40 hex
through 47 hex. These registers are dedicated to the
FPSC configuration and readback functions, as
detailed in Tables 36 and 37. The FPGA configuration
control-status register (FCCSR) is a 16-bit register at
address 40 hex—41 hex, and the FPGA configuration
data register (FCDR) is a 32-bit register at address
44 hex—47 hex.
When the FPSC is configured via the PCI interface,
there is a priority issue that must be resolved. The Subsystem vendor ID and subsystem ID that reside at
2Ch—2Fh in the PCI configuration space can be
assigned during FPGA configuration, but these same
pieces of information may be needed by system software to determine which FPSC configuration bit stream
to use for each FPSC when two or more FPSCs reside
on one PCI bus. For this reason, the OR3LP26B FPSC
is designed to allow for two different configuration
schemes.
The first option is more flexible; in this scheme, the
FPSC is first configured without employing the PCI
interface (e.g., via serial PROM). The access to the
FPSC's configuration registers via the PCI interface
occurs after this first configuration completes, so that
when the subsystem vendor ID and subsystem ID are
finally read, they properly and uniquely identify the card
on which the FPSC resides. This initial configuration bit
stream is only required to provide correct subsystem
vendor ID and subsystem ID values for system software use, but it may in addition be the first version of
the FPSC's application code. The PCI system software
is then able to invoke the proper procedures that will
reconfigure the FPSC using the desired version of the
configuration bit stream.
The disadvantage of the first option is that it requires
that the FPSC be preconfigured prior to receiving the
working bit stream via the PCI interface. In a proprietary system, however, a second option may be
employed if the configuring software may already know
which bit stream to use to configure the FPSC. The
system software can simply locate the OR3LP26B by
reading the vendor ID and device ID, and then proceed
directly to FPSC configuration via the PCI bus. This
feature takes advantage of the fact that the PCI interface is functional even before the FPSC has been configured.
126
The following is an example sequence which configures the FPSC via the PCI interface:
1. Read the vendor ID and device ID registers. If the
vendor ID is 11C1 hex, the vendor, or chip manufacturer, is Lucent. If, in addition, the device ID is
5401 hex, the device is a Lucent OR3LP26B PCI
FPSC; go to step 2.
2. At this point, the configuration software may do one
of two things. If this is a proprietary system and the
configuration software already knows how to configure any Lucent OR3LP26B, the software may skip
the next two steps, and the FPSC does not need to
be preconfigured. If this is a standard system, the
configuration software must perform the next two
steps to uniquely identify the application that is utilizing the OR3LP26B.
3. Read the FCCSR [1] until Done goes active-high,
signaling that the FPSC preconfiguration operation
has completed, typically via a serial configuration
PROM.
4. Read the class code, revision ID, subsystem vendor
ID, and subsystem ID registers. This information is
programmed into the FPSC by the preconfiguration
step. This information is used by the configuration
software to locate the correct FPSC configuration
bit stream and driver for the FPSC's application,
and is provided by the manufacturer of the adapter
card containing the FPSC.
5. Read the FCCSR until bit 0 goes high. If communication with the FPSC is underway via the boundaryscan hardware, this signal will remain inactive-low
until it completes.
6. Write to the FCCSR three times, first with PrgmN
high, then low, then high.
7. Write to the FCCSR with ConfigFPGA high. This will
initiate an FPSC configuration session via the PCI
interface.
8. Wait for the RAM initialization to complete by monitoring FCCSR [2]. Wait for 1.5 ms, and then send
one word of all ones. If InitN is high, continue with
real data; otherwise, repeat or declare the problem.
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Data Sheet
March 2000
FPSC Configuration (continued)
9. Write a DWORD of FPSC configuration data to
FCDR. This will set pciregvld in the FCCSR to
active-high, indicating that it holds a valid DWORD
of data. The user should always continue to monitor initn and Done.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
3. Read the FCCSR until sregfull goes active-high,
indicating that a DWORD of data is available in register FCDR.
4. Read the data from the FCDR.
5. Repeat steps 3 and 4 until all readback data has
been accessed.
6. Write RdCfgN high.
10. Read the FCCSR until pciregvld goes inactivelow, and srempty goes high indicating that the
DWORD it contained has been transferred to the
shift register that feeds the serial configuration data
to the FPSC. The user should always continue to
monitor initn and Done.
10.Write CongfigFPGA low.
11. Repeat steps 9 and 10 until all the configuration
data has been written. The user should always
continue to monitor initn and Done.
Interaction Among Configuration Modes
12. Read the FCCSR and verify that Done went activehigh, indicating that the configuration was successful.
13. Write configFPGA low.
Readback via PCI interface
The procedure for performing a readback via the PCI
interface is similar to the above procedure for configuring, and also similar to the standard readback procedure. The steps are outlined below:
1. Read the FCCSR until bit 0 goes high. If communication with the FPSC is underway via the boundaryscan hardware, this signal will remain inactive-low
until it completes.
7. Write ConfigFPGA high (no pulse on prgmn)
8. Write all 1s to FCDR
9. Loop on FCCSR until srempty goes high and pciregvld goes low.
The basic configuration options, including configuration
via the microprocessor and boundary-scan interfaces,
are performed in a manner identical to that of ORCA
Series 3 FPGAs. FPSC configuration via the PCI interface is available at any time, either prior to or after the
FPSC has been configured and regardless of the value
to which the FPGA configuration mode pins (M2, M1,
and M0) have been strapped. In addition, a PCIdirected configuration will override any strapped configuration operation already underway, an FPGA configuration via the boundary-scan interface will override one
via the PCI interface, and the PRGM pin overrides
both.
2. Write to the FCCSR with rdcfgn active-low. This
enables the readback mode.
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127
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Clocking Options at FPGA/Core
Boundary
The OR3LP26B supports a wide variety of integrated
FPGA/core clocking schemes which, in conjunction
with the FIFO interfaces between the PCI bus and the
FPGA, gives the designer many flexible options.
The Master and Target FIFOs are independently
clocked on the FPGA side by either fclk1 or fclk2. The
clocks used for the Master FIFO and Target FIFO interfaces to the FPGA logic are independent when the
interface is configured in quad-port mode, but they
must be tied to the same clock signal for dual-port
mode.
Figure 48 illustrates the special clock paths provided to
service the clocking needs of PCI functions. The various clocking options shown in Figure 48 are discussed
below.
Although there are many clocking options, minimum
clock skew is obtained by following the following recommendations. This section is divided into internally generated clocks, external system clocks, external express
clocks, and external corner clocks that utilize the PLLs.
Refer to the Series 3L data sheet and application notes
for a full description of all of the clocking options available for the Series 3L parts.
PCI Clock as System Clock
The clock received from the PCI interface can be
brought across the PCI core into the FPGA logic section and used as the clock for the entire FPSC, or even
as the clock for the entire board on which the FPSC
resides. It is important that this signal be available via
the PCI core since PCI rules allow for only one load per
agent on the PCI bus clock. The FPSC incorporates
special clock lines for the purpose of distributing the
PCI clock; these lines are hard-connected to the PCI
core's circuitry but can also be passed up onto the
FPGA portion's clock grid. From there, in addition to
feeding clocks to all PFUs and PIOs, this clock can also
drive the clock inputs to the FPGA side of the Master
and/or Target FIFOs, and can be made available offchip.
Data Sheet
March 2000
that both the Master and Target logic and FIFOs can be
independently set to use the PCI clock or another
clock. Clocks can be fed from any I/O pad, from
express clock inputs, or from internal logic, and can be
fed via the programmable clock manager (PCM).
Internally Generated Clocks
■
There are no limitations for using 1 or 2 internally
generated clocks to connect to the fclk1 and/or fclk2
clock input pins.
External System Clocks
External system clocks are clock inputs that do not use
the three dedicated eclk input clock pins of the device.
■
Keep the clocks toward the center of a side instead
of in the corners for minimal skew across the FPGA.
■
The best skew across the FPGA/ASIC boundary is
obtained by selecting pins on the left or right side of
the die. Avoid using general I/O as clock inputs on
the top of the device.
■
Refer to the Series 3 clocking application note for
general FPGA clocking rules.
External Express Clocks
External express clocks are externally generated
clocks that enter on one of the three eclk pins of the
device.
■
The best skew across the FPGA/ASIC boundary is
obtained by selecting the eclk pin on the right side of
the device (eclkr). Avoid using the top or left side
eclk inputs.
Externally Generated Clocks Entering Through
PCM Input Pins
External PCM clocks are clocks entering and going
through the programmable clock managers.
■
When using a programmable clock manager, either
the upper right or lower left clock managers may be
used.
Clock Sourced from pciclk
■
There are no limitations for using the pciclk clock
output to connect to the fclk1 and/or fclk2 clock
input pins.
Local Clock as System Clock
The FIFO-buffered interface between the PCI logic and
the FPGA allows other clocks to be utilized in the
FPGA as well. The Master and Target interfaces each
have independent clock nets and can be connected to
the same or separate clocks. Essentially, this means
128
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Clocking Options at FPGA/Core Boundary (continued)
FPGA
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
PFU
FCLK1
PCICLK
FCLK2
PCI CORE
BUS MUX
NETWORK
BUS MUX
NETWORK
TARGET
READ
FIFO
TARGET
WRITE
FIFO
MASTER
WRITE
FIFO
MASTER
READ
FIFO
PCI BUS
INTERFACE
LOGIC
PCI CLOCK
5-7553(F)
Figure 48. FPSC Block Diagram and Clock Network
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129
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
FPGA Configuration Data Format
FPGA Configuration Data Frame
The ORCA Foundry development system interfaces
with front-end design entry tools and provides tools to
produce a fully configured FPSC. This section discusses using the ORCA Foundry development system
to generate configuration RAM data and then provides
the details of the configuration frame format.
Configuration data can be presented to the FPSC in
two frame formats: autoincrement and explicit. A
detailed description of the frame formats is shown in
Figure 49, Figure 50, and Table 43. The two modes are
similar except that autoincrement mode uses assumed
address incrementation to reduce the bit stream size,
and explicit mode requires an address for each data
frame. In both cases, the header frame begins with a
series of 1s and a preamble of 0010, followed by a
24-bit length count field representing the total number
of configuration clocks needed to complete the loading
of the FPSC.
Using ORCA Foundry to Generate
Configuration RAM Data
The configuration data bit stream defines the PCI
embedded core configuration, the FPGA logic functionality, and the I/O configuration and interconnection. The
data bit stream is generated by the ORCA Foundry
development tools. The bit stream created by the bit
stream generation tool is a series of 1s and 0s used to
write the FPSC configuration RAM. It can be loaded
into the FPSC using one of the configuration modes
discussed elsewhere in this data sheet.
For FPSCs, the bit stream is prepared in two separate
steps in the design flow. The configuration options of
the embedded core are specified using ORCA
OR3LP26B Design Kit Software at the beginning of the
design process. This offers the designer a specific configuration to simulate and design the FPGA logic to.
Upon completion of the design, the bit stream generator combines the embedded core options and the
FPGA configuration into a single bit stream for download into the FPSC.
The mandatory ID frame contains data used to determine if the bit stream is being loaded to the correct type
of ORCA device (i.e., a bit stream generated for an
OR3LP26B is being sent to an OR3LP26B). Error
checking is always enabled for Series 3+ devices,
through the use of an 8-bit checksum. One bit in the ID
frame also selects between the autoincrement and
explicit address modes for this load of the configuration
data.
A configuration data frame follows the ID frame. A data
frame starts with a one-start bit pair and ends with
enough one-stop bits to reach a byte boundary. If using
autoincrement configuration mode, subsequent data
frames can follow. If using explicit mode, one or more
address frames must follow each data frame, telling the
FPSC at what addresses the preceding data frame is to
be stored (each data frame can be sent to multiple
addresses).
Following all data and address frames is the postamble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
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Data Sheet
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FPGA Configuration Data Format (continued)
CONFIGURATION DATA
CONFIGURATION DATA
0 0 1 0
0 1
PREAMBLE LENGTH
COUNT
ID FRAME
0 1
CONFIGURATION
DATA FRAME 1
0 0
CONFIGURATION
DATA FRAME 2
POSTAMBLE
5-5759(F)
CONFIGURATION HEADER
Figure 49. Serial Configuration Data Format—Autoincrement Mode
CONFIGURATION DATA
0 0 1 0
PREAMBLE LENGTH
COUNT
0 1
ID FRAME
CONFIGURATION DATA
0 0
CONFIGURATION
DATA FRAME 1
0 1
ADDRESS
FRAME 1
0 0
CONFIGURATION
DATA FRAME 2
ADDRESS
FRAME 2
0 0
POSTAMBLE
5-5760(F)
CONFIGURATION HEADER
Figure 50. Serial Configuration Data Format—Explicit Mode
Table 43. Configuration Frame Format and Contents
Header
ID Frame
Configuration
Data
Frame
(repeated for each
data frame)
Configuration
Address
Frame
Postamble
11110010
24-bit Length Count
11111111
0101 1111 1111 1111
Configuration Mode
Reserved [41:0]
ID
Checksum
11111111
01
Data Bits
Alignment Bits = 0
Checksum
11111111
00
14 Address Bits
Checksum
11111111
00
11111111 111111
1111111111111111
Preamble.
Configuration frame length.
Trailing header—8 bits.
ID frame header.
00 = autoincrement, 01 = explicit.
Reserved bits set to 0.
20-bit part ID.
8-bit checksum.
Eight stop bits (high) to separate frames.
Data frame header.
Number of data bits depends upon device.
String of 0 bits added to bit stream to make frame header, plus
data bits reach a byte boundary.
8-bit checksum.
Eight stop bits (high) to separate frames.
Address frame header.
14-bit address of location to start data storage.
8-bit checksum.
Eight stop bits (high) to separate frames.
Postamble header.
Dummy address.
16 stop bits.
Note: For slave parallel mode, the byte containing the preamble must be 11110010. The number of leading header dummy bits must
be (n * 8) + 4, where n is any nonnegative integer and the number of trailing dummy bits must be (n * 8), where n is any positive
integer. The number of stop bits/frame for slave parallel mode must be (x * 8), where x is a positive integer. Note also that the bit
stream generator tool supplies a bit stream that is compatible with all configuration modes, including slave parallel mode.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
FPGA Configuration Data Format
(continued)
The length and number of data frames and information
on the PROM size for the OR3LP26B is given in Table
44.
Data Sheet
March 2000
If using either of the MPI modes or the PCI embedded
core to configure the FPSC, the specific type of bit
stream error is written to one of the MPI registers or a
PCI register, respectively, by the FPGA configuration
logic. The PGRM bit of the MPI control register or the
PCI embedded core can also be used to reset out of
the error condition and restart configuration.
Table 44. Configuration Frame Size
Devices
OR3LP26B
n of Frames
1880
Data Bits/Frame
292
Configuration Data (# of frames • # of
data bits/frame)
Maximum Total # Bits/Frame (align
bits, 01 frame start, 8-bit checksum,
eight stop bits)
548,960
312
Maximum Configuration Data
(# bits/frame • # of frames)
586,560
Maximum PROM Size (bits)
(add configuration header and postamble)
586,728
Bit Stream Error Checking
There are three different types of bit stream error
checking performed in the ORCA Series 3+ FPSCs:
ID frame, frame alignment, and CRC checking.
The ID data frame is sent to a dedicated location in the
FPSC. This ID frame contains a unique code for the
device for which it was generated. This device code is
compared to the internal code of the FPSC. Any differences are flagged as an ID error. This frame is automatically created by the bit stream generation program
in ORCA Foundry.
Each data and address frame in the FPSC begins with
a frame start pair of bits and ends with eight stop bits
set to 1. If any of the previous stop bits were a 0 when a
frame start pair is encountered, it is flagged as a frame
alignment error.
Error checking is also done on the FPSC for each
frame by means of a checksum byte. If an error is found
on evaluation of the checksum byte, then a
checksum/parity error is flagged.
FPGA Configuration Modes
There are eight methods for configuring the FPSC. Six
of the configuration modes are selected on the M0, M1,
and M2 input and are shown in Table 45. The seventh
mode is PCI bus configuration as previously discussed
and the eighth configuration mode is accessed through
the boundary-scan interface. A fourth input, M3, is
used to select the frequency of the internal oscillator,
which is the source for CCLK in some configuration
modes. The nominal frequencies of the internal oscillator are 1.25 MHz and 10 MHz. The 1.25 MHz frequency is selected when the M3 input is unconnected
or driven to a high state.
Note that the Master parallel mode of configuration that
is available in the ORCA Series 3 FPGAs is not available in the OR3LP26B. This is due to the use of Master
parallel configuration pins for the PCI bus interface.
More information on the general FPGA modes of configuration can be found in the ORCA Series 3 data
sheet.
Table 45. Configuration Modes
M2 M1 M0
CCLK
0
0
0
0
0
1
0
1
0
Output
Input
Output
0
1
1
Output
1
1
1
1
0
0
1
1
0
1
0
1
Output
Input
Configuration
Mode
Master Serial
Slave Parallel
Microprocessor:
Motorola* PowerPC
Microprocessor:
Intel † i960
Reserved
Async Peripheral
Reserved
Slave Serial
Data
Serial
Parallel
Parallel
Parallel
Parallel
Serial
* Motorola is a registered trademark of Motorola, Inc.
† Intel is a registered trademark of Intel Corporation.
When any of the three possible errors occur, the FPSC
is forced into an idle state, forcing INIT low. The FPSC
will remain in this state until either the RESET or PRGM
pins are asserted.
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Data Sheet
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Powerup Sequencing for Series OR3LP26B Device
ORCA Series OR3LP26B device use two power supplies: one to power the device I/Os and the ASIC core (VDD)
which is set to 3.3 V for 3.3 V operation and 5 V tolerance, and another supply for the internal FPGA logic (VDD2)
which is set to 2.5 V. It is understood that many users will derive the 2.5 V core logic supply from a 3.3 V power
supply, so the following recommendations are made as to the powerup sequence of the supplies and allowable
delays between power supplies reaching stable voltages.
In general, both the 3.3 V and the 2.5 V supplies should ramp-up and become stable as close together in time as
possible. There is no delay requirement if the VDD2 (2.5 V) supply becomes stable prior to the VDD (3.3 V) supply.
There is a delay requirement imposed if the V DD supply becomes stable prior to the VDD2 supply.
The requirement is that the VDD2 (2.5 V) supply transition from 0 V to 2.3 V within 15.7 ms if the VDD (3.3 V) supply
is already stable at a minimum of 3.0 V. If the VDD supply has not yet reached 3.0 V when the VDD2 supply has
reached 2.3 V, then the requirement is that the VDD2 supply reach a minimum of 2.3 V within 15.7 ms of when the
VDD supply reaches 3.0 V.
If the chosen power supplies cannot meet this delay requirement, it is always possible to hold-off configuration of
the FPGA by asserting INIT or PRGM until the VDD2 supply has reached 2.3 V. This process eliminates any power
supply sequencing issues.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection currents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 46. Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Storage Temperature
Tstg
–65
150
°C
I/O and ASIC Supply Voltage with Respect to
Ground
VDD
—
≤4.2
V
Internal FPGA Supply Voltage with Respect
to Ground
VDD2
—
≤3.2
V
Input Signal with Respect to Ground
CMOS Inputs
5 V Tolerant Inputs
—
—
–0.5
–0.5
VDD + 0.3
5.8
V
V
Signal Applied to High-impedance Output
—
–0.5
VDD + 0.3
V
Note: For PCI bus signals used for 5 V signaling and FPGA inputs used as 5 V tolerant, the maximum value is 5.8 V.
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Data Sheet
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Recommended Operating Conditions
Table 47. Recommended Operating Conditions
OR3LP26B
Mode
Commercial
Temperature Range
(Ambient)
I/O
Supply Voltage
(VDD)
Internal Supply Voltage
(VDD2)
0 °C to 70 °C
3.0 V to 3.6 V
2.38 V to 2.63 V
Note: The maximum recommended junction temperature (TJ) during operation is 125 °C.
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Electrical Characteristics
Table 48. Electrical Characteristics
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Parameter
Symbol
Input Voltage:
High
Low
VIH
VIL
Input Voltage:
High
Low
VIH
VIL
Output Voltage:
High
Low
VOH
VOL
Input Leakage Current
OR3LP26B
Test Conditions
Unit
Min
Max
50% VDD
GND – 0.5
VDD + 0.3
30% VDD
V
V
50% VDD
GND – 0.5
5.8 V
30% VDD
V
V
VDD = min, IOH = 6 mA or 3 mA
VDD = min, IOL = 12 mA or 6 mA
2.4
—
—
0.4
V
V
Input configured as CMOS
(clamped to VDD)
Input configured as TTL
(5 V tolerant)
IL
VDD = max, VIN = VSS or VDD
–10
10
µA
Standby Current
IDDSB
(TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)
internal oscillator running, no output loads,
inputs at VDD or GND
(after configuration)
—
TBD
mA
Standby Current
IDDSB
(TA = 25 °C, VDD = 3.3 V, VDD2 = 2.5 V)
internal oscillator stopped, no output loads,
inputs at VDD or GND
(after configuration)
—
TBD
mA
Data Retention Voltage
VDR
TA = 25 °C
TBD
—
V
Powerup Current
IPP
TBD
—
mA
Input Capacitance
CIN
TA = 25 °C,
VDD = 3.3 V, VDD2 = 2.5 V
Test frequency = 1 MHz
—
8
pF
COUT
TA = 25 °C,
VDD = 3.3 V, VDD2 = 2.5 V
Test frequency = 1 MHz
—
8
pF
DONE Pull-up Resistor*
RDONE
—
100
—
kΩ
M[3:0] Pull-up Resistors*
RM
—
100
—
kΩ
I/O Pad Static Pull-up
Current*
IPU
VDD = 3.6 V,
VIN = VSS, TA = 0 °C
14.4
50.9
µA
I/O Pad Static
Pull-down Current
IPD
VDD = 3.6 V,
VIN = VSS, TA = 0 °C
26
103
µA
I/O Pad Pull-up Resistor*
RPU
VDD = all, VIN = VSS, TA = 0 °C
100
—
kΩ
I/O Pad Pull-down
Resistor
RPD
VDD = all, VIN = VDD, TA = 0 °C
50
—
kΩ
Output Capacitance
Power supply current at approximately
1 V, within a recommended power supply
ramp rate of 1 ms—200 ms
* On the Series 3 devices, the pull-up resistor will externally pull the pin to a level 1.0 V below VDD.
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Data Sheet
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Timing Characteristics
Description
The most accurate timing characteristics are reported
by the timing analyzer in the ORCA Foundry Development System. A timing report provided by the development system after layout divides path delays into logic
and routing delays. The timing analyzer can also provide logic delays prior to layout. While this allows routing budget estimates, there is wide variance in routing
delays associated with different layouts.
The logic timing parameters noted in the Electrical
Characteristics section of this data sheet are the same
as those in the design tools. In the PFU timing, symbol
names are generally a concatenation of the PFU operating mode and the parameter type. The setup, hold,
and propagation delay parameters, defined below, are
designated in the symbol name by the SET, HLD, and
DEL characters, respectively.
The values given for the parameters are the same as
those used during production testing and speed binning of the devices. The junction temperature and supply voltage used to characterize the devices are listed
in the delay tables. Actual delays at nominal temperature and voltage for best-case processes can be much
better than the values given.
It should be noted that the junction temperature used in
the tables is generally 85 °C. The junction temperature
for the FPGA depends on the power dissipated by the
device, the package thermal characteristics (ΘJA), and
the ambient temperature, as calculated in the following
equation and as discussed further in the Package
Thermal Characteristics Summary section:
Supply VDD)
Power Supply Voltage
TJ
(°C)
3.0 V
3.3 V
3.6 V
–40
0
25
85
100
125
0.82
0.91
0.98
1.00
1.23
1.34
0.72
0.80
0.85
0.99
1.07
1.15
0.66
0.72
0.77
0.90
0.94
1.01
Table 50. Derating for Commercial Devices (I/O
Supply VDD2)
Power Supply Voltage
TJ
(°C)
2.38 V
2.5 V
2.63 V
–40
0
25
85
100
125
0.86
0.94
0.99
1.00
1.23
1.33
0.71
0.79
0.84
0.99
1.05
1.13
0.67
0.73
0.77
0.92
0.96
1.03
Note: The derating tables shown above are for a typical critical path
that contains 33% logic delay and 66% routing delay. Since the
routing delay derates at a higher rate than the logic delay,
paths with more than 66% routing delay will derate at a higher
rate than shown in the table. The approximate derating values
vs. temperature are 0.26% per °C for logic delay and 0.45%
per °C for routing delay. The approximate derating values vs.
voltage are 0.13% per mV for both logic and routing delays at
25 °C.
TJmax = TAmax + (P • ΘJA) °C
Note: The user must determine this junction temperature to see if the delays from ORCA Foundry
should be derated based on the following derating tables.
Table 49 and Table 50 provide approximate power supply and junction temperature derating for OR3LP26B
commercial devices. The delay values in this data
sheet and reported by ORCA Foundry are shown as
1.00 in the tables. The method for determining the
maximum junction temperature is defined in the Package Thermal Characteristics section. Taken cumulatively, the range of parameter values for best-case vs.
worst-case processing, supply voltage, and junction
temperature can approach three to one.
Table 49. Derating for Commercial Devices (I/O
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Timing Characteristics (continued)
In addition to supply voltage, process variation, and operating temperature, circuit and process improvements of
the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those
listed for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing
parameters may be several speed grades higher than that designated on a product brand. Design practices need
to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing.
The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal interconnect
in the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to
reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates
prior to design compilation based on fan-out. This is because the CAE software may delete redundant logic
inserted by the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting.
The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet.
The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and
the values they reflect are described below.
Propagation Delay—The time between the specified reference points. The delays provided are the worst case of
the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state
enable.
Setup Time—The interval immediately preceding the transition of a clock or latch enable signal, during which the
data must be stable to ensure it is recognized as the intended value.
Hold Time—The interval immediately following the transition of a clock or latch enable signal, during which the
data must be held stable to ensure it is recognized as the intended value.
3-State Enable—The time from when a 3-state control signal becomes active and the output pad reaches the
high-impedance state.
Clock Timing
Table 51. ExpressCLK (ECLK) and Fast Clock (fclk) Timing Characteristics
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Device
(TJ = 85 °C, VDD = min)
ECLK Delay (middle pad)
ECLK Delay (corner pad)
fclk Delay (middle pad)
fclk Delay (corner pad)
Symbol
Min
Max
Unit
eclkm_del
eclkc_del
fclkm_del
fclkc_del
—
—
—
—
1.99
4.20
5.24
7.46
ns
ns
ns
ns
Notes:
The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIC clock input.
The fclk delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay
and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
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Data Sheet
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Timing Characteristics (continued)
Table 52. General-Purpose Clock Timing Characteristics (Internally Generated Clock)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Device (TJ = 85 °C, VDD = min)
OR3LP26B
Symbol
clk_del
Min
—
Max
3.95
Unit
ns
Notes:
This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on
any side of the device which is then distributed to the PFU/PIO clock inputs. If the clock tree input used is located at any other PIC, see the
results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the general clock network. The delay will be reduced if any of the clock branches are not
used. See pin-to-pin timing in Table 55 for clock delays of clocks input on general I/O pins.
Table 53. OR3LP26B ExpressCLK to Output Delay (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description
(TJ = 85 °C, VDD = min)
Min
Max
Unit
ECLK Middle Input Pin→OUTPUT Pin (Fast)
—
5.82
ns
ECLK Middle Input Pin→OUTPUT Pin (Slewlim)
—
6.61
ns
ECLK Middle Input Pin→OUTPUT Pin (Sinklim)
—
11.05
ns
Additional Delay if ECLK Corner Pin Used
—
2.2
ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the ExpressCLK network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The given timing requires that the input clock pin be located at
one of the six ExpressCLK inputs of the device, and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
ECLK
ECLK
5-4846(F).a
Figure 51. ExpressCLK to Output Delay
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Timing Characteristics (continued)
Table 54. OR3LP26B Fast Clock (fclk) to Output Delay (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description
(TJ = 85 °C, VDD = min)
Min
Max
Unit
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)
ECLK Middle Input Pin →OUTPUT Pin (Fast)
—
9.06
ns
ECLK Middle Input Pin →OUTPUT Pin (Slewlim)
—
9.86
ns
ECLK Middle Input Pin →OUTPUT Pin (Sinklim)
—
14.3
ns
Additional Delay if ECLK Corner Pin Used
—
2.2
ns
Notes:
Timing is without the use of the programmable clock manager (PCM).
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the six ExpressCLK inputs of the device and that a PIO FF be used.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
CLKCNTRL
ECLK
fclk
5-4846(F).b
Figure 52. Fast Clock to Output Delay
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Data Sheet
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Timing Characteristics (continued)
Table 55. OR3LP26B General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description
(TJ = 85 °C, VDD = min)
Min
Max
Unit
Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Clock Input Pin (mid-PIC) →OUTPUT Pin (Fast)
—
9.86
ns
Clock Input Pin (mid-PIC) →OUTPUT Pin (Slewlim)
—
10.66
ns
Clock Input Pin (mid-PIC) →OUTPUT Pin (Sinklim)
—
15.10
ns
Additional Delay if Non-mid-PIC Used as Clock Pin
—
0.83
ns
Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Additional Delay if Output Not on Same Side as Input Clock Pin
—
0.83
ns
Note: This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing
to the PIO CLK input, the clock→Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock
branches are not used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the
device and that a PIO FF be used. For clock pins located at any other PIO, see the results reported by ORCA Foundry.
PIO FF
D
Q
OUTPUT (50 pF LOAD)
SCLK
5-4846(F)
Figure 53. System Clock to Output Delay
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Timing Characteristics (continued)
Table 56. OR3LP26B Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description
(TJ = 85 °C, VDD = min)
Min
Max
Unit
Input to ECLK Setup Time (middle ECLK pin)
0.97
—
ns
Input to ECLK Setup Time (middle ECLK pin, delayed data input)
9.98
—
ns
Input to ECLK Setup Time (corner ECLK pin)
0.0
—
ns
Input to ECLK Setup Time (corner ECLK pin, delayed data input)
8.11
—
ns
Input to ECLK Hold Time (middle ECLK pin)
0.0
—
ns
Input to ECLK Hold Time (middle ECLK pin, delayed data input)
0.0
—
ns
Input to ECLK Hold Time (corner ECLK pin)
0.0
—
ns
Input to ECLK Hold Time (corner ECLK pin, delayed data input)
0.0
—
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIO clock input.
PIO ECLK LATCH
INPUT
D
Q
CLKCNTRL
CLK
ECLK
5-4847(F).b
Figure 54. Input to ExpressCLK Setup/Hold Time
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 57. OR3LP26B Input to Fast Clock Setup/Hold Time (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description
(TJ = 85 °C, VDD = min)
Min
Max
Unit
Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)
ns
Input to fclk Setup Time (middle ECLK pin)
0.0
—
ns
Input to fclk Setup Time (middle ECLK pin, delayed data input)
5.58
—
Input to fclk Setup Time (corner ECLK pin)
0.0
—
ns
Input to fclk Setup Time (corner ECLK pin, delayed data input)
3.77
—
ns
Input to fclk Hold Time (middle ECLK pin)
4.62
—
ns
Input to fclk Hold Time (middle ECLK pin, delayed data input)
0.0
—
ns
Input to fclk Hold Time (corner ECLK pin)
6.54
—
ns
Input to fclk Hold Time (corner ECLK pin, delayed data input)
0.0
—
ns
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
The fclk delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay
and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
PIO FF
INPUT
D
Q
CLKCNTRL
ECLK
fclk
5-4847(F).a
Figure 55. Input to Fast Clock Setup/Hold Time
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 58. OR3LP26B Input to General System Clock (SCLK) Setup/Hold Time (Pin-to-Pin)
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Min
Max
Input to SCLK Setup Time
0.0
—
Unit
ns
Input to SCLK Setup Time (delayed data input)
5.02
—
ns
Input to SCLK Hold Time
5.47
—
ns
Input to SCLK Hold Time (delayed data input)
Additional Hold Time if Non-mid-PIC Used as SCLK Pin (no
delay on data input)
0.0
—
ns
0.83
—
ns
Description (TJ = 85 °C, VDD = min)
Notes:
The pin-to-pin timing parameters in this table should be used instead of results reported by ORCA Foundry.
This clock delay is for a fully routed clock tree that uses the clock network. It includes both the input buffer delay and the clock routing to the PIO
FF CLK input. The delay will be reduced if any of the clock branches are not used. The given setup (delayed and no delay) and hold (delayed)
timing allows the input clock pin to be located in any PIO on any side of the device, but a PIO FF must be used. The hold (no delay) timing
assumes the clock pin is located at one of the four middle PICs on any side of the device and that a PIO FF is used. If the clock pin is located
elsewhere, then the last parameter in the table must be added to the hold (no delay) timing.
PIO FF
INPUT
D
Q
SCLK
5-4847(F)
Figure 56. Input to System Clock Setup/Hold Time
Table 59. OR3LP26B PCI and FPGA Interface Clock Operation Frequencies
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Speed
–8
Description (TI = 85 °C, VDD = min, VDD2 = min)
Signal
Clk (PCI clock)
Fclk1 (user interface clock)
Fclk2 (user interface clock)
Unit
Min
Typ
Max
0
0
0
66*
66†
66†
66*
100‡
100‡
MHz
MHz
MHz
* The PCI clock frequency is based on the internal register to register frequency and the 66 MHz PCI I/O specifications.
† The maximum user interface clock frequencies are values based on registering all signals at the FPGA/ASIC boundary. This number will be
lower depending on the design implementation and number of FPGA logic levels into and out of the ASIC.
‡ This is the typical operating frequency for a real design that does not register signals at the FPGA/ASIC boundary.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 60. OR3LP26B FPGA to PCI, and PCI to FPGA, Combinatorial Path Delays
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
Source
Destination
pci_intan (FPGA side)
clk (PCI side)
rstn (PCI side)
intan (PCI side)
pciclk (FPGA side)
pci_rstn (FPGA side)
Min
Max
Unit
—
—
—
4.094
3.226
1.622
ns
ns
ns
Notes:
The FPGA to PCI combinatorial path delays include the ASIC path delay and the output buffer delay under a 10 pF load. They do not include the
interbuf delay on the FPGA side.
The PCI to FPGA combinatorial path delays include the ASIC input buffer delay, and ASIC path delay entering the FPGA. They do not include
the interbuf delay on the FPGA side.
Table 61. OR3LP26B FPGA Side Interface Combinatorial Path Delay Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
Source
Destination
fifo_sel
fifo_sel
twdataenn
twdataenn
datatofpga[63:0]
datatofpgax[7:0]
twlastcycn
datatofpga[63:0] (dualport mode)
datatofpgax[7:0] (dualport mode)
twdata[35:0] (quad-port
mode)
trlastcycn
mrlastcycn
twlastcycn
tstatecntr[2:0]
datatofpga[63:0] (dualport mode)
datatofpgax[7:0] (dualport mode)
twdata[35:0] (quad-port
mode)
treqn
mstatecntr[2:0]
mstatecntr[2:0]
pci_tdfg_stat
pci_mdfg_stat
twdataenn
twdataenn
trdataenn
mrdataenn
taenn
taenn
taenn
taenn
taenn
taenn
maenn
mcmd
tcfgshiftenn
mcfgshiftenn
Min
Max
Unit
—
—
—
—
3.253
2.652
5.220
6.114
ns
ns
ns
ns
—
5.847
ns
—
6.114
ns
—
—
—
—
—
5.558
5.237
5.406
4.767
5.944
ns
ns
ns
ns
ns
—
5.763
ns
—
5.944
ns
—
—
—
—
—
4.958
5.860
5.662
4.227
5.300
ns
ns
ns
ns
ns
Note: The combinatorial path parameters are measured from the input to the output (both on the FPGA side), excluding the interbufs, which
traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the
clock and data paths.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 62. OR3LP26B Interbuf Delays
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
Min
Max
Unit
—
—
0.592
0.429
ns
ns
Interbuf from FPGA to ASIC
Interbuf from ASIC to FPGA
Note: The interbufs are buffers that interface between the FPGA and the ASIC.
Table 63. OR3LP26B FPGA Side Interface Clock to Output Delays, pciclk Synchronous Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
mw_emptyn
mr_fulln
tr_emptyn
tw_fulln
tcmd[3:0]
bar[2:0]
Min
Max
Unit
—
—
—
—
—
—
4.985
4.458
4.686
4.703
4.345
4.139
ns
ns
ns
ns
ns
ns
Note: The clock to out parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the
ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data
paths.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 64. OR3LP26B FPGA Side Interface Clock to Output Delays, fclk Synchronous Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
fpga_msyserror
pci_mcfg_stat
ma_fulln
mstatecntr[2:0]
m_ready
mw_fulln
mw_afulln
datatofpga[63:0] (dual-port mode)
datatofpgax[7:0] (dual-port mode)
mrdata[35:0] (quad-port mode)
twdata[35:0] (quad-port mode)
mr_emptyn
mr_aemptyn
mrlastcycn
disctimerexpn
pci_tcfg_stat
treqn
t_ready
tstatecntr[2:0]
tw_emptyn
tw_aemptyn
twlastcycn
tr_fulln
tr_afulln
trlastcycn
Min
Max
Unit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.779
4.404
4.314
5.796
4.758
4.348
3.734
8.679
7.974
8.479
6.867
3.840
3.684
7.536
3.436
3.777
4.932
4.817
4.355
3.893
3.759
7.557
4.358
3.915
5.533
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The clock to out parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which
traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the
clock and data paths.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Timing Characteristics (continued)
Table 65. OR3LP26B FPGA Side Interface Input Setup Delays, pciclk Synchronous Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
fpga_mbusyn
deltrn
mwpcihold
fpga_mstopburstn
fpga_tabort
fpga_tretryn
twburstpendn
trpcihold
trburstpendn
fpga_syserror
Min
Max
Unit
–0.514
–1.486
–1.190
–1.208
1.744
0.864
–1.561
–1.542
–1.557
–0.828
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The input setup parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the
ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data
paths.
Table 66. OR3LP26B FPGA Side Interface Input Setup Delays, fclk Synchronous Signals
OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C.
Description (TI = 85 °C, VDD = min, VDD2 = min)
mcfgshiftenn
maenn
mfifoclrn
mcmd[3:0]
mwdataenn
datafmfpga[63:0] (dual-port mode)
datafmfpgax[7:0] (dual-port mode)
mwdata[35:0] (quad-port mode)
trdata[35:0] (quad-port mode)
mwlastcycn
mrdataenn
tcfgshiftenn
tfifoclrn
taenn
twdataenn
trdataenn
Min
Max
Unit
1.752
4.777
5.934
5.251
4.806
5.333
5.978
5.978
5.226
4.896
3.246
1.209
3.395
3.893
3.677
3.773
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: The input setup parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which
traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the
clock and data paths.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Input/Output Buffer Measurement Conditions
VCC
GND
1 kΩ
TO THE OUTPUT UNDER TEST
50 pF
TO THE OUTPUT UNDER TEST
50 pF
A. Load Used to Measure Propagation Delay
B. Load Used to Measure Rising/Falling Edges
5-3234(F)
Note: Switch to VDD for TPLZ/TPZL; switch to GND for TPHZ/TPZH.
Figure 57. ac Test Loads
ts[i]
PAD ac TEST LOADS (SHOWN ABOVE)
OUT
out[i]
VDD
out[i] VDD/2
VSS
PAD 1.5 V
OUT
0.0 V
TPLL
TPHH
5-3233.a(F)
Figure 58. Output Buffer Delays
PAD
IN
in[i]
3.0 V
PAD IN 1.5 V
0.0 V
VDD
in[i] VDD/2
VSS
TPLL
TPHH
5-3235(F)
Figure 59. Input Buffer Delays
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Embedded Master/Target PCI Interface
Data Sheet
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Output Buffer Characteristics
90
110
80
IOL
IOL
90
OUTPUT CURRENT, IO (mA)
OUTPUT CURRENT, IO (mA)
100
80
70
60
IOH
50
40
30
20
70
60
50
40
IOH
30
20
10
10
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
OUTPUT VOLTAGE, VO (V)
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
5-6865(F)
Figure 60. Sinklim (TJ = 25 °C, VDD = 3.3 V)
5-6866(F)
Figure 63. Sinklim (TJ = 125 °C, VDD = 3.0 V)
140
120
IOL
IOL
100
OUTPUT CURRENT, IO (mA)
OUTPUT CURRENT, IO (mA)
120
100
80
60
IOH
40
20
80
60
IOH
40
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
3.5
0.0
OUTPUT VOLTAGE, VO (V)
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
5-6868(F)
5-6867(F)
Figure 61. Slewlim (TJ = 25 °C, VDD = 3.3 V)
Figure 64. Slewlim (TJ = 125 °C, VDD = 3.0 V)
140
120
IOL
IOL
100
OUTPUT CURRENT, IO (mA)
OUTPUT CURRENT, IO (mA)
120
100
80
60
IOH
40
80
60
IOH
40
20
20
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
OUTPUT VOLTAGE, VO (V)
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1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE, VO (V)
5-6867(F)
Figure 62. Fast (TJ = 25 °C, VDD = 3.3 V)
0.5
5-6868(F)
Figure 65. Fast (TJ = 125 °C, VDD = 3.0 V)
149
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Estimating Power Dissipation
The total operating power dissipated is estimated by summing the FPGA standby (IDDSB), internal, and external
power dissipated, in addition to the PCI core internal and I/O power.
Table 67. PCI Core Internal Power Dissapation
Power Dissipated
Operating Frequency
(MHz)
Min
Max
33
66
—
—
292
584
Unit
mW
mW
The following discussion relates to the FPGA portion of the device. The internal and external power is the power
consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The
total operating power is as follows:
PT = Σ PPLC + Σ PPIC
The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output
power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two:
PPFU = 0.078 mW/MHz
For each PFU output that switches, 0.136 mW/MHz needs to be multiplied times the frequency (in MHz) that the
output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor;
for example, 20%.
The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/
clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power
from the subset of those PFUs that are configured as synchronous memory. Therefore, the clock power can be calculated for the four parts using the following equations:
OR3LP26B Clock Power
P = [0.22 mW/MHz
+ (0.39 mW/MHz/Branch) (# Branches)
+ (0.008 mW/MHz/PFU) (# PFUs)
+ (0.002 mW/MHz/PIO (# PIOs)]
For a quick estimate, the worst-case (typical circuit) OR3LP26BB clock power = 4.8 mW/MHz
The following discussions are relavant to FPGA I/Os and the PCI core I/Os. The power dissipated in a PIC is the
sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power
dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or
input/output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as
POUT. This is because the output feeds back to the input.
The power dissipated by an input buffer is (VIH = VDD – 0.3 V or higher) estimated as:
PIN = 0.09 mW/MHz
The ac power dissipation from an output or bidirectional is estimated by the following:
POUT = (CL + 8.8 pF) × VDD2 × F Watts
where the unit for CL is farads, and the unit for F is Hz.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information
This section describes the pins and signals that perform FPGA-related functions. Any pins not described in Table 7
or here in Table 68 are user-programmable I/Os. During configuration, the user-programmable I/Os are 3-stated
and pulled-up with an internal resistor. If any FPGA function pin is not used (or not bonded to package pin), it is
also 3-stated and pulled-up after configuration.
Table 68. FPGA Common-Function Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
VDD
—
3.3 V power supply.
VDD2
—
2.5 V power supply.
Ground supply.
GND
—
RESET
I
During configuration, RESET forces the restart of configuration and a pull-up is
enabled. After configuration, RESET can be used as an FPGA logic direct input,
which causes all PLC latches/FFs to be asynchronously set/reset.
CCLK
I
In the Master and asynchronous peripheral modes, CCLK is an output which strobes
configuration data in. In the slave or synchronous peripheral mode, CCLK
is input synchronous with the data on DIN or D[7:0]. In microprocessor and PCI
modes, CCLK is used internally and output for daisy-chain operation.
DONE
I
As an input, a low level on DONE delays FPGA start-up after configuration.*
O
As an active-high, open-drain output, a high level on this signal indicates that configuration is complete. DONE is also used in the embedded PCI core start-up sequence.
DONE has an optional pull-up resistor.
PRGM
I
PRGM is an active-low input that forces the restart of configuration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
RD_CFG
I
This pin must be held high during device initialization until the INIT pin goes high. This
pin always has an active pull-up.
During configuration, RD_CFG is an active-low input that activates the TS_ALL function and 3-states all of the I/O.
After configuration, RD_CFG can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream
option, a high-to-low transition on RD_CFG will initiate readback of the configuration
data, including PFU output states, starting with frame address 0.
RD_DATA/TDO
O
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides configuration data out. If used in boundary scan, TDO is test data out.
I
During powerup and initialization, M0—M2 are used to select the configuration mode
with their values latched on the rising edge of INIT; see Table 45 for the configuration
modes. During configuration, a pull-up is enabled.
Special-Purpose Pins
M0, M1, M2
I/O
M3
I
I/O
After configuration, M2 can be a user-programmable I/O.*
During powerup and initialization, M3 is used to select the speed of the internal oscillator during configuration with their values latched on the rising edge of INIT. When
M3 is low, the oscillator frequency is 10 MHz. When M3 is high, the oscillator is
1.25 MHz. During configuration, a pull-up is enabled.
After configuration, M3 can be a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 68. FPGA Common-Function Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
TDI, TCK, TMS
I
If boundary scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited
once configuration is complete. Even if boundary scan is not used, either TCK or
TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled
during configuration.
I/O After configuration, these pins are user-programmable I/O.*
RDY/RCLK/
MPI_ALE
O
During configuration in peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the
same status is also available on D7 in asynchronous peripheral mode.
O
During the Master parallel configuration mode, RCLK is a read output signal to an
external memory. This output is not normally used.
I
In i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
HDC
O
High During Configuration is output high until configuration is complete. It is used as
a control output indicating that configuration is not complete.
LDC
O
Low During Configuration is output low until configuration is complete. It is used as a
control output indicating that configuration is not complete.
INIT
CS0, CS1
I/O INIT is a bidirectional signal before and during configuration. During configuration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an activelow open-drain output, INIT is held low during power stabilization and internal clearing of memory. As an active-low input, INIT holds the FPGA in the wait-state before
the start of configuration.
I
CS0 and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. The FPGA is selected when CS0 is low and CS1 is
high. During configuration, a pull-up is enabled.
I/O After configuration, these pins are user-programmable I/O pins.*
RD/MPI_STRB
I
RD is used in the asynchronous peripheral configuration mode. A low on RD
changes D7 into a status output. As a status indication, a high indicates ready, and a
low indicates busy. WR and RD should not be used simultaneously. If they are, the
write strobe overrides.
I
This pin is also used as the microprocessor interface (MPI) data transfer strobe. For
PowerPC, it is the transfer start (TS). For i960, it is the address/data strobe (ADS).
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*
WR
I
WR is used in the asynchronous peripheral configuration mode. When the FPGA is
selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an
internal data buffer. WR and RD should not be used simultaneously. If they are, the
write strobe overrides.
I/O After configuration, this pin is a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 68. FPGA Common-Function Pin Descriptions (continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
MPI_IRQ
O
MPI active-low interrupt request output.
I/O If the MPI is not in use, this is a user-programmable I/O.
MPI_BI
O
PowerPC mode MPI burst inhibit output.
I/O If the MPI is not in use, this is a user-programmable I/O.
MPI_ACK
O
In PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA)
output. For i960 MPI operation, it is the active-low ready/record (RDYRCV) output.
If the MPI is not in use, this is a user-programmable I/O.
MPI_RW
I
In PowerPC mode MPI operation, this is the active-low write/ active-high read control
signals. For i960 operation, it is the active-high write/active-low read control signal.
I/O If the MPI is not in use, this is a user-programmable I/O.
MPI_CLK
I
This is the clock used for the synchronous MPI interface. For PowerPC, it is the CLKOUT signal. For i960, it is the system clock that is chosen for the i960 external bus
interface.
I/O If the MPI is not in use, this is a user-programmable I/O.
A[4:0]
I
For PowerPC operation, these are the PowerPC address inputs. The address bit
mapping (in PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/
A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs
are not used in i960 MPI mode.
I/O If the MPI is not in use, this is a user-programmable I/O.
A[1:0]/MPI_BE[1:0]
I
For i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are
used as address bits A[1:0] in i960 byte-wide operation.
D[7:0]
I
During Master parallel, peripheral, and slave parallel configuration modes, D[7:0]
receive configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0 is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the address/data pins for i960 microprocessor mode.
I/O After configuration, the pins are user-programmable I/O pins.*
DIN
I
During slave serial or Master serial configuration modes, DIN accepts serial configuration data synchronous with CCLK. During parallel configuration modes, DIN is the
D0 input. During configuration, a pull-up is enabled.
I/O After configuration, this pin is a user-programmable I/O pin.*
DOUT
O
During configuration, DOUT is the serial data output that can drive the DIN of daisychained slave LCA devices. Data out on DOUT changes on the falling edge of
CCLK.
I/O After configuration, DOUT is a user-programmable I/O pin.*
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Package Compatibility
Table 69 lists the number of user I/Os available for the ORCA OR3LP26B FPSC for each available package. Each
package has six dedicated configuration pins and six dedicated special-purpose pins.
Table 70 provides the package pin and pin function for the ORCA OR3LP26B FPSC in each available package. The
bond pad name is identified in the PIC nomenclature used in the ORCA Foundry design editor.
When the number of FPGA bond pads exceeds the number of package pins, bond pads are unused. When the
number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects).
When a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device pad column
for the FPGA.
Table 69. ORCA OR3LP26B I/Os Summary
User I/Os*
VDD
VDD2
VSS
Configuration/Special-Purpose Pins†
PCI Interface Pins
Unused Pins
PCI Core Section
FPGA Section
352-Pin PBGA
680-Pin PBGAM
162
16
11
68
12
93
26
0
242
56
76
100
12
93
90
11
* User I/O count includes three ExpressCLK inputs.
† Configuration pins: CCLK, DONE, RESET, PRGM, RD_CFG;
Special-purpose pins: RD_DATA/TDO, HDC, LDC, INIT, M0, M1, M2.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
VSS
VSS
VSS*
VSS*
VDD
VDD
VDD*
VDD*
VSS
VSS
VSS*
VSS*
PL1D
I/O
B1
D1
PL1C
I/O
C2
F4
PL1B
I/O
C1
F3
PL1A
I/O
D2
F2
VDD
VDD
VDD*
VDD*
PL2D
I/O-A0-MPI_BE0
D3
F1
PL2C
I/O
—
G5
PL2B
I/O
—
G4
PL2A
I/O
D1
G2
PL3D
I/O
E2
G1
PL3C
I/O
—
H5
PL3B
I/O
E4
H4
PL3A
I/O
E3
H2
VSS
VSS
VSS*
VSS*
PL4D
I/O
—
—
VDD2
VDD2
E1
VDD2
PL4C
I/O
F2
H1
PL4B
I/O
G4
J5
PL4A
I/O
—
J4
PL5D
I/O
F3
J3
PL5C
I/O
—
J2
PL5B
I/O
—
J1
PL5A
I/O
—
K5
VDD
VDD
VDD*
VDD*
PL6D
I/O
F1
K4
PL6C
I/O
G2
K3
PL6B
I/O
G1
K2
PL6A
I/O
—
K1
PL7D
I/O-A1-MPI_BE1
G3
L5
PL7C
I/O
—
L4
PL7B
I/O
—
L2
PL7A
I/O
—
L1
VSS
VSS
VSS*
VSS*
PL8D
I/O
H2
M5
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PL8C
I/O
J4
M4
PL8B
I/O
H1
M2
PL8A
I/O-A2
H3
M1
PL9D
I/O
J2
N5
PL9C
I/O
J1
N4
PL9B
I/O
K2
N3
PL9A
I/O-A3
J3
N2
VDD
VDD
VDD*
VDD*
PL10D
I/O
K1
—
VDD2
VDD2
—
VDD2
PL10C
I/O
—
N1
PL10B
I/O
—
P5
PL10A
I/O
K4
P4
PL11D
I/O
L2
P3
PL11C
I/O
—
P2
PL11B
I/O
—
P1
PL11A
I/O-A4
K3
R5
VSS
VSS
VSS*
VSS*
PL12D
I/O
L1
R4
PL12C
I/O
—
R2
PL12B
I/O
—
R1
PL12A
I/O
M2
—
VDD2
VDD2
—
VDD2
PL13D
I/O
M1
T5
PL13C
I/O
—
T4
PL13B
I/O
—
T2
PL13A
I/O
L3
T1
VSS
VSS
VSS*
VSS*
PECKL
I-ECKL
N2
U5
PL14D
—
—
—
PL14C
I/O
M4
U3
PL14B
I/O
N1
U2
PL14A
I/O-MPI_CLK
M3
U1
VDD
VDD
VDD*
VDD*
PL15D
I/O
P2
V1
PL15C
——
—
—
VDD2
VDD2
P4
VDD2
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PL15B
I/O
P1
V2
PL15A
I/O-MPI_RW
N3
V3
VSS
VSS
VSS*
VSS*
PL16D
I/O-MPI_ACK
R2
V4
PL16C
I/O
—
V5
PL16B
I/O
—
W1
PL16A
I/O
P3
W2
PL17D
I/O
R1
W4
PL17C
I/O
—
W5
PL17B
I/O
—
Y1
PL17A
I/O-MPI_BI
T2
Y2
VSS
VSS
VSS*
VSS*
PL18D
I/O
R3
Y4
PL18C
I/O
—
Y5
PL18B
I/O
—
AA1
PL18A
I/O-SECKLL
T1
AA2
PL19D
†
No Connect
R4
AA3
PL19C
No Connect†
—
AA4
PL19B
No Connect†
—
AA5
PL19A
I/O-MPI_IRQ
U2
AB1
VDD
VDD
VDD*
VDD*
PL20D
No Connect†
T3
AB2
PL20C
†
U1
AB3
†
U4
—
VDD2
VDD2
—
VDD2
PL20A
No Connect†
V2
AB4
PL21D
VDD
U3
AB5
PL21C
VSS
V1
AC1
PL20B
No Connect
No Connect
PL21B
VSS
W2
AC2
PL21A
intan
W1
AC4
VSS
VSS
VSS*
VSS*
PL22D
rstn
V3
AC5
PL22C
gntn
Y2
AD1
PL22B
No Connect†
—
AD2
PL22A
†
No Connect
—
AD4
PL23D
reqn
W4
AD5
—
AE1
PL23C
No Connect
†
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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Embedded Master/Target PCI Interface
Data Sheet
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Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
PL23B
PL23A
VDD
PL24D
PL24C
PL24B
PL24A
PL25D
PL25C
PL25B
PL25A
VSS
PL26D
VDD2
PL26C
PL26B
PL26A
PL27D
PL27C
PL27B
PL27A
VDD
PL28D
PL28C
PL28B
PL28A
VSS
PCCLK
VDD
VSS
VDD
VSS
PB1A
PB1B
PB1C
PB1D
VDD
PB2A
Function
Connect†
No
No Connect†
VDD
ad31
No Connect†
No Connect†
ad30
No Connect†
ad29
ad28
ad27
VSS
—
VDD2
ad26
No Connect†
ad25
ad24
c_be3n
No Connect†
idsel
VDD
ad23
No Connect†
No Connect†
vio
VSS
CCLK
VDD
VSS
VDD
VSS
ad22
No Connect†
ad21
ad20
VDD
ad19
PBGA 352
PBGAM 680
—
—
VDD*
Y1
—
—
W3
—
AA2
Y4
AA1
VSS*
—
Y3
AB2
—
AB1
AA3
AC2
—
AB4
VDD*
AC1
AB3
AD2
AC3
VSS*
AD1
VDD*
VSS*
VDD*
VSS*
AF2
AE3
AF3
AE4
VDD*
AD4
AE2
AE3
VDD*
AE4
AE5
AF1
AF2
AF3
AF4
AF5
AG1
VSS*
—
VDD2
AG2
AG4
AG5
AH1
AH2
AH4
AH5
VDD*
AJ3
AJ4
AK1
AK2
VSS*
AL1
VDD*
VSS*
VDD*
VSS*
AP4
AN5
AM6
AN6
VDD*
AP6
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
PB2B
PB2C
PB2D
VDD2
PB3A
PB3B
PB3C
PB3D
VSS
PB4A
PB4B
PB4C
PB4D
PB5A
PB5B
PB5C
PB5D
VSS
PB6A
PB6B
PB6C
PB6D
PB7A
PB7B
PB7C
PB7D
VSS
PB8A
PB8B
PB8C
PB8D
PB9A
PB9B
PB9C
PB9D
VDD
VDD2
PB10A
Function
Connect†
No
No Connect†
—
VDD2
ad18
No Connect†
ad17
ad16
VSS
c_be2n
perrn
serrn
par
c_be1n
ad15
ad14
ad13
VSS
ad12
No Connect†
No Connect†
ad11
ad10
No Connect†
No Connect†
ad9
VSS
ad8
No Connect†
No Connect†
c_be0n
ad7
No Connect†
No Connect†
ad6
VDD
VDD2
No Connect†
PBGA 352
PBGAM 680
—
—
—
AF4
AE5
—
AC5
AD5
VSS*
AF5
AE6
AC7
AD6
AF6
AE7
AF7
AD7
VSS*
AE8
—
—
AC9
AF8
—
—
AD8
VSS*
AE9
—
—
AF9
AE10
—
—
AD9
VDD*
—
AF10
AK7
AL7
—
VDD2
AN7
AP7
AK8
AL8
VSS*
AN8
AP8
AK9
AL9
AM9
AN9
AP9
AK10
VSS*
AL10
AM10
AN10
AP10
AK11
AL11
AN11
AP11
VSS*
AK12
AL12
AN12
AP12
AK13
AL13
AM13
AN13
VDD*
VDD2
—
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
PB10B
PB10C
PB10D
PB11A
PB11B
PB11C
PB11D
VDD
PB12A
PB12B
PB12C
PB12D
PB13A
PB13B
PB13C
PB13D
VSS
PB14A
VDD2
PB14B
PB14C
PB14D
VSS
PECKB
PB15A
PB15B
PB15C
PB15D
VSS
PB16A
VDD2
PB16B
PB16C
PB16D
PB17A
PB17B
PB17C
PB17D
Function
Connect†
No
No Connect†
ad5
ad4
No Connect†
No Connect†
ad3
VDD
ad2
No Connect†
No Connect†
ad1
ad0
No Connect†
No Connect†
framen
VSS
No Connect†
VDD2
irdyn
trdyn
devseln
VSS
clk
—
stopn
ack64n
req64n
VSS
—
VDD2
No Connect†
No Connect†
c_be7n
c_be6n
No Connect†
No Connect†
c_be5n
PBGA 352
PBGAM 680
—
—
AC10
AE11
—
—
AD10
VDD*
AF11
—
—
AE12
AF12
—
—
AD11
VSS*
AE13
—
AC12
AF13
AD12
VSS*
AE14
—
AC14
AF14
AD13
VSS*
—
AE15
—
—
AD14
AF15
—
—
AE16
AP13
AK14
AL14
AM14
AN14
AP14
AK15
VDD*
AL15
AN15
AP15
AK16
AL16
AN16
AP16
AK17
VSS*
—
VDD2
AM17
AP17
AP18
VSS*
AN18
—
AM18
AL18
AK18
VSS*
—
VDD2
AP19
AN19
AL19
AK19
AP20
AN20
AL20
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
VDD
PB18A
PB18B
PB18C
PB18D
PB19A
PB19B
PB19C
PB19D
VDD2
VDD
PB20A
PB20B
PB20C
PB20D
PB21A
PB21B
PB21C
PB21D
VSS
PB22A
PB22B
PB22C
PB22D
PB23A
PB23B
PB23C
PB23D
VSS
PB24A
PB24B
PB24C
PB24D
PB25A
VDD2
PB25B
PB25C
PB25D
VDD
HDC
No Connect†
No Connect†
c_be4n
ad63
No Connect†
No Connect†
No Connect†
VDD2
VDD
LDC
No Connect†
No Connect†
ad62
ad61
No Connect†
No Connect†
ad60
VSS
ad59
No Connect†
No Connect†
No Connect†
ad58
No Connect†
ad57
ad56
VSS
INIT
ad55
ad54
ad53
—
VDD2
ad52
ad51
ad50
VDD*
AD15
—
—
AF16
AC15
—
—
AE17
—
VDD*
AD16
—
—
AF17
AC17
—
—
AE18
VSS*
AD17
—
—
—
AF18
—
AE19
AF19
VSS*
AD18
AE20
AC19
AF20
—
AD19
AE21
AC20
AF21
VDD*
AK20
AP21
AN21
AM21
AL21
AK21
AP22
—
VDD2
VDD*
AN22
AM22
AL22
AK22
AP23
AN23
AL23
AK23
VSS*
AP24
AN24
AL24
AK24
AP25
AN25
AM25
AL25
VSS*
AK25
AP26
AN26
AM26
—
VDD2
AL26
AK26
AP27
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
VSS
PB26A
PB26B
PB26C
PB26D
PB27A
PB27B
PB27C
PB27D
VDD
PB28A
PB28B
PB28C
PB28D
VSS
PDONE
VDD
VSS
PRESETN
PPRGMN
PR28A
PR28B
PR28C
PR28D
VDD
VDD2
PR27A
PR27B
PR27C
PR27D
PR26A
PR26B
PR26C
PR26D
VSS
PR25A
PR25B
PR25C
VSS
ad49
ad48
No Connect†
ad47
ad46
No Connect†
No Connect†
ad45
VDD
ad44
ad43
No Connect†
par64
VSS
DONE
VDD
VSS
RESET
PRGM
M0
No Connect†
ad42
ad41
VDD
VDD2
No Connect†
No Connect†
No Connect†
ad40
ad39
ad38
No Connect†
ad37
VSS
ad36
ad35
ad34
VSS*
AD20
AE22
—
AF22
AD21
AE23
—
AC22
VDD*
AF23
AD22
AE24
AD23
VSS*
AF24
VDD*
VSS*
AE26
AD25
AD26
—
AC25
AC24
VDD*
—
AC26
—
—
AB25
AB23
AB24
—
AB26
VSS*
AA25
Y23
AA24
VSS*
AN27
AL27
AK27
AP28
AN28
AL28
AK28
AP29
VDD*
AN29
AM29
AP30
AN30
VSS*
AP31
VDD*
VSS*
AL34
AK33
AK34
AJ31
AJ32
AJ33
VDD*
VDD2
—
AJ34
AH30
AH31
AH33
AH34
AG30
AG31
VSS*
AG33
AG34
AF30
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
162
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
PR25D
PR24A
PR24B
PR24C
PR24D
VDD
PR23A
PR23B
PR23C
PR23D
PR22A
PR22B
PR22C
PR22D
VSS
PR21A
PR21B
PR21C
PR21D
VDD2
PR20A
PR20B
PR20C
PR20D
VDD
PR19A
PR19B
PR19C
PR19D
PR18A
PR18B
PR18C
PR18D
VSS
PR17A
PR17B
PR17C
PR17D
Function
No
Connect†
ad33
No Connect†
No Connect†
No Connect†
VDD
ad32
enumn
No Connect†
ledn
No Connect†
No Connect†
No Connect†
M1
VSS
ejectsw
No Connect†
No Connect†
No Connect†
VDD2
No Connect†
No Connect†
No Connect†
No Connect†
VDD
I/O-M2
No Connect†
No Connect†
No Connect†
I/O
I/O
I/O
I/O
VSS
I/O-M3
I/O
I/O
I/O
PBGA 352
PBGAM 680
—
AA26
—
—
—
VDD*
Y25
Y26
—
Y24
—
—
—
W25
VSS*
V23
W26
W24
—
V25
V26
U25
V24
U26
VDD*
U23
—
—
T25
U24
—
—
T26
VSS*
R25
—
—
R26
AF31
AF32
AF33
AF34
AE30
VDD*
AE31
AE32
AE33
AE34
AD30
AD31
AD33
AD34
VSS*
AC30
AC31
AC33
—
VDD2
AC34
AB30
AB31
AB32
VDD*
AB33
AB34
AA30
AA31
AA32
AA33
AA34
Y30
VSS*
Y31
Y33
Y34
W30
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
Lucent Technologies Inc.
Lucent Technologies Inc.
163
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PR16A
PR16B
PR16C
PR16D
VDD2
VSS
PR15A
PR15B
PR15C
PR15D
VDD
PECKR
PR14A
PR14B
PR14C
PR14D
VSS
PR13A
VDD2
PR13B
PR13C
PR13D
PR12A
PR12B
PR12C
PR12D
VSS
PR11A
PR11B
PR11C
PR11D
PR10A
PR10B
PR10C
PR10D
VDD2
VDD
PR9A
I/O
I/O
I/O
I/O
VDD2
VSS
I/O
I/O
I/O
I/O
VDD
I-ECKR
—
I/O
I/O
I/O
VSS
—
VDD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O-CS1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD2
VDD
I/O-CS0
T24
—
—
P25
—
VSS*
R23
P26
R24
N25
VDD*
N23
—
N26
P24
M25
VSS*
—
N24
—
—
M26
L25
—
—
M24
VSS*
L26
—
—
M23
K25
—
—
L24
—
VDD*
K26
W31
W33
W34
—
VDD2
VSS*
V30
V32
V33
V34
VDD*
U34
—
U33
U32
U31
VSS*
—
VDD2
U30
T34
T33
T31
T30
R34
R33
VSS*
R31
R30
P34
P33
P32
P31
P30
—
VDD2
VDD*
N34
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
164
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PR9B
PR9C
PR9D
PR8A
PR8B
PR8C
PR8D
VSS
PR7A
PR7B
PR7C
PR7D
PR6A
PR6B
PR6C
PR6D
VDD
PR5A
PR5B
PR5C
PR5D
PR4A
VDD2
PR4B
PR4C
PR4D
VSS
PR3A
PR3B
PR3C
PR3D
PR2A
PR2B
PR2C
PR2D
VDD
PR1A
PR1B
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O-RD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
—
VDD2
I/O
I/O
I/O
VSS
I/O-WR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
K23
J25
K24
J26
H25
H26
J24
VSS*
G25
—
—
—
H23
—
G26
—
VDD*
H24
—
—
—
—
F25
G23
F26
G24
VSS*
E25
E26
—
F24
D25
—
—
E23
VDD*
D26
E24
N33
N32
N31
N30
M34
M33
M31
VSS*
M30
L34
L33
L31
L30
K34
K33
K32
VDD*
K31
K30
J34
J33
—
VDD2
J32
J31
J30
VSS*
H34
H33
H31
H30
G34
G33
G31
G30
VDD*
F34
F32
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
Lucent Technologies Inc.
Lucent Technologies Inc.
165
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PR1C
PR1D
VSS
PRD_CFGN
VDD
VSS
VDD
VSS
PT28D
PT28C
PT28B
PT28A
VDD
PT27D
PT27C
PT27B
PT27A
PT26D
PT26C
PT26B
PT26A
VSS
PT25D
PT25C
PT25B
PT25A
PT24D
PT24C
PT24B
PT24A
VSS
PT23D
VDD2
PT23C
PT23B
PT23A
PT22D
PT22C
I/O
I/O
VSS
RD_CFGN
VDD
VSS
VDD
VSS
I/O-SECKUR
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O-RDY/RCLK
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O-D7
I/O
I/O
I/O
VSS
—
VDD2
I/O
I/O
I/O
I/O
I/O
C25
D24
VSS*
C26
VDD*
VSS*
VDD*
VSS*
A25
B24
A24
B23
VDD*
C23
—
—
A23
B22
D22
—
C22
VSS*
A22
B21
D20
C21
A21
B20
A20
C20
VSS*
—
B19
D18
A19
—
C19
—
F31
E33
VSS*
D34
VDD*
VSS*
VDD*
VSS*
A31
A30
C29
B29
VDD*
A29
E28
D28
B28
A28
E27
D27
B27
VSS*
A27
E26
D26
C26
B26
A26
E25
D25
VSS*
—
VDD2
C25
B25
A25
E24
D24
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
166
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PT22B
PT22A
VSS
PT21D
PT21C
PT21B
PT21A
PT20D
PT20C
PT20B
PT20A
VDD
PT19D
PT19C
PT19B
PT19A
PT18D
VDD2
PT18C
PT18B
PT18A
VDD
PT17D
PT17C
PT17B
PT17A
PT16D
PT16C
PT16B
PT16A
VSS
PECKT
PT15D
PT15C
VDD2
PT15B
PT15A
VSS
I/O
I/O
VSS
I/O
I/O
I/O
I/O
I/O-D6
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O
I/O
VDD2
I/O
I/O
I/O-D5
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D4
VSS
I-ECKT
—
I/O
VDD2
I/O
I/O-D3
VSS
—
—
VSS*
B18
—
—
A18
B17
—
—
C18
VDD*
A17
—
—
D17
B16
—
—
—
C17
VDD*
A16
—
—
B15
A15
—
—
C16
VSS*
B14
—
D15
—
A14
C15
VSS*
B24
A24
VSS*
E23
D23
B23
A23
E22
D22
C22
B22
VDD*
A22
E21
D21
C21
—
VDD2
B21
A21
E20
VDD*
D20
B20
A20
E19
D19
B19
A19
E18
VSS*
D18
—
—
VDD2
C18
A18
VSS*
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
Lucent Technologies Inc.
Lucent Technologies Inc.
167
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PT14D
PT14C
PT14B
VDD2
PT14A
VSS
PT13D
PT13C
PT13B
PT13A
PT12D
PT12C
PT12B
PT12A
VDD
PT11D
PT11C
PT11B
PT11A
PT10D
PT10C
PT10B
PT10A
VDD
PT9D
VDD2
PT9C
PT9B
PT9A
PT8D
PT8C
PT8B
PT8A
VSS
PT7D
PT7C
PT7B
PT7A
I/O
I/O
—
VDD2
I/O-D2
VSS
I/O-D1
I/O
I/O
I/O
I/O
I/O
I/O
I/O-D0-DIN
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-DOUT
VDD
I/O
VDD2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VSS
I/O
I/O
I/O
I/O
B13
D13
—
A13
C14
VSS*
B12
—
—
C13
A12
—
—
B11
VDD*
C12
—
—
A11
D12
—
—
B10
VDD*
C11
—
—
—
A10
D10
—
—
B9
VSS*
C10
—
—
A9
A17
B17
—
VDD2
C17
VSS*
D17
E17
A16
B16
D16
E16
A15
B15
VDD*
D15
E15
A14
B14
C14
D14
E14
A13
VDD*
—
VDD2
B13
C13
D13
E13
A12
B12
D12
VSS*
E12
A11
B11
D11
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
168
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PT6D
PT6C
PT6B
PT6A
VSS
PT5D
PT5C
PT5B
PT5A
VDD2
PT4D
PT4C
PT4B
PT4A
VSS
PT3D
PT3C
PT3B
PT3A
PT2D
PT2C
PT2B
PT2A
VDD
PT1D
PT1C
PT1B
PT1A
VSS
PRD_DATA
VDD
VDD2
‡
‡
‡
‡
‡
‡
I/O
I/O
I/O
I/O-TDI
VSS
I/O
I/O
I/O
—
VDD2
I/O
I/O
I/O
I/O-TMS
VSS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VDD
I/O
I/O
I/O
I/O-TCK
VSS
RD_DATA/TDO
VDD
VDD2
VDD
VDD
VDD
VDD
VDD
VDD
B8
—
—
A8
VSS*
C9
B7
D8
—
A7
C8
B6
D7
A6
VSS*
C7
—
—
B5
A5
C6
B4
D5
VDD*
A4
C5
B3
C4
VSS*
A3
VDD*
—
—
—
—
—
—
—
E11
A10
B10
C10
VSS*
D10
E10
A9
—
VDD2
B9
C9
D9
E9
VSS*
A8
B8
D8
E8
A7
B7
D7
E7
VDD*
A6
C6
D6
B5
VSS*
A4
VDD*
VDD2
—
A3
A32
—
B3
B4
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
Lucent Technologies Inc.
Lucent Technologies Inc.
169
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D6
D11
D16
D21
—
—
—
—
—
F4
F23
L4
L23
T4
T23
AA4
AA23
—
—
—
—
B31
B32
C1
C2
C4
C7
C11
C15
C20
C24
C28
C31
C33
C34
D2
D3
—
—
—
—
—
—
D32
D33
G3
G32
L3
L32
R3
R32
Y3
Y32
AD3
AD32
AH3
AH32
AL2
AL3
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
170
Lucent
Technologies
Lucent
TechnologiesInc.
Inc.
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
—
AC6
AC11
AC16
AC21
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AL32
AL33
AM1
AM2
AM4
AM7
AM11
AM15
AM20
AM24
AM28
AM31
AM33
AM34
AN3
AN4
AN31
AN32
—
AP3
AP32
—
C5
C30
D5
D30
E3
E4
E5
E6
E29
E30
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
Lucent Technologies Inc.
Lucent Technologies Inc.
171
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A1
A2
—
—
—
—
—
—
—
A26
—
B2
B25
B26
—
C3
—
—
—
—
E31
E32
F5
F30
AJ5
AJ30
AK3
AK4
AK5
AK6
AK29
AK30
AK31
AK32
AL5
AL30
AM5
AM30
A1
A2
—
—
—
—
—
—
A33
A34
B1
B2
B33
B34
—
C3
C8
C12
C16
C19
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
172
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
—
—
C24
—
D4
D9
D14
D19
D23
—
—
H4
J23
—
—
N4
P23
—
—
V4
W23
—
—
AC4
AC8
AC13
AC18
AC23
—
AD3
—
—
—
—
—
—
AD24
C23
C27
C32
—
D4
—
—
—
D31
H3
H32
M3
M32
T3
T32
—
—
W3
W32
AC3
AC32
AG3
AG32
AL4
—
—
—
AL31
—
AM3
AM8
AM12
AM16
AM19
AM23
AM27
AM32
—
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
AE1
AE2
—
—
AE25
—
AF1
—
—
—
—
—
—
—
—
AF25
AF26
L11
L12
L13
—
—
—
—
L14
L15
L16
M11
M12
M13
—
—
—
—
M14
M15
M16
N11
AN1
AN2
—
—
AN33
AN34
AP1
AP2
—
—
—
—
—
—
—
AP33
AP34
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
R13
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
174
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VDD2
VDD2
N12
N13
—
—
—
—
N14
N15
N16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R14
R15
R16
R17
R18
R19
R20
R21
R22
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
V13
V14
V15
V16
V17
V18
V19
V20
V21
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
VSS
VSS
VSS
VSS
VSS
VSS
VDD2
VDD2
VDD2
VDD2
—
—
—
—
—
—
—
—
—
—
—
P11
P12
P13
—
—
—
—
P14
P15
P16
R11
R12
R13
—
—
—
—
R14
R15
R16
T11
T12
T13
—
—
—
—
V22
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AB13
AB14
AB15
AB16
AB17
AB18
AB19
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
176
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Pin Information (continued)
Table 70. Pinout Information (continued)
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
‡
‡
‡
VSS
VSS
VSS
T14
T15
T16
AB20
AB21
AB22
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the position of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Package Thermal Characteristics
Summary
There are three thermal parameters that are in common use: ΘJA, ψJC, and ΘJC. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
ΘJA
This is the thermal resistance from junction to ambient
(theta-JA, R-theta, etc.).
TJ – TA
Q
Θ JA = --------------------
where TJ is the junction temperature, TA is the ambient
air temperature, and Q is the chip power.
Experimentally, ΘJA is determined when a special thermal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (TJ) is determined by the forward drop on the diodes, and the ambient temperature (TA) is noted. Note that ΘJA is
expressed in units of °C/W.
ψJC
ΘJC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by:
TJ – TC
Q
Θ JC = -------------------The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink to draw most of the heat generated by the
chip out the top of the package. It is this difference in
the measurement process that differentiates ΘJC from
ψJC. ΘJC is a true thermal resistance and is expressed
in units of °C/W.
ΘJB
This is the thermal resistance from junction to board
(ΘJB). It is defined by:
TJ – TB
Q
Θ JB = -------------------where TB is the temperature of the board adjacent to a
lead measured with a thermocouple. The other parameters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board to draw most of the heat out
of the leads. Note that ΘJB is expressed in units of
°C/W, and that this parameter and the way it is measured are still in JEDEC committee.
FPGA Maximum Junction Temperature
This JEDEC designated parameter correlates the junction temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by:
TJ – TC
ψ JC = ------------------Q
where TC is the case temperature at top dead center,
TJ is the junction temperature, and Q is the chip power.
During the ΘJA measurements described above,
besides the other parameters measured, an additional
temperature reading, TC, is made with a thermocouple
attached at top-dead-center of the case. ψJC is also
expressed in units of °C/W.
178
Data Sheet
March 2000
Once the power dissipated by the FPGA has been
determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA
can be found. This is needed to determine if speed derating of the device from the 85 °C junction temperature
used in all of the delay tables is needed. Using the
maximum ambient temperature, TAmax, and the power
dissipated by the device, Q (expressed in °C), the maximum junction temperature is approximated by:
TJmax = TAmax + (Q • ΘJA)
Table 71 lists the thermal characteristics for all packages used with the ORCA OR3LP26B Series of
FPGAs.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Package Thermal Characteristics Summary (continued)
Table 71. ORCA OR3LP26B Plastic Package Thermal Guidelines
ΘJA (°C/W)
Package*
352-Pin PBGA† ‡
680-Pin
PBGAM† ‡
0 fpm
200 fpm
500 fpm
TA = 70 °C Max
TJ = 125 °C Max
0 fpm (W)
19.0
14.5
16.0
TBD
15.0
TBD
2.9
3.8
* Mounted on a four-layer JEDEC standard test board with two power/ground planes.
† With thermal balls connected to board ground plane.
‡ The value of ψJC for all packages is <1 °C/W.
Package Coplanarity
The coplanarity limits of the ORCA Series 3 packages are as follows.
Table 72. Package Coplanarity
Package Type
Coplanarity Limit
(mils)
PBGA
PBGAM
8.0
8.0
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Package Parasitics
The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the
package parasitics. Table 73 lists eight parasitics associated with the ORCA packages. These parasitics represent
the contributions of all components of a package, which include the bond wires, all internal package routing, and
the external leads.
Four inductances in nH are listed: LSW and LSL, the self-inductance of the lead; and LMW and LML, the mutual
inductance to the nearest neighbor lead. These parameters are important in determining ground bounce noise and
inductive crosstalk noise. Three capacitances in pF are listed: CM, the mutual capacitance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to
be grounded). These parameters are important in determining capacitive crosstalk and the capacitive loading effect
of the lead. The lead resistance value, RW, is in mΩ.
The parasitic values in Table 73 are for the circuit model of bond wire and package lead parasitics. If the mutual
capacitance value is not used in the designer’s model, then the value listed as mutual capacitance should be added
to each of the C1 and C2 capacitors.
Table 73. Package Parasitics
Package Type
352-Pin PBGA
680-Pin EBGA
LSW
LMW
C1
(pF)
C2
(pF)
CM
(pF)
LML
(nH)
RW
(mΩ)
LSL
(nH)
(nH)
(nH)
5
3.8
2
1.3
220
250
1.5
1.0
1.5
1.0
1.5
0.3
7—12
2.8—5.0
3—6
0.5—1.0
LSW
RW
LSL
BOARD PAD
PAD N
C1
LMW CM
C2
LML
PAD N + 1
LSW
RW
LSL
C1
C2
5-3862(F).a
Figure 66. Package Parasitics
180
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Package Outline Diagrams
Terms and Definitions
Basic Size (BSC):
The basic size of a dimension is the size from which the limits for that dimension are derived
by the application of the allowance and the tolerance.
Design Size:
The design size of a dimension is the actual size of the design, including an allowance for fit
and tolerance.
Typical (TYP):
When specified after a dimension, this indicates the repeated design size if a tolerance is
specified or repeated basic size if a tolerance is not specified.
Reference (REF):
The reference dimension is an untoleranced dimension used for informational purposes only.
It is a repeated dimension or one that can be derived from other values in the drawing.
Minimum (MIN) or
Maximum (MAX):
Indicates the minimum or maximum allowable size of a dimension.
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Package Outline Diagrams (continued)
352-Pin PBGA
Dimensions are in millimeters.
35.00 ± 0.20
+0.70
30.00 –0.00
A1 BALL
IDENTIFIER ZONE
30.00 +0.70
–0.00
35.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.56 ± 0.06
2.33 ± 0.21
SEATING PLANE
0.20
0.60 ± 0.10
SOLDER BALL
25 SPACES @ 1.27 = 31.75
CENTER ARRAY
FOR THERMAL
ENHANCEMENT
A1 BALL
CORNER
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.75 ± 0.15
25 SPACES
@ 1.27 = 31.75
1 2 3 4 5 6 7 8 9 10
12 14 16 18 20 22 24 26
11 13 15 17 19 21 23 25
5-4407(F)
182
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Package Outline Diagrams (continued)
680-Pin PBGA
Dimensions are in millimeters.
35.00
+ 0.70
30.00 – 0.00
A1 BALL
IDENTIFIER ZONE
35.00
+ 0.70
30.00 – 0.00
1.170
0.61 ± 0.08
SEATING PLANE
0.20
SOLDER BALL
0.50 ± 0.10
2.51 MAX
33 SPACES @ 1.00 = 33.00
AP
AN
AM
AL
AK
AJ
AH
AG
AF
0.64 ± 0.15
AE
AD
AC
AB
AA
Y
W
33 SPACES
@ 1.00 = 33.00
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 BALL
CORNER
Lucent Technologies Inc.
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1
3
2
5
4
7
6
9
8
11 13 15 17 19 21 23 25 27 29 31 33
10 12 14 16 18 20 22 24 26 28 30 32 34
183
ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Ordering Information
OR3L P2 6 BA 352
DEVICE TYPE
NUMBER OF PINS
EMBEDDED CORE TYPE
FPSC BASE ARRAY
PACKAGE TYPE
5-6435(F).h
Table 74. Voltage Options
Table 77. Embedded Core Type
Device
Voltage
Symbol
Description
OR3L
2.5 V
P2
32-/64-bit, 33/66 MHz PCI bus interface
with 64-bit back-end data path in each
direction.
Table 75. Package Options
Symbol
Description
BA
BM
Plastic Ball Grid Array (PBGA)
Plastic Ball Grid Array Multilayer (PBGAM)
Table 78. FPSC Base Array
Symbol
Description
6
OR3L125 based 18 x 28 array.
Table 76. ORCA Series 3+ Package Matrix
Package
Device
OR3LP26B
352-Pin PBGA
680-Pin PBGAM
BA352
CI
BM680
CI
Key: C = commercial, I = industrial.
For additional information, contact your Microelectronics Group Account Manager or the following:
http://www.lucent.com/micro, or for FPGA information, http://www.lucent.com/orca
INTERNET:
docmaster@micro.lucent.com
E-MAIL:
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN:
Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. ORCA is a registered trademark of Lucent Technologies Inc. Foundry is a trademark of Xilinx, Inc.
Copyright © 2000 Lucent Technologies Inc.
All Rights Reserved
March 2000
DS00-151FPGA (Replaces DS00-047FPGA)