TI SN74HC21D

SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND GATES
SCLS087C – DECEMBER 1982 – REVISED MAY 1997
D
SN54HC21 . . . J OR W PACKAGE
SN74HC21 . . . D OR N PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
1A
1B
NC
1C
1D
1Y
GND
description
These devices contain two independent 4-input
AND gates. They perform the Boolean function
Y
A • B • C • D or Y
A B C D
in positive logic.
+
+ ) ) )
C
D
OUTPUT
Y
H
H
H
H
H
L
X
X
X
L
X
L
X
X
L
X
X
L
X
L
X
X
X
L
L
3
12
4
11
5
10
6
9
7
8
VCC
2D
2C
NC
2B
2A
2Y
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2C
NC
NC
NC
2B
1Y
GND
NC
2Y
2A
B
13
1B
1A
NC
VCC
2D
NC
NC
1C
NC
1D
FUNCTION TABLE
(each gate)
A
14
2
SN54HC21 . . . FK PACKAGE
(TOP VIEW)
The SN54HC21 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74HC21 is characterized for
operation from –40°C to 85°C.
INPUTS
1
NC – No internal connection
logic symbol†
1A
1B
1C
1D
2A
2B
2C
2D
1
2
&
6
4
1Y
5
9
10
8
12
2Y
13
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND GATES
SCLS087C – DECEMBER 1982 – REVISED MAY 1997
logic diagram (positive logic)
1A
1B
1C
1D
1
2
4
5
6
2A
2B
2C
2D
1Y
9
10
12
13
8
2Y
Pin numbers shown are for the D, J, N, and W packages.
absolute maximum ratings over operating free-air temperature range†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
recommended operating conditions
SN54HC21
VCC
VIH
Supply voltage
High-level input voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
tt
TA
2
Low-level input voltage
VCC = 4.5 V
VCC = 6 V
Input voltage
NOM
MAX
2
5
6
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
0
0.5
0
0.5
0
1.35
0
1.35
0
1.8
0
1.8
0
0
0
0
VCC
VCC
VCC = 2 V
VCC = 4.5 V
0
1000
0
1000
0
500
0
500
VCC = 6 V
0
400
0
400
–55
125
–40
85
Operating free-air temperature
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UNIT
V
V
VCC
VCC
Output voltage
Input transition (rise and fall) time
SN74HC21
MIN
V
V
V
ns
°C
SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND GATES
SCLS087C – DECEMBER 1982 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –20 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –5.2 mA
IOL = 20 µA
VOL
VI = VIH or VIL
IOL = 4 mA
IOL = 5.2 mA
II
ICC
VI = VCC or 0
VI = VCC or 0,
IO = 0
MIN
TA = 25°C
TYP
MAX
SN74HC21
MIN
MIN
MAX
2V
1.9
1.998
1.9
1.9
4.5 V
4.4
4.499
4.4
4.4
6V
5.9
5.999
5.9
5.9
4.5 V
3.98
4.3
3.7
3.84
6V
5.48
5.8
5.2
MAX
UNIT
V
5.34
2V
0.002
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
4.5 V
0.17
0.26
0.4
0.33
6V
0.15
0.26
0.4
0.33
6V
±0.1
±100
±1000
±1000
nA
2
40
20
µA
3
10
10
10
pF
6V
Ci
SN54HC21
2 V to 6 V
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
TA = 25°C
TYP
MAX
SN54HC21
SN74HC21
MIN
MIN
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
44
110
165
140
tpd
A, B, C, or D
Y
4.5 V
14
22
33
28
6V
11
19
28
24
tt
Y
MIN
MAX
MAX
2V
29
75
110
95
4.5 V
10
15
22
19
6V
8
13
19
16
UNIT
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
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TYP
25
UNIT
pF
3
SN54HC21, SN74HC21
DUAL 4-INPUT POSITIVE-AND GATES
SCLS087C – DECEMBER 1982 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
Input
VCC
50%
50%
0V
CL = 50 pF
(see Note A)
tPLH
In-Phase
Output
LOAD CIRCUIT
50%
10%
tPHL
90%
90%
tr
Input
50%
10%
90%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
tf
VOH
50%
10%
VOL
tf
tPLH
50%
10%
tf
50%
10%
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. The outputs are measured one at a time with one input transition per measurement.
D. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
4
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