AGERE T8100

Advisory
March 1999
Ambassador TM T8100
H.100/H.110 Interface and Time-Slot Interchanger
This advisory details two changes to the AmbassadorTM T8100 H.100/H.110 Interface and Time-Slot
Interchanger Preliminary Data Sheet: DS98-195NTNB.
Change Affecting Page 15, Section 2.1.3 Address Mode Register
Problem:
There is a minor bug in the T8100. If a write is issued to the address mode register (AMR)
address 0x70 (local bus, holding registers, and reset), the T8100’s RDY line gets stuck low (not
ready state).
Workaround:
To solve this, issue another write command to any of the four direct registers (MCR, LAR,
AMR, or IDR) and the RDY signal will reset.
Change Affecting Page 38, Section 2.4.2 Dividers and Rate Multipliers
There is an anomaly in the digital phase-lock loop (DPLL) performance of the device. The behavior affects all
versions of the T8100 but has been corrected in the T8100A, T8102, and T8105. This anomaly affects applications that use the DPLL for CT bus clock generation.
When used for clocking, the DPLL uses the 16.384 MHz internal oscillator to rate multiply an 8 kHz input signal. In order for the DPLL to lock to the 8.000000 kHz signal, the required internal oscillator frequency range
should be centered at 16.388 MHz. A frequency of 16.384 MHz is too low for the DPLL to perform properly.
If this crystal adaptation is used for the DPLL, there are several limitations. First, do not select the crystal as a
fallback clock source. When the crystal is a clock source, the generated clocks are all multiples of the crystal. In
that case, they will be offset by the same ratio as the crystal. Second, do not use TCLKOUT. It is also derived
from the crystal and will be offset by the same ratio. Third, the watchdogs will be slightly more sensitive due to
the increased clock frequency. In designs affected by these limitations, conversion to the T8100A is recommended.
For additional information, contact your Microelectronics Group Account Manager or the following:
http://www.lucent.com/micro
INTERNET:
docmaster@micro.lucent.com
E-MAIL:
N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256
Tel. (65) 778 8833, FAX (65) 777 7495
CHINA:
Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai
200233 P. R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652
JAPAN:
Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
EUROPE:
Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148
Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot),
FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki),
ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. Ambassador is a trademark of Lucent Technologies Inc.
Copyright © 1999 Lucent Technologies Inc.
All Rights Reserved
March 1999
AY99-019NTNB (Replaces AY99-011NTNB and must accompany DS98-195NTNB)
Preliminary Data Sheet
August 1998
Ambassador TM T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
1.1 Introduction
Increasingly, enhanced telephony services are provided by equipment based on mass-market computer-telephony architectures. The H.100 timedivision multiplexed (TDM) bus has emerged as the
industry standard used in these systems. The
Ambassador T8100 is a single device that provides a
complete interface for H.100/H.110-based systems.
The T8100 will support the newer bus standards,
H-MVIP * and ECTF H.100, but remain downward
compatible with MVIP-90 and Dialogic’s† SC-Bus.
Data can be buffered in either minimum delay or constant delay modes on a connection-by-connection
basis.
The T8100 will take advantage of new technology: it
is based on 0.35 micron feature sizes and a robust
standard-cell library. It utilizes associative memory
(content addressable memories [CAM]) in addition to
traditional static RAM and register file structures for
the connection and data memories. The T8100 operates on a single 3.3 V supply, but all inputs are 5 V
tolerant and standard TTL output levels are maintained.
1.2 Features
■
Complete solution for interfacing board-level circuitry to the H.100 telephony bus
■
H.100 compliant interface; all mandatory signals
■
Programmable connections to any of the 4096 time
slots on the H.100 bus
■
Up to 16 local serial inputs and 16 local serial
outputs, programmable for 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s operation per CHI
specifications
■
Programmable switching between local time slots,
up to 1024 connections
■
Programmable switching between local time slots
and H.100 bus, up to 256 connections
■
Choice of frame integrity or minimum latency
switching on a per-time-slot basis
— Frame integrity to ensure proper switching of
wideband data
— Minimum latency switching to reduce delay in
voice channels
■
On-chip phase-locked loop (PLL) for H.100, MVIP,
or SC-Bus clock operation in master or slave clock
modes
■
Serial TDM bus rate and format conversion
between most standard buses
■
Optional 8-bit parallel input and/or 8-bit parallel
output for local TDM interfaces
■
High-performance microprocessor interface
— Provides access to device configuration registers and to time-slot data
— Supports both Motorola‡ nonmultiplexed and
Intel § multiplexed/nonmultiplexed modes
■
Two independently programmable groups of up to
12 framing signals each
■
3.3 V supply with 5 V tolerant inputs and TTL-compatible outputs
■
Boundary-scan testing support
■
208-pin, plastic SQFP package
■
217-pin BGA package (industrial temperature
range)
*
†
‡
§
MVIP is a registered trademark of GO-MVIP, Inc.
Dialogic is a registered trademark of Dialogic Corporation.
Motorola is a registered trademark of Motorola, Inc.
Intel is a registered trademark of Intel Corporation.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Table of Contents
Contents
Page
1 Product Overview .....................................................1
1.1 Introduction ........................................................1
1.2 Features .............................................................1
1.3 Pin Information ...................................................5
1.4 Enhanced Local Stream Addressing ................10
1.5 Full H.100 Stream Address Support ................10
1.6 Onboard PLLs and Clock Monitors ..................11
1.7 Phase Alignment of Referenced and
Generated Frames ...........................................11
1.8 Interfaces .........................................................11
1.8.1 Microprocessors ..........................................11
1.8.2 Framing Groups ..........................................11
1.8.3 General-Purpose Register and I/O..............11
1.9 Applications ......................................................11
1.10 Application Overview .....................................11
2 Architecture and Functional Description.................12
2.1 Register/Memory Maps ....................................14
2.1.1 Main Registers ............................................14
2.1.2 Master Control and Status Register ............14
2.1.3 Address Mode Register...............................15
2.1.4 Control Register Memory Space .................16
2.2 Local Bus Section ............................................21
2.2.1 Constant Frame Delay and Minimum
Delay Connections ......................................22
2.2.2 Serial and Parallel .......................................23
2.2.3 Data Rates and Time-Slot Allocation ..........23
2.2.4 LBS: Local Stream Control, 0x0C ...............27
2.2.5 State Counter Operation .............................28
2.3 H-Bus Section ..................................................29
2.3.1 Memory Architecture ...................................29
2.3.2 CAM Operation and Commands .................31
2.3.3 H-Bus Access..............................................35
2.3.4 L-Bus Access ..............................................36
2.3.5 H-Bus Rate Selection and Connection
Address Format...........................................36
2.4 Clocking Section ..............................................36
2.4.1 Clock and NETREF Selection .....................38
2.4.2 Dividers and Rate Multipliers.......................38
2.4.3 State Machines ...........................................39
2.4.4 Bit Sliding (Frame Locking) .........................39
2.4.5 Clock Fallback .............................................39
2.4.6 Clock Control Register Definitions...............41
2.4.7 CKMD, CKND, CKRD: Clocks, Main,
NETREF, Resource Dividers, 0x07, 0x08,
and 0x09 .....................................................46
2.5 Interface Section ..............................................46
2.5.1 Microprocessor Interface.............................46
2.5.2 General-Purpose Register...........................47
2.5.3 Framing Groups ..........................................47
2.6 Error Registers .................................................50
2.7 The JTAG Test Access Port ............................51
2.7.1 Overview of the JTAG Architecture .............51
2.7.2 Overview of the JTAG Instructions..............51
2
Contents
Page
2.7.3 Elements of JTAG Logic............................. 52
2.8 Testing and Diagnostics .................................. 53
2.8.1 Testing Operations ..................................... 53
2.8.2 Diagnostics................................................. 53
3 Using the T8100 .................................................... 55
3.1 Resets ............................................................. 55
3.1.1 Hardware Reset ......................................... 55
3.1.2 Software Reset........................................... 55
3.1.3 Power-On Reset......................................... 55
3.2 Basic Connections .......................................... 55
3.2.1 Physical Connections for H.110 ................. 56
3.2.2 H.100 Data Pin Series Termination............ 56
3.2.3 PC Board Considerations........................... 56
3.3 Using the LAR, AMR, and IDR for
Connections .................................................... 57
3.3.1 Setting Up Local Connections .................... 57
3.3.2 Setting Up H-Bus Connections................... 59
3.3.3 Programming Examples ............................. 62
3.2.4 Miscellaneous Commands ......................... 65
4 Electrical Characteristics ....................................... 66
4.1 Absolute Maximum Ratings ............................ 66
4.2 Handling Precautions ...................................... 66
4.3 Crystal Oscillator ............................................. 67
4.4 dc Electrical Characteristics, H-Bus
(ECTF H.100 Spec., Rev. 1.0) ........................ 67
4.4.1 Electrical Drive Specifications—CT_C8
and /CT_FRAME ........................................ 67
4.5 dc Electrical Characteristics, All Other Pins .... 68
4.6 H-Bus Timing (Extract from H.100
Spec., Rev. 1.0) .............................................. 69
4.6.1 Clock Alignment ........................................ 69
4.6.2 Frame Diagram .......................................... 70
4.6.3 Detailed Timing Diagram............................ 71
4.6.4 ac Electrical Characteristics, Timing,
H-Bus (H.100, Spec., Rev. 1.0).................. 72
4.6.5 Detailed Clock Skew Diagram.................... 73
4.3.6 ac Electrical Characteristics, Skew
Timing, H-Bus (H.100, Spec., Rev. 1.0) ..... 73
4.6.7 Reset and Power On .................................. 73
4.7 ac Electrical Characteristics, Local
Streams, and Frames ...................................... 74
4.8 ac Electrical Characteristics, Microprocessor Timing ............................................. 75
4.8.1 Microprocessor Access Intel Multiplexed
Write and Read Cycles............................... 75
4.8.2 Microprocessor Access Motorola Write
and Read Cycles ........................................ 76
4.8.3 Microprocessor Access Intel Demultiplexed
Write Cycle ................................................. 77
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Table of Contents (continued)
Contents
Page
5 Outline Diagram......................................................78
5.1 208-Pin Square Quad Flat Package (SQFP) ...78
5.2 217-Pin Ball Grid Array (PBGA) ......................79
6 Ordering Information...............................................79
Appendix A. Application of Clock Modes...................80
Appendix B. Minimum Delay and Constant Delay
Connections ...........................................86
B.1 Connection Definitions .....................................86
B.2 Delay Type Definitions ....................................87
B.2.1 Exceptions to Minimum Delay.....................88
B.2.2 Lower Stream Rates ...................................88
B.2.3 Mixed Minimum/Constant Delay .................89
Figures
Page
Figure 1. Pin Diagram .................................................5
Figure 2. 217 PBGA—Top View .................................6
Figure 3. Block Diagram of the T8100 ......................13
Figure 4. Local Bus Section Function .......................21
Figure 5. Local Bus Memory Connection Modes ......22
Figure 6. Local Streams, Memory Structure .............24
Figure 7. Local Memory, Fill Patterns .......................25
Figure 8. Simplified Local Memory State Timing,
65.536 MHz Clock ...................................28
Figure 9. CAM Architecture ......................................30
Figure 10. Simplified H-Bus State Timing,
65.536 MHz Clock ...................................32
Figure 11. Illustration of CAM Cycles .......................34
Figure 12. Clocking Section ......................................37
Figure 13. A, B, and C Clock Fallback State
Diagram ..................................................40
Figure 14. Frame Group Output Options ..................49
Figure 15. External Connection to PLLs ...................55
Figure 16. Physical Connections for H.110 ..............56
Figure 17. Local-to-Local Connection
Programming ..........................................58
Figure 18. CAM Programming, H-Bus-to-Local
Connection ..............................................60
Figure 19. Clock Alignment ......................................69
Figure 20. Frame Diagram .......................................70
Figure 21. Detailed Timing Diagram .........................71
Figure 22. Detailed Clock Skew Diagram .................73
Figure 23. ac Electrical Characteristics, Local
Streams, and Frames .............................74
Lucent Technologies Inc.
Figures
Page
Figure 24. Microprocessor Access Intel Multiplexed Write Cycle ................................. 75
Figure 25. Microprocessor Access Intel Multiplexed Read Cycle ................................. 75
Figure 26. Microprocessor Access Motorola
Write Cycle ............................................. 76
Figure 27. Microprocessor Access Motorola
Read Cycle ............................................ 76
Figure 28. Microprocessor Access Intel
Demultiplexed Write Cycle ..................... 77
Figure 29. Microprocessor Access Intel
Demultiplexed Read Cycle ..................... 77
Figure 30. E1, CT Bus Master, Compatibility Clock
Master, Clock Source = 2.048 MHz
from Trunk .............................................. 81
Figure 31. T1, CT Bus Master, Compatibility Clock
Master, Clock Source = 1.544 MHz
from Trunk .............................................. 82
Figure 32. E1, Slave to CT Bus, Clock Source Is
Either a 16 MHz or a 4 MHz or a
2 MHz and Frame, NETREF
Source = 2.048 MHz from Trunk ............ 83
Figure 33. T1, Slave to CT Bus, Clock Source Is
Either a 16 MHz or a 4 MHz or a
2 MHz and Frame, NETREF Source
= 1.544 MHz from Trunk ........................ 84
Figure 34. Constant Delay Connections,
CON[1:0] = 0X ........................................ 87
Figure 35. Minimum Delay Connections,
CON[1:0] = 0X ........................................ 88
Figure 36. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10] ......................... 89
Figure 37. Extended Linear (Mixed Minimum/Constant) Delay, CON[1:0] = 11 ................... 90
3
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Table of Contents (continued)
Tables
Page
Table 1. Pin Descriptions: Clocking and Framing
Pins ..............................................................6
Table 2. Pin Descriptions: Local Streams Pins ...........8
Table 3. Pin Descriptions: H-Bus Pins ........................8
Table 4. Pin Descriptions: Microprocessor Interface
Pins ..............................................................9
Table 5. Pin Descriptions: JTAG Pins .......................9
Table 6. Pin Descriptions: Power Pins ......................9
Table 7. Pin Descriptions: Other Pins ......................10
Table 8. Addresses of Programming Registers ........14
Table 9. Master Control and Status Register ..........14
Table 10. Address Mode Register ............................15
Table 11. Control Register Memory Space ..............16
Table 12. CKM: Clocks, Main Clock Selection,
0x00 .........................................................17
Table 13. CKN: Clocks, NETREF Selections,
0x01 .........................................................17
Table 14. CKP: Clocks, Programmable Outputs,
0x02 .........................................................17
Table 15. CKR: Clocks, Resource Selection,
0x03 .........................................................17
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................17
Table 17. CK32: Clocks, Locals 3 and 2, 0x05 ........17
Table 18. CK10: Clocks, Locals 1 and 0, 0x06 ........17
Table 19. CKMD: Clocks, Main Divider; CKND:
Clocks, NETREF Divider; CKRD: Clocks,
Resource Divider, 0x07, 0x08, 0x09 ........18
Table 20. LBS: Local Stream Control, 0x0C ............18
Table 21. CON: Connection Delay Type, 0x0E .......18
Table 22. HSL: H-Bus Stream Control, Low
Byte, 0x10 ...............................................18
Table 23. HSH: H-Bus Stream Control, High
Byte, 0x11 ...............................................18
Table 24. GPR: General-Purpose I/O Register,
0x18 .........................................................18
Table 25. FRLA: Frame Group A, Start Address
Low, 0x20 ................................................19
Table 26. FRHA: Frame Group A, High Address
and Control, 0x21 ....................................19
Table 27. FRLB: Frame Group B, Start Address
Low, 0x22 ................................................19
Table 28. FRHB: Frame Group B, High Address
and Control, 0x23 ....................................19
Table 29. FRPL: Frame Group B, Programmed
Output, Low, 0x24 ...................................19
Table 30. FRPH: Frame Group B, Programmed
Output, High, 0x25 ..................................19
Table 31. CLKERR1: Clock Error Register, Error
Indicator, 0x28 .........................................20
Table 32. CLKERR2: Clock Error Register, Current
Status, 0x29 ............................................20
Table 33. SYSERR: System Error Register,
0x2A ........................................................20
Table 34. CKW: Clock Error/Watchdog Masking
Register, 0x2B .........................................20
4
Tables
Page
Table 35. DIAG1: Diagnostics Register 1, 0x30 ..... 20
Table 36. DIAG2: Diagnostics Register 2, 0x31 ..... 20
Table 37. DIAG3: Diagnostics Register 3, 0x32 ..... 20
Table 38. LBS: Local Stream Control, 0x0C ........... 27
Table 39. CKM: Clocks, Main Clock Selection,
0x00 ......................................................... 41
Table 40. CKN: Clocks, NETREF Selections,
0x01 ......................................................... 42
Table 41. CKP: Clocks, Programmable Outputs,
0x02 ......................................................... 43
Table 42. CKR: Clocks, Resource Selection,
0x03 ......................................................... 44
Table 43. CKS: Clocks, Secondary (Fallback)
Selection, 0x04 ........................................ 45
Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1,
and 0, 0x05 and 0x06 .............................. 46
Table 45. FRHA, Frame Group A High Address
and Control, 0x21 ................................... 47
Table 46. FRHB, Frame Group B High Address
and Control, 0x23 .................................... 47
Table 47. FRPH: Frame Group B, Programmed
Output, High, 0x25 .................................. 48
Table 48. CLKERR1 and CLKERR2: Error Indicator
and Current Status, 0x28 and 0x29 ......... 50
Table 49. SYSERR: System Error Register,
0x2A ........................................................ 50
Table 50. T8100 JTAG Instruction Set ................... 51
Table 51. T8100 JTAG Scan Register .................... 52
Table 52. Time-Slot Bit Decoding ............................ 57
Table 53. IDR: Indirect Data Register, Local
Connections Only .................................... 58
Table 54. IDR: Indirect Data Register, H-Bus
Connections Only ................................... 59
Table 55. Crystal Oscillator ..................................... 67
Table 56. Alternative to Crystal Oscillator ............... 67
Table 57. Electrical Drive Specifications—CT_C8
and /CT_FRAME ..................................... 67
Table 58. dc Electrical Characteristics, All Other
Pins .......................................................... 68
Table 59. ac Electrical Characteristics, Timing,
H-Bus (H.100, Spec., Rev. 1.0) .............. 72
Table 60. ac Electrical Characteristics, Skew
Timing, H-Bus (H.100, Spec., Rev. 1.0) . 73
Table 61. Reset and Power On ............................... 73
Table 62. ac Electrical Characteristics, Local
Streams, and Frames .............................. 74
Table 63. Microprocessor Access Timing (See
Figure 24 through Figure 29.) ................. 77
Table 64. Clock Register Programming Profile for
the Four Previous Examples .................. 85
Table 65. Table of Special Cases (Exceptions) ....... 88
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview (continued)
CT_D26
CT_D25
CT_D24
VSS
CT_D23
CT_D22
CT_D21
CT_D20
VDD
CT_D19
CT_D18
CT_D17
CT_D16
VSS
CT_D15
CT_D14
CT_D13
CT_D12
VSS
CT_D11
CT_D10
(NC)
CT_D9
CT_D8
VDD
CT_D7
CT_D6
CT_D5
CT_D4
VSS
CT_D3
CT_D2
VDD
CT_D1
CT_D0
VSS
/CT_FRAME_A
VSS
CT_C8_A
VSS
CT_NETREF
/FR_COMP
/CT_FRAME_B
VSS
CT_C8_B
VSS
SCLK
VSS
SCLKX2
VDD
C2
VSS
1.3 Pin Information
105
157
53
1
/C4
VSS
/C16+
/C16–
VSS
FGA0
FGA1
FGA2
FGA3
FGA4
FGA5
VDD
FGA6
FGA7
FGA8
FGA9
FGA10
FGA11
VSS
FGB0
FGB1
FGB2
FGB3
FGB4
FGB5
VDD
FGB6
FGB7
FGB8
FGB9
FGB10
FGB11
VSS
GP0
GP1
GP2
GP3
GP4
GP5
TODJAT/GP6
FROMDJAT/GP7
VDD
(NC)
(NC)
(NC)
(NC)
PRIREFOUT
VSS
(NC)
EN1
4MHZIN
PLL1VDD
3MHZIN
(NC)
EN2
DPUE
TRST
TDO
TDI
TMS
TCLK
TTS
VSS
SYSERR
CLKERR
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
RESET
RDY (DTACK)
WR (R/W)
RD (DS)
CS
ALE
A0
A1
VDD
L_SC0
L_SC1
L_SC2
L_SC3
VSS
L_REF0
L_REF1
L_REF2
L_REF3
L_REF4
L_REF5
L_REF6
L_REF7
VDD
XTALIN
XTALOUT
VSS
(NC)
PLL1GND
(NC)
CT_D27
VDD
CT_D28
CT_D29
CT_D30
CT_D31
VSS
LDO0
LDO1
LDO2
LDO3
VDD
LDO4
LDO5
LDO6
LDO7
VSS
LDO8
LDO9
LDO10
LDO11
VDD
LDO12
LDO13
LDO14
LDO15
XCS
VSS
LDI0
LDI1
LDI2
LDI3
LDI4
LDI5
LDI6
LDI7
VDD
LDI8
LDI9
LDI10
LDI11
LDI12
LDI13
LDI14
LDI15
(NC)
TCLKOUT
VSS
(NC)
PLL2GND
(NC)
PLL2VDD
5-6118bF
Figure 1. Pin Diagram
Lucent Technologies Inc.
5
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
Preliminary Data Sheet
August 1998
(continued)
1.3 Pin Information (continued)
A
1
184
180
176
173
171
167
164
162
160
158
155
151
148
144
140
139
B
2
VSS
183
179
175
172
168
165
161
159
156
152
149
145
141
VSS
138
C
6
3
VSS
182
178
174
170
166
163
157
153
150
147
142
VSS
137
134
D
10
7
4
VSS
181
177
169
VDD
VSS
VDD
154
146
143
VSS
136
133
130
E
13
11
9
5
135
132
129
127
F
17
14
12
8
131
128
126
125
G
20
18
15
16
123
124
122
121
H
22
21
19
VDD
VSS
VSS
VSS
VDD
120
119
118
J
24
23
25
VSS
VSS
VSS
VSS
VSS
117
115
116
K
26
27
28
VDD
VSS
VSS
VSS
VDD
111
113
114
L
29
30
32
31
108
107
110
112
M
33
34
36
39
100
104
106
109
N
35
37
40
43
97
101
103
105
P
38
41
44
VSS
51
54
62
VDD
VSS
VDD
77
85
89
VSS
96
99
102
R
42
45
VSS
50
55
58
61
65
71
74
78
82
86
90
VSS
95
98
T
46
VSS
49
53
57
60
64
67
69
73
76
80
83
87
91
VSS
94
U
47
48
52
56
59
63
66
68
70
72
75
79
81
84
88
92
93
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
5-6626(F)
Figure 2. 217 PBGA—Top View
Table 1. Pin Descriptions: Clocking and Framing Pins
6
Symbol
L_REF[7:0]
Pin
45—38
/C16+
/C16–
102
101
Ball
P3, N4, R1, P2, N3,
M4, P1, N2
R14
P13
Type
Name/Description
Local Frame Reference Inputs. 50 kΩ internal pull-up.
I
I/O
H-MVIP 16.384 MHz Clock Signals. Differential 24 mA
drive, Schmitt in, 50 kΩ internal pull-up.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
1 Product Overview (continued)
1.3 Pin Information (continued)
Table 1. Pin Descriptions: Clocking and Framing Pins (continued)
Symbol
/C4
Pin
104
C2
106
SCLK
110
SCLKX2
108
L_SC[3:0]
36—33
FGA[5:0]
94—99
FGA[11:6]
87—92
FGB[5:0]
80—85
FGB[11:6]
73—78
PRIREFOUT
PLL1VDD
58
53
PLL1GND
51
EN1
55
4MHZIN
54
PLL2VDD
208
PLL2GND
206
EN2
3
3MHZIN
XTALIN
1
47
XTALOUT
TCLKOUT
48
203
Lucent Technologies Inc.
Ball
U16
Type
Name/Description
I/O MVIP 4.096 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ
internal pull-up.
T17
I/O MVIP 2.048 MHz Clock. 8 mA drive, Schmitt in, 50 kΩ
internal pull-up.
R17
I/O SC-Bus 2/4/8 MHz Clock. 24 mA drive, Schmitt in, 50 kΩ
internal pull-up.
P15
I/O SC-Bus Inverted 4/8 MHz Clock (Active-Low). 24 mA
drive, Schmitt in, 50 kΩ internal pull-up.
M3, N1, M2, M1
O Local Selected Clocks. 1.024 MHz, 2.048 MHz,
4.096 MHz, 8.192 MHz, 16.384 MHz, frame (8 kHz), or secondary (NETREF). 8 mA drive, 3-state.
R12, T13, U14, P12,
O Frame Group A. 8 mA drive, 3-state.
R13, T14
T11, P11, R11, U12,
T12, U13
U9, R9, U10, T10,
O Frame Group B. 8 mA drive, 3-state.
R10, U11
U6, T7, R8, U7, T8,
U8
P5
O Output from Primary Clock Selector/Divider. 8 mA drive.
U1
— PLL #1 VCO Power. This pin must be connected to power,
even if PLL #1 is not used.
— PLL #1 VCO Ground. This pin must be connected to
No ball for this
ground, even if PLL #1 is not used.
signal, internally
connected.
PLL #1 Enable. Requires cap to VSS to form power-on
T3
I
reset, or may be driven with RESET line. 50 kΩ internal
pull-up.
PLL #1 Rate Multiplier. Can be 2.048 MHz or 4.096 MHz.
U2
I
50 kΩ internal pull-up.
A2
— PLL #2 VCO Power. This pin must be connected to power
if PLL #2 is not used and 3MHZIN is used. Can be left floating only if both PLL #2 and 3MHZIN are not used.
— PLL #2 VCO Ground. This pin must be connected to
No ball for this
ground if PLL #2 is not used and 3MHZIN is used. Can be
signal, internally
left floating only if both PLL #2 and 3MHZIN are not used.
connected.
PLL #2 Enable. Requires cap to VSS to form power-on
C2
I
reset, or may be driven with RESET line. 50 kΩ internal
pull-up.
PLL #2 Rate Multiplier. Input, 50 kΩ internal pull-up.
A1
I
16.384 MHz Crystal Connection or External Clock
R2
I
Input.
T1
O 16.384 MHz Crystal, Feedback Connection.
C4
O Selected output to drive framers. 8 mA drive, 3-state.
7
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
Preliminary Data Sheet
August 1998
(continued)
1.3 Pin Information (continued)
Table 2. Pin Descriptions: Local Streams Pins
Symbol
LDI[15:8]
LDI[7:0]
LDO[15:12]
LDO[11:8]
LDO[7:4]
LDO[3:0]
Pin
201—194
192—185
182—179
177—174
172—169
167—164
Ball
A3, B4, C5, D6, A4, B5, C6, A5
B6, A6, C7, D7, B7, A7, C8, B8
C9, A9, B9, A10
B10, A11, C10, B11
D11, C11, B12, A13
B13, A14, C13, D12
Type
I
O
Name/Description
Local Data Input Streams. 50 kΩ internal pull-up.
Local Data Output Streams. 8 mA
drive, 3-state.
Table 3. Pin Descriptions: H-Bus Pins
8
Symbol
CT_D[31:28]
CT_D[27:24]
CT_D[23:20]
CT_D[19:16]
CT_D[15:12]
CT_D[11:10]
CT_D[9:8]
CT_D[7:4]
CT_D[3:2]
CT_D[1:0]
/CT_FRAME_A
Pin
162—159
157—154
152—149
147—144
142—139
137—136
134—133
131—128
126—125
123—122
120
Ball
A15, D13, C14, B15
A17, C16, D15, E14
C17, D16, E15, F14
D17, E16, F15, E17
F16, F17, G15, G14
G16, G17
H15, H16
H17, J15, J17, J16
K17, K16
L17, K15
L14
Type
I/O
/CT_FRAME_B
114
P17
I/O
/FR_COMP
115
M15
I/O
CT_NETREF
116
N17
I/O
CT_C8_A
118
M16
I/O
CT_C8_B
112
M14
I/O
DPUE
4
D3
I
Name/Description
H-Bus, Data Lines. Variable rate 2 Mbits/s,
4 Mbits/s, 8 Mbits/s. 5 V tolerant, PCI compliant,
50 kΩ internal pull-up.
To conform to H.100, connect an external 24 Ω
series, 1/8 W resistor between each pin and the
bus. Also, data lines 16—31 should be programmed to 8 Mbits/s.
I/O
H-Bus, 8 kHz, Frame. 5 V tolerant, PCI compliant,
24 mA drive, Schmitt in. No pull-up.
H-Bus, Alternate 8 kHz Frame. 5 V tolerant, PCI
compliant, 24 mA drive. Schmitt in. No pull-up.
H-Bus, Compatibility Frame Signal. 24 mA drive,
Schmitt in, 50 kΩ internal pull-up.
H-Bus, Network Reference. 8 kHz, 2.048 MHz, or
1.544 MHz. 8 mA drive, slew rate limited, Schmitt
in. Not internally pulled up.
H-Bus, Main Clock. 5 V tolerant, PCI compliant,
24 mA drive, Schmitt in. No pull-up.
H-Bus, Alternate Main Clock. 5 V tolerant, PCI
compliant, 24 mA drive, Schmitt in. No pull-up.
Data Pull-Up Enable. High enables pull-ups on
CT_Dxx only for H.100, low disables for H.110.
50 kΩ internal pull-up.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
1 Product Overview (continued)
1.3 Pin Information (continued)
Table 4. Pin Descriptions: Microprocessor Interface Pins
Symbol
Pin
24
Ball Type
Name/Description
Master Reset (Active-Low). See Section 3.1 Resets. 50 kΩ internal pullJ1
I
RESET
up.
Microprocessor Interface, Address Lines. Internal 20 kΩ pull-down.
A[1:0]
31—30 L4,
I
L2
I/O Microprocessor Interface, Data Lines. 8 mA drive, 50 kΩ internal pull-up.
D[7:0]
22—15 H1,
H2,
G1,
H3,
G2,
F1,
G4,
G3
Address Latch Enable. Internal 20 kΩ pull-down.
ALE
29
L1
I
Chip
Select (Active-Low). 50 kΩ internal pull-up.
28
K3
I
CS
Read Strobe (Intel Mode [Active-Low]), Data Strobe (Motorola [Active27
K2
I
RD (DS)
Low]). 50 kΩ internal pull-up.
Write Strobe (Intel [Active-Low]), Read/Write Select (Motorola [Active26
K1
I
WR (R/W)
Low]). 50 kΩ internal pull-up.
25
J3
O Data Ready (Intel), Data Transfer (Motorola [Active-Low]).
RDY (DTACK)
8 mA, open drain (user should add pull-up to this line).
CLKERR
13
E1
O Clock Error. Logical OR of CLKERR register flags (only). 8 mA drive,
3-state
SYSERR
12
F3
O System Error. Logical OR of all CLKERR and SYSERR register flags.
8 mA drive, 3-state.
Table 5. Pin Descriptions: JTAG Pins
Symbol
TCLK
TMS
TDI
TDO
TRST
Pin
9
8
7
6
5
Ball
E3
F4
D2
C1
E4
Type
I
I
I
O
I
Name/Description
JTAG Clock Input.
JTAG Mode Select. 50 kΩ internal pull-up.
JTAG Data Input. 50 kΩ internal pull-up.
JTAG Data Output. 8 mA drive, 3-state.
JTAG Reset (Active-Low). 50 kΩ internal pull-up.
Table 6. Pin Descriptions: Power Pins
Symbol
VSS
VDD
Pin
Ball
B2, B16, C3, C15, D4,
11, 23, 37, 49, 57, 72,
86, 100, 103, 105, 109, D9, D14, H8, H9, H10,
J4, J8, J9, J10, J14,
111, 113, 117, 119, 121,
127, 138, 143, 153, 163, K8, K9, K10, L15, N14,
P4, P9, P14, P16, R3,
173, 184, 204
R15, T2, T15, T16,
U15, U17
A16, D8, D10, F2, H4,
14, 32, 46, 63, 79, 93,
107, 124, 132, 148, 158, H14, K4, K14, L16, P8,
P10, T9
168, 178, 193
Lucent Technologies Inc.
Type
Name/Description
Chip Ground.
—
—
3.3 V Supply Voltage.
9
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview
Preliminary Data Sheet
August 1998
(continued)
1.3 Pin Information (continued)
Table 7. Pin Descriptions: Other Pins
Symbol
GP[5:0]
Pin
66—71
Ball
T5, R6, U5, T6, R7, P7
TODJAT/GP6
65
U4
FROMDJAT/GP7
64
R5
XCS
183
A8
TTS
10
D1
(NC)
2, 50, 52, 56,
59, 60, 61, 62,
135, 202, 205,
207
A12, B1, B3, B14, B17,
C12, D5, E2, J2, L3, M17,
N15, N16, P6, R4, R16,
T4, U3
Type
Name/Description
I/O General-Purpose Bidirectional Register. 8 mA drive, Schmitt in, 50 kΩ internal pull-up.
I/O Output from Selector to Drive DJAT
(for NETREF) or GP Register Bit 6.
8 mA drive, Schmitt in, 50 kΩ internal
pull-up.
I/O Smoothed Input to NETREF Divider
and Drivers or GP Register Bit 7.
8 mA drive, input, Schmitt in, 50 kΩ
internal pull-up.
Serial Output from Connection MemO
ory. 8 mA drive, 3-state.
Test Type Select. 0 = JTAG, 1 = forced
I
output test, internal pulldown.
Reserved, No Connection.
—
1.4 Enhanced Local Stream Addressing
1.5 Full H.100 Stream Address Support
Local stream addressing has 1024 locations. Separate
connection and data memories maintain all necessary
information for local stream interconnections. The
streams may operate at maximum rate on eight physical inputs and eight physical outputs. Choices for
slower input or output rates allow enabling of additional
physical inputs or outputs for a maximum of 16 pins
each. Data rates are 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s.
The T8100 provides access to the full 4096 H.100 bus
slots (32 streams x 128 slots) or any standard subset
(H-MVIP has a maximum 24 streams x 128 time
slots, for example). The number of stored time-slot
addresses is limited to 256 at any one time, but these
may be updated on the fly. In addition, accesses to and
from the H.100 bus can be directed through the 1024
local stream/time slots, giving a total space of 5120
time slots. Data rates are programmable on each of
the 32 physical streams, selected in groups of four.
The rates are 2.048 Mbits/s, 4.096 Mbits/s, or
8.192 Mbits/s.
In addition to the enhanced serial streaming, the local
memories may be used for 8-line-serial-in/1-byte-parallel-out, 1-byte-parallel-in/8-line-serial-out, or 1-byteparallel-in/1-byte-parallel-out options. All three data
rates are supported in the parallel modes. The
addresses for the local memories have been simplified
so that stream and time-slot designations are automatically translated to the appropriate memory address,
regardless of rate or serial/parallel modes.
10
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
1 Product Overview (continued)
1.8.3 General-Purpose Register and I/O
1.6 Onboard PLLs and Clock Monitors
A general-purpose register is provided as either a bytewide input or byte-wide output through a separate set
of pins.
The T8100 uses rate multipliers and state machines to
generate onboard frequencies for supporting the
H.100, H-MVIP, MVIP, MC-1, and SC-Buses. Pins are
provided for coupling the internal clock circuitry with
commonly available clock adapters and jitter attenuators. If external resources are not available, an internal
digital phase-locked loop (DPLL) can be used to generate all the bus frequencies and remain synchronized to
an 8 kHz reference. One of several clock input reference sources may be selected, and separate inputactive detection logic can identify the loss of the individual input references. The entire clocking structure operates from a 16.384 MHz crystal or external input.
1.9 Applications
■
Computer-telephony systems
■
Enhanced service platforms
■
WAN access devices
■
PBXs
■
Wireless base stations
1.10 Application Overview
1.7 Phase Alignment of Referenced and
Generated Frames
If this resource is selected, special control logic will create bit-sliding in the data streams when the reference
frame and generated frame are out of phase. The bitsliding refers to removing a fraction of a bit time per
frame until the frames are in phase.
1.8 Interfaces
1.8.1 Microprocessors
The T8100 provides the user a choice of either Motorola or Intel interfacing through an 8-bit data bus, a 2-bit
address bus, and multifunction control pins. All access
to T8100 memory blocks and registers use indirect
addressing.
1.8.2 Framing Groups
Two groups of programmable framing signals are available. Each group is composed of 12 sequenced lines
operating in one of four modes. The T8100 supports
1-bit, 2-bit, 1-byte, and 2-byte pulse widths. Starting
position of the pulse sequences are also programmable.
Lucent Technologies Inc.
The integration of computers and telecommunications
has enabled a wide range of new communications
applications and has fueled an enormous growth in
communications markets. A key element in the development of computer-based communications equipment
has been the addition of an auxiliary telecom bus to
existing computer systems. Most manufacturers of
high-capacity, computer-based telecommunications
equipment have incorporated some such telecom
bus in their systems. Typically, these buses and bus
interfaces are designed to transport and switch
N x 64 kbits/s low-latency telecom traffic between
boards within the computer, independent of the computer’s I/O and memory buses. At least a half dozen of
these PC-based telecom buses emerged in the early
1990s for use within equipment based on ISA/EISA
and MCA computers.
With the advent of the H.100 bus specification by the
Enterprise Computer Telephony Forum, the computertelephony industry has agreed on a single telecom bus
for use with PCI and compact PCI computers. H.100
facilitates interoperation of components, thus providing
maximum flexibility to equipment manufacturers, valueadded resellers, system integrators, and others building computer-based telecommunications applications.
11
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description
The T8100 is an H.100-compliant device that provides
a complete interface between the H.100 bus and a
wide variety of telephony interface components, processors, and other circuits. The bus interface provides
all signals needed for the H.100 bus, the H-MVIP and
MVIP-90 buses, or the SC-Bus. Local interfaces
include 16 serial inputs and 16 serial outputs based on
the Lucent Technologies Microelectronics Group concentration highway interface (CHI). Two built-in timeslot interchangers are included. The first provides a
local switching domain with up to 1024 programmable
connections between time slots on the local CHI inputs
and outputs. The second supports up to 256 programmable connections between any time slot on the H.100
bus and any time slot in the local switching domain.
The Ambassador is configured via a microprocessor
interface. This interface can also read and write time
slot and device data. Onboard clock circuitry, including
a DPLL, supports all H.100 clock modes including
12
Preliminary Data Sheet
August 1998
MVIP and SC-Bus compatibility clocks.
The local CHI interfaces support PCM rates of
2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s. The
T8100 has internal circuitry to support either minimum
latency or multi-time-slot frame integrity. Frame integrity
is a requisite feature for applications that switch wideband data (ISDN H-channels). Minimum latency is
advantageous in voice applications.
The T8100 has four major sections:
■
Local bus—refers to the local streams.
■
H-Bus—refers to the H.100/H.110/H-MVIP and
legacy streams.
■
Interface—refers to the microprocessor interface,
frame groups, and general-purpose I/O (GPIO).
■
Timing—the rate multipliers, DPLL, and clocking
functions.
Figure 3 shows a T8100 block diagram. The T8100
operates on a 3.3 V supply for both the core and I/Os,
though the I/Os are TTL compatible and 5 V tolerant.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
H.100, H.110, H-MVIP, MVIP, SC-BUS
S/P AND P/S CONVERTERS
256
LOCATION
DATA
SRAM
THREE 256
LOCATION
CONNECTION
CAMs
INPUT
LOGIC
AND S/P
CONVERT
LOCAL IN
1024
LOCATION
DATA
MEMORY
OUTPUT
LOGIC
AND P/S
CONVERT
1024
LOCATION
CONNECTION
MEMORY
INTERNAL
ADDRESS
AND
CONTROL
LOCAL OUT
INTERNAL
DATA
INTERNAL
CLOCKS AND
STATE
COUNTER
ADDR[1:0]
DATA[7:0]
MICROPROCESSOR
INTERFACE
FRAME GROUP
INTERFACE
LOGIC
TIMING AND
CONTROL
…
…
…
µP CONTROLS
MISC. I/O
CLOCKS AND REFS
FRAME
GROUPS
5-6101.a (F)
Figure 3. Block Diagram of the T8100
Lucent Technologies Inc.
13
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps
In this section, a general overview of the registers and the indirect mapping to different memory spaces is
described. More detailed descriptions for using the registers in software can be found in Section 3.2 Basic Connections.
(Throughout this document, all registers are defined with the MSB on the left and the LSB on the right.)
2.1.1 Main Registers
The address bits are used to map a large memory space.
All registers default to 0 at powerup.
Table 8. Addresses of Programming Registers
A1
0
0
1
1
A0
0
1
0
1
Name
MCR
LAR
AMR
IDR
Description
Master Control and Status Register (read/write)
Lower Address Register—Lower Indirect Address (time slot) (write only)
Address Mode Register—Upper Address (stream) and Address Type (write only)
Indirect Data Register (read/write)
2.1.2 Master Control and Status Register
Table 9. Master Control and Status Register
14
Bit
7
6
5
Name
MR
CER
SER
4
AP
3
HBE
2
1
LBE
LCE
0
CB
Description
Master (Software) Reset. A high reinitializes the T8100 registers.
Clock Error Reset. A high resets the error bits of the CLKERR registers.
System Error Reset. A high resets the error bits of the SYSERR register. (Note that MR,
CER, and SER are automatically cleared by the T8100 after the requested reset is complete.)
Active Page. This bit identifies which of the double-buffered data memories are active. A
zero indicates buffer 0; a one indicates buffer 1. The AP identifies which data buffer is being
accessed during a write operation (i.e., input from local streams or input from H-Bus).
H-Bus Enable. On powerup or software reset, all H-Bus pins (including clocks) are disabled.
HBE must be set high to reenable the 3-stated buffers.
Local Bus Enable. Same function as HBE for local data outputs.
Local Clock Enable. Enables all other local functions: clocks, frame groups, etc. (Note that
the TCLKO is disabled during a Master Reset and is unaffected by HBE, LBE, or LCE,
though there are control bits for this signal in the CKP register, Section 2.4.6 Clock Control
Register Definitions.)
CAM Busy. A status bit indicating microprocessor activity in any of the CAM blocks. A high
means that one (or more) of the CAMs is being accessed by the microprocessor. In most
cases, this bit will read low since there are many internal operational cycles dedicated to the
microprocessor, which allow it to finish quickly.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps (continued)
2.1.3 Address Mode Register
The AMR is defined in Table 10 below where (aaaa) is the stream address and the LAR is the time-slot address of
the selected memory space.
Note: All unused AMR values are reserved.
Table 10. Address Mode Register
Bits 7—4
Bits 3—0
0000
0001
0010
0100
0101
0111
1001
1010
1011
1011
1011
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111
0000
(aaaa)
(aaaa)
(aaaa)
(aaaa)
0000
0000
0000
0000
0001
0010
0000
0001
0011
0100
0101
0111
1000
1001
1011
1100
1101
1111
0000
0001
0011
1000
1001
1011
1100
1111
Lucent Technologies Inc.
Register Function
Control Registers.
Local Bus, Data Memory 1.
Local Bus, Data Memory 2.
Local Bus, Connection Memory, Time-Slot Field.
Local Bus, Connection Memory, Stream, and Control Bit Field.
Local Bus, Holding Registers, Reset.
CAM, Data Memory 1.
CAM, Data Memory 2.
CAM, Connection, Time-Slot Field.
CAM, Connection, Stream, and Control Bit Field.
CAM, Connection, Tag Field.
CAM, Even, Make Connection (MKCE). Write to next free location.
CAM, Odd, Make Connection (MKCO). Write to next free location.
CAM, Local, Make Connection (MKCL). Write to next free location.
CAM, Even, Break Connection (BKCE).
CAM, Odd, Break Connection (BKCO).
CAM, Local, Break Connection (BKCL).
CAM, Even, Clear Location (CLLE). Requires LAR.
CAM, Odd, Clear Location (CLLO). Requires LAR.
CAM, Local, Clear Location (CLLL). Requires LAR.
CAM, Even, Read Location (RDCE). Requires LAR, IDR holds results.
CAM, Odd, Read Location (RDCO). Requires LAR, IDR holds results.
CAM, Local, Read Location (RDCL). Requires LAR, IDR holds results.
CAM, Even, Find Entry (FENE). IDR holds results.
CAM, Odd, Find Entry (FENO). IDR holds results.
CAM, Local, Find Entry (FENL). IDR holds results.
CAM, Even, Reset (RSCE).
CAM, Odd, Reset (RSCO).
CAM, Local, Reset (RSCL).
CAM, Holding Registers, Reset (RCH).
CAM, Initialize (CI). Reset all CAM locations and holding registers.
15
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps (continued)
2.1.4 Control Register Memory Space
Function of LAR values when AMR = 0x00. All control registers reset to 0x00.
Table 11. Control Register Memory Space
Register
Address
Register
Mnemonic
0, 0x00
1, 0x01
2, 0x02
3, 0x03
4, 0x04
5, 0x05
6, 0x06
7, 0x07
8, 0x08
9, 0x09
10—11, 0x0A—0x0B
12, 0x0C
13, 0x0D
14, 0x0E
15, 0x0F
16, 0x10
17, 0x11
18—23, 0x12—0x17
24, 0x18
25—31, 0x19—0x1F
32, 0x20
33, 0x21
34, 0x22
35, 0x23
36, 0x24
37, 0x25
38—39, 0x26—0x27
40, 0x28
41, 0x29
42, 0x2A
43, 0x2B
44—47, 0x2C—0x2F
48, 0x30
49, 0x31
50, 0x32
51—255, 0x33—0x0FF
CKM
CKN
CKP
CKR
CKS
CK32
CK10
CKMD
CKND
CKRD
(Reserved)
LBS
(Reserved)
CON
(Reserved)
HSL
HSH
(Reserved)
GPR
(Reserved)
FRLA
FRHA
FRLB
FRHB
FRPL
FRPH
(Reserved)
CLKERR1
CLKERR2
SYSERR
CKW
(Reserved)
DIAG1
DIAG2
DIAG3
(Reserved)
16
Refer to
Section
Description
Clocks, Main Clock Selections
Clocks, NETREF Selections
Clocks, Programmable Outputs
Clocks, Resource Selection
Clocks, Secondary (Fallback) Selection
Clocks, Locals 3 and 2
Clocks, Locals 1 and 0
Clocks, Main Divider
Clocks, NETREF Divider
Clocks, Resource Divider
—
Local Stream Control
—
Connection Delay Type
—
H-Bus Stream Control, Low Byte
H-Bus Stream Control, High Byte
—
General-purpose I/O Register
—
Frame Group A, Start Address, Low
Frame Group A, High Address and Control
Frame Group B, Start Address, Low
Frame Group B, High Address and Control
Frame Group B, Programmed Output, Low
Frame Group B, Programmed Output, High
—
Clock Error Register, Error Indicator
Clock Error Register, Current Status
System Error Register
Clock Error/Watchdog Masking Register
—
Diagnostics Register 1
Diagnostics Register 2
Diagnostics Register 3
—
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
2.4.6
—
2.2.4
—
Appendix B
—
2.3.5
2.3.5
—
2.5.2
—
2.5.3
2.5.3
2.5.3
2.5.3
2.5.3
2.5.3
—
2.6
2.6
2.6
2.4.6 & 2.6
—
2.8.2
2.8.2
2.8.2
—
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps (continued)
2.1.4 Control Register Memory Space (continued)
This section is a summary of the register functions. The
reader is encouraged to read through the rest of this
specification to learn the details of the individual registers and their interactions with the overall architecture.
Table 12. CKM: Clocks, Main Clock Selection, 0x00
Bit
7
6
5
4
3
2
1
0
Description
Phase Alignment Enable
Phase Alignment Select
Compatibility Clock Direction
Input Clock Invert
Input Clock Select, MSB
Input Clock Select
Input Clock Select
Input Clock Select, LSB
Table 13. CKN: Clocks, NETREF Selections, 0x01
Bit
7
6
5
4
3
2
1
0
Description
Output Enable
I/O Select
Bypass Select
Input Clock Invert
Input Clock Select, MSB
Input Clock Select
Input Clock Select
Input Clock Select, LSB
Table 14. CKP: Clocks, Programmable Outputs,
0x02
Bit
7
6
5
4
3
2
1
0
Description
TCLK Select, MSB
TCLK Select
TCLK Select, LSB
CT_C8 Pins, Input Type Select
CT_C8A Output Enable
CT_C8B Output Enable
CT_C8 Pins, Output Type Select
(Reserved)
Lucent Technologies Inc.
Table 15. CKR: Clocks, Resource Selection, 0x03
Bit
7
6
5
4
3
2
1
0
Description
Resource Select, MSB
Resource Select, LSB
PLL #1 Bypass
PLL #1 Rate Select
PLL #2 Bypass
PLL #2 Rate Select
SCLK Output Select, MSB
SCLK Output Select, LSB
Table 16. CKS: Clocks, Secondary (Fallback)
Selection, 0x04
Bit
7
6
5
4
3
2
1
0
Description
Secondary Resource Select, MSB
Secondary Resource Select, LSB
Fallback Type Select, MSB
Fallback Type Select, LSB
Fallback, Force Selection of Secondary Input
Secondary Input Clock Select, MSB
Secondary Input Clock Select
Secondary Input Clock Select, LSB
Table 17. CK32: Clocks, Locals 3 and 2, 0x05
Bit
7
6
5
4
3
2
1
0
Description
Local Clock 3 Select, MSB
Local Clock 3 Select
Local Clock 3 Select
Local Clock 3 Select, LSB
Local Clock 2 Select, MSB
Local Clock 2 Select
Local Clock 2 Select
Local Clock 2 Select, LSB
Table 18. CK10: Clocks, Locals 1 and 0, 0x06
Bit
7
6
5
4
3
2
1
0
Description
Local Clock 1 Select, MSB
Local Clock 1 Select
Local Clock 1 Select
Local Clock 1 Select, LSB
Local Clock 0 Select, MSB
Local Clock 0 Select
Local Clock 0 Select
Local Clock 0 Select, LSB
17
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps (continued)
2.1.4 Control Register Memory Space (continued)
Table 19. CKMD: Clocks, Main Divider; CKND:
Clocks, NETREF Divider; CKRD: Clocks,
Resource Divider, 0x07, 0x08, 0x09
Bit
7
6
5
4
3
2
1
0
Description
Divide Value, MSB
Divide Value
Divide Value
Divide Value
Divide Value
Divide Value
Divide Value
Divide Value, LSB
Table 20. LBS: Local Stream Control, 0x0C
Bit
7
6
5
4
3
2
1
0
Description
Parallel/Serial Select, MSB
Parallel/Serial Select, LSB
Local Group A Rate Select, MSB
Local Group A Rate Select, LSB
Local Group B Rate Select, MSB
Local Group B Rate Select, LSB
Local Group C Rate Select, MSB
Local Group C Rate Select, LSB
Table 21. CON: Connection Delay Type, 0x0E
Bit
7
6
5
4
3
2
1
0
18
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Disabled Connection-by-Connection Delay
Setting
Enable Linear Delay
Preliminary Data Sheet
August 1998
Table 22. HSL: H-Bus Stream Control, Low Byte,
0x10
Bit
7
6
5
4
3
2
1
0
Description
H-Bus Group D Rate Select, MSB
H-Bus Group D Rate Select, LSB
H-Bus Group C Rate Select, MSB
H-Bus Group C Rate Select, LSB
H-Bus Group B Rate Select, MSB
H-Bus Group B Rate Select, LSB
H-Bus Group A Rate Select, MSB
H-Bus Group A Rate Select, LSB
Table 23. HSH: H-Bus Stream Control, High Byte,
0x11
Bit
7
6
5
4
3
2
1
0
Description
H-Bus Group H Rate Select, MSB
H-Bus Group H Rate Select, LSB
H-Bus Group G Rate Select, MSB
H-Bus Group G Rate Select, LSB
H-Bus Group F Rate Select, MSB
H-Bus Group F Rate Select, LSB
H-Bus Group E Rate Select, MSB
H-Bus Group E Rate Select, LSB
Table 24. GPR: General-Purpose I/O Register, 0x18
Bit
7
6
5
4
3
2
1
0
Description
General-Purpose I/O, MSB
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O
General-Purpose I/O, LSB
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
Table 27. FRLB: Frame Group B, Start Address
Low, 0x22
Bit
2.1 Register/Memory Maps (continued)
2.1.4 Control Register Memory Space (continued)
Table 25. FRLA: Frame Group A, Start Address
Low, 0x20
Bit
7
6
5
4
3
2
1
0
Description
Start Address, Bit 7, or Programmed Output,
Bit 7
Start Address, Bit 6, or Programmed Output,
Bit 6
Start Address, Bit 5, or Programmed Output,
Bit 5
Start Address, Bit 4, or Programmed Output,
Bit 4
Start Address, Bit 3, or Programmed Output,
Bit 3
Start Address, Bit 2, or Programmed Output,
Bit 2
Start Address, Bit 1, or Programmed Output,
Bit 1
Start Address, LSB, or Programmed Output,
Bit 0
Table 26. FRHA: Frame Group A, High Address and
Control, 0x21
Bit
7
6
5
4
3
2
1
0
Description
Rate Select, MSB
Rate Select, LSB
Pulse Width Select, MSB
Pulse Width Select, LSB
Frame Invert, or Programmed Output, Bit 11
Start Address, MSB, or Programmed Output,
Bit 10
Start Address, Bit 9, or Programmed Output,
Bit 9
Start Address, Bit 8, or Programmed Output,
Bit 8
7
6
5
4
3
2
1
0
Start Address, Bit 7
Start Address, Bit 6
Start Address, Bit 5
Start Address, Bit 4
Start Address, Bit 3
Start Address, Bit 2
Start Address, Bit 1
Start Address, LSB
Table 28. FRHB: Frame Group B, High Address and
Control, 0x23
Bit
7
6
5
4
3
2
1
0
Description
Rate Select, MSB
Rate Select, LSB
Pulse Width Select, MSB
Pulse Width Select, LSB
Frame Inversion Select
Start Address, MSB
Start Address, Bit 9
Start Address, Bit 8
Table 29. FRPL: Frame Group B, Programmed
Output, Low, 0x24
Bit
7
6
5
4
3
2
1
0
Description
Programmed Output, Bit 7
Programmed Output, Bit 6
Programmed Output, Bit 5
Programmed Output, Bit 4
Programmed Output, Bit 3
Programmed Output, Bit 2
Programmed Output, Bit 1
Programmed Output, Bit 0
Table 30. FRPH: Frame Group B, Programmed
Output, High, 0x25
Bit
7
6
5
4
3
2
1
0
Lucent Technologies Inc.
Description
Description
Group A Output Pins Select, MSB
Group A Output Pins Select, LSB
(Reserved, Use 0)
Group B Output Pins Select
Programmed Output, Bit 11
Programmed Output, Bit 10
Programmed Output, Bit 9
Programmed Output, Bit 8
19
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.1 Register/Memory Maps (continued)
2.1.4 Control Register Memory Space (continued)
Table 31. CLKERR1: Clock Error Register, Error
Indicator, 0x28
Bit
7
6
5
4
3
2
1
0
Description
C8A or Frame A Error
C8B or Frame B Error
FR_COMPn Error
C16+ or C16– Error
C4n or C2 Error
SCLKX2 Error
SCLK Error
NETREF Error
Table 32. CLKERR2: Clock Error Register, Current
Status, 0x29
Bit
7
6
5
4
3
2
1
0
Description
C8A or Frame A Fault Status
C8B or Frame B Fault Status
FR_COMPn Fault Status
C16+ or C16– Fault Status
C4n or C2 Fault Status
SCLKX2 Fault Status
SCLK Fault Status
NETREF Fault Status
Table 33. SYSERR: System Error Register, 0x2A
Bit
7
6
5
4
3
2
1
0
20
Description
Even CAM Underflow Error (No Match)
Odd CAM Underflow Error (No Match)
Local CAM Underflow Error (No Match)
Even CAM Overflow or No-Match Error
Odd CAM Overflow or No-Match Error
Local CAM Overflow or No-Match Error
(Reserved)
Fallback Enable Indicator
Preliminary Data Sheet
August 1998
Table 34. CKW: Clock Error/Watchdog Masking
Register, 0x2B
Bit
7
6
5
4
3
2
1
0
Description
C8A and Frame A Error Mask
C8B and Frame B Error Mask
FR_COMPn Error Mask
C16+ and C16– Error Mask
C4n and C2 Error Mask
SCLKX2 Error Mask
SCLK Error Mask
NETREF Error Mask
Table 35. DIAG1: Diagnostics Register 1, 0x30
Bit
7
6
5
4
3
2
1
0
Description
Frame Group A Output Select, MSB
Frame Group A Output Select, LSB
Frame Group B Output Select, MSB
Frame Group B Output Select, LSB
Memory Fill Enable
Memory Fill Pattern Select, MSB
Memory Fill Pattern Select, LSB
Memory Fill Status Bit (Read Only)
Table 36. DIAG2: Diagnostics Register 2, 0x31
Bit
7
6
5
4
3
2
1
0
Description
Frame Groups Cycle Test Enable
Break State Counter into Subsections
Bypass Internal Frame with FR_COMPn
(Reserved)
Enable State Counter Parallel Load
Parallel Load Value of State Counter, MSB
Parallel Load Value of State Counter, Bit 9
Parallel Load Value of State Counter, Bit 8
Table 37. DIAG3: Diagnostics Register 3, 0x32
Bit
7
6
5
4
3
2
1
0
Description
Parallel Load Value of State Counter, Bit 7
Parallel Load Value of State Counter, Bit 6
Parallel Load Value of State Counter, Bit 5
Parallel Load Value of State Counter, Bit 4
Parallel Load Value of State Counter, Bit 3
Parallel Load Value of State Counter, Bit 2
Parallel Load Value of State Counter, Bit 1
Parallel Load Value of State Counter, LSB
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section
Figure 4 shows the local bus section function diagram.
Note:
Routing and MUXing for the H-Bus section is included since the H-Bus requires access to the converters
for local bus-to-H-Bus or H-Bus-to-local bus transfers (the H-Bus is discussed in Section 2.3 H-Bus Section).
XCS is a pseudo serial stream, read out from the connection memory on each memory access. It is read out
directly, i.e., not passing through any parallel/serial converters or holding registers, so it precedes the connection
associated with it by one time slot.
FROM CAM
TO CAM
CAMLOCAL
SELECT
S/P
BYPASS
8
SERIAL
TO
PARALLEL
(S/P)
LOCAL STREAM
INPUTS
8
PARALLEL
TO
SERIAL
(P/S)
8
DATA BUFFERREGISTER
8
8
11
11
ADDRESS 10
BUFFER &
DECODER
P/S
BYPASS
(1024 LOCATIONS
x BITS) x 2
DATA
MEMORY
LOCAL STREAM
OUTPUTS
INTERNAL
DATA BUS
(PATTERN MODE)
CTL BITS
INTERNAL
ADDRESS
BUS
(AMR) + (LAR)
CONNECTION
BUFFERREGISTER
11
ADDRESS
BUFFER &
DECODER
10
1024 LOCATIONS
x 15 bits
CONNECTION
MEMORY
XCS
EACH LOCATION:
STREAM = 4 bits
TIME SLOT = 7 bits
TIME-SLOT ENABLE BIT
CONSTANT/MIN DELAY BIT
PATTERN MODE BIT
XCS BIT
5-6102F
Figure 4. Local Bus Section Function
Lucent Technologies Inc.
21
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.1 Constant Frame Delay and Minimum Delay Connections
The local bus section contains the local connection memory and the double-buffered local data memory. Collectively, the connection memory and data memory are referred to as local memory since it is used for implementing
local-to-local switching only. Operation is similar to other time-slot interchangers. Data is written into the memory in
a fixed order and then read out according to the indirect addresses held in the connection memory. If any of the
connections on the T8100 are operating in constant frame delay (also called constant delay) mode, then the output
data is accessed from a second block of data memory. The input data will not be output until the next frame boundary has been crossed and the memory blocks have swapped functions. Figure 5 shows an example of a set of connections which create the delay types referred to as minimum delay and constant delay.
WRITE N
0
1
2
3
FRAME N DATA
0
1
2
3
READ N
FRAME N – 1 DATA
READ N – 1
CONSTANT DELAY
CONNECTION
MINIMUM DELAY
CONNECTION 1020
1021
1022
1023
1020
1021
1022
1023
DATA BLOCK 1
DATA BLOCK 0
FRAME N
0
1
2
3
FRAME N DATA
READ N
WRITE N + 1
CONSTANT DELAY
CONNECTION
1020
1021
1022
1023
DATA BLOCK 0
0
1
2
3
FRAME N – 1 DATA
READ N + 1
MINIMUM DELAY
CONNECTION
1020
1021
1022
1023
DATA BLOCK 1
FRAME N + 1
5-6103F
Figure 5. Local Bus Memory Connection Modes
22
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.2 Serial and Parallel
Nominally, the memory will be accessed by serial data
streams which will require conversion of serial-to-parallel (S/P) for write accesses and parallel-to-serial (P/S)
for read accesses. Since the local memory can have up
to 16 serial inputs and 16 serial outputs, there will be a
maximum of 16 S/P converters and 16 P/S converters
operating simultaneously. If desired, eight of the S/P
converters, local inputs 0—7, can be bypassed for a
direct parallel write to the data memory. Likewise, eight
of the P/S converters, local outputs 0—7, can be
bypassed for a direct parallel read of the data memory.
Unused S/P or P/S converters are nonfunctional in
these modes.
Note: The normal serial-to-serial local streaming is not
available simultaneously with any of the parallel
modes.
2.2.3 Data Rates and Time-Slot Allocation
At its maximum, the T8100 will be able to process
1024 nonblocking-to-local connections. The data rate
8.192 Mbits/s corresponds to 128 time slots,
4.096 Mbits/s corresponds to 64 time slots, and
2.048 Mbits/s corresponds to 32 time slots. Since different data rates require different amounts of memory,
the local memory can be filled in a number of ways. A
nonblocking switch permits any time slot on any stream
to be switched to another time slot on any stream in
any direction.
Lucent Technologies Inc.
The local streams are arranged in three groups: A, B,
and C. Group A corresponds to the local data pins 0—
7, group B with local data pins 8—11, and group C with
local data pins 12—15. The groups may be operated at
any of the three data rates: 2.048 Mbits/s,
4.096 Mbits/s, or 8.192 Mbits/s; however, group B is
activated only when group A is operating below
8.192 Mbits/s. Likewise, group C is activated when
group B is operating below 8.192 Mbits/s.
Note: In order to efficiently fill the memory, the memory locations are read or filled in the same order
regardless of their activation or rate.
The streams are scanned in intervals equal to
8.192 Mbits/s time slots: first group A from 0 through 7,
then group B from 8 through 11, then group C from 12
through 15. If a group is active, the data is input from or
output to the streams in that group. If a group is operating below 8.192 Mbits/s and has already been scanned
(at the 8.192 Mbits/s rate), then the data transfer operation is ignored.
For T8100 addressing, the user directly provides
stream and time-slot information. The T8100 will map
this into the physical memory, regardless of which
stream groups are active or at what rate. While this
makes programming simpler, it makes the internal
operation more difficult to understand. Several diagrams are required to illustrate how the memory utilization works.
Unassigned time slots in the local output section are 3stated. Therefore, multiple lines can be connected
together.
23
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.3 Data Rates and Time-Slot Allocation (continued)
Figure 6 below shows the overall structure of the local memory:
Note: Both the connection and two data memories are arranged in four blocks of 256 locations each
(i.e., 4 x [4 x 64]).
The arrangement is important to establishing a memory fill pattern which supports all of the various groups and
rates. The rows of each memory, which are split into four groups of 4, correspond to the 16 streams. The columns
correspond to 64 time-slot addresses.
4
4
4
4
4
CONNECTION
MEMORY
4
4
4
DATA MEMORY 0
DATA MEMORY 1
LOCATION 0
LOCATION 15
EACH (SMALL) SQUARE
REPRESENTS 15 bits
OF CONNECTION
INFORMATION
EACH (SMALL)
SQUARE
REPRESENTS 1
byte OF DATA
TO/FROM
LOCAL
STREAMS
64
64
LOCATION 1023
5-6104F
Figure 6. Local Streams, Memory Structure
24
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.3 Data Rates and Time-Slot Allocation (continued)
Examples of how the memory is filled are found in Figure 7.
Note: Again, the user needs only to provide stream and time-slot addresses; the T8100 will generate the internal
memory addresses.
Both the connection and data memories are filled using the same algorithm. In the case where group C is running
at 8.192 Mbits/s, group B is at 4.096 Mbits/s (or 2.048 Mbits/s), and group A is at 2.048 Mbits/s, then an additional
virtual memory space of 4 x 64 locations is created by the T8100 from unused locations in other parts of the memory.
STREAM
0—3
64 TIME SLOTS
STREAM
4—7
STREAM
0—3
STREAM
4—7
STREAM
0—3
STREAM
4—7
STREAM
8—11
STREAM
8—11
TIME SLOT 0
TIME SLOT 1
TIME SLOT 0
TIME SLOT 0
TIME SLOT 1
TIME SLOT 2
TIME SLOT 3
TIME SLOT 1
TIME SLOT 2
TIME SLOT 3
TIME SLOT 4
TIME SLOT 5
TIME SLOT 2
TIME SLOT 4
TIME SLOT 5
GROUP A,
EVEN
TIME SLOTS
GROUP A,
ODD
TIME SLOTS
GROUP A,
ALL
TIME
SLOTS
GROUP
B, EVEN
TIME
SLOTS
GROUP
B, ODD
TIME
SLOTS
64 TIME SLOTS
GROUP A AT 8.192 Mbits/s
GROUPS B AND C OFF
GROUP A AT 4.096 Mbits/s
GROUP B AT 8.192 Mbits/s
AND GROUP C OFF
5-6105F
Figure 7. Local Memory, Fill Patterns
Lucent Technologies Inc.
25
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.3 Data Rates and Time-Slot Allocation (continued)
64 TIME SLOTS
STREAM
4—7
STREAM
8—11
STREAM
12—15
TIME SLOT 0
TIME SLOT 0
TIME SLOT 0
TIME SLOT 0
TIME SLOT 0
TIME SLOT 0 TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
TIME SLOT 1
(USED FOR GROUP C)
TIME SLOT 1
TIME SLOT 2 TIME SLOT 3
TIME SLOT 2
TIME SLOT 2
TIME SLOT 2
TIME SLOT 1
TIME SLOT 2
TIME SLOT 4 TIME SLOT 5
GROUP A,
ALL
TIME
SLOTS
GROUP
B,
ALL
TIME
SLOTS
GROUP
C,
ALL
TIME
SLOTS
GROUP A,
ALL
TIME
SLOTS
GROUP
B,
ALL
TIME
SLOTS
GROUP A AT 4.096 Mbits/s
GROUP B AT 4.096 Mbits/s
GROUP C AT 4.096 Mbits/s
STREAM
0—3
64 TIME SLOTS
STREAM
4—7
STREAM
8—11
STREAM
12—15
GROUP
C,
EVEN
TIME
SLOTS
STREAM
12—15
GROUP C, ODD (VIRTUAL) TIME SLOTS
STREAM
0—3
GROUP A AT 2.048 Mbits/s
GROUP B AT 4.096 Mbits/s
GROUP C AT 8.192 Mbits/s
5-6106F
Figure 7. Local Memory, Fill Patterns (continued)
In any of the parallel modes (S/P, P/S, P/P), the local memories treat parallel data as a series of sequential time
slots (i.e., all one stream): 8.192 Mbits/s corresponds to 1024 time slots, 4.096 Mbits/s corresponds to 512 time
slots, and 2.048 Mbits/s corresponds to 256 time slots. The memory locations are scanned in order from 0 to 1023
at 8.192 Mbits/s, even locations are scanned at 4.096 Mbits/s (odd locations are skipped), and at 2.048 Mbits/s,
every second even location is scanned.
26
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.4 LBS: Local Stream Control, 0x0C
The normal mode of operation for local streams is serial in/serial out, but parallel modes are available. Modes and
data rates are controlled by register LBS. The mapping is shown below. See the preceding pages for a full description.
Table 38. LBS: Local Stream Control, 0x0C
REG
LBS
R/W
—
Symbol
P/S
Bit
7—6
SGa
5—4
SGb
3—2
SGc
1—0
Bit 7
Bit 6
P/S
Bit 5
Bit 4
SGa
Bit 3
Bit 2
SGb
Bit 1
Bit 0
SGc
Name/Description
P/S = 00. Serial In/Serial Out.
The SGa bits control the group A pins, SGb bits control the group B pins, and SGc bits control the
group C pins. As serial streams, input and output rates within the same group are constrained to
be identical so both inputs and outputs share the same 2 bits for programming.
The SGb bits are enabled when SGa ≠ 11.
The SGc bits are enabled when SGb ≠ 11.
P/S = 01. Serial In/Parallel Out.
SGa sets input (serial) rate using the rate definition within this table.
SGb is reserved.
SGc sets the output (parallel) rate using the rate definition within this table.
P/S = 10. Parallel In/Serial Out.
SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (serial) rate.
P/S = 11. Parallel In/Parallel Out.
SGa sets input (parallel) rate.
SGb is reserved.
SGc sets output (parallel) rate.
SGa = 00, 3-state.
SGa = 01, 2.048 Mbits/s.
SGa = 10, 4.096 Mbits/s.
SGa = 11, 8.192 Mbits/s.
SGb = 00, 3-state.
SGb = 01, 2.048 Mbits/s.
SGb = 10, 4.096 Mbits/s.
SGb = 11, 8.192 Mbits/s.
SGc = 00, 3-state.
SGc = 01, 2.048 Mbits/s.
SGc = 10, 4.096 Mbits/s.
SGc = 11, 8.192 Mbits/s.
There are no additional registers required for addressing the local memory other than the main address registers
(discussed in Section 2.1 Register/Memory Maps). The data and connection memory locations can be queried for
their contents by indirect reads through the main address registers; however, the memory locations are referred to
by the stream and time-slot designators, rather than physical address locations, to simplify the queries.
Lucent Technologies Inc.
27
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.2 Local Bus Section (continued)
2.2.5 State Counter Operation
All operations are synchronized to the master state counter. The state counter is in turn synchronized to the internal frame signal and driven by an internal 65.536 MHz clock. In normal operation, the internal frame and clock are
synchronized to either the H-Bus or trunks (see Section 2.4 Clocking Section, for a more detailed explanation of
clocking options). The local memory states are illustrated in Figure 8. The state counter is a modulo-8192 counter
(7 bits for time slot, 4 bits for stream, 2 bits for state function) which can also be reset and loaded with other values
for diagnostic purposes (as described in Section 2.8 Testing and Diagnostics). The H-Bus memories are also referenced to this state counter so that T8100 maintains synchronization with the H-Bus to ensure proper access to the
bus as well as ensure synchronization between the H-Bus and local memory structures. The H-Bus memories are
discussed in Section 2.3 H-Bus Section.
L0
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
976 ns
61 ns
CONNECTION
MEMORY
DATA
SRAM
H6 READ
H6 WRITE
MICROPROCESSOR
MICROPROCESSOR
H6 READ
MICROPROCESSOR
CLOCK
15.25 ns
5-6107F
Figure 8. Simplified Local Memory State Timing, 65.536 MHz Clock
28
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.3 H-Bus Section
2.3.1 Memory Architecture
To access the H-Bus, the T8100 uses a new twist
on an existing approach to accessing large address
spaces: the data is stored in an independent doublebuffered SRAM which acts like the local data memory,
but the connection information for the H-Bus is held in
three 256 location CAMs. Two CAMs are used for two
groups of 16 H-Bus streams each, and one CAM for all
16 local input/output pairs. Each CAM compares
16 streams for read and write and allows access time
to the host microprocessor for updates to the connections. Thus, each stream is allotted three operations
per 976 ns time slot, so there are a maximum of 48
accesses per CAM per time slot. The CAMs must operate for at least 20.34 ns/access* or faster. The selected
technology operates at 13 ns/access maximum, so an
internal clock speed of 15.26 ns (65.536 MHz) is used.
For the following discussions, the reader should refer to
Figure 9. The combined comparison plus retrieval
operations take 2 CAM cycles, leaving little time for
microprocessor updates. To circumvent this, a separate
SRAM (actually, a register file) is tied to each CAM.
Each entry of this register file is associated with an
entry in the CAM on a location-by-location basis. (For
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example, physical address 0xA7 in the CAM is coupled
with physical address 0xA7 of the register file.) The
CAMs will have only the comparand field for stream
and time-slot addresses, and the associated register
files will hold the data field, which is comprised of a tag
(an indirect pointer to the double-buffered data SRAM)
and some control bits. Using the associated SRAM
allows the operations to be pipelined so that the data
retrieval occurs while the CAMs are doing the next
comparison. The SRAM is double-buffered to permit
constant delay or minimum delay on a connection-byconnection basis, as described in Section 2.2.1 Constant Frame Delay and Minimum Delay Connections
and as illustrated in Figure 5.
* The H-Bus presents a unique set of problems. A full nonblocking,
double-buffered switch of 5120 locations has significant barriers in
size and in control of memory access time. Further, the traffic
between the local bus and H-Bus is generally limited to a small
number of time slots at any given moment (120 full duplex is typical,
although we are permitting 128 duplex or 256 simplex connections),
but the requirement to access any time slot out of the full range of
5120 locations remains. To solve this, content addressable memories (CAM) are utilized. They provide access to the full 5120 locations through an encoded width (13 bits), but require a depth equal
to the maximum number of connections required (256).
29
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.1 Memory Architecture (continued)
READ/WRITE
VALID ENTRY MARKER
ADDRESS
A
11
TAG
A
………………… 1
T
T
7 ……………… 0
H-BUS:
EVEN STREAMS
A12 = 0
A0 = 0
……………………
0
CAM-E
PATTERN/NORMAL
DATA SRAM SELECT
PATTERN MODE
OUTPUTS TAG
TO H-BUS
READ/WRITE AND
SRAM SELECT
CE-SRAM
255
ADDRESS
A
11
…………………
D
D
D D
7 ……………… 0 7 ……………… 0
TAG
T
T
7 ……………… 0
A
1
0
CAM-O
CO-SRAM
H-BUS
DATA SRAM
……………………
H-BUS:
ODD STREAMS
1 = 01
A12 = 0
A0 = 1
……………………
0
255
ADDRESS
A
10
…………………
TAG
255
T
T
7 ……………… 0
A
0
DATA BUFFER 0 DATA BUFFER 1
LOCAL 0—15
A12.A11 = 11
CAM-L
……………………
0
THIS IS THE H-BUS DATA MEMORY:
EFFECTIVE ACCESS TIME < 10 ns
CL-SRAM
LOCAL I/O
255
THIS IS THE H-BUS CONNECTION MEMORY:
3 CAMS, MAXIMUM OF 48 ACCESSES PER 976 ns
TIME SLOT, REQUIRES <20 ns/ACCESS
PATTERN MODE
OUTPUTS TAG
TO LOCAL OUT
5-6108F
Figure 9. CAM Architecture
The maximum number of connections is set by the number of locations in the data SRAM and the CAMs. In this
implementation, 256 simplex connections are permitted. Since one connection requires two CAM entries pointing
to a common data location, the maximum number of connections could be reduced to 128 simplex if all connection
entries reside within only one CAM. The maximum number of connections is increased above 256 simplex if the
connection type is broadcast, i.e., from one to many.
30
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands
The three CAMs operate in parallel. Each CAM’s comparand field is compared with the state counter (Section 2.2.5 State Counter Operation) which holds the
existing stream and time-slot value*. If there is a match,
the CAM issues a hit. If there is more than one match,
then it is considered a multiple hit. Likewise, no match
is a miss. As a part of the state counter, a bit is toggled
for read/write. The read/write bit is stored in the CAM,
so it becomes part of the value to be compared. If the
comparison for a write yields a hit, then there is a
request for write access to the data memory for the
incoming data from the H-Bus. If the comparison for a
read yields a hit, then there is a request for a read
access from the data memory for outgoing data to the
H-Bus. Any multiple hit within one CAM block is treated
as a controlled error although it is not reported. The
action taken is to acknowledge the hit which corresponds to the lowest physical address of the CAM. A
miss implies no action. A multiple hit is assigned to be
more than one valid connection. These are prioritized
Lucent Technologies Inc.
such that the match with the lowest physical address
(i.e., closest to CAM location 0x0) is the address which
is processed. Thus, errors are handled in a controlled
manner. Multiple hits can occur because multiple locations are assigned to the same time slot. Bad software
can cause this problem. A controlled error has no
impact on performance, and the CAM contents are not
changed as a result of the error. The data SRAMs are
actually dual-port register files which will process both
writes and reads on each clock cycle of the clock. The
T8100 can process a read and write request from each
CAM and two microprocessor requests during the time
of one address comparison. Due to the fixed order of
operations, the data SRAM cannot overflow or underflow like the CAMs. The timing is shown in Figure 10.
* As mentioned in Section 2.2.5 State Counter Operation, for each
stream and time-slot value, the state counter goes through four
functional states for each stream and time slot. These states are
used to synchronize the CAMs, pipeline register files, data SRAMs,
and microprocessor accesses just as they are used to synchronize
local memory operations and the frame groups. (Microprocessor
accesses to the memories are initiated asynchronously, though the
actual microprocessor cycles are synchronous.)
31
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands (continued)
H0
H1
L0
H2
H3
L1
H4
H5
L2
H6
H7
L3
H8
H9
L4
H10
H11
L5
H12
H13
L6
H14
H15
L7
H16
H17
L8
H18
H19
L9
H20
H21
L10
H22
H23
L11
H24
H25
L12
H26
H27
L13
H28
H29
L14
H30
H31
L15
976 ns
61 ns
CAM-E
H12 WRITE
MICROPROCESSOR
H12 READ
MICROPROCESSOR
CAM-O
H13
WRITE
MICROPROCESSOR
H13 READ
MICROPROCESSOR
CAM-L
L6 WRITE
MICROPROCESSOR
L6 READ
MICROPROCESSOR
C0-SRAM
H12 WRITE
MICROPROCESSOR
H12 READ
MICROPROCESSOR
C1-SRAM
H13
WRITE
MICROPROCESSOR
H13 READ
MICROPROCESSOR
CL-SRAM
L6 WRITE
MICROPROCESSOR
L6 READ
MICROPROCESSOR
DATA SRAM WRITES
EVEN (H12)
ODD (H13)
LOCAL (L6)
MICROPROCESSOR
DATA SRAM READS
MICROPROCESSOR
EVEN (H12)
ODD (H13)
LOCAL (L6)
CLOCK
15.25 ns
5-6109F
Figure 10. Simplified H-Bus State Timing, 65.536 MHz Clock
32
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands (continued)
A number of commands are available to control the
CAMs. Connections can be made or broken, entry data
can be searched for, individual locations may be read
or cleared, or the CAMs can be reset. The address
mode register (AMR) (see Section 2.1 Register/Memory Maps) is used to issue the CAM control commands.
Some commands require the use of the lower address
register (LAR), and some use the IDR as a transfer register.
The tags in each CAM’s associated register file reference the storage location of the data being transferred,
so each CAM/tag location also has control information.
The three control bits are read-to/write-from data
SRAM (i.e., a direction bit, located in the CAM and
used during the comparison operations), a pattern
mode enable, which bypasses the data SRAM and outputs the tag directly into the specified time slot for
writes to the bus, and an SRAM buffer select that controls the minimum delay or constant delay select,
equivalent to the local memory’s selection of minimum
or constant delay.
In addition, the CAM carries a valid entry bit. This is an
identifier for the status of the CAM (and corresponding
register file) location. If the bit is low, as all validity bits
are after a reset, then the location is available to be
written into. When data is written into a location, then
this bit is set, indicating that this is a valid entry. If specific data is no longer valid, such as when a connection
is broken, then the bit is cleared.
Lucent Technologies Inc.
The CAM commands make use of either one or two
cycles. The two cycles are described pictorially in Figure 11. The reader will note that matching and retrieval
are actually separate cycles. The need for two cycles
accounts for the requirement of the pipeline register
files.
Detailed descriptions of the commands follow:
The basic make connection command is referred to as
MKCn, where n is the CAM designator*. The MKCn
uses two CAM cycles: first, the CAM is searched to
determine where to find the next free location (as determined by the validity bits), and during the second cycle,
the next empty location is written into. The MKCn command uses holding registers which convey the connection information to the CAM and its associated register
file. The three holding registers contain the lower connection address (i.e., time slot), the upper connection
address (stream plus control bits), and the tag. An
attempt to write to a full CAM (all 256 locations fully
occupied) results in an overflow error flagged through
the system error register, SYSERR (see Section 2.6
Error Registers).
Note: A single MKCn command only specifies one half
of a connection. The MKCn specifies the connection address and a pointer to the data memory, but a second connection address and
pointer to the same data memory location must
also be provided for a complete connection.
* The H-Bus CAM covering the 16 even-numbered H-Bus streams is
designated E, the H-Bus CAM covering the 16 odd-numbered HBus streams is designated O, and the CAM that services the 16
local stream pairs is designated L.
33
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands (continued)
APPLY COMPARAND,
i.e., STREAM + TIME SLOT
CONTROLS,
e.g., SEARCH
FOR EMPTY
ONE CYCLE CAM
OPERATION:
MATCH COMPARAND
OR
GET STATUS
IDENTIFY HIT OR EMPTY
(FLAGS) THEN RETRIEVE
PHYSICAL LOCATION IN CAM,
i.e., LOCATION 0—255
FLAGS
RETRIEVE
PHYSICAL LOCATION
CONTROLS
APPLY PHYSICAL LOCATION TO
CAM, i.e., LOCATION 0—255
FLAGS
ONE CYCLE CAM
OPERATION:
GET COMPARAND OR
TAG, OR
CHANGE STATUS
RETRIEVE COMPARAND OR DATA,
i.e., GET STREAM + TIME SLOT FROM CAM
OR GET TAG FROM PIPELINE REGISTER FILE
APPLY COMPARAND,
i.e., STREAM + TIME SLOT
CONTROLS
PHYSICAL
LOCATION
IN
TWO CYCLE CAM
OPERATIONS:
IDENTIFY COMPARAND
AND RETRIEVE TAG
OR
IDENTIFY COMPARAND
AND CHANGE STATUS
FLAGS
PHYSICAL
LOCATION
OUT
RETRIEVE DATA,
i.e., GET TAG FROM PIPELINE REGISTER FILE
5-6110F
Figure 11. Illustration of CAM Cycles
34
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.2 CAM Operation and Commands (continued)
If the user determines that a stream/time slot is no
longer valid, then the validity bit may be cleared by presenting the connection address to the CAM and by
using the BKCn, break connection, command. The
connection that the user intends to break, which consists of the time slot, and the stream plus control bits,
but not the tag, is transferred to the holding registers
prior to issuing this command. This is a two-cycle command: during the first cycle, the connection address is
presented to the CAM to identify which physical location holds that connection address, and then, in the
second cycle, the validity bit is cleared for the identified
physical location. If there is a miss, it flags a no-match
error through the underflow bit in SYSERR.
Note: A complete connection break requires two
BKCn commands, one for each half of the connection, as with the MKCn command.
The clear location command, CLLn, is a one-cycle
command. The LAR contains the physical address (i.e.,
the physical CAM location) to be cleared. When it is
presented to the CAM, the validity bit is cleared, returning the location to an empty status (i.e., it becomes
available for new make connection commands). The
CLLn can also be regarded as the second cycle of a
break connection command. CLLn is valuable if several
outputs are driven from a common input (broadcast)
and the user wishes to break one of the output connections, but leave the others intact. When the physical
location in the CAM is identified, either by software
tracking or by use of the find entry command (later in
this section), then the CLLn can be issued.
Lucent Technologies Inc.
If the user wishes to poll the CAM for its contents, then
the RDCn or read CAM command can be used to
query a particular location (0—255) in a specific block
using the LAR for the location address. The contents of
the CAM and tag location are transferred to the holding
registers, and then the time slot, stream plus control,
and tag are returned (in sequence) from three consecutive IDR reads. The actual RDCn operation is onecycle.
The converse of the RDCn is the FENn, or find entry
command. It can be thought of as the first cycle of a
BKCn command. Only time slot and stream plus control bits are necessary for identifying the location. The
tag is not needed. The value returned to the IDR is the
physical location of the entry in the CAM block, if it is
found. If the entry is not found, then the underflow error
bit in the SYSERR register will be set. FENn is a onecycle command.
RSCn is the reset CAM command, and this renders all
locations in one CAM block invalid. This can be considered a CLLn for all locations in the CAM. Two special
resets are the RCH command, which resets only the
holding registers, and the CI command, which resets
all three CAM blocks and the holding registers. All
resets are one-cycle.
2.3.3 H-Bus Access
There are 32 bidirectional pins available for accessing
the H-Bus. The direction of the pins is selected by the
CAM read and write bits. Data rates for the pins are
selected in accordance with the H.100/H.110 specifications. Unassigned time slots on the H-bus are 3-stated.
Details about rate selection are provided below. Two
bits of the 13-bit address are used to select the CAM
block as indicated in Figure 9. The remaining
11 bits plus a read/write bit form a comparand that is
stored in a CAM location.
35
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.3 H-Bus Section (continued)
2.3.4 L-Bus Access
The input and output of the CAM have the appropriate
links to the local stream pins so that the H-Bus streams
may be routed to and from the local bus streams. The
LBS register (Section 2.2.4 LBS: Local Stream Control,
0x0C) programs the local stream rates even if
accessed by the CAMs. To address the local bus CAM
block, the two most significant address bits of the physical address are set to the appropriate values as
described in Figure 9. The other bits form the comparand along with a read/write bit. When the CAM is
outputting data to the local bus, it has priority over the
local bus memory. In other words, if both the local bus
and H-Bus access the same local stream and time slot,
the H-Bus data memory will provide the actual data,
not the local connection.
2.3.5 H-Bus Rate Selection and Connection
Address Format
Operating rates are selected in a manner similar to the
local side. Two registers, HSH and HSL, shown below,
define the operation of the 32 streams. Again, SGx
refers to stream groups: HSH holds SGh—SGe where
SGh programs streams 28—31, SGg programs
streams 24—27, SGf programs streams 20—23, and
SGe programs streams 16—19. HSL holds SGd—SGa
where SGd programs streams 12—15, SGc programs
streams 8—11, SGb programs streams 4—7, and SGa
programs streams 0—3.
SGh
SGd
SGg
SGc
SGf
SGb
Thirteen bits are required to cover the 5120 possible
time slots, but the MSB, LSB combination is used to
determine which H-Bus CAM is accessed: even H-Bus
(0, 0), odd H-Bus (0, 1). The local H-Bus is accessed
by selecting the upper 2 MSBs, both equal to 1. The
CAM address can be thought of as following this format:
CAM Select Field Time-Slot Field
2 bits
A quick summary:
7 bits
Stream Field
4 bits
This format is rate independent. The CAM select field is
part of the address mode register (AMR) for CAM commands (Section 2.1.3 Address Mode Register and Section 2.3.2 CAM Operation and Commands). Programming examples for setting up connections can be found
in Section 3.2 Basic Connections.
2.4 Clocking Section
The clocking section performs several functions which
are detailed in the following paragraphs. In general,
when the T8100 is a bus master, it will have one or
more companion devices which provide the basic clock
extraction and jitter attenuation from a source (such as
a trunk). As a slave, the T8100 can work independently
of, or in conjunction with, external resources. Examples
of different operating modes are provided in Appendix
A. Refer to Figure 12 for a block diagram of the T8100
clocking section.
When the T8100 is used as a bus master, an input
clock of a tolerance of ±32 ppm is required. This can
come from several sources. For example:
■
SGe
SGa
SGn = 00, 3-state
SGn = 01, 2.048 Mbits/s
SGn = 10, 4.096 Mbits/s
SGn = 11, 8.192 Mbits/s
Preliminary Data Sheet
August 1998
±32 ppm crystal tolerance is the suggested value if
either the DPLL is used or fallback to the oscillator is
enabled while mastering the bus. Otherwise, a crystal with a lesser tolerance can be used.
■
If a crystal is not used, a 16.384 MHz (±32 ppm tolerance or less) signal must be provided to the XTALIN
pin, and XTALOUT should be left unconnected.
■
The L_REF inputs can also be used and must conform to ±32 ppm in a bus master situation.
The CAMs and the pipeline register files operate as
connection memories. The key CAM operation is based
on 11 bits of stream and time slot plus 1 bit of read/
write in the CAM locations compared against the state
counter which tracks the current stream and time slots
(Section 2.2.5 State Counter Operation). Each H-Bus
CAM is looking for matches on 16 of the 32 H-Bus
streams, and the local CAM is looking for a match on
16 local inputs and 16 local outputs per time slot.
36
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
TODJAT/GP6
FROMDJAT/GP7
NETREF
INT/EXT
SELECT
GP6
GP7
THESE INPUTS
FORM
TRANSCEIVERS
WITH THE
CORRESONDING
OUTPUTS
DJAT BYPASS
(AND GP6/7 ENABLE)
DIVIDE REGISTER
FRAME
EN_B
C8
÷ BY 8
BIT SLIDER
CONTROLS
FRAME SYNC
FRAME
SEL.
/FR_COMP
4 MHz
BIT SLIDER
INTERNAL CONTROL
CLOCKS AND SYNC
CT_C8_A
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B
COMPATIBILITY
CLOCKS DIRECTION
16.384 MHz
STATE
MACHINES
2 MHz
CLOCK
SEL.
CT_NETREF
FRAME
NETREF
SELECT
/CT_FRAME_A
/CT_FRAME_B
EN_NETREF
NETREF
EN_A
C8
NETREF
DIVIDE-BY-N
NETREF
SEL.
2.048 MHz
4.096 MHz
PLL #1 BYPASS
DPLL
/CT16 ±
C2
/C4
2.048 MHz
4.096 MHz
L_REF7
CT_NETREF
CT_C8_A
CT_C8_B
/C16±
/C4
C2
SCLK
SCLKx2
THESE INPUTS
FORM
TRANSCEIVERS
WITH THE
CORRESPONDING
OUTPUTS
SCLK
RESOURCE
DIVIDE-BY-N
L_REF0
CLOCK
SEL.
AND
INPUT
STATE
MACH.
8.192 MHz
PLL #1
DIVIDE REGISTER
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
65.536 MHz
MEMORY
CLOCK
x16
CLOCK
RESOURCE
SELECT
SCSEL
4.096 MHz
x32
8.192 MHz
FRAME
RATE SELECT
SCLK2
/FR_COMP
SEC8K
PLL #2 BYPASS
FRAME
DIVIDE
BY 4*
2.048 MHz
(FALLBACK PATH*)
4.096 MHz
DIVIDE
BY 2
PLL #2
L_SC0
8.192 MHz
16.384 MHz
x8
DPLL#2 ÷ 2
x16
RATE SELECT
XTALIN
TCLK
SELECT
L_SC CTL
TCLK
ENABLE
PRIREFOUT
4MHzIN
3MHzIN
(1 OF 4
L_SC[1:3]
NOT SHOWN)
TCLKO
5-6111F
* The path for XTALIN divide-by-4 is for fallback only.
Figure 12. Clocking Section
Lucent Technologies Inc.
37
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.1 Clock and NETREF Selection
The inputs to the T8100 clocking come from three
selectors. The clock selector and frame selector operate from a common set of selection options in register
CKM (see Section 2.4.6 Clock Control Register Definitions for register details), where FRAMEA is selected
along with clock C8A and FRAMEB is selected along
with clock C8B. Typically, one of the local references
(LREF[0:7]) will be selected when the T8100 is operating as a master, though the local oscillator is also available. As a slave, the most common selections will be
one of the bus types. Each bus type has a state
machine associated with it for determining the frame
sync. All clock inputs are sampled to check for proper
switching. If the expected clock edge does not occur,
and there is no switching on CT_NETREF for 125 µs, a
bit corresponding to the errant clock is set in the CLKERR register (see Section 2.6 Error Registers for more
details). NETREF can be created from one of the local
references or from the oscillator independent of the
clock generation.
2.4.2 Dividers and Rate Multipliers
The clock and NETREF selections are routed to dividers*. In the case of NETREF, the divider is
usually used to reduce a bit rate clock to 8 kHz,
so the most common divisors will be 1, 193
(1.544 MHz/8 kHz), and 256 (2.048 MHz/8 kHz),
although a full range of values (from 1—256) is possible. For the clock selector, the signal will most often be
routed through the main divider when the T8100 is
operating as a master or through the resource divider
when operating as a slave. Both the main and resource
dividers are fully programmable.
38
Preliminary Data Sheet
August 1998
The ultimate destination for the main or resource
divider is intended to be PLL #1. PLL #1 accepts either
a 2.048 MHz or 4.096 MHz input and will rate multiply
up to 65.536 MHz. The divisor of the main or resource
dividers is chosen in conjunction with the rate select of
the PLL, i.e., a divisor which generates a 4.096 MHz
output and a rate selection of x16, or a divisor which
generates a 2.048 MHz output and a rate selection of
x32. This provides a great deal of flexibility in adapting
to a variety of (external) clock adapters and jitter attenuators while acting as a master, as well as slaving to
several bus types.
A digital PLL that can rate multiply to either 2.048 MHz
or 4.096 MHz from an 8 kHz source in the absence of
an external clock adapter is also provided. PLL #1 can
be bypassed for diagnostic purposes or if an external
clock adapter is used that provides a high-speed output
(65.536 MHz). The input to the DPLL is for an 8 kHz
signal only.
A second rate multiplier is provided for supporting T1
applications. It is optimized around either a 1.544 MHz
or 3.088 MHz input rate which multiplies to 24.704 MHz
and is then divided down to provide 50% duty cycle
clocks of 12.352 MHz, though the direct 24.704 MHz is
available as well. A bypass is provided so that an external clock can be buffered through the TCLK output. The
internal oscillator or the various outputs derived from
PLL #1 can also be selected for the TCLK output.
* If the A clocks have been selected as the clock source through the
CKM register (described in Section 2.4.6 Clock Control Register
Definitions), then the CT_C8A is the signal sent to the main and
resource dividers; likewise, selecting B clocks results in sending
CT_C8B; the MVIP selection sends /C4; the H-MVIP selection
sends the recovered /C16 (derived from differential inputs); selecting SC2 sends SCLKX2; and SC4/8 sends SCLK to the dividers.
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.3 State Machines
The purpose of the state machines is to generate
internal control signals for the remainder of the T8100
circuitry and to provide all bus clocks when operating
as a master. The state machines operate from the
65.536 MHz clock generated by PLL #1, and they are
time referenced to the frame sync derived from the
selected clock and frame inputs. As a master, the time
sync is based on the T8100’s own generated frame.
The dominant internal control signals are a noninverted
32.768 MHz clock, an inverted 16.384 MHz state clock,
and a noninverted 122 ns wide sync pulse centered
around the beginning of a frame. The memories are
synchronized to the 65.536 MHz clock.
2.4.4 Bit Sliding (Frame Locking)
The T8100 generates its own frame signal based on
the incoming clock and frame references and its generated clock signals. When slaving, it is sometimes necessary to align the edges of this generated frame
signal to the incoming frame reference.
To accomplish this, the T8100 will compare the
referenced frames with the current state of its clock
state machine, and if the difference exceeds one
65.536 MHz clock cycle, the entire stream will have a
fraction of a bit time removed from each frame; this is
referred to as bit sliding. The process will repeat until
the measurements fall within one clock cycle. The
actual bit sliding will take place by reducing the generated frame by one 65.536 MHz clock cycle at the
beginning of the frame. This means that the frame
edges will phase-align at the rate of approximately
15.26 ns per frame. The maximum phase difference is
slightly less than one frame or 124.985 µs. Thus, it will
require approximately 8000 frames, or 1 second, to
phase-align the frame. This is also mean time interval
error (MTIE) compliant; performing phase adjustment
of 162 ns per 1.326 ms of total sample time. Refer to
the MTIE specifications document (ATT 62411).
Lucent Technologies Inc.
The alternatives to bit sliding are snap alignment and
no alignment. Snap alignment refers to an instantaneous phase alignment, i.e., a reset at the frame
boundary. This mode is common to other devices. If no
alignment is chosen, the T8100’s generated frame is
frequency-locked to the incoming frame sync, but not
phase-aligned.
2.4.5 Clock Fallback
The following conditions must be met before fallback is
initiated:
■
Fallback must be enabled in register CKS.
■
Failure of one or more of the clocks selected through
the CKSEL bits in the CKM register.
■
All clocks which comprise the selection from CKSEL
must be unmasked in register CKW (see Section 2.6
Error Registers).
The T8100 contains a fallback register which enables a
backup set of controls for the clock resources during a
clock failure. In addition, a fallback state machine provides some basic decision-making for controlling some
of the clock outputs when the feature is enabled. While
slaving to the bus, the primary course of action in fallback is the swap between the A-clocks and B-clocks as
the primary synchronization sources. A slave may
become a master only under software control; i.e.,
there is no automatic promotion mechanism. As a master, the T8100 can detect its own failures and remove
its clocks from the bus. If it detects a failure on the other
main set (e.g., B master detects failures on the A master), then it can assume the role as the primary synchronization source by driving all compatibility clocks
(H-MVIP and SC-Bus). Clock failures are flagged
through the CLKERR1 and CLKERR2 registers (Section 2.6 Error Registers). Additional fallback details are
discussed in relationship to the clock registers in the
next section. The divide-by-4 block for XTALIN, shown
in Figure 12, is used only for fallback. See Figure 13 for
a diagram of the basic state machine which controls
the A, B, and C (compatibility) clocks.
39
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.5 Clock Fallback (continued)
DIAG_ABC = DRIVES A CLOCKS, B CLOCKS,
AND C CLOCKS, NO FALLBACK PERMITTED
DIAG_AB = DRIVES A CLOCKS AND B CLOCKS,
NO FALLBACK PERMITTED
C_ONLY = DRIVES C CLOCKS ONLY,
NO FALLBACK PERMITTED
DIAG_ABC
B_ONLY = DRIVES B CLOCKS,
CAN DRIVE
C CLOCKS IN
FALLBACK CONDITION
A_ONLY = DRIVES A CLOCKS,
CAN DRIVE
C CLOCKS IN
FALLBACK CONDITION
DIAG_AB
THE T8100 ENTERS AND
LEAVES THESE STATES
BASED ON REGISTER
COUNTERS
B_MASTER = DRIVES B AND C CLOCKS,
ALL CLOCKS SHUT OFF IN
FALLBACK CONDITION
A_MASTER = DRIVES A AND C CLOCKS,
ALL CLOCKS SHUT OFF IN
FALLBACK CONDITION
C_ONLY
DIAGNOSTIC/FORCED CLOCKING
FALLBACK CLOCKING, ASSUMES
FALLBACK ENABLED IN CKS REGISTER
INITIAL
B_ERROR = NO CLOCKING,
WAITING FOR B CLOCKS TO BE
REPROGRAMMED
A_ERROR = NO CLOCKING,
WAITING FOR A CLOCKS TO BE
REPROGRAMMED
B CLOCKS FAIL
B_ONLY
B_ERROR
A CLOCKS FAIL
B_MASTER
REPROGRAM
B CLOCKS
B CLOCKS FAIL
A CLOCKS FAIL
A_ONLY
A_ERROR
B CLOCKS FAIL
A_MASTER
REPROGRAM
A CLOCKS
A CLOCKS
FAIL
5-6112F
Figure 13. A, B, and C Clock Fallback State Diagram
40
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions
Table 39. CKM: Clocks, Main Clock Selection, 0x00
The first register, 0x00, is the clock main (CKM) register. There are ten registers to control the various aspects of
clocking.
REG
CKM
Symbol
PAE
PAS
CCD
CKI
CKSEL
R/W
—
Bit
7
Bit 7
PAE
Bit 6
PAS
Bit 5
CCD
Bit 4
CKI
Bit 3
Bit 2
Bit 1
CKSEL
Bit 0
Name/Description
Phase Alignment Enable.
PAE = 0,
Retains frequency lock without phase alignment
PAE = 1,
Enables phase alignment
6 Phase Alignment.
PAS = 0,
Phase alignment, snap
PAS = 1,
Phase alignment, slide
5 The CCD bit is the compatibility clock direction. This controls the I/O for the compatibility
clocks /C16+/–, /C4, C2, SCLK, SCLKX2, and /FR_COMP (compatibility frame). The user can
think of the CCD bit (in some respects) as a master/slave select for the compatibility clocks,
though other registers require proper setup to establish true master or slave operation. The
T8100 will assume control of this bit during a fallback if the previously designated compatibility
clock master fails.
CCD = 0,
Slave, monitors compatibility signals
CCD = 1,
Master, drives compatibility signals
Note: If bit 4 of the programmable clocks register, CKP, is low, then the state machines of the
A clock and B clock will assume this is an MC-1 system and interpret the clocks as
/C4(L/R) and FRAME(L/R). If this bit is high, then it interprets the clocks as C8(A/B)
and FRAME(A/B).
4 CKI is used to invert the output of the clock selector, i.e., the signal which feeds the main
divider, resource divider, and DPLL:
CKI = 0,
Normal
CKI = 1,
Invert
3—0 The decode for the clock selector (CKSEL) is illustrated below. These selections determine
which input state machine is utilized*:
CKSEL = 0000,
Internal oscillator
CKSEL = 0001,
CT_NETREF
CKSEL = 0010,
A clocks (C8A & FRAMEA); ECTF or MC-1
CKSEL = 0011,
B clocks (C8B & FRAMEB); ECTF or MC-1
CKSEL = 0100,
MVIP
CKSEL = 0101,
H-MVIP
CKSEL = 0110,
SC-Bus, 2 MHz
CKSEL = 0111,
SC-Bus, 4 MHz or 8 MHz
CKSEL = 1000—1111 Selects local references 0—7
* Selecting A clocks synchronizes the T8100 to CT_C8A and /CT_FRAMEA; selecting B clocks synchronizes the T8100 to CT_C8B and
/CT_FRAMEB; MVIP uses /C4, C2, and /FR_COMP; H-MVIP uses /C16+/–, /C4, C2, and /FR_COMP; SC2 uses SCLKX2 and /FR_COMP;
SC4/8 requires SCLK, SCLKX2, and /FR_COMP. MC-1 fallback clocks use the same inputs and state machine as the A clocks and B clocks
with an inversion selected from register CKP. A pictorial view of the various clocks may be seen in Section 4.6.1 Clock Alignment.
Lucent Technologies Inc.
41
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions (continued)
Table 40. CKN: Clocks, NETREF Selections, 0x01
Clock register 0x01 is CKN, the CT_NETREF select register. This register selects features for generating and routing the CT_NETREF signal.
REG
CKN
Symbol
NOE
NIO
NDB
NRI
NRSEL
42
R/W
—
Bit 7
NOE
Bit 6
NIO
Bit 5
NDB
Bit 4
NRI
Bit 3
Bit 2
Bit 1
NRSEL
Bit 0
Bit
7
Name/Description
The NOE bit enables the NETREF output:
NOE = 0,
CT_NETREF output disabled (3-state)
NOE = 1,
CT_NETREF output enabled (NIO must be low)
6 The NIO bit controls the internal/external selector. It selects either the NETREF divider for outputs or the NETREF input. Since the latter is used for routing NETREF to the local clock outputs, it will automatically prevent the NETREF output from being enabled:
NIO = 0,
Select NETREF divider, i.e., NETREF as output
NIO = 1,
Select NETREF input (disables NETREF output)
Note: When the NIO bit is high, general-purpose register (GPR), bits 6 and 7 are available.
(The GPR is discussed in Section 2.5.2 General-Purpose Register.)
5
NDB = 0,
TODJAT pin comes from NETREF selector, and FROMDJAT pin
goes to NETREF divider
NDB = 1,
NETREF selector goes directly to NETREF divider
4 NRI inverts the output of the NETREF selector.
NRI = 0,
Normal
NRI = 1,
Invert
3—0 The NRSEL is similar to CKSEL but with fewer choices:
NRSEL = 0000,
Internal oscillator divided by 8
NRSEL = 0001,
Internal oscillator
NRSEL = 0010—0111, (Reserved)
NRSEL = 1000—1111, Local references 0—7
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions (continued)
Table 41. CKP: Clocks, Programmable Outputs, 0x02
Clock register 0x02, CKP, is the programmed clocks register. It is used for programming the CT_C8 clocks and
enabling its outputs. It is also used to program the TCLK selector. CT_C8 may be operated as either 8 MHz (normal or inverted) or 4 MHz (normal or inverted). The register format is as follows:
REG
CKP
Symbol
PTS
C8IS
CAE
CBE
C8C4
CFW
R/W
—
Bit 7
Bit 6
PTS
Bit 5
Bit 4
C8IS
Bit 3
CAE
Bit 2
CBE
Bit 1
C8C4
Bit 0
CFW
Bit
Name/Description
7—5 The three PTS bits select the output sent to the TCLK. This output is intended to be used for
driving framers.
PTS = 000,
3-state
PTS = 001,
Oscillator, buffered output
PTS = 010,
PLL #2, direct output
PTS = 011,
PLL #2, output divided by 2
PTS = 100,
2.048 MHz from state machines
PTS = 101,
4.096 MHz from state machines
PTS = 110,
8.192 MHz from state machines
PTS = 111,
16.384 MHz from state machines
4 C8IS is used to invert the synchronization on C8A and C8B when they are selected for input.
The C8 and FRAME signals, which are also generated internally, are routed to both the
CT_C8A and /CT_FRAMEA and to the CT_C8B and /CT_FRAMEB. The CAE and CBE pins
enable these output pairs independently. The C8C4 pin selects 8.192 MHz or 4.096 MHz signals to be output on C8A and C8B (for supporting for either ECTF or MC-1* applications).
CFW selects the output width of the compatibility frame.
C8IS = 0,
MC-1 (A and B clocks inputs interpreted as /C4 with /FRAME)
C8IS = 1,
ECTF (A and B clocks inputs interpreted as C8 with /FRAME)
3
CAE = 0,
Disable CT_C8A & /CT_FRAMEA outputs
CAE = 1,
Enable CT_C8A & /CT_FRAMEA outputs (The T8100 will automatically disable these on an A clock failure.)
2
CBE = 0,
Disable CT_C8B & /CT_FRAMEB outputs
CBE = 1,
Enable CT_C8B & /CT_FRAMEB outputs (The T8100 will automatically disable these on a B clock failure.)
1
C8C4 = 0,
Inverted 4.096 MHz (MC-1 output mode)
C8C4 = 1,
Noninverted 8.192 MHz (ECTF output mode)
0
CFW = 0,
(Reserved)
CFW = 1,
(Reserved)
* MC-1 is a multichassis communication standard based on MVIP. The T8100 supports this standard.
Lucent Technologies Inc.
43
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions (continued)
Table 42. CKR: Clocks, Resource Selection, 0x03
Clock register 0x03, CKR, is the clock resources register. It is used for selecting and programming miscellaneous
internal resources, the two PLLs, the DPLL, and the clock resource selector. It is also used to program the
SCLK/SCLKX2 clock outputs. The register format is as follows:
REG
CKR
Symbol
CRS
P1B
P1R
P2B
P2R
SCS
44
R/W
—
Bit 7
Bit 6
CRS
Bit 5
P1B
Bit 4
P1R
Bit 3
P2B
Bit 2
P2R
Bit 1
Bit 0
SCS
Bit
Name/Description
7—6 The CRS[7:6] bits are used to select the input to PLL #1.
CRS = 00,
External input (through the 4 MHz In pin)
CRS = 01,
Resource divider
CRS = 10,
DPLL @ 2.048 MHz
CRS = 11,
DPLL @ 4.096 MHz
5 P1B and P1R control PLL #1.
P1B = 0,
Normal PLL #1 operation
P1B = 1,
Bypass PLL #1
4
P1R = 0,
PLL #1 rate multiplier = 16
P1R = 1,
PLL #1 rate multiplier = 32
3 P2B and P2R control PLL #2.
P2B = 0,
Normal PLL #2 operation
P2B = 1,
Bypass PLL #2
2
P2R = 0,
PLL #2 rate multiplier = 8
P2R = 1,
PLL #2 rate multiplier = 16
1—0 The SCS[1:0] bits are used to program the outgoing SC-Bus compatibility signals.
SCS = 00,
SC-Bus outputs 3-stated
SCS = 01,
SCLK @ 2.048 MHz, SCLKX2 @ 4.096 MHz
SCS = 10,
SCLK @ 4.096 MHz, SCLKX2 @ 8.192 MHz
SCS = 11,
SCLK @ 8.192 MHz, SCLKX2 @ phase shifted 8.192 MHz
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions (continued)
Table 43. CKS: Clocks, Secondary (Fallback) Selection, 0x04
Clock register 0x04 is CKS, the secondary clock selection register. This is also referred to as fallback. Along with
programming the CKS register, CKW and CKS should be programmed last. The register is defined as follows:
REG
CKS
Symbol
FRS
FTS
FF
FCSEL
R/W
—
Bit 7
Bit 6
FRS
Bit 5
Bit 4
FTS
Bit 3
FF
Bit 2
Bit 1
FCSEL
Bit 0
Bit
Name/Description
7—6 FRS provides an alternate clock resource selection. FTS determines the basic fallback mode.
FF forces the use of the FRS, FTS, and FCSEL. FCSEL is used to select an alternate synchronization source.
FRS forces the clock resource selector to choose a new source for PLL #1.
FRS = 00, External input (through the 4 MHz In pin)
FRS = 01, Resource divider
FRS = 10, DPLL @ 2.048 MHz
FRS = 11, DPLL @ 4.096 MHz
Note: The decode is the same as that of the CRS bits (in the clock resource register, CKR).
5—4 For fallback type select, the two FTS bits are used to enable the automatic fallback. These work
in conjunction with the various clocks as described in Section 2.4.5 Clock Fallback. If the C8
input select (C8IS of the CKP register above) is low, then the T8100 is assumed to be in an
MC-1 system. Thus, the A/B clocks can be interpreted as /C4L (or /C4R) for C8A and /C4R (or
/C4L) for C8B.
FTS = 00,
Fallback from main clock to the oscillator divided by 4* when main clock fails.
(Main clock determined by CKSEL bits of the CKM register.)
FTS = 01,
Fallback disabled; this is not recommended for operation, it is intended for initialization and diagnostic purposes only.
FTS = 10,
Fallback from main selection to secondary source (FCSEL).
FTS = 11,
Fallback from A or B clock (ECTF/MC-1) to secondary; this also enables the
fallback state machine.
When one of the selected bits goes high in the CLKERR register (i.e., clock failure, see Section
2.6 Error Registers), then clocks are changed to the selection indicated by FCSEL, the A or B
clocks are disabled (if applicable), and the compatibility clocks are either driven or disabled (if
applicable). Note that the change is “sticky”; once the fallback has occurred, it will stay in its
new state until the system is reprogrammed. Clearing the CLKERR registers through the MCR
(Section 2.1.2 Master Control and Status Register) clears the fallback condition. A bit in the
SYSERR register will also note when a fallback has occurred.
3 FF is used as a test of the fallback, but can also be used as a software-initiated fallback.
FF = 0,
Normal operation
FF = 1,
Force use of secondary (fallback) resources
2—0 The FCSEL choices are a subset of the CKSEL values from the CKM register above. The list is
presented below:
FCSEL = 000,
Internal oscillator divided by 4
FCSEL = 001,
Internal oscillator
FCSEL = 010,
A clocks (C8A & FRAMEA); ECTF or MC-1
FCSEL = 011,
B clocks (C8B & FRAMEB); ECTF or MC-1
FCSEL = 100,
NETREF
FCSEL = 101—111,
Selects local references 1—3
* This bypasses the CRS/FRS multiplexer and is the default condition. It is equivalent to letting the T8100 free run on a clock failure. It assumes
PLL #1 has been set for x16. If PLL #1 is set for x32, then use FCSEL = 8 kHz local reference, FRS = 10, and FTS = 10.
Lucent Technologies Inc.
45
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.4 Clocking Section (continued)
2.4.6 Clock Control Register Definitions (continued)
Table 44. CK32 and CK10: Clocks, Locals 3, 2, 1, and 0, 0x05 and 0x06
Registers 0x05 and 0x06 set up L_SC0, 1, 2, & 3. The outputs L_SC[3:0] can be used as bit clocks for the local
streams or as a secondary NETREF. These are programmed using CK32 and CK10, which are presented below:
REG
CK32
CK10
Register
CK32
CK32
CK10
CK10
R/W
—
—
Bit
7—4
3—0
7—4
3—0
Symbol
LSC3
LSC2
LSC1
LSC0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
LSC3
LSC1
Bit 2
Bit 1
Bit 0
LSC2
LSC0
Name/Description
LSCn = 0000, Output low
LSCn = 0001, Local frame
LSCn = 0010, NETREF (Sec8K)
LSCn = 0011, PLL #2 ≠ 2
LSCn = 0100, 2.048 MHz
LSCn = 0101, 4.096 MHz
LSCn = 0110, 8.192 MHz
LSCn = 0111, 16.384 MHz
LSCn = 1000, Output high
LSCn = 1001, Local frame, inverted
LSCn = 1010, NETREF, inverted
LSCn = 1011, PLL #2 ≠ 2, inverted
LSCn = 1100, 2.048 MHz, inverted
LSCn = 1101, 4.096 MHz, inverted
LSCn = 1110, 8.192 MHz, inverted
LSCn = 1111, 16.384 MHz, inverted
2.4.7 CKMD, CKND, CKRD: Clocks, Main, NETREF,
Resource Dividers, 0x07, 0x08, and 0x09
The remaining clock registers are used to program the
three dividers. The main divider is programmed
through CKMD; the NETREF divider, through CKND;
and the resource divider, through CKRD. The dividers
are fully programmable, but only binary divides (1, 2, 4,
8, etc.) and divide by 193 produce 50% duty-cycle outputs. All other divisors will produce a pulse equal to
one-half of a (selected) clock cycle in width.
0x00 => Divide by 1 (bypass divider)
0x01 => Divide by 2
:
0xC0 => Divide by 193
:
0xFF => Divide by 256
2.5 Interface Section
2.5.1 Microprocessor Interface
The grouping of the read, write, chip select, and
address latch enable signals, along with the data bus
and the address bus, permit access to the T8100 using
Intel nonmultiplexed interface (ALE = low), Motorola
nonmultiplexed interface (ALE = high), or Intel multiplexed interface (ALE = active). ALE controls the microprocessor mode. All control and status registers and
data and connection memory accesses are controlled
through this interface. All accesses are indirect, following the pin descriptions in Table 1 and Table 2. Programming examples and a more detailed discussion of
the indirect accesses can be found in Section 3 Using
the T8100.
In general, the register value is the binary equivalent of
the divisor-minus-one; e.g., an intended divisor of 193
is reduced by 1 to 192, so the register is loaded with
the binary equivalent of 192 which is 0xC0.
46
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.5 Interface Section (continued)
2.5.2 General-Purpose Register
A simple, general-purpose I/O register is available. The
GPR has eight dedicated pins to the T8100. A write to
the register forces it to operate as an output. It remains
as an output until a read from the register is performed
(which 3-states the output). The register powers up in
the input state with a cleared register. The GPR corresponds with I/O pins GP[0:7]. GP6 and GP7 are
unavailable if bit 5 of register CKN is low (see Section
2.4.6 Clock Control Register Definitions).
2.5.3 Framing Groups
Two groups of frame pulses are available. Each frame
group consists of 12 lines which are enabled sequentially after a programmed starting point. They are
denoted as group A and group B. This section
describes framing group A. Framing group B is made
up of similar registers. Each frame group is controlled
by a pair of registers: FRHA and FRLA control the
spacing of the 12 frame pulses, their pulse width,
polarity, and the offset of the first pulse from the frame
boundary.
Table 45. FRHA, Frame Group A High Address and Control, 0x21
REG
FRHA
R/W
—
Symbol
Rate
Bit
7—6
Type
5—4
FAI
3
Hi Start
2—0
Rate
Rate
Rate
Rate
Type
Type
Type
Type
FAI
FAI
Hi Start
Bit 7
Bit 6
Bit 5
Rate
=
=
=
=
=
=
=
=
=
=
=
Bit 4
Type
Bit 3
FAI
Bit 2
Bit 1
Hi Start
Bit 0
Name/Description
00,
Frame group disabled, 3-state
01,
2.048 Mbits/s
10,
4.096 Mbits/s
11,
8.192 Mbits/s
00,
Bit-wide pulse
01,
Double bit-wide pulse
10,
Byte-wide pulse
11,
Double byte-wide pulse
0,
Normal pulse
1,
Inverted pulse
Upper 3 bits of group start address or programmed output
Table 46. FRHB, Frame Group B High Address and Control, 0x23
REG
FRHB
R/W
—
Symbol
Rate
Bit
7—6
Type
5—4
FAI
3
Hi Start
2—0
Rate
Rate
Rate
Rate
Type
Type
Type
Type
FAI
FAI
Hi Start
Lucent Technologies Inc.
Bit 7
Bit 6
Rate
=
=
=
=
=
=
=
=
=
=
=
Bit 5
Bit 4
Type
Bit 3
FAI
Bit 2
Bit 1
Hi Start
Bit 0
Name/Description
00,
Frame group disabled, 3-state
01,
2.048 Mbits/s
10,
4.096 Mbits/s
11,
8.192 Mbits/s
00,
Bit-wide pulse
01,
Double bit-wide pulse
10,
Byte-wide pulse
11,
Double byte-wide pulse
0,
Normal pulse
1,
Inverted pulse
Upper 3 bits of group start address
47
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.5 Interface Section (continued)
2.5.3 Framing Groups (continued)
The 12 outputs of the frame group are pulsed in
sequence, one every 8 bit times, where the bit time is
set by the rate option. Thus, the rate option controls the
spacing between output pulses. The pulse width is set
by the type option, and the pulse polarity is set by the
FAI bit. Note that double byte-wide types will produce
overlapping pulses.
The remaining bits (3 hi-start bits in FRHA and 8 bits of
FRHB) make up an 11-bit start address that sets the
offset of the group’s first output (pin FGA0) relative to
the frame boundary. The offset is in increments of
61 ns (1/16.384 MHz). Thus, 211 values corresponding
to the 11-bit start address allow programming offsets
from 0 ns to 125 µs. Notice that the resolution is less
than 1 bit. For example, if the frame group clock is programmed to 2.048 MHz, the resolution is 0.125 of a bit.
Preliminary Data Sheet
August 1998
At zero offset, the rising edge of the first frame group
output is coincident with the rising edge of the 8 MHz,
4 MHz, and 2 MHz of the L_SC[3:0] clocks that occur in
the center of the CT_FRAME. This defines the start of
the frame, and the start of the first bit of the first time
slot on both the CT bus and local input and local output
buses.
In addition to sequenced pulses, the frame groups can
be used as simple programmed output registers. When
group A is used as a programmed output, the bits are
sent from the FRLA [0x20] and FRHA [0x21] registers.
Bits [0:7] of the programmed output come from bits
[0:7] of FRLA [0x20]. Bits [8:10] of the programmed
output come from the high start (bits [0:2]) of FRHA
[0x21], and bit 11 of the programmed output comes
from the FAI bit (bit 3) of FRHA [0x21]. When group B is
used as a programmed output, bits 0:7 of the output
come from bits 0:7 of separate register FRPL [0x24],
and bits [8:11] of the output come from bits 0:3 of
another register FRPH [0x25]. The upper nibble of
FRPH [0x25] also has output routing functions associated with it. Register FRPH [0x25] is illustrated below;
see Figure 14 for a diagram of the selection options.
The frame boundary, shown in Figure 19 through Figure 21, is the point where /CT_FRAME is low and
CT_C8 is starting its low-to-high transition.
Table 47. FRPH: Frame Group B, Programmed Output, High, 0x25
REG
FRPH
Symbol
FAO
R/W
—
Bit
7—6
Bit 7
FAO = 00,
FAO = 01,
FAO = 10,
FAO = 11,
X
FBO
Hi Prog
48
Bit 6
FAO
Bit 5
X
Bit 4
FBO
Bit 3
Bit 2
Bit 1
Hi Prog
Bit 0
Name/Description
Frame group A bits [0:11] on output pins [0:11]
Programmed output A bits [0:11] on output pins [0:11]
Frame group A bits [0:5] on output pins [0:5], and frame group B bits [0:5] on
output pins [6:11]
Programmed output A bits [0:5] on output pins [0:5], and frame group B bits
[0:5] on output pins [6:11]
5
4
X (Reserved)
FBO = 0,
Frame group B routed to group B output pins
FBO = 1,
Programmed output B routed to group B output pins
3—0
High Prog = Upper 4 bits of programmed output B
Note: In the programmed output mode, the rate must not equal 00; otherwise, the outputs
corresponding to the group bits are 3-stated; the rate will have no effect other than
enabling the mode. Type bits have no effect in the programmed modes.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.5 Interface Section (continued)
2.5.3 Framing Groups (continued)
FRAME GROUP A, BITS [0:5]
T8100
INTERNAL
SIGNALS
T8100
OUTPUT
PINS
FGA[0:5]
PROGRAMMED OUTPUT A, BITS [0:5]
FAO
FRAME GROUP A, BITS [6:11]
PROGRAMMED OUTPUT A, BITS [6:11]
FRAME GROUP B, BITS [0:5]
FGA[6:11]
FBO
FRAME GROUP B, BITS [0:11]
FGB[0:11]
PROGRAMMED OUTPUT B, BITS [0:11]
5-6113F
Figure 14. Frame Group Output Options
Lucent Technologies Inc.
49
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.6 Error Registers
Four error registers are present in the T8100:
■
■
■
■
CLKERR1 [0x28]
CLKERR2 [0x29]
CKW [0x2B]
SYSERR [0x2A]
When programming the clock registers, writing to CKW
and CKS should be programmed last.
These are the clock error, watchdog enable, and system error registers. The CLKERR1 register is used to
indicate failing clocks, and the CLKERR2 indicates
whether the failure is permanent or transient in nature.
If the clocks fail, i.e., disappear or momentarily drop
out, then corresponding bits in both registers will be
set. If the clock is reestablished, i.e., a transient error,
then the T bit(s) will clear, but the E bit(s) will remain
set. All of the E bits are ORed together and drive the
CLKERR pin.
The clocks listed above are sampled by the
16.384 MHz internal clock. Effectively, each clock has a
watchdog. If the clock is switching, the watchdog
clears. If the clocks stop, then the watchdog sets the
appropriate E and T bits. If the clock is reestablished,
then the E bits remain stuck, but the T bits clear with
the watchdog. Since fallback is triggered on the E bits,
a transient clock can force a fallback.
Table 48. CLKERR1 and CLKERR2: Error Indicator
and Current Status, 0x28 and 0x29
Table 48 describes both CLKERR1 and CLKERR2:
Name
CAE
CAT
CBE
CBT
CFE
CFT
C16E
C16T
C42E
C42T
SCE
SCT
SC2E
SC2T
NRE
NRT
50
Bit
7 CA
3
Name/Description
=> Reports failures on CT_C8A
or /CT_FRAMEA
CB => Reports failures on CT_C8B
or /CT_FRAMEB
CF => Reports failures on
/FR_COMP
C16 => Reports failures on /C16+ or
/C16–
C42 => Reports failures on /C4 or C2
2
SC
1
SC2 => Reports failures on SCLKX2
0
NR
6
5
4
Preliminary Data Sheet
August 1998
The CKW register works in conjunction with the two
registers above and with the clock circuitry. It is used to
enable the watchdogs for the clock lines. CKW uses the
same mapping as CLKERR1 and CLKERR2, so, for
example, a high in bit 7 will enable the watchdogs for
CT_C8A and /CT_FRAMEA. CKW functions as a
masking register for CLKERR1 and CLKERR2. If the
appropriate bit is not set, then a failing clock will not be
reported.
The SYSERR register is shown below, the bits are
ORed together with the CLKERR1 bits which, in turn,
drives the SYSERR pin. The SYSERR bits are sticky
as are the CLKERR1 bits so they must be reset by
clearing the register by setting a bit in the MCR (Section 2.1 Register/Memory Maps).
Table 49. SYSERR: System Error Register, 0x2A
Table 49 describes SYSERR:
Name
CUE
Bit
7
CUO
6
CUL
5
COE
4
COO
3
COL
2
(RES)
FBE
1
0
Name/Description
CUE => Even CAM underflow, set by
an unmatched comparison
CUO => Odd CAM underflow, set by
an unmatched comparison
CUL => Local CAM underflow, set by
an unmatched comparison
COE => Even CAM overflow, set by a
write to a full CAM
COO => Odd CAM overflow, set by a
write to a full CAM
COL => Local CAM overflow, set by a
write to a full CAM
RES
Reserved bit position
FBE => Fallback enabled, status
which indicates that a clock
error has occurred and fallback operations are in
effect*.
* This error bit is selective. It will only flag an error if the clocks that
fail correspond to the selected clock mode. For example, if MVIP
mode is selected (in register CKM), the proper fallback mode has
been set (in register CKS), and the MVIP clocks are not masked
(register CKW, above), then FBE will go high when a failure is
detected on /FR_COMPn, C2, or /C4. Thus, unmasked, failing nonMVIP clocks will be flagged in the CLKERR1 and CLKERR2 registers but will not set the FBE flag in SYSERR.
=> Reports failures on SCLK
=> Reports failures on
CT_NETREF
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.7 The JTAG Test Access Port
2.7.1 Overview of the JTAG Architecture
Tap
A 5-pin test access port, consisting of input pins TCK, TMS, TDI, TDO,
and TRST, provides the standard interface to the test logic. TRST is an
active-low signal that resets the circuit.
TAP Controller
The TAP controller implements the finite state machine which controls the
operation of the test logic as defined by the standard. The TMS input
value sampled on the rising edge of TCK controls the state transitions.
The state diagram underlying the TAP controller is shown below.
Instruction Register (JIR)
A 3-bit scannable JTAG instruction register that communicates data or
commands between the TAP and the T8100 during test or HDS operations.
Boundary-Scan Register (JBSR)
A 211-bit JTAG boundary-scan register containing one scannable register
cell for every I/O pin and every 3-state enable signal of the device, as
defined by the standard. JBSR can capture from parallel inputs or update
into parallel outputs for every cell in the scan path. JBSR may be configured into three standard modes of operation (EXTEST, INTEST, and
SAMPLE) by scanning the proper instruction code into the instruction register (JIR). An in-depth treatment of the boundary-scan register, its physical structure, and its different cell types is given in Table 51.
Bypass Register (JBPR)
A 1-bit long JTAG bypass register to bypass the boundary-scan path of
nontargeted devices in board environments as defined by the standard.
2.7.2 Overview of the JTAG Instructions
The JTAG block supports the public instructions as shown in the table below.
Table 50. T8100 JTAG Instruction Set
Instruction
Mnemonics
Instruction
Codes
Public/Private
Mode
EXTEST
SAMPLE
Reserved
Reserved
Reserved
Reserved
Reserved
BYPASS
000
001
010
011
100
101
110
111
Public
Public
—
—
—
—
—
Public
—
—
—
—
—
—
—
—
Lucent Technologies Inc.
Description
Select B-S register in extest mode
Select B-S register in sample mode
—
—
—
—
—
Select BYPASS register
51
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
2 Architecture and Functional Description (continued)
2.7 The JTAG Test Access Port (continued)
2.7.3 Elements of JTAG Logic
Table 51. T8100 JTAG Scan Register
Cell
Type
Signal Name/Function
Cell
Type
Signal Name/Function
66
67
68
0
69—76
1
77
78
79
80
81
82
83
84
85—88
44
89—96
97
98
45
99
100
46
101
43
102
42
103—108
41
109—120
63
I
O
O
CC
Bdir
CC
I
O
I
I
I
I
I
I
O
CC
I
I
O
CC
O
O
CC
Bdir
CC
Bdir
CC
Bdir
CC
O
CC
CK_3MHZIN
SYSERR
CLKERR
Controls cells 67:68
D[0:7]
Controls cells 69:76
RESTN
RDY
WRN
RDN
CSN
ALE
A0
A1
L_SC[0:3]
Controls cells 85:88
L_REF[0:7]
CK_4MHZIN
PRIREFOUT
Controls cell 98
TESTOUT1
REFCLK1O
Controls cells 99, 100
FROMDJAT
Controls cell 101
TODJAT
Controls cell 102
GP[5:0]
Controls cells 103—108
FGB[11:0]
Controls cells 109—120
121—132
64
133
134
135
136
5
137
7
138
6
139
140
3
141
4
142
8
143
144
2
145—176
9—40
177—192
47—62
193
0
194—209
210
65
O
CC
Bdir
Bdir
Bdir
Bdir
CC
Bdir
CC
Bdir
CC
Bdir
Bdir
CC
Bdir
CC
Bdir
CC
Bdir
Bdir
CC
Bdir
CC
O
CC
O
CC
I
O
CC
FGA[11:0]
Controls cells 121—132
C16N_MINUSA
C16N_PLUSA
C4N
C2
Controls cells 133—136
SCLKX2NA
Controls cell 137
SCLKA
Controls cell 138
CT_C8_BA
CT_FRAME_BNA
Controls cells 139—140
FRN_COMPA
Controls cell 141
CT_NETREF
Controls cell 142
CT_C8_AA
CT_FRAME_ANA
Controls cells 143—144
CT_D[0:31]
Controls cells 145—176
LDO[0:15]
Controls cells 177—192
XCS
Controls cell 193
LDI[0:15]
PMCTCLKO
Controls cell 65
52
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.8 Testing and Diagnostics
There are several testing operations available for the
T8100:
■
JTAG
■
Forced output testing
■
Onboard diagnostics
During manufacturing, the T8100 is run through standard functional and electrical testing.
2.8.1 Testing Operations
JTAG is used primarily to test the array portion of the
T8100. It will not provide coverage for the CAMs, register files, SRAMs, or PLLs. In JTAG, the manufacturer
provides a drop-in control block and scan-chain which
ties internal points to registers on the periphery of the
T8100, which are, in turn, tied to the I/O pins. Serial bit
patterns are shifted into the T8100 through the TDI pin,
and the results can be observed at the I/O and at a corresponding JTAG serial output, TDO. Since this JTAG
conforms to the JTAG standard, the TDI and TDO can
be linked to the JTAGs of other devices for systemic
testing. The TTS pin must be low for JTAG operations
to work. The TTS pin has an internal pull-down resistor
that defaults the T8100 to JTAG operations.
2.8.2 Diagnostics
The T8100 has onboard diagnostic modes for testing
the frame groups, SRAMs and CAMs, and some internal structures. These are intended for testing some of
the T8100 resources while it is in an application environment (rather than a manufacturing test environment).
The diagnostics allow critical internal nodes to be output through the frame groups, or to have the frame
groups operated in special cyclical manner, or to provide automatic filling of all memories (including CAMs)
with one of four selected patterns. The diagnostics are
activated and selected using three registers: DIAG1
[0x30], DIAG2 [0x31], or DIAG3 [0x32].
DIAG1 is used to select the frame group pins as either
monitors for internal nodes or normal operation (i.e., as
frame groups or programmed outputs). DIAG1 is also
used to control the memory fill diagnostic.
DIAG2 and DIAG3 modify the normal operation of the
frame groups and the main state counter. Normally, the
frame groups begin their cascade sequence when the
state counter (i.e., the frame-synchronized master
counter of the T8100) reaches a value equal to the
frame group’s starting address. DIAG2 and DIAG3
allow the state counter to be modified for one of two different tests.
In forced output testing, the outputs are set to a particular state to measure their dc parameters. This can also
be used in applications for board-level diagnostics.
Forced output testing is selected by setting the TTS
(test type select) pin high. In this mode, the JTAG clock
pin, TCK, will act as an input pin. All outputs will be
enabled, and each output provides either an inverting
or normal response to the input pin. Adjacent pins
alternate inverting and normal function (i.e., a checkerboard pattern).
Lucent Technologies Inc.
53
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
2 Architecture and Functional Description (continued)
2.8 Testing and Diagnostics (continued)
2.8.2 Diagnostics (continued)
The three registers are presented in order below:
DFA
DFC
DSB
DFB
DXF
DMF
(Res.)
DMP
DSE
DMD
DSH
DSL
The register fields are interpreted as follows:
DFA—Diagnostics, Frame Pin Selects, Group A:
DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame
group pins [10:0], pin 11 = L
DFn = 10, Even CAM hit routed to pin 11, pin 10 has
odd CAM hit, pins [9:0] have local data
memory address
DFn = 11, Pin 11 gets CUE error bit, pin 10 gets CUO
error bit, pin 9 gets CUL error bit, pin 8 gets
COE error bit, pins [5:0] get page pointers—
8 MHz read, 8 MHz write, 4 MHz read,
4 MHz write, 2 MHz read, and 2 MHz write
DFB—Diagnostics, Frame Pin Selects, Group B:
DFn = 00, Normal operation
DFn = 01, State counter bits [10:0] routed to frame
group pins [10:0], pin 11 = L
DFn = 10, CAM state register [1:0] indicating four substates, routed to pins [11:10], and local connection memory address routed to pins [9:0]
DFn = 11, Pin 11 gets local CAM hit flag, and pins
[10:0] get CAM state counter
DMF—Diagnostics, Memory, Fill Test Enable:
DMF = 0, Normal operation
DMF = 1, Fill all memories with the pattern selected
by DMP
DMP—Diagnostics, Memory, Fill Test Pattern
Select:
DMP = 00, Checkerboard 0—even locations get 0x55,
odd locations get 0xAA
DMP = 01, Checkerboard 1—even locations get 0xAA,
odd locations get 0x55
DMP = 10, Data locations equal address bits [7:0]
(CAMs are filled with their physical address)
DMP = 11, Data locations equal inverted address bits
[7:0]
54
Preliminary Data Sheet
August 1998
DMD—Diagnostics, Memory, Done Indicator:
This is a status bit which indicates that the chosen
memory pattern has been written to all locations. Additional writes to the memory are disabled and reads are
enabled. This condition remains until the user clears
this bit.
DFC—Diagnostics, Frame Groups Cycle Test
Mode:
DFC = 0, Normal operation
DFC = 1, Cycle test mode enabled; forces the frame
groups to constantly cycle without waiting for
a frame signal to synchronize the start.
DSB—Diagnostics, State Counter, Break Carry
Bits:
DSB = 0, Normal operation
DSB = 1, Breaks the carry bits between the subsections of the state counter so that the state
counter is operating as three counters running in parallel. (This can be viewed on the
frame pins using the DFn = 01 selection
described above.) Status counter bits [0:3]
and [4:7] run as modulo-16 counters, and bits
[8:10] run as a modulo-8 counter.
DXF—Diagnostics, External Frame Input:
DXF = 0, Normal operation
DXF = 1, Forces /FR_COMP to act as a direct input
signal for T8100 framing. This effectively
bypasses the internally generated frame signal. The user is again cautioned since the
external frame can operate asynchronously
to the generated clocks if care is not taken.
DSE—Diagnostics, State Counter, Enable Parallel
Load:
DSE = 0, Normal operation
DSE = 1, Forces the state counter to load the value
held in DSH and DSL and continuously cycle
as a modulo-n counter where the n value is
determined by (DSH and DSL). With the DSE
pin high, the state counter is no longer synchronized to the frame signal.
DSH—Diagnostics, State Counter, High Bits of Parallel Load:
DSH = State counter bits [10:8]
DSL—Diagnostics, State Counter, Low Bits of Parallel Load:
DSL = State counter bits [7:0]
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
3 Using the T8100
3.2 Basic Connections
3.1 Resets
At a minimum, the T8100 requires power, ground, and
a 16.384 MHz crystal (or 16.384 MHz crystal oscillator). It is also recommended that the internal PLLs be
treated as other analog circuits are, so the user should
provide the appropriate filtering between the PLL1VDD
and VDD pins (as well as PLL2VDD and VDD pins). The
RDY pin is operated as an open collector output. It is
actively driven low or into 3-state. The user should
apply a pull-up (e.g., 10 kΩ) to maintain standard
microprocessor interfacing. It is recommended that the
10 kΩ be tied to 3.3 V (since the T8100’s nominal
VOH is 3.3 V), but the resistor may also be tied up
to 5 V without damaging the device. PLL connections
are shown in Figure 15. The H.100/H.110 clock
signals, CT_C8_A, CT_C8_B, /CT_FRAME_A,
/CT_FRAME_B, and CT_NETREF each require an
individual external pull-up of 100 kΩ to 5 V or 50 kΩ to
3.3 V.
3.1.1 Hardware Reset
A hardware reset utilizes the (active-low) RESET pin.
On activation, it immediately places all outputs into
3-state. Individual output sections must be reenabled
by setting the appropriate bits high in the MCR register.
Internally, the local memory is in an undefined state, all
CAM empty bits are set, all state machines are reset,
and all registers are cleared to zero.
3.1.2 Software Reset
This is accomplished by setting the MSB of the master
control and status register (see Section 2.1.2 Master
Control and Status Register). The local and H-Bus connections are rendered invalid, all registers are cleared
except MCR, CLKERR1, CLKERR2, and SYSERR
(these registers are cleared with separate MCR control
bits); the state machines are also reset. Applying the
value 0xE0 to the MCR is a full software reset. Applying
0x0E enables all pin groups (though individual pins still
require setup). This soft reset is clocked by the crystal
oscillator.
VDD = 3.3 V
25 Ω
10 kΩ
50 kΩ
NETREF,
C8s, AND
FRAMES
3.1.3 Power-On Reset
No power-on reset is available. It is expected that the
host microprocessor or applications board will provide
an external control to the RESET pin for performing a
hardware reset. The PLLs must not be enabled prior to
establishing a stable supply voltage. There are two
methods to accomplish this:
■
Tie the En1 and En2 pins to the same line that drives
the RESET which forces the PLLs into an off condition while the T8100 resets asynchronously.
■
Add external capacitors from En1 to ground and from
En2 to ground. (The values of the capacitors should
be 1 µF or greater.) The capacitors will form RC circuits with the En1 and En2 internal pull-ups and will
charge up to enable the PLLs after several milliseconds. The RC circuit affects the power-on reset for
the PLLs. The long rise time provides some delay.
RDY
T8100
PLLVDDS
TANTALUM
33 µF
PLLGNDS
5-6114.aF
Lucent Technologies Inc.
Figure 15. External Connection to PLLs
55
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.2 Basic Connections (continued)
CT_FRAMEA
CT_FRAMEA
33 Ω
10 kΩ
LUCENT T8100
3.2.1 Physical Connections for H.110
Figure 16 shows the T8100 physical connections
required for use in an H.110 environment. There are
electrical differences between H.100 and H.110. For
H.110, external components are required to meet specifications. Figure 16 shows the T8100 NETREF terminations and the required terminations for CT_C8A,
CT_FRAMEA, CT_C8B, and CT_FRAMEB. Each signal has a mechanism to short the 33 Ω series resistor
and, in addition, a 10 kΩ pulldown resistor. The 50 kΩ
internal pull-ups on the CT data bus are used for
H.100. For H.110, the DPUE pin should be tied low,
disabling these internal pull-ups. H.110 requires the CT
data bus to have pull-ups of 18 kΩ to 0.7 V. The control
leads of the FET switches would typically go to the
microprocessor.
CTC8A_SRC
CT_C8A
CTC8A_SRC
CT_FRAMEB
CTC8B_SRC
CT_C8B
CT_C8B
33 Ω
10 kΩ
VPULL-UP =
0.7 V
CTC8B_SRC
18 kΩ
CT_NETREFB
3.2.3 PC Board Considerations
There are no special requirements for the thermal balls
on the BGA package when designing a printed-circuit
board.
CT_FRAMEB
33 Ω
10 kΩ
3.2.2 H.100 Data Pin Series Termination
All data bus lines must have a 24 Ω series
resistor, even if only data lines 16—31 are used
at 8.192 Mbits/s.
CT_C8A
33 Ω
10 kΩ
CT_NETREF
24 Ω
VPULL-UP =
0.7 V
CTR_NETB
18 kΩ
RDY AND PLL
CONNECTIONS
ARE THE SAME
AS IN H.100
CT_NETREFA
24 Ω
CTR_NETA
0 Ω DEPOPULATE
SCLK
SCLK
0 Ω DEPOPULATE
SCLKX2
SCLKX2
24 Ω
32
CTD[0:31]
CTD[0:31]
18 kΩ
DPUE
0.7 V
5-7142F
Figure 16. Physical Connections for H.110
56
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections
3.3.1 Setting Up Local Connections
Local connections require a physical location in the
local connection memory corresponding to the output
stream and time slot. The location contains a pointer to
a local data memory location which holds the actual
data that has come in or will be sent out. The local
memories are based on 1024 locations, so 10 bits are
required to specify the physical memory location where
a connection is placed or where data is stored. To simplify the programming, the user supplies 11 bits in a
stream and time-slot format, which is converted by the
T8100 to the appropriate physical location. Relative to
describing a connection, a data memory location corresponds with the FROM stream and time slot, and a
connection memory location corresponds with the TO
stream and time slot. To program a connection, the
user loads the data memory location into the connection memory location, effectively identifying where the
data resides.
The user programs 7 bits of the LAR for the time-slot
value (or 8 bits for pattern mode) and the lowest 4 bits
of the AMR for the stream value; these will then be converted to the physical memory address. The upper bits
of the AMR select which field in the connection memory is being written into. Since the connection information itself is 15 bits, two transfers (i.e., two fields) must
be made to the address in the connection memory.
In each case, the transfer is an indirect write of data to
the indirect data register, the IDR: The first transfer is
the lowest 7 bits (time-slot address) of the desired data
memory location. It is placed in the IDR after the LAR
and AMR have been set up with the appropriate connection address.
Table 52. Time-Slot Bit Decoding
Address
Value
2 Mbits/s
Time Slot
4 Mbits/s
Time Slot
8 Mbits/s
Time Slot
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
:
0x1E
0x1F
0x20
:
0x3E
0x3F
0x40
:
0x7E
0x7F
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
NA
:
NA
NA
NA
:
NA
NA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
32
:
62
63
NA
:
NA
NA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
:
30
31
32
:
62
63
64
:
126
127
Table 52 illustrates the decoding of the time-slot bits
(address value in the table refers to the hex value of the
7 bits comprising time slot).
When programming the registers for fallback, the CKS
and CKW registers should be programmed last.
Lucent Technologies Inc.
57
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.1 Setting Up Local Connections (continued)
Table 53. IDR: Indirect Data Register, Local Connections Only
The second transfer requires that data in the IDR be defined as follows:
REG
IDR
R/W
—
Bit 7
Bit 6
Bit 5
Control
PME
FME
XCS
Symbol
XCS
Bit
7
PME
6
FME
5
CHE
Address
4
3—0
Bit 4
Bit 3
CHE
—
Bit 2
Bit 1
Address
—
—
Bit 0
—
Name/Description
A programmable bit which is routed to the XCS pin one time slot prior to the data to
which it relates.
A high enables the pattern mode; the lower 8 bits of the connection address (time slot
and stream LSB) is routed to the time slot instead of data.
A high enables the use of the alternate data buffer; refer to Appendix B for minimum
and constant delay settings.
Enables the time-slot connection; a low in this bit forces 3-state during the time slot.
All 4 bits are used for the stream address of the desired data memory location.
After the second transfer is made, the entire 15 bits will be loaded into the connection memory; i.e., the second
transfer triggers the actual memory access. Figure 17 shows how the connections are made from the perspective
of the registers and memory contents.
If the user wishes to set up a pattern mode connection, then the first transfer is a full 8 bits (i.e., the pattern), rather
than the 7-bit time-slot value. This pattern byte will be stored in the lowest 8 bits of the selected connection memory
location. The pattern byte will be sent instead of a byte from local data memory during the output stream and time
slot which corresponds to the connection memory location.
LOCAL MEMORY PROGRAMMING EXAMPLE: CONNECT FROM 14, 7 TO 3, 29 (STREAM, TIME SLOT)
FIRST TRANSFER:
WRITE TO
TIME-SLOT
FIELD IN
CONNECTION
MEMORY
AMR
LAR
0100 0011
0001 1101
SECOND TRANSFER:
WRITE TO
CONTROL/STREAM
FIELD IN
IDR
CONNECTION
0000 0111
MEMORY
3, 27
3, 27
3, 28
3, 28
3, 29
3, 30
3, 31
0000 0111
3, 29
CONNECTION 3, 30
MEMORY
3, 31
AMR
LAR
IDR
0101 0011
0001 1101
0001 1110
0001
1110
0000 0111
CONNECTION
MEMORY
5-6115aF
Figure 17. Local-to-Local Connection Programming
58
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.2 Setting Up H-Bus Connections
Table 54. IDR: Indirect Data Register, H-Bus Connections Only
REG
IDR
R/W
—
Bit 7
R/W
Symbol
R/W
PME
FME
Address
Bit 6
Control
PME
Bit 5
Bit 4
Bit 3
FME
—
—
Bit 2
Address
—
Bit 1
Bit 0
—
—
Bit
7
Name/Description
Refers to the direction in the CAM data memory. A read sends data to the bus; a write loads
data from the bus.
6
Pattern mode enable, similar to above, except the tag byte is output instead of the lower
address bits.
5
Data buffer selection for setting delay type. (Refer to Appendix B for minimum and constant
delay setting.)
4—0 All 5 bits are used for the stream address of the desired data memory location.
The CAM blocks are 256 locations each and the operations for the CAM blocks are selected by AMR (see
Section 2.1.3 Address Mode Register and Section
2.3.2 CAM Operation and Commands). Since the block
address is carried in the AMR, this reduces the number
of bits which are necessary to establish a connection.
Eleven (11) address bits, i.e., bits for stream and timeslot identification, the 8-bit tag (pointer to the H-Bus
data memory), and 3 control bits all need to be written
into the selected CAM block for setting up a connection. (The empty bit is a status bit that is changed internally as a result of operations on the CAM.) Three
transfers, indirect writes through the IDR, are required
to set up a connection in the CAM, though the method
of transfer is different than with the local memory. Since
a specific physical address is not always necessary, the
CAM will automatically fill the first available slot. Thus,
the LAR is not required for setting up the connection.
(See the notes below.) The first transfer after programming the AMR requires that the 7 bits which identify the
time-slot number (refer to Section 2.3.5 H-Bus Rate
Selection and Connection Address Format for the
proper format) be loaded into the IDR. The second
transfer uses a similar field description for the IDR as
presented for local connections (Section 3.3.1 Setting
Up Local Connections above). The address field contains the stream number (5 bits), and the control field
contains only three control bits.
The third (and final) transfer for CAM connection setup
is the transfer of the 8-bit tag field. The tag is loaded
into the IDR. The connection for the CAM is actually set
up, i.e., the memory access takes place, using a fourth
write. It is an indirect write to the AMR (again through
the IDR) which corresponds with the specific command
and blocks the user requests. All CAM commands
Lucent Technologies Inc.
require that the IDR be loaded with the same command
value as the AMR rather than a don’t care or dummy
value.
Notes: If an address is to be matched, such as the
break connection command, then only the first
two transfers are required. The tag is unnecessary for identifying a connection.
The LAR is only used to read or query a specific location (i.e., 0—255) in a particular CAM
block. Refer to Section 2.1.3 Address Mode
Register and Section 2.3.2 CAM Operation
and Commands for details on these commands.
For the CAMs, pattern mode is a 1/2 connection. Only
the intended output to the H-Bus (or to the local pins)
needs to be specified. The setup is the same as
described above, three transfers to the holding registers followed by the make connection command to the
appropriate CAM block. When the address is matched,
the tag value (from the pipeline SRAM) will be sent as
output to the bus.
Figure 18 illustrates how a CAM connection is made
from the perspective of registers and the memory locations. Note that each half of the connection, that is the
FROM and the TO, requires a separate setup, though
each half will point to the same location in the H-Bus
data memory.
Following Figure 18, some simple programming examples are shown using pseudoassembler code. The
local-to-local and H-Bus-to-local switching examples
from Figure 17 and Figure 18 are reused in code examples #2 and #3. The connections are referred to in
stream, time-slot format.
59
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.2 Setting Up H-Bus Connections (continued)
CAM PROGRAMMING EXAMPLE:
CONNECT FROM H-BUS 14, 7 TO LOCAL 3, 29,
KEEP DATA IN LOCATION 49
:
FIRST TRANSFER:
WRITE TO TIME-SLOT
HOLDING REGISTER
AMR
LAR (UNUSED)
IDR
1011 0000
XXXX XXXX
0000 0111
HOLDING REGISTERS
0000 0111
CTLS/STREAM
TIME SLOT
TAG
SECOND TRANSFER:
WRITE TO CONTROLS/STREAM
HOLDING REGISTER
DIRECTION BIT: FROM
BUS TO DATA MEMORY
AMR
LAR (UNUSED)
IDR
1011 0001
XXXX XXXX
000 01110
000 01110
0000 0111
CTLS/STREAM
TIME SLOT
HOLDING REGISTERS
TAG
THIRD TRANSFER:
WRITE TO TAG
HOLDING REGISTER
AMR
LAR (UNUSED)
IDR
1011 0010
XXXX XXXX
0011 0001
DATA LOCATION 49
000 01110
0000 0111
0011 0001
CTLS/STREAM
TIME SLOT
TAG
HOLDING REGISTERS
LOAD CAM:
TRANSFER HOLDING
REGISTERS TO NEXT FREE
LOCATION IN EVEN CAM
AMR
LAR (UNUSED)
IDR (MUST = AMR)
1110 0000
XXXX XXXX
1110 0000
CTLS/STREAM
TIME SLOT
TAG
000 01110
0000 0111
0011 0001
HOLDING REGISTERS
LOCATION USED—NOT EMPTY
(LOCATION USED—NOT EMPTY)
000 01110
0000 0111
(NOT EMPTY)
0000 0111
(LOCATION NOT USED—EMPTY)
(EMPTY)
EVEN CAM
PIPELINE SRAM
5-6116F
A. First Half of Connection, H-Bus Side
Figure 18. CAM Programming, H-Bus-to-Local Connection
60
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.2 Setting Up H-Bus Connections (continued)
CAM PROGRAMMING EXAMPLE (CONTINUED):
CONNECT FROM H-BUS 14, 7 TO LOCAL 3, 29,
KEEP DATA IN LOCATION 49
FIRST TRANSFER:
WRITE TO TIME-SLOT
HOLDING REGISTER
AMR
LAR (UNUSED)
IDR
1011 0000
XXXX XXXX
0001 1101
0001 1101
CTLS/STREAM
TIME SLOT
HOLDING REGISTERS
TAG
SECOND TRANSFER:
WRITE TO CONTROLS/STREAM
HOLDING REGISTER
DIRECTION BIT: TO BUS
FROM DATA MEMORY
AMR
LAR (UNUSED)
IDR
1011 0001
XXXX XXXX
100 00011
100 00011
0001 1101
CTLS/STREAM
TIME SLOT
HOLDING REGISTERS
TAG
THIRD TRANSFER:
WRITE TO TAG
HOLDING REGISTER
AMR
LAR (UNUSED)
IDR
1011 0010
XXXX XXXX
0011 0001
DATA LOCATION 49
100 00011
0001 1101
0011 0001
CTLS/STREAM
TIME SLOT
TAG
HOLDING REGISTERS
LOAD CAM:
TRANSFER HOLDING
REGISTERS TO NEXT FREE
LOCATION IN LOCAL CAM
AMR
LAR (UNUSED)
IDR (MUST = AMR)
1110 0011
XXXX XXXX
1110 0011
CTLS/STREAM
TIME SLOT
TAG
100 00011
0001 1101
0011 0001
HOLDING REGISTERS
LOCATION USED—NOT EMPTY
(LOCATION USED—NOT EMPTY)
NEXT FREE LOCATION
100 00011
0001 1101
(NOT EMPTY)
0011 0001
(LOCATION NOT USED—EMPTY)
(EMPTY)
LOCAL CAM
PIPELINE SRAM
5-6117F
B. Second Half of Connection, Local Side
Figure 18. CAM Programming, H-Bus-to-Local Connection (continued)
Lucent Technologies Inc.
61
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.3 Programming Examples
;All programming examples included are in a pseudoassembler format.
;The basic commands used are the “move direct” and “move indirect.”
;A move direct command is indicated by the letters “MD” followed by
;the register name, then the data. Similarly, a move indirect command
;is indicated by the letters “MI” followed by the register name, then by
;data or another register reference (the register may not be indirect).
;The semicolon delineates comments. Direct data is followed by the
;letter “h” for Hex and “b” for binary.
;*******EXAMPLE #1 - Set Up Clocks, Local Bus, H-Bus, and Framers
;
;*******Misc. Stuff
;
MD,AMR,00h
;Define control space
;all specific register names are equivalent
;to the LAR addresses (from Table 11)
;
;
;*******Set up Clocks
;**Main Clock Register
MD,IDR,0C2h
;Load IDR with values for bit slider on, slave mode,
;and synced to ECTF Bus A Clocks
MI,CKM,IDR
;The data in IDR is moved into CKM via the LAR register.
;
;**NETREF Registers
MD,IDR,88h
;Set up NETREF from Local Reference 0, 2.048 MHz bit clock
in, divided value
;value out (i.e., 8 kHz), enable the DJAT connections
MI,CKN,IDR
;Move the data to CKN
MD,IDR,0FFh
;Set up NETREF divider with divide-by-256
MI,CKND,IDR
;Move the data to CKND
;
;**Programmable Clocks
MD,IDR,26h
;This selects the oscillator for the TCLKO, A Clock
outputs off, and
;driving ECTF B Clocks
MI,CKP,IDR
;Move the data
;
;**Clock Resources
MD,IDR,40h
;Synced to bus so select Resource divider, x16 on PLL #1 &
x8 PLL #2, SC Clocks off
MI,CKR,IDR
;Make it so
MD,IDR,01h
;Set up Resource divider with divide-by-2 for 4 MHz signal
into PLL #1
MI,CKRD,IDR
;Move the data to divider
;
62
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.3 Programming Examples (continued)
;**Secondary Controls (Fallback)
MD,IDR,35h
;Enable ECTF Fallback: Become the new A Clock master on A
Clock failure,
;synchronizes to a bit clock on local reference 1, but
requires the main divider
;with external input (assumes a CLAD is between the
divider and 4MHzIn).
MI,CKS,IDR
;Move the data to CKS
MD,IDR,0FFh
;Set up Main divider with divide-by-256
MI,CKMD,IDR
;Move the data to divider
;
;**Local Clocks
MD,IDR,0E4h
;Local Selected Clock 3 gets inverted 8.192 MHz, LSC2 gets
2.048 MHz
MI,CK32,IDR
;Move it to CK32
MD,IDR,80h
;LSC1 is high & LSC0 is low
MI,CK10,IDR
;Move it to CK10
;
;*******Set up Local Streams
;
MD,IDR,30h
;8 Streams at 8 Mbits/s
MI,LBS,IDR
;Define input streams per IDR
;
;*******Set up H Bus Streams
;
MD,IDR,0AAh
;Define H-Bus Streams 0 - 15 for 4 Mbits/s
MI,HSL,IDR
;Do it
;
MD,IDR,0FFh
;Define H-Bus Streams 16-31 for 8 Mbits/s
MI,HSH,IDR
;Engage
;*******Set up Framers
;
MD,IDR,00h
MI,FRLA,IDR
MI,FRLB,IDR
MI,FRPH,IDR
MD,IDR,0F0h
MI,FRHA,IDR
MD,IDR,0F4h
MI,FRHB,IDR
;This sequence sets up Group A
;
to start coincident
;
with the Frame
;
boundary and Group B
;
to start halfway through
;
the Frame. The Groups
;
operate in normal framing mode
;
at 8 Mbits/s and are Double Byte wide.
;Note: FRPH sets up the correct routing.
;
;*******Connect the T8100 to the outside world
;
MD,MCR,0Eh
;
Enable H-Bus Streams & Clock, Local Streams,
local
;
Clocks including Framers
;
;*******END OF EXAMPLE #1
Lucent Technologies Inc.
63
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.3 Programming Examples (continued)
;*******EXAMPLE #2 - Setting up Local Connections
;
;
Use 8 Mbits/s rate set up from Example #1...
;
Send data from Stream 7/Time Slot 60 to Stream 0/Time Slot 2
;
The data is coming from Data Location Stream 07h, Time Slot 3Ch, and is
;
being accessed by Connection Memory Location Stream 00h, Time Slot 02h
;
in the next frame (unframed operation).
;
MD,LAR,1Dh
;Set up lower address, i.e., Time Slot 29
MD,AMR,43h
;
Set up upper address bits (Stream 3), and
point to the
;
the Time Slot field of the connection memory
MI,IDR,07h
;Put a “7” in the Time Slot field of connection location
3,29
;
;Syntactically, “MI,IDR,data” is a special case since IDR is not the final recipient
of the data
;
MD,AMR,53h
;Maintain the same upper address, but get ready to load the
;
remaining connection info (upper bits +
control)
MI,IDR,0001_1110b
;This decodes as follows: XCS bit low, pattern mode off
;
(not set), frame bit low, time slot enabled,
and stream = 1110b (14)
;
;*******END OF EXAMPLE #2
;*******EXAMPLE #3 - Setting up H-Bus Connections
;
; Use rate set up from Example #1...
; Send data from Stream 14/Time Slot 7 of the H.100 bus to Stream 3/Time Slot 29
; on the Local side. The data is coming in at 4 Mbits/s from E-CAM, and is sent
; out at 8 Mbits/s to through L-CAM. We’re using Data Memory location 49 to hold
; the actual data. LAR is not used for the CAM connection setups; it is used for
; reading specific CAM locations or writing and reading the associated Data
; Memory Locations.
;
;******Set up the “from” connection
;
MD,AMR,0B0h
;Point to the Time-Slot holding register
MI,IDR,07h
;This is the Time-Slot value (7) for the H-Bus address
MD,AMR,0B1h
;Point to the upper bits of the connection
MI,IDR,000_01110b
:Set up a write into data memory from ECTF bus,
;
disable pattern mode, minimum delay,
;
and set stream number equal to 01110b (14).
MD,AMR,0B2h
;Point to tag field
MI,IDR,31h
;Use location 49 of the associated Data RAM to store the data
;
MD,AMR,0E0h
;Write to next free location in the Even CAM
MI,IDR,0E0h
;The command is executed with the indirect to IDR which
;uses the same command value as in the AMR.
64
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
3 Using the T8100 (continued)
3.3 Using the LAR, AMR, and IDR for Connections (continued)
3.3.3 Programming Examples (continued)
;
;**Optional: Test CAM Busy bit**
TEST:
MD,ACC,MCR
;Move MCR contents into (host’s) accumulator (for example)
AND,01h
;Logical AND, i.e., mask off all but LSB of the MCR register
JNZ TEST
;If the LSB is zero (not busy), continue, else jump back and
;retest
;
CONTINUE:
;
;******Set up the “to” connection
;
MD,AMR,0B0h
;Point to the Time-Slot holding register
MI,IDR,1Dh
;This is the Time-Slot value (29) for the Local address
MD,AMR,0B1h
;Point to the upper bits of the connection
MI,IDR,100_00011b
:Set up a read from data memory to Local pins,
;
disable pattern mode, minimum delay, and set
;
stream number equal to 00011b (3).
MD,AMR,0C2h
;Point to tag field
MI,IDR,31h
;Use location 49 of the associated Data RAM to store the data
;
MD,AMR,0E3h
;Write to next free location in the Local CAM
MI,IDR,0E3h
;The command is executed with the indirect to IDR
;
;
;
;**CAM Busy bit can be tested here**
;
;
;*******END OF EXAMPLE #3
3.2.4 Miscellaneous Commands
These commands (i.e., 0x70, 0xF8, all reset commands in the AMR register) require two writes: first the value is
written to the AMR register; then the same value is written to the IDR register. After writing to the IDR register, the
command will be executed.
Lucent Technologies Inc.
65
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics
4.1 Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Description
Supply Voltage
XTALIN and XTALOUT Pins
Voltage Applied to I/O Pins
Operating Temperature:
208-pin SQFP
217-pin BGA
Storage Temperature
Symbol
Min
Max
Unit
VDD
—
—
—
VSS
VSS – 0.5
3.6
VDD
VDD + 3.4
V
V
V
—
—
Tstg
0
−40
–55
70
85
125
°C
°C
°C
4.2 Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Lucent employs a human-body model (HBM)
and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation. ESD voltage
thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been
adopted for CDM. However, a standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely used and
therefore can be used for comparison purposes. The HBM ESD threshold presented here was obtained by using
these circuit parameters:
HBM ESD Threshold Voltage
Device
Rating
T8100
2500 V
66
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.3 Crystal Oscillator
Table 55. Crystal Oscillator
The T8100 requires a 16.384 MHz clock source. To supply this, a 16.384 MHz crystal can be connected between
the RCLK and XTALOUT pins. External 18 pF, 5% capacitors must be connected from XTALIN and XTALOUT to
VSS. Crystal specifications are shown below. The ±32 ppm tolerance is the suggested value if either the DPLL is
used or fallback to the oscillator is enabled while mastering the bus. Otherwise, a crystal with a lesser tolerance
can be used.
Parameter
Frequency
Oscillation Mode
Effective Series Resistance
Load Capacitance
Shunt Capacitance
Frequency Tolerance and Stability
Value
16.384 MHz
Fundamental, Parallel Resonant
40 Ω maximum
14 pF
7 pF maximum
32 ppm
XTALOUT
18 pF
T8100
1 MΩ
18 pF
XTALIN
16.384 MHZ
VSS
5-6390(F)
Table 56. Alternative to Crystal Oscillator
When XTALIN is driven by a CMOS signal instead of an oscillator, it must meet the requirements shown below:
Parameter
Value
16.384 MHz
5 ns
Frequency
Maximum Rise or Fall Time
Minimum Pulse Width
Low
20 ns
High
20 ns
4.4 dc Electrical Characteristics, H-Bus (ECTF H.100 Spec., Rev. 1.0)
4.4.1 Electrical Drive Specifications—CT_C8 and /CT_FRAME
Table 57. Electrical Drive Specifications—CT_C8 and /CT_FRAME
VDD = 3.3 and VSS = 0.0 unless otherwise specified.
Parameter
Output High Voltage
Output Low Voltage
Positive-going Threshold
Negative-going Threshold
Hysteresis (Vt+ – Vt–)
Input Pin Capacitance
Symbol
Condition
Min
Max
Unit
VOH
VOL
Vt+
Vt–
VHYS
CIN
IOUT = –24 mA
IOUT = 24 mA
—
—
—
—
2.4
–0.25
1.2
0.6
0.4
—
3.3
0.4
2.0
1.6
—
10
V
V
V
V
V
pF
PCI-compliant data line I/O cells are used for the CT bus data lines. (See PCI Specification, Rev. 2.1, Chapter 4.)
/C16, /C4, C2, SCLK, SCLKX2, and /FR_COMP all use the same driver/receiver pairs as those specified for the
CT_C8 and /CT_FRAME signals, though this is not explicitly stated as a part of the H.100 Specification.
Lucent Technologies Inc.
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Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
4 Electrical Characteristics
Preliminary Data Sheet
August 1998
(continued)
4.5 dc Electrical Characteristics, All Other Pins
Table 58. dc Electrical Characteristics, All Other Pins
VDD = 3.3 and VSS = 0.0 unless otherwise specified.
Description
Supply Current
Supply Voltage
Input High Voltage
Input Low Voltage
Input Current
Input Capacitance (input only)
Input Capacitance (I/O pins)
Input Clamp Voltage
Output High Voltage
Output Low Voltage
Output Short-circuit Current
Symbol
Min
Typ
Max
Condition
Unit
IDD
VDD
VIL
VIH
II
CI
CIO
VC
VOH
VOL
IOS
—
3.0
—
2.0
—
—
—
—
2.4
—
—
270
—
—
—
—
—
—
—
—
—
—
450*
3.6
0.8
—
1
5
10
–1.0
—
0.4
100
—
—
—
—
—
—
—
—
—
—
VOH tied to GND
mA
V
V
V
µA
pF
pF
V
V
V
mA
* Circuit simulation indicates a worst-case current of 450 mA. This parameter is not tested in production.
68
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0)
4.6.1 Clock Alignment
FRAME BOUNDARY
/CT_FRAME (A/B)
CT_C8 (A/B)
/FR_COMP
/C16
C2
/C4
SCLK
(2.048 MHz)
SCLKx2
(2.048 MHz MODE)
SCLK
(4.096 MHz MODE)
SCLKx2
(4.096 MHz MODE)
SCLK
(8.192 MHz MODE)
SCLKx2
(8.192 MHz MODE)
5-6119F
Figure 19. Clock Alignment
Lucent Technologies Inc.
69
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
4 Electrical Characteristics
Preliminary Data Sheet
August 1998
(continued)
4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0) (continued)
4.6.2 Frame Diagram
FRAME BOUNDARY
125 µs
/CT_FRAME
CT_C8
CT_DX
TIME
SLOT
8
1
2
3
4
5
6
7
8
1
0
2
3
4
5
6
7
8
1
127
5-6120F
Note: Bit 1 is the MSB. Bit 8 is the LSB. MSB is always transmitted first in all transfers.
Figure 20. Frame Diagram
70
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0) (continued)
4.6.3 Detailed Timing Diagram
FRAME BOUNDARY
1 BIT CELL
tFS
tFH
2.0 V
/CT_FRAME
0.6 V
tFP
tC8H
tC8I
2.0 V
CT_C8
0.6 V
tC8P
tZDO
tDOD
2.4 V
DATA OUT
tS127
BIT 8
tS0
BIT 1
0.4 V
tDOZ
tDV
DATA IN
1.4 V
tSAMP
tDIV
5-6121F
Figure 21. Detailed Timing Diagram
Lucent Technologies Inc.
71
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
4 Electrical Characteristics
Preliminary Data Sheet
August 1998
(continued)
4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0) (continued)
4.6.4 ac Electrical Characteristics, Timing, H-Bus (H.100, Spec., Rev. 1.0)
Table 59. ac Electrical Characteristics, Timing, H-Bus (H.100, Spec., Rev. 1.0)
Symbol
—
tC8P
tC8H
tC8L
tSAMP
tDOZ
tZDO
tDOD
tDV
tDIV
tFP
tFS
tFH
Φ
Parameter
Clock Edge Rate (all clocks)
Clock CT_C8 Period
Clock CT_C8 High Time
Clock CT_C8 Low Time
Data Sample Point
Data Output to HiZ Time
Data HiZ to Output Time
Data Output Delay Time
Data Valid Time
Data Invalid Time
/CT_FRAME Width
/CT_FRAME Setup Time
/CT_FRAME Hold Time
Phase Correction
Min
Typ
Max
Unit
Notes
0.25
122.066 – Φ
49 – Φ
49 – Φ
—
–20
0
0
0
102
90
45
45
0
—
—
—
—
90
—
—
—
—
—
122
—
—
—
2
122.074 + Φ
73 + Φ
73 + Φ
—
0
22
22
69
112
180
90
90
10
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 4
2, 4, 5
2, 4, 6
2, 4, 6
2, 4, 9
2, 3, 4, 7, 11
2, 3, 4, 7, 11
2, 3, 4, 7
2, 3, 4, 8, 10
2, 4
2, 4
2, 4
2, 4
12
1.
The rise and fall times are determined by the edge rate in V/ns. A maximum edge rate is the fastest rate at which a clock transitions.
CT_NETREF has a separate requirement. (See Section 2.4 Clocking Section.)
2. Measuring conditions, data lines: VTH (threshold voltage) = 1.4 V, VHI (test high voltage) = 2.4 V, VLO (test low voltage) = 0.4 V, input signal
edge rate = 1 V/ns measuring conditions, clock and frame lines: Vt+ (test high voltage) = 2.0 V, Vt– (test low voltage) = 0.6 V, input signal
edge rate = 1 V/ns.
3. Test load—200 pF.
4. When RESET is active, every output driver is 3-stated.
5. tC8P minimum and maximum are under free-run conditions assuming ±32 ppm clock accuracy.
6. Noncumulative, tC8P requirements still need to be met.
7. Measured at the transmitter.
8. Measured at the receiver.
9. For reference only.
10. tDV = maximum clock cable delay + max. data cable delay + max. data HiZ to output time = 12 ns + 35 ns + 22 ns = 69 ns. Max. clock cable
delay and maximum data cable delay are worst-case numbers based on electrical simulation.
11. tDOZ and tZDO apply at every time-slot boundary.
12. F (phase correction) results from PLL timing corrections.
72
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.6 H-Bus Timing (Extract from H.100 Spec., Rev. 1.0) (continued)
4.6.5 Detailed Clock Skew Diagram
Vt+
Vt+
CT_C8_A
CT_C8_A
tSKC8
tSKCOMP
Vt+
Vt+
COMPATIBILITY
CLOCKS
CT_C8_B
Vt–
tSKCOMP
5-6122F
Figure 22. Detailed Clock Skew Diagram
4.3.6 ac Electrical Characteristics, Skew Timing, H-Bus (H.100, Spec., Rev. 1.0)
Table 60. ac Electrical Characteristics, Skew Timing, H-Bus (H.100, Spec., Rev. 1.0)
Symbol
tSKC8
Parameter
Max Skew Between CT_C8 A and B
tSKCOMP Max Skew Between CT_C8_A and Any Compatibility Clock
1.
2.
3.
4.
Min
Typ
Max
Unit
Notes
—
—
ns
1, 2, 3, 4
—
—
±10
±Φ
±5
ns
1
Test load—200 pF.
Assumes A and B masters in adjacent slots.
When static skew is 10 ns and, in the same clock cycle, each clock performs a 10 ns phase correction in opposite directions, a maximum
skew of 30 ns will occur during that clock cycle.
Meeting the skew requirements in Table 10 and the requirements of Section 2.3 H-Bus Section could require the PLLs generating CT_C8
to have different time constants when acting as primary and secondary clock masters.
4.6.7 Reset and Power On
Table 61. Reset and Power On
Symbol
tRD
tRS
Parameter
Output Float Delay from Reset Active
Reset Active from Power Good
Lucent Technologies Inc.
Min
Typ
Max
Unit
—
—
—
5
1
—
µs
µs
73
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
4 Electrical Characteristics
Preliminary Data Sheet
August 1998
(continued)
4.7 ac Electrical Characteristics, Local Streams, and Frames
Table 62. ac Electrical Characteristics, Local Streams, and Frames
Symbol
tPD
tS
tH
tOFF
tD0
Description
Data Propagation Delay
Data Setup Time
Data Hold Time
Data 3-state Off Time
Data Bit 0 3-state
3/4 POINT
3/4 POINT
Min
Max
Condition
Unit
0
10
5
—
–20
20
—
—
20
0
Load = 50 pF
—
—
—
—
ns
ns
ns
ns
ns
3/4 POINT
LOCAL SELECTED CLOCKS LSC[3:0]
(NONINVERTED SHOWN):
16.384 MHz
8.192 MHz
4.096 MHz
2.048 MHz
LOCAL DATA STREAMS:
8.192 Mbits/s
tD0
tPD
LDO
7
LDO
0
tS
8.192 Mbits/s
LDO
6
LDI
6
LDI
5
tD0
4.096 Mbits/s
tPD
LDO
0
tH
LDI
7
LDI
6
tPD
LDO
6
LDO
7
tS
tH
LDI
7
2.048 Mbits/s
FRAME GROUP:
LDO
5
LDO
6
tS
tD0
LDO
3
LDI
4
LDO
7
LDO
0
4.096 Mbits/s
2.048 Mbits/s
LDO
4
tH
LDI
7
LDI
0
LDO
5
tPD
5-6548F
Note: LDO7 is the MSB, LDO0 is the LSB. MSB is always transmitted first in all transfers.
Figure 23. ac Electrical Characteristics, Local Streams, and Frames
74
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.8 ac Electrical Characteristics, Microprocessor Timing
4.8.1 Microprocessor Access Intel Multiplexed Write and Read Cycles
For Intel write and read cycles, when RDY is low, wait-states are inserted. RDY is brought high when tIACC is met.
This is true for both read and write cycles.
AD[7:0]
A[1:0]
tAS
tAH
D[7:0]
tDS
tDH
ALE
CS
WR
tRDY
tIACC
RDY
(RDY DRIVEN LOW DURING
MEMORY ACCESSES ONLY)
5-6124.bF
Figure 24. Microprocessor Access Intel Multiplexed Write Cycle
AD[7:0]
A[1:0]
tAS
D[7:0]
tAH
tDV
tDI
ALE
CS
RD
tRDY
tIACC
RDY
(RDY DRIVEN LOW DURING
MEMORY ACCESSES ONLY)
5-6125.bF
Figure 25. Microprocessor Access Intel Multiplexed Read Cycle
Lucent Technologies Inc.
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Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
4 Electrical Characteristics
Preliminary Data Sheet
August 1998
(continued)
4.8 ac Electrical Characteristics, Microprocessor Timing (continued)
4.8.2 Microprocessor Access Motorola Write and Read Cycles
A[1:0]
tAH
tAS
R/W
DS (RD)
CS
tMACC
DTACK (RDY)
tDS
tDH
D[7:0]
5-6126.bF
Figure 26. Microprocessor Access Motorola Write Cycle
A[1:0]
tAS
tAH
R/W
DS (RD)
CS
tMACC
DTACK (RDY)
tDV
tDI
D[7:0]
5-6127.bF
Figure 27. Microprocessor Access Motorola Read Cycle
76
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
4 Electrical Characteristics (continued)
4.8 ac Electrical Characteristics, Microprocessor Timing (continued)
4.8.3 Microprocessor Access Intel Demultiplexed Write Cycle
A[1:0]
tAS
tAH
CS
WR
tIACC
tRDY
(RDY DRIVEN LOW
DURING MEMORY
ACCESSES ONLY)
RDY
tDS
tDH
D[7:0]
5-6128.cF
Figure 28. Microprocessor Access Intel Demultiplexed Write Cycle
A[1:0]
tAS
tAH
CS
RD
tRDY
RDY
tIACC
(RDY DRIVEN LOW
DURING MEMORY
ACCESSES ONLY)
tDV
tDI
D[7:0]
5-6128.bF
Figure 29. Microprocessor Access Intel Demultiplexed Read Cycle
Table 63. Microprocessor Access Timing (See Figure 24 through Figure 29.)
Symbol
Description
Min
Max
Condition
Unit
tAS
tAH
tDV
tDI
tRDY
tIACC
tMACC
Address Setup Time
Address Hold Time
Data Valid
Data Invalid
Active to Ready Low (Intel)
Active to Ready High (Intel)
Active to DTACK Low (Motorola)
7
0
—
0
—
145
—
145
8
0
—
—
13
11
14
255
14
255
—
—
Load = 100 pF
—
—
—
Memory Access
Memory Access
Register Access
Memory Access
—
—
ns
ns
ns
ns
ns
ns
ns
tDS
tDH
Data Setup Time
Data Hold Time
Lucent Technologies Inc.
ns
ns
77
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
5 Outline Diagram
5.1 208-Pin Square Quad Flat Package (SQFP)
30.60 ± 0.20
28.00 ± 0.20
PIN #1 IDENTIFIER ZONE
208
157
1
156
28.00
± 0.20
30.60
± 0.20
105
52
53
104
DETAIL A
DETAIL B
3.40 ± 0.20
4.10 MAX
SEATING PLANE
0.08
0.50 TYP
0.25 MIN
1.30 REF
0.25
0.090/0.200
GAGE PLANE
SEATING PLANE
0.17/0.27
0.50/0.75
DETAIL A
0.10
M
DETAIL B
5-2196(F)
Note:
78
The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design
efforts, please contact your Lucent Technologies Microelectronics Group Account Manager.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
5 Outline Diagram (continued)
5.2 217-Pin Ball Grid Array (PBGA)
23.00 ± 0.20
+0.70
19.50 –0.00
A1 BALL
IDENTIFIER ZONE
+0.70
19.50 –0.00
TOP VIEW
23.00
± 0.20
MOLD
COMPOUND
PWB
1.17 ± 0.05
0.36 ± 0.04
2.13 ± 0.19
SEATING PLANE
0.20
SIDE VIEW
0.60 ± 0.10
SOLDER BALL
16 SPACES @ 1.27 = 20.32
U
T
R
P
N
M
BOTTOM VIEW
0.75 ± 0.15
L
K
J
16 SPACES
@ 1.27 = 20.32
H
G
F
E
D
C
B
A
A1 BALL
CORNER
1 2
3 4 5 6 7
8 9 10 11 12 13 14 15 16 17
5-6562(F)
6 Ordering Information
Device Part No.
Description
Ambassador H.100 Interface
T8100- - -SC
Ambassador H.100 Interface
T8100- - -BAL
Lucent Technologies Inc.
Package
208-Pin SQFP
217-Pin BGA
Comcode
108125873
108194184
79
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Appendix A. Application of Clock
Modes
In the diagrams that follow, four clock modes are illustrated using Figure 12, the T8100 clocking diagram, as
the basis of each illustration. The key signal paths are
shown in solid lines, and unused paths with narrow
dashes. Two examples also indicate fallback paths. A
register profile (programming values) for all four examples is on the last page of the appendix.
In Figure 30, the T8100 is operating as a bus master,
so it must link to either an 8 kHz recovered frame reference or 2.048 MHz recovered bit clock reference from
the E1 framers. In addition, the T8100 can provide one
of the basic resource clocks to run the framers. In
this case, the TCLK is selecting the T8100’s
16.384 MHz oscillator. The framers are returning a
2.048 MHz bit clock which is selected through the clock
selector. It is not divided, so the main divider is
bypassed (divide-by-1), the clock is smoothed
through an external DJAT, and the smooth 2.048 MHz
signal is routed to PLL #1 through the clock resource
selector. PLL #1 multiplies the 2.048 MHz input up to
65.536 MHz which, in turn, runs the rest of the T8100,
all bus clocks, and the local clocks (if desired). If the
T8100 is not providing NETREF generation, then the
NETREF from the bus is routed to the local clocks via
the NETREF internal/external selector. Since the
NETREF generation resources are not needed here,
the TODJAT and FROMDJAT pins are free for use with
the general-purpose register as bits GP6 and GP7,
respectively.
Figure 31 shows the T1 version of a bus master. In this
scenario, a 1.544 MHz recovered bit clock from the
framers is routed to a multiclock adapter (with built-in
jitter attenuation) which produces smooth 4.096 MHz
and 3.088 MHz outputs. The 4.096 MHz is routed
up to PLL #1 for a times-16 rate multiplication to
65.536 MHz. This drives the bus clocks and the local
clocks. The smooth 3.088 MHz is also rate multiplied
times 8. This produces a 24.704 MHz clock. This is
80
Preliminary Data Sheet
August 1998
divided back down to produce a smooth 12.352 MHz
which is fed back to the framers. (PLL outputs produce
one tightly bound edge and one with significant phase
jitter. Dividing a higher-frequency signal based on its
clean edge produces a lower frequency with two clean
edges.)
Figure 32 shows an H-MVIP slave arrangement for E1.
In this example, the C16 differential clocks provide the
main source for PLL #1. The 16.384 MHz signal is
divided down to 4.096 MHz and then rate multiplied up
to 65.536 MHz for driving the rest of the T8100. The
frame sync for the state machines is derived from the
/FRAME and C16 inputs as well as the state information provided by C2 and /C4.
Note: The bit slider is enabled for a smooth phase
alignment between the internal frame and the
frame sync.
The bus clocks are not driven, but the local clocks are
available. A path for NETREF is shown as well, also
based on a 2.048 MHz input. The signal is smoothed
and then divided down to an 8 kHz signal via the
NETREF divider. The internal oscillator is again chosen
for routing to the framers via TCLK.
Figure 33 shows an H-MVIP slave for T1. This is identical to the E1 case with regard to slaving, and a
NETREF path is illustrated in this example, too. The
NETREF divider has been changed to accommodate
the 1.544 MHz bit clock rate. The primary difference is
the use of the C16 clock through the main divider to
generate a 2.048 MHz signal which can be routed offchip and adapted to a 1.544 MHz signal using an external device. The 1.544 MHz signal is returned to the
T8100 via the 3MHzIN for rate multiplication up to
24.704 MHz and then division to a clean 12.352 MHz
signal which is routed to the framers via TCLK.
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix A. Application of Clock Modes (continued)
TODJAT/GP6
FROMDJAT/GP7
NETREF
INT/EXT
SELECT
GP6
GP7
EN_NETREF
NETREF
DIVIDE-BY-N
NETREF
SEL.
DJAT BYPASS
(AND GP6/7 ENABLE)
NETREF
EN_A
C6
DIVIDE REGISTER
FRAME
EN_B
C8
÷ BY 8
NETREF
SELECT
/CT_FRAME A
/CT_FRAME B
FRAME
SEL.
BIT SLIDER
4 MHz
STATE
MACHINES
2 MHz
CLOCK
SEL.
CT_C8B
/C4
2.048 MHz
2.048 MHz
LREF0
4.096 MHz
RESOURCE
DIVIDE-BY-N
LREF7
CT_NETREF
CT_C8
CLKB
/C16±
/C4
C2
SCLK
SCLK2
/CT_FRAMEA
/CT_FRAMEB
COMPATIBILITY
CLOCKS DIRECTION
16.384 MHz
/CT16 ±
2.048 MHz
C2
4.096 MHz
PLL #1 BYPASS
DPLL
CT_C8A
FRAME
BIT SLIDER
CONTROLS
FRAME SYNC
/FR_COMP
CT_NETREF
CLOCK
SEL.
AND
INPUT
STATE
MACH.
8.192 MHz
PLL #1
DIVIDE REGISTER
SCSEL
4.096 MHz
65.536 MHz
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
x16
CLOCK
RESOURCE
SELECT
SCLK
8.192 MHz
x32
FRAME
RATE SELECT
SCLK2
/FR_COMP
SEC8K
PLL #2 BYPASS
FRAME
DIVIDE
BY 4
2.048 MHz
(FALLBACK PATH)
4.096 MHz
DIVIDE
BY 2
PLL #2
L_SC0
8.192 MHz
16.384 MHz
x8
x16
DPLL#2-2
RATE SELECT
XTALIN
TCI
SELECT
PRIREFO
4MHzIN
2MHz DJAT
3MHzIN
L_SC CTL
TCLK
TCLK
ENABLE
(1 OF 4
L_SC[1:3]
NOT SHOWN)
FRAMERS
5-6129aF(r3)
Figure 30. E1, CT Bus Master, Compatibility Clock Master, Clock Source = 2.048 MHz from Trunk
Lucent Technologies Inc.
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Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix A. Application of Clock Modes (continued)
TODJAT/GP6
FROMDJAT/GP7
NETREF
INT/EXT
SELECT
GP6
GP7
NETREF
SEL.
EN_NETREF
NETREF
DIVIDE-BY-N
NETREF
EN_A
C6
DIVIDE REGISTER
FRAME
EN_B
C8
÷ BY 8
NETREF
SELECT
/CT_FRAME_A
/CT_FRAME_B
FRAME
SEL.
1.544 MHz
L_REF0
L_REF7
CT_NETREF
CT_C8
CLKB
/C16±
/C4
C2
SCLK
SCLK2
STATE
MACHINES
2 MHz
4.096 MHz
PLL #1 BYPASS
DPLL
/CT_FRAME_A
CT_C8_B
/CT_FRAME_B
COMPATIBILITY
CLOCKS DIRECTION
16.384 MHz
/CT16 ±
2.048 MHz
C2
BIT SLIDER
FRAME SYNC
4 MHz
CLOCK
SEL.
CT_C8_A
FRAME
BIT SLIDER
CONTROL
/FR_COMP
CT_NETREF
/C4
2.048 MHz
4.096 MHz
SCLK
RESOURCE
DIVIDE-BY-N
CLOCK
SEL.
AND
INPUT
STATE
MACH.
8.192 MHz
PLL #1
DIVIDE REGISTER
SCSEL
4.096 MHz
65.536 MHz
x16
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
8.192 MHz
x32
CLOCK
RESOURCE
SELECT
FRAME
RATE SELECT
SCLK2
/FR_COMP
SEC8K
PLL #2 BYPASS
FRAME
DIVIDE
BY 4
2.048 MHz
(FALLBACK PATH)
4.096 MHz
DIVIDE
BY 2
PLL #2
L_SC0
8.192 MHz
x8
16.384 MHz
x16
DPLL#2-2
RATE SELECT
XTALIN
TCI
SELECT
(XTALIN STILL DRIVES
OTHER INTERNALS.)
PRIREFOUT
4MHzIN
3MHzIN
JITTER ATTENUATED
MULTICLOCK ADAPTER
L_SC CTL
TCLK
ENABLE
TCLK
(1 OF 4
L_SC[1:3]
NOT SHOWN)
FRAMERS
5-6130aF(r4)
Figure 31. T1, CT Bus Master, Compatibility Clock Master, Clock Source = 1.544 MHz from Trunk
82
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix A. Application of Clock Modes (continued)
2 MHz DJAT
TODJAT/GP6
FROMDJAT/GP7
NETREF
INT/EXT
SELECT
GP6
GP7
NETREF
SEL.
EN_NETREF
NETREF
DIVIDE-BY-N
DJAT BYPASS
(AND GP 6/7 ENABLE)
NETREF
EN_A
C6
DIVIDE REGISTER
FRAME
EN_B
C8
÷ BY 8
NETREF
SELECT
/CT_FRAME_A
/CT_FRAME_B
FRAME
SEL.
/FR_COMP
BIT SLIDER
4 MHz
STATE
MACHINES
2 MHz
CLOCK
SEL.
CT_C8_B
/C4
2.048 MHz
4.096 MHz
L_REF0
RESOURCE
DIVIDE-BY-N
2.048 MHz
L_REF7
CT_NETREF
CT_C8
CLKB
/C16±
/C4
C2
SCLK
SCLK2
/CT_FRAME_A
/CT_FRAME_B
COMPATIBILITY
CLOCKS DIRECTION
16.384 MHz
/CT16 ±
2.048 MHz
C2
4.096 MHz
PLL #1 BYPASS
DPLL
CT_C8_A
FRAME
BIT SLIDER
CONTROLS
FRAME SYNC
CT_NETREF
CLOCK
SEL.
AND
INPUT
STATE
MACH.
8.192 MHz
PLL #1
DIVIDE REGISTER
SCSEL
4.096 MHz
65.536 MHz
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
x16
CLOCK
RESOURCE
SELECT
SCLK
8.192 MHz
x32
FRAME
RATE SELECT
SCLK2
/FR_COMP
SEC8K
PLL #2 BYPASS
FRAME
DIVIDE
BY 4
2.048 MHz
(FALLBACK PATH)
4.096 MHz
DIVIDE
BY 2
PLL #2
L_SC0
8.192 MHz
x8
16.384 MHz
x16
DPLL#2-2
RATE SELECT
XTALIN
TCI
SELECT
PRIREFOUT
4MHzIN
3MHzIN
L_SC CTL
TCLK
TCLK
ENABLE
(1 OF 4
L_SC[1:3]
NOT SHOWN)
FRAMERS
5-6131aF(r3)
Figure 32. E1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
Source = 2.048 MHz from Trunk
Lucent Technologies Inc.
83
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix A. Application of Clock Modes (continued)
1.5 MHz DJAT
TODJAT/GP6
FROMDJAT/GP7
NETREF
INT/EXT
SELECT
GP6
GP7
EN_NETREF
NETREF
DIVIDE-BY-N
NETREF
SEL.
DJAT BYPASS
(AND GP6/7 ENABLE)
NETREF
EN_A
C8
DIVIDE REGISTER
FRAME
EN_B
C8
÷ BY 8
NETREF
SELECT
/CT_FRAME_A
/CT_FRAME_B
FRAME
SEL.
4 MHz
STATE
MACHINES
4.096 MHz
PLL #1 BYPASS
DPLL
CT_C8_B
/C4
2.048 MHz
4.096 MHz
L_REF0
RESOURCE
DIVIDE-BY-N
1.544 MHz
L_REF7
CT_NETREF
CT_C8
CLKB
/16±
/C4
C2
SCLK
SCLK2
/CT_FRAME_A
/CT_FRAME_B
COMPATIBILITY
CLOCKS DIRECTION
16.384 MHz
/CT16 ±
2.048 MHz
C2
BIT SLIDER
2 MHz
CLOCK
SEL.
CT_C8_A
FRAME
BIT SLIDER
CONTROL
FRAME SYNC
/FR_COMP
CT_NETREF
CLOCK
SEL.
AND
INPUT
STATE
MACH.
8.192 MHz
PLL #1
DIVIDE REGISTER
SCSEL
4.096 MHz
65.536 MHz
x16
MAIN
DIVIDE-BY-N
DIVIDE REGISTER
CLOCK
RESOURCE
SELECT
SCLK
8.192 MHz
x32
FRAME
RATE SELECT
SCLK2
/FR_COMP
SEC8K
PLL #2 BYPASS
FRAME
DIVIDE
BY 4
2.048 MHz
(FALLBACK PATH)
4.096 MHz
DIVIDE
BY 2
PLL #2
L_SC0
8.192 MHz
x8
16.384 MHz
x16
DPLL#2-2
RATE SELECT
XTALIN
TCLI
SELECT
PRIREFOUT
4MHzIN
JITTER ATTENUATED
MULTICLOCK ADAPTER
3MHzIN
L_SC CTL
TCLK
ENABLE
TCLK
(1 OF 4
L_SC[1:3]
NOT SHOWN)
FRAMERS
5-6132aF(r5)
Figure 33. T1, Slave to CT Bus, Clock Source Is Either a 16 MHz or a 4 MHz or a 2 MHz and Frame, NETREF
Source = 1.544 MHz from Trunk
84
Lucent Technologies Inc.
Preliminary Data Sheet
August 1998
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Appendix A. Application of Clock Modes (continued)
Table 64. Clock Register Programming Profile for the Four Previous Examples
Register Name
CT Bus Master (E1) CT Bus Master (T1)
CKM
CKN
CKP
CKR
CKS
CK32
CK10
CKMD
CKND
CKRD
Watchdog: CKW
0010_1000b
0110_0000b
0010_0001b
0001_0000b
0000_0000b
1001_0100b
1101_1111b
0000_0000b
0000_0000b
0000_0000b
0011_1001b
0010_1000b
0110_0000b
0110_0001b
0000_0000b
0000_0000b
1001_0100b
1101_1111b
0000_0000b
0000_0000b
0000_0000b
0011_1001b
CT Bus Slave (E1)
CT Bus Slave (T1)
1100_0101b
1000_1111b
0010_0000b
0100_0000b
0000_0000b
0010_0100b
1000_0000b
0000_0000b
1111_1111b
0000_0011b
0011_1001b
1100_0101b
1000_1111b
0110_0000b
0100_0000b
0000_0000b
0010_0100b
1011_1101b
0000_0111b
1100_0000b
0000_0011b
0011_1001b
The programming displays how similar the four basic modes of operation are. Local outputs (CK32 and CK10) are
obviously not constrained by the mode of operation. The primary difference between E1 and T1 is in the use of the
PLL #2 (which is optional). The primary difference between master and slave is in the clock path to PLL #1, which
is covered by registers CKM, CKR, CKMD, and CKRD.
Note:
CKR does include an example of running PLL #1 at X32 for E1 master and X16 for all other cases.
The watchdogs have been set up to monitor all CT Bus signals, though fallback (to the oscillator) is shown as
enabled in all examples. It is recommended that the default condition, CKS = 0x00, be used for systems which do
not have specific fallback clocking schemes. Also, while programming the T8100 on powerup, it is recommended
that the watchdogs are disabled (CKW = 0x00) until the device is fully programmed to prevent false error conditions
(uninitialized clocks, for example) from changing the operating mode.
Lucent Technologies Inc.
85
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Appendix B. Minimum Delay and Constant Delay Connections
B.1 Connection Definitions
Forward
Connection
Reverse
Connection
A forward connection is defined as one
in which the output (to) time slot has a
greater value than the input (from) time
slot, or put another way, the delta
between them is positive.
A reverse connection is defined as one
in which the input (from) time slot has
a lesser value than the output (to) time
slot, and the delta between them is
negative.
So, for example, going from TS(1) to TS(38) is a forward connection, and the TS∆ is +37, but going from
TS(38) to TS(1) is a reverse connection, with a TS∆ of
–37:
Preliminary Data Sheet
August 1998
The user can utilize the TS∆ to control the latency of
the resulting connection. In some cases, the latency
must be minimized. In other cases, such as a block of
connections which must maintain some relative integrity while crossing a frame boundary, the required
latency of some of the connections may exceed one
frame (>128 time slots) to maintain the integrity of this
virtual frame.
The T8100 contains several bits for controlling latency.
Each connection has a bit which is used for selecting
one of two alternating data buffers. These bits are set
in the local connection memory for local switching or in
the tag register files of the CAM section for H-Bus
switching. There are also 2 bits in the CON register,
address 0x0E, which can control the buffer selection on
a chip-wide basis. Bit 1 of the register overrides the
individual FME bits. Bit 0 becomes the global, chipwide, FME setting.
where TS∆ = TS(to) – TS(from).
Similarly, a delta can be introduced for streams which
will have a bearing in certain exceptions (discussed
later):
STR∆ = STR(to) – STR(from)
There is only one combination which forms a TS∆ of
+127 or –127:
TS∆ = TS(127) – TS(0) = +127, and
TS∆ = TS(0) – TS(127) = –127,
but there are two combinations which form TS∆s of
+126 or –126:
TS∆ = TS(127) – TS(1) = TS(126) – TS(0) = +126, and
TS∆ = TS(1) – TS(127) = TS(0) – TS(126) = –126,
there are three combinations which yield +125 or –125,
and so on.
86
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix B. Minimum Delay and Constant Delay Connections (continued)
Minimum Delay This is the most common type of
switching, but has a shorter range
than constant delay, and the user must
be aware of exceptions caused by
interactions between the T8100's
internal pipeline and the dual buffering. The to time slot is at least three
time slots after the from time slot, but
no more than 128 time slots after the
from time slot. Exceptions exist at
TS∆s of +1, +2, –126, and –127.
B.2 Delay Type Definitions
Constant Delay In the T8100, this is a well-defined,
predictable, and linear region of
latency in which the to time slot is at
least 128 time slots after the from time
slot, but no more than 256 time slots
after the from time slot.
Forward Connections, FME = 0: L = TS∆ (3 ≤ TS∆ ≤
127)
Mathematically, constant delay latency is described as
follows*, with L denoting latency, and FME set to the
value indicated:
Reverse Connections, FME = 1: L = 128 + TS∆ (–125 ≤
TS∆ ≤ 0)
Forward Connections, FME = 1: L = 128 + TS∆ (0 ≤
TS∆ ≤ 127)
Example:
Using the same switching from the
example above, TS(37) to TS(1), the
delta is –36, so FME is set to 1 to effect
the minimum delay (setting to 0 effects
constant delay), and the resulting
latency is 128 – 36 = 92 time slots. The
relative positions of the end time slots
are the same in both minimum and constant delay (i.e., they both switch to
TS[1]), but the actual data is delayed by
an additional frame in the constant delay
case.
Simple
Summary:
Use minimum delay for latencies of 3 to
128 time slots, set FME = 0 for forward
connections, set FME = 1 for reverse
connections.
Reverse Connections, FME = 0: L = 256 + TS∆ (–127 ≤
TS∆ ≤ 0)
Example:
Switching from TS(37) to TS(1) as a constant delay, the delta is –36, so FME is
set to 0 and the resulting latency is 256 –
36 = 220 time slots. Thus, the connection will be made from TS(37) of
Frame(n) to TS(1) of Frame(n + 2).
Simple
Summary:
Use constant delay for latencies of 128
to 256 time slots, set FME = 1 for forward
connections, set FME = 0 for reverse
connections.
* Since TS∆ = TS(to) – TS(from), the user can modify the equations
to solve for either TS(to) or TS(from).
127
255
APPLIED DELTA
(TIME SLOTS)
F
0
128
=
ME
1
RESULTING LATENCY
(TIME SLOTS)
FM
E=
256
0
–127
129
5-6223 (F)
Figure 34. Constant Delay Connections, CON[1:0] = 0X
Lucent Technologies Inc.
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Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Appendix B. Minimum Delay and Constant Delay Connections (continued)
Preliminary Data Sheet
August 1998
B.2.2 Lower Stream Rates
The discussion has centered on 128 time-slot frames
which correspond to 8.192 Mbits/s data rates. How
does one make similar predictions for lower stream
rates?
B.2 Delay Type Definitions (continued)
B.2.1 Exceptions to Minimum Delay
For 4.096 Mbits/s, multiply the to and from time-slot
values by two, i.e., time slot 0 at 4.096 Mbits/s corresponds to time slot 0 at 8.192 Mbits/s, and time slot 63
at 4.096 Mbits/s corresponds to time slot 126 at 8.192
Mbits/s. Similarly, multiply values by four to convert
2.048 Mbits/s values. The latency equations can then
be applied directly.
Up until this point in the discussion, the STRDs have
not been discussed because the to and from streams
have been irrelevant in the switching process*. Rather
than try to list the exceptions mathematically, a table is
provided. The latencies in these cases may exceed two
frames due to the interaction of the intrinsic pipeline
delays with the double buffering.
Table 65. Table of Special Cases (Exceptions)
FME Value
TS∆
Latency for
STR∆ < 0
Latency for
STR∆ ≥ 0
0
0
1
1
+1
+2
–126
–127
257
258
258
257
257
2
2
257
* The one universally disallowed connection on the T8100 is a TS∆ of
0 and a STR∆ of 0. This is a stream and time-slot switching to itself.
Loopback on the local bus, e.g., LDO_0 to LDI_0 is permissible.
Graphically, the minimum delay latency equations are
illustrated below. The exceptions to the minimum delay
have been included in the diagram, connected to the
main function by dashed lines.
127
127
FM
0
E=
SPECIAL LONG LATENCY
CONNECTIONS
(SEE TEXT)
APPLIED DELTA
(TIME SLOTS)
2
2
0
RESULTING LATENCY
(TIME SLOTS)
0
FM
E=
258
128......256
1
–126
–127
2
257
5-6224(F)
Figure 35. Minimum Delay Connections, CON[1:0] = 0X
88
Lucent Technologies Inc.
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix B. Minimum Delay and Constant Delay Connections (continued)
ping appears as a linear monotonic function covering
255 time slots. (Graphs are in the section which follows.) The latency equations follow:
B.2 Delay Type Definitions (continued)
CON[1:0] = 10:
B.2.3 Mixed Minimum/Constant Delay
Forward Connections: L = TS∆ (3 ≤ TS∆ ≤ 127).
Reverse Connections: L = 256 + TS∆ (–127 ≤ TS∆ ≤
0).
An interesting mix of delays occurs when the individual
FME bits are overridden and a chip-wide selection for
FME is used. In short, when the T8100 is placed in this
mode, and when register bits CON[1:0] = 10, forward
connections provide minimum delay, reverse connections provide constant delay. When CON[1:0] = 11,
reverse connections provide minimum delay, forward
connections provide constant delay. The latter is interesting because, graphically, the TS∆ to latency map-
CON[1:0] = 11:
Forward and Reverse: L = 128 + TS∆ (–125 ≤ TS∆ ≤
127).
Table 65, Table of Special Cases (Exceptions), applies
to the mixed delays in a similar manner. Simply use bit
0 of CON for the FME value in Table 65.
127
SPECIAL LONG LATENCY
CONNECTIONS
(SEE TEXT)
FM
E
=
0
127
258
128
2
0
0
256
RESULTING LATENCY
(TIME SLOTS)
FM
E
=
0
APPLIED DELTA
(TIME SLOTS)
2
–127
–127
129
5-6225(F)
Figure 36. Mixed Minimum/Constant Delay Connections, CON[1:0 = 10]
Lucent Technologies Inc.
89
Ambassador T8100
H.100/H.110 Interface and Time-Slot Interchanger
Preliminary Data Sheet
August 1998
Appendix B. Minimum Delay and Constant Delay Connections (continued)
B.2 Delay Type Definitions (continued)
B.2.3 Mixed Minimum/Constant Delay (continued)
127
APPLIED DELTA
(TIME SLOTS)
FM
E
=
1
255
128
0
0
256
RESULTING LATENCY
(TIME SLOTS)
SPECIAL LONG LATENCY
CONNECTIONS
(SEE TEXT)
–126
–127
2
258
257
5-6226(F)
Figure 37. Extended Linear (Mixed Minimum/Constant) Delay, CON[1:0] = 11
For additional information, contact your Microelectronics Group Account Manager or the following:
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Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No
rights under any patent accompany the sale of any such product(s) or information. Ambassador is a trademark of Lucent Technologies Inc.
Copyright © 1998 Lucent Technologies Inc.
All Rights Reserved
August 1998
DS98-195NTNB (Replaces DS98-130NTNB, DA98-011NTNB, DA98-014NTNB, and AY98-015NTNB)