AGERE T8538B

Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Features
■
3.3 V operation
■
Per-channel programmable gains, equalization,
termination impedance, and hybrid balance
■
Programmable µ-law, linear, or A-law modes:
— Up to 256 time slots per frame
— Supports PCM data rates of 512 kbits/s to
16.384 Mbits/s
— Double-clock mode timing compatible with
ISDN standard interfaces
■
Fully programmable time-slot assignment with bit
offset
■
Analog and digital loopback test modes
■
Serial microprocessor interface:
— Normal and byte-by-byte control modes
— Fast scan mode
■
Six bidirectional control leads per channel, for
SLIC and line card function control
■
Differential analog output:
— Mates directly to SLICs, eliminating external
components
■
Sigma-delta converters with dither noise reduction
■
Quad design to minimize package count on dense
line card applications
■
Meets or exceeds ITU-T G.711—G.712 and relevant Telcordia TechnologiesTM requirements
Description
The device consists of four independent channels of
codec and digital signal processing functions on one
chip. In addition to the classic A-to-D and D-to-A conversion, each channel provides termination impedance synthesis and a hybrid balance network.
The device is controlled by a serial microprocessor
interface, and a series of bidirectional I/O leads are
provided so that this control mechanism can be utilized to operate the battery feed device, ringing voltage switches, etc. Common data and clock paths can
be shared over any number of devices. All the filter
coefficients, signal processing, SLIC, and test features are accessible through this interface. This
serial interface can be operated at speeds up to
16 Mbits/s.
The choice of a PCM bus is also programmable, with
any channel capable of being assigned to any time
slot. The PCM bus can be operated at speeds up to
16.384 Mbits/s, allowing for a maximum of 256 time
slots. Separate transmit and receive interfaces are
available for 4-wire bus designs, or they can be
strapped together for a 2-wire PCM bus.
The device is available in two packages.
The T8538B 64-pin TQFP features five data latches
per channel and the 100-pin TQFP features six data
latches per channel.
Both devices are pin-compatible with the T8536B 5 V
quad programmable codecs.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Table of Contents
Contents
Page
Features ......................................................................1
Description...................................................................1
General Description.....................................................3
Pin Information ............................................................5
Functional Description .................................................9
Clocking Considerations ...........................................9
The Control Interface ................................................9
Modes ....................................................................9
Protocol ................................................................10
Write Command ...................................................12
Read Command ...................................................14
Fast Scan Mode ...................................................17
Write All Channels................................................19
Reset Functionality .................................................19
Memory Control Mapping .....................................20
Standby Mode.........................................................20
Test Capabilities .....................................................20
SLIC Control Capabilities ........................................21
Suggested Initialization Procedures........................21
Signal Processing ...................................................22
Absolute Maximum Ratings.......................................22
Operating Ranges .....................................................23
Handling Precautions ................................................23
Electrical Characteristics ...........................................24
dc Characteristics ...................................................24
Analog Interface......................................................25
Gain and Dynamic Range .......................................26
Noise Characteristics ..............................................28
Distortion and Group Delay.....................................29
Crosstalk .................................................................30
Timing Characteristics ...............................................31
Control Interface Timing..........................................31
Serial Control Port Timing ....................................31
Normal Mode........................................................32
Byte-by-Byte Mode...............................................32
PCM Interface Timing .............................................33
Single-Clocking Mode ..........................................33
Double-Clocking Mode.........................................35
Software Interface .....................................................37
Applications ...............................................................41
Outline Diagrams.......................................................42
100-Pin TQFP .........................................................42
64-Pin TQFP ...........................................................43
Ordering Information..................................................44
Figures
Page
Figure 1. Functional Block Diagram, Each Section .....3
Figure 2. 100-Pin TQFP Pin Diagram..........................5
Figure 3. 64-Pin TQFP Pin Diagram............................7
Figure 4. Command Frame Format, Master to Slave,
Read or Write Commands..........................11
Figure 5. Command Frame Format, Slave to Master,
Read Commands .......................................11
Figure 6. Write Operation, Normal Mode
(Continuous DCLK) ....................................12
Figure 7. Write Operation, Normal Mode (Gapped
DCLK) ........................................................12
2
Figure 8. Write Operation, Byte-by-Byte Mode
(Gapped DCLK)......................................... 13
Figure 9. Write Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................... 13
Figure 10. Read Operation, Normal Mode
(Continuous DCLK) ................................. 14
Figure 11. Read Operation, Normal Mode
(Gapped DCLK) ...................................... 15
Figure 12. Read Operation, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 15
Figure 13. Read Operation, Byte-by-Byte Mode
(Continuous DCLK) ................................. 16
Figure 14. Fast Scan, Normal Mode
(Continuous DCLK) ................................. 17
Figure 15. Fast Scan, Normal Mode (Gapped
DCLK) ..................................................... 18
Figure 16. Fast Scan, Byte-by-Byte Mode
(Gapped DCLK) ...................................... 18
Figure 17. Fast Scan, Byte-by-Byte Mode
(Continuous DCLK) ................................. 19
Figure 18. Hardware Reset Procedure..................... 19
Figure 19. Internal Signal Processing....................... 22
Figure 20. Serial Interface Timing, Normal Mode
(One Byte Transfer and Continuous
DCLK Shown) ......................................... 32
Figure 21. Byte-by-Byte Mode Timing
(Gapped DCLK Shown) .......................... 32
Figure 22. Single-Clocking Mode (TXBITOFF = 0,
RXBITOFF = 0, PCMCTRL2 = 0x00) ...... 34
Figure 23. Single-Clocking Mode (TXBITOFF = 1,
RXBITOFF = 2, PCMCTRL2 = 0x01) ...... 34
Figure 24. Double-Clocking Mode (RXBITOFF =
0x20, PCMCTRL2 = 0x00) ...................... 36
Figure 25. POTS Interface........................................ 41
Tables
Page
Table 1. Pin Assignments, 100-Pin TQFP,
Per-Channel Functions................................. 5
Table 2. Pin Assignments, 100-Pin TQFP,
Common Functions ...................................... 6
Table 3. Pin Assignments, 64-Pin TQFP,
Per-Channel Functions................................. 7
Table 4. Pin Assignments, 64-Pin TQFP,
Common Functions ...................................... 8
Table 5. Bit Assignments for Fast Scan Mode ......... 17
Table 6. dc Characteristics ....................................... 24
Table 7. Analog Interface ......................................... 25
Table 8. Power Dissipation....................................... 25
Table 9. Gain and Dynamic Range .......................... 26
Table 10. Per-Channel Noise Characteristics .......... 28
Table 11. Distortion and Group Delay ...................... 29
Table 12. Crosstalk................................................... 30
Table 13. Serial Control Port Timing ........................ 31
Table 14. PCM Interface Timing: Single-Clocking
Mode ........................................................ 33
Table 15. PCM Interface Timing: Double-Clocking
Mode ........................................................ 35
Table 16. Memory Mapping...................................... 37
Table 17. Control Bit Definition................................. 38
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
General Description
Refer to Figure 1 for the following discussion.
DIGITAL GAIN
(GAIN TRANSFER)
PER
CHANNEL
HYBRID
BALANCE
NETWORK
µ-LAW
OR
A-LAW
CONVERSION
DIGITAL
LOOPBACK 1
TERMINATION
IMPEDANCE
ANALOG
LOOPBACK 2
DIGITAL
LOOPBACK 2
ANALOG
LOOPBACK 1
TO/FROM
SLIC
VFROPn
VFRONn
PCM BUS
INTERFACE
DX0
DX1
TSX0
TSX1
TO/FROM
PCM BUS
DR0
DR1
D/A
CONVERTER
DIGITAL GAIN
(GAIN TRANSFER)
ANALOG
BUFFER
FS
BCLK
CONTROL AND DATA SIGNALS
SLIC
CONTROL LATCHES
5 OR 6
POWER AND
GROUND
COMMON
A/D
CONVERTER
DIGITAL
LOOPBACK 3
VFXIn
ANALOG
GAIN
18
MICROPROCESSOR CONTROL
PER
CHANNEL
COMMON
FREQUENCY
SYNTHESIZER
4
RST
SERIAL
CONTROL
INTERFACE
5-8125CF
Figure 1. Functional Block Diagram, Each Section
This device performs virtually all the signal processing
functions associated with a central office line termination. Functionality includes line termination impedance
synthesis, fixed hybrid balance impedance synthesis,
and level conversion both in the analog sense to
accommodate various subscriber line interface circuits
(SLICs) and in the digital sense for adjustment of the
levels on the PCM bus. In general, the termination
impedance synthesis generates the equivalent of a circuit with the parallel combination of a capacitor and a
resistor in series with a resistor or the parallel combination of a resistor and the series combination of a resistor and capacitor. These general forms of impedance
characteristic will satisfy most of the requirements
specified throughout the world. Programmable selection of either µ-law or A-law encoding further aids
worldwide deployment. All coefficients used in the filtering algorithms can be computed off-line in advance and
Agere Systems Inc.
downloaded to the device at the time of powerup. All
signal processing is contained within the device, and
there are only three interfaces of consequence to the
system designer: the SLIC interface, the PCM interface, and the control interface.
The SLIC interface is designed to be flexible and convenient to use with a variety of SLIC circuits. With an
appropriate choice of SLIC, few external components
are required in the interface.
3
T8538B Quad Programmable Codec
General Description (continued)
The PCM bus interface is flexible in that it allows, independently, the transmit and receive data for any channel to be placed in any time slot. The bus can be
operated at a maximum 16.384 Mbits/s rate to accommodate a maximum 256 time slots. Separate pins
are provided for each direction of transmission to
allow 4-wire bus operation. The frame strobe signal is
an 8 kHz signal that defines the beginning of the frame
structure for all four channels. The interface will count
8 bits per time slot and insert or read the data for each
channel as programmed. Lower speeds of the PCM
bus are allowed. The PCM clock must be synchronous
with the frame strobe signal.
4
Preliminary Data Sheet
August 2001
The microprocessor control interface is a serial interface that uses the classical chip select type of operation. The interface controls the device by writing or
reading various internal addresses. The command set
consists of simple read and write operations, with the
address determining the effect. All the memory locations, including the per-chip functions, are organized by
channel.
There are several test modes included to facilitate confirmation of correct operation. In the signal path, two
analog and three digital loopback tests are available,
while in the microprocessor interface, there is a write/
read test mode that tests the operation of the memory.
Use of external test access switches allows a complete
test of the signal path through the line card so that correct operation of various operational modes can be verified.
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
39
40
41
42
43
44
45
46
47
48
49
50
27
28
29
30
31
32
33
34
35
36
37
38
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DX1
TSX0
DR0
DX0
DGND
NC
BCLK
FS
VDD
SLIC1d
SLIC0d
NC
NC
NC
NC
NC
NC
VFRONd
VFROPd
VFXId
VDDd
AGNDd
SLIC5c
SLIC4c
DGND
SLIC0b
VFRONb
VFROPb
VFXIb
VDDb
AGNDb
NC
NC
AGNDc
NC
VDDc
NC
NC
NC
NC
VFXIc
VFROPc
VFRONc
NC
VDD
SLIC0c
SLIC1c
SLIC2c
SLIC3c
NC
VDD
NC
NC
DGND
SLIC1a
SLIC0a
NC
NC
NC
NC
VFRONa
NC
VFROPa
VFXIa
NC
VDDa
AGNDa
SLIC5b
SLIC4b
DGND
SLIC3b
NC
SLIC2b
SLIC1b
VDD
100
99
98
97
96
95
SLIC2a
SLIC3a
SLIC4a
SLIC5a
NC
NC
NC
NC
NC
NC
INTS
CS
DCLK
DI
DO
NC
DGND
VDD
RST
SLIC4d
SLIC3d
SLIC5d
SLIC2d
TSX1
DR1
Pin Information
5-8885a (F)
Figure 2. 100-Pin TQFP Pin Diagram
Table 1. Pin Assignments, 100-Pin TQFP, Per-Channel Functions
Ckt
Name
Type
54
AGND
36
41
55
56
VDD
VFXI
28
42
57
VFROP
11
27
43
58
VFRON
6
5
100
99
98
97
26
24
23
21
19
18
46
47
48
49
52
53
65
66
78
80
81
79
SLIC0
SLIC1
SLIC2
SLIC3
SLIC4
SLIC5
GND Analog Ground. A common AGND, DGND plane is highly
recommended.
PWR Analog Power Supply.
I
Voice Frequency Transmit Input. For complex terminations,
this node requires a 10 MΩ or 20 MΩ resistance to AGND.
O
Voice Frequency Receive Output, Positive Polarity. This pin
can drive 2000 Ω (or greater) loads.
O
Voice Frequency Receive Output, Negative Polarity. This pin
can drive 2000 Ω (or greater) loads.
I/O SLIC Control 0.
I/O SLIC Control 1.
I/O SLIC Control 2.
I/O SLIC Control 3.
I/O SLIC Control 4.
I/O SLIC Control 5.
a
b
c
d
17
31
34
16
14
30
29
13
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Name/Description
5
T8538B Quad Programmable Codec
Preliminary Data Sheet
August 2001
Pin Information (continued)
Table 2. Pin Assignments, 100-Pin TQFP, Common Functions
Pin
1, 25, 45, 67, 83
2, 3, 7—10, 12, 15,
22, 32, 33, 35,
37—40, 44, 50,
59—64, 70, 85,
91—96
4, 20, 51, 71, 84
Name
VDD
NC
Type
Name/Description
PWR Digital Power Supply (3.3 V).
—
No Connect. Pin may be used as a tie point.
DGND
GND
68
FS
I
69
BCLK
I
72
73
74
DX0
DR0
O
I
O
6
TSX0
75
76
77
DX1
DR1
TSX1
O
I
O
82
RST
I
86
87
88
89
DO
DI
DCLK
CS
O
I
I
I
90
INTS
I
Digital Ground. Logic ground and return for logic power supply. A common AGND, DGND plane is highly recommended.
PCM Frame Strobe Input. This 8 kHz clock must be derived from the
same source as BCLK.
PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock rates.
PCM Transmit Data Output 0. This is a 3-state output.
PCM Receive Data Input 0.
Backplane Line Driver Enable 0 (Active-Low). Normally, these opendrain outputs are floating in a high-impedance state. When a time slot is
active on DX0, this output pulls low to enable a backplane line driver.
PCM Transmit Data Output 1. This is a 3-state output.
PCM Receive Data Input 1.
Backplane Line Driver Enable 1 (Active-Low). Normally, these opendrain outputs are floating in a high-impedance state. When a time slot is
active on DX1, this output pulls low to enable a backplane line driver.
Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1 µF capacitor for a power-on reset function,
or it may be driven by external logic. This lead has an internal pull-up.
Serial Data Output. This is a 3-state output.
Serial Data Input.
Serial Data Clock Input.
Chip Select Input. This lead determines the interval that the serial interface is active.
Serial Interface Select. Leaving this lead open places the serial interface
in the normal mode; grounding it places the interface into the byte-by-byte
mode. This lead has an internal pull-up.
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
SLIC2a
SLIC3a
SLIC4a
INTS
CS
DCLK
DI
DO
DGND
VDD
RST
SLIC4d
SLIC3d
SLIC2d
TSX1
DR1
Pin Information (continued)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD
DGND
SLIC1a
SLIC0a
VFRONa
VFROPa
VFXIa
VDDa
AGNDa
SLIC4b
DGND
SLIC3b
SLIC2b
SLIC1b
VDD
SLIC0b
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DX1
TSX0
DR0
DX0
DGND
BCLK
FS
VDD
SLIC1d
SLIC0d
VFRONd
VFROPd
VFXId
VDDd
AGNDd
SLIC4c
VFRONb
VFROPb
VFXIb
VDDb
AGNDb
AGNDc
VDDc
VFXIc
VFROPc
VFRONc
VDD
SLIC0c
SLIC1c
SLIC2c
SLIC3c
DGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
5-7187iF
Figure 3. 64-Pin TQFP Pin Diagram
Table 3. Pin Assignments 64-Pin TQFP, Per-Channel Functions
Ckt
Name
Type
34
AGND
23
24
35
36
VDD
VFXI
18
25
37
VFROP
5
17
26
38
VFRON
4
3
64
63
62
16
14
13
12
10
28
29
30
31
33
39
40
51
52
53
SLIC0
SLIC1
SLIC2
SLIC3
SLIC4
GND Analog Ground. A common AGND, DGND plane is highly
recommended.
PWR Analog Power Supply.
I
Voice Frequency Transmit Input. For complex terminations,
this node requires a 10 MΩ or 20 MΩ resistance to AGND.
O
Voice Frequency Receive Output, Positive Polarity. This
pin can drive 2000 Ω (or greater) loads.
O
Voice Frequency Receive Output, Negative Polarity. This
pin can drive 2000 Ω (or greater) loads.
I/O SLIC Control 0.
I/O SLIC Control 1.
I/O SLIC Control 2.
I/O SLIC Control 3.
I/O SLIC Control 4.
a
b
c
d
9
21
22
8
7
20
19
6
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Name/Description
7
T8538B Quad Programmable Codec
Preliminary Data Sheet
August 2001
Pin Information (continued)
Table 4. Pin Assignments 64-Pin TQFP, Common Functions
Pin
1, 15, 27, 41, 55
2, 11, 32, 44, 56
Name
VDD
DGND
42
FS
43
BCLK
45
46
47
DX0
DR0
8
TSX0
48
49
50
DX1
DR1
TSX1
54
RST
57
58
59
60
DO
DI
DCLK
CS
61
INTS
Type
Name/Description
PWR Digital Power Supply (3.3 V).
GND Digital Ground. Logic ground and return for logic power supply. A common
AGND, DGND plane is highly recommended.
I
PCM Frame Strobe Input. This 8 kHz clock must be derived from the same
source as BCLK.
I
PCM Bit Clock Input. This lead is used to develop internal clocks for certain clock rates.
O
PCM Transmit Data Output 0. This is a 3-state output.
I
PCM Receive Data Input 0.
O
Backplane Line Driver Enable 0 (Active-Low). Normally, these opendrain outputs are floating in a high-impedance state. When a time slot is
active on DX0, this output pulls low to enable a backplane line driver.
O
PCM Transmit Data Output 1. This a 3-state output.
I
PCM Receive Data Input 1.
O
Backplane Line Driver Enable 1 (Active-Low). Normally, these opendrain outputs are floating in a high-impedance state. When a time slot is
active on DX1, this output pulls low to enable a backplane line driver.
I
Power-On Reset. A low causes a reset of the entire chip. This pin may be
connected to DGND with a 0.1 µF capacitor for a power-on reset function, or
it may be driven by external logic. This lead has an internal pull-up.
O
Serial Data Output. This is a 3-state output.
I
Serial Data Input.
I
Serial Data Clock Input.
I
Chip Select Input. This lead determines the interval that the serial interface
is active.
I
Serial Interface Select. Leaving this lead open places the serial interface in
the normal mode; grounding it places the interface into the byte-by-byte
mode. This lead has an internal pull-up.
Agere Systems Inc.
Preliminary Data Sheet
August 2001
Functional Description
Clocking Considerations
The PCM bus uses a bit clock (BCLK) and a frame synchronization pulse (FS) to determine the location of the
beginning of a frame. These two clocks must be
derived from the same source. Internally, the device
develops all the internal clocks with a phase-locked
loop that uses BCLK as the timing source. BCLK and
FS must be continuously present and without gaps in
order for the device to operate correctly.
DCLK is used to clock the internal serial interface and
may be asynchronous to the other clocks. There is no
need to derive this clock from the same source as the
other clocks. The serial bus may be operated at any
speed up to 4.096 Mbits/s. DCLK can be gapped.
There is no limit on the number of devices on the same
serial bus.
The Control Interface
The device is controlled via a series of memory locations accessed by a serial data connection to the external master controller. This interface operates using the
chip select lead to enable transmission of information.
All chip functions are enabled or disabled by setting or
clearing bits in the control memory. Filter coefficients
and gain adjustments are also stored in this memory.
The codec has both a serial input lead and a serial output lead. These may be used individually for a 4-wire
serial interface, or tied together for a 2-wire interface.
The line driver circuitry is capable of driving relatively
high currents so that in the event that the line is long
enough to show significant transmission line effects, it
can be terminated in the characteristic impedance at
each end with resistors to V CC and ground.
All data transfers on the serial bus are byte oriented
with the least significant bit (shown in this data sheet as
bit 0) transmitted first, followed by the more significant
bits. For data fields, the least significant byte of the first
data byte is transmitted first, followed by the more significant bytes, each byte transmitted LSB first. This format is compatible with the serial port on most
microcontrollers.
T8538B Quad Programmable Codec
Modes
There are two different modes of operation for the
serial interface: the normal mode and the byte-by-byte
mode. These two modes differ in the data clocking and
the manner in which CS is used to control the transfer.
Note that the CS lead is used to control the transfer of
serial data from master controller to slave codec and in
the reverse direction.
In normal mode (INTS pin open), the CS lead must go
low for the duration of the transfer. CS is latched by
DCLK on a positive-going clock edge. DI is latched by
DCLK on a negative-going clock edge. DCLK may be
continuous, but only needs to be present to clock data
when CS is low (gapped clock). When using gapped
clock, DCLK can remain high or low when CS is high.
The only error check performed by the codec is to verify that CS is low for an integral number of bytes.
Detection of an active chip select for other than an integral multiple of 8 bits results in the operation being terminated. The next active excursion of chip select will
be interpreted as a new command; hence, the serial
I/O interface can always be initialized by asserting CS
for a number of clock periods that is not an integral
multiple of 8. CS is captured using DCLK, so DCLK
must be transitioned to perform this initialization.
The byte-by-byte mode (INTS pin tied to ground) uses
CS to control each byte of the transfer. In this mode,
CS goes low for exactly 8 bits at a time, corresponding
to a 1-byte transfer either to or from the codec chip.
DCLK can be continuous or gapped. When using a
gapped clock, DCLK can remain high or low when CS
is high. CS and DI are latched by DCLK on a positivegoing clock edge. Repeated transitions of CS are used
to control subsequent bytes of data to/from the codec.
For a write command in this mode, CS must go low for
each byte of the transfer until the transfer is complete.
For a read command, CS will go low for each of the
3 bytes of the read command transferred to the device,
then low again for each byte to be read. Notice that the
total number of bytes transferred (and excursions on
CS) is N + 3, where N is the number of bytes to be read
in the command. This mode of operation is useful in
cases where the master is a microprocessor with a
built-in UART that transfers 1 byte at a time. Error
detection is limited to detection of an active CS for
other than an integral multiple of 8 bits. Recovery is the
same as normal mode.
Flow control can be accomplished by suspending the
transitions on DCLK by holding either state. During the
data transfer, CS must remain low while clock transitions are suspended with DCLK in either state.
Agere Systems Inc.
9
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Protocol
The format of the command protocol is shown in Figures 4 and 5.
The control interface operates with one external master
controller and multiple slave codec devices. Each
transfer is initiated by the master, and the slave
responds for either read operations or the fast scan
mode. The slave does not check the bus for activity
prior to transmitting; it only checks for an active CS.
The master should allow for a wait between the end of
a read command until CS becomes active for the read
data. The master must refrain from sending additional
commands to the slave chip until the response is
received. On a 4-wire bus, commands to other devices
may be initiated before the response is received, but
care in generating the CS function is needed to ensure
that the multiple responses do not interfere. It should
be noted that multiple memory locations can be
accessed in the same command by setting the data
10
Preliminary Data Sheet
August 2001
field length field to the desired number of bytes to be
transferred. If flow control is desired, it must be performed by using separate commands, each transferring smaller blocks of information, or by controlling the
serial clock (gapping the serial clock), or with CS in the
case of byte-by-byte mode.
There is no response from the slave to the master for a
write operation. The response to a read operation simply includes the data to be read in the data field. Commands from the master controller include data for write
operations, but not for read operations.
All data is transmitted in a byte-oriented fashion with
the least significant bit of each byte transferred first.
Multibyte fields are transferred least significant byte
first in both directions. The data field will contain the
first addressed data location first, with subsequent data
locations transmitted in ascending order.
Since the coefficients and gains are stored in volatile
memory, all the coefficients and gains must be loaded
after powerup. There is, however, no need to reload
them when switching from active to standby modes, or
vice versa.
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Protocol (continued)
LSB
MSB LSB
COMMAND (8 bits)
MSB LSB
START ADDRESS (8 bits)
MSB LSB
DATA FIELD LENGTH (8 bits)
DATA FIELD (VARIABLE LENGTH) WRITE OPERATIONS ONLY
TIME
7
6
5
4
3
2
1
MSB
0
LSB
START ADDRESS:
7
6
5
4
3
2
1
MSB
0
LSB
DATA FIELD LENGTH:
7
6
5
4
3
2
1
MSB
COMMAND:
CKT SELECT:
CKT a:
CKT b:
CKT c:
CKT d:
00
01
10
11
0*
0
LSB
0*
CKT
SELECT
0
0
COMMAND
COMMANDS: FAST SCAN MODE:
WRITE MEMORY:
WRITE ALL CHANNELS:
READ MEMORY:
10
01
11
00
* Location of memory bank selection. All user controls are in memory bank 0; other memory banks contain internal state information for the
device.
Note: Data field length is in bytes for all operations. All data is transmitted in bytes with the LSB for each byte transmitted first. For 16-bit memory operations, the least significant byte of the first memory location is transmitted first, followed by the most significant byte; each byte is
transmitted LSB first. Additional memory locations are loaded in ascending sequence.
Figure 4. Command Frame Format, Master to Slave, Read or Write Commands
LSB
DATA FIELD (VARIABLE LENGTH) READ OPERATIONS ONLY
Note: All data is transmitted in bytes with the LSB for each byte transmitted first. For memory operations, the least significant byte of the first
memory location is transmitted first, followed by the most significant byte, each byte transmitted LSB first. Additional memory locations
are loaded in ascending sequence.
Figure 5. Command Frame Format, Slave to Master, Read Commands
Agere Systems Inc.
11
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Write Command
A write command is used to write to the memory addresses. Figures 6—9 illustrate normal or byte-by-byte operation with continuous or gapped DCLKs. For gapped DCLK operation, transitions, not frequency, are critical (as long
as the transitions do not exceed the maximum DCLK frequencies).
COMMAND FRAME
COMMAND
CS
0
DCLK
1
0
DI
START ADDRESS
7
1
0
1
0
7
7
1
0
7
DATA
LENGTH
1
0
7
1
0
7
1
0
*
7
1
7
0078B
* Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 6. Write Operation, Normal Mode (Continuous DCLK)
COMMAND FRAME
COMMAND
CS
0
DCLK
1
0
DI
START ADDRESS
7
1
0
7
1
0
7
1
0
7
1
0
DATA
LENGTH
7
1
0
7
1
0
*
7
1
7
0078C
* Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 7. Write Operation, Normal Mode (Gapped DCLK)
12
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Write Command (continued)
COMMAND FRAME
COMMAND
CS
0
DCLK
1
0
DI
*
START ADDRESS
7
1
0
1
0
7
LENGTH
*
7
1
0
7
0
1
1
DATA
*
7
0
7
†
1
0
7
1
7
0072C
* Shows customary usage, CS not required to go high between bytes.
† Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 8. Write Operation, Byte-by-Byte Mode (Gapped DCLK)
COMMAND FRAME
COMMAND
CS
0
DCLK
DI
0
*
1
1
START ADDRESS
7
7
0
0
1
1
LENGTH
*
7
7
0
0
1
1
DATA
*
7
7
0
0
†
1
1
7
7
0074B
* Shows customary usage, CS not required to go high between bytes.
† Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 9. Write Operation, Byte-by-Byte Mode (Continuous DCLK)
Agere Systems Inc.
13
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Read Command
The normal flow of information to the master controller is always in response to a read command. All control memory locations are accessed in 8-bit bytes. All read commands from the master controller require a response from
the addressed codec. It is the responsibility of the master controller to ensure that only one device is transmitting
on the serial interface line at any one time. The master controller must also ensure that the CS lead goes high after
transferring the 3-byte sequence used to initiate the read, and then it goes low again for the response. In this case,
it should be noted that the device expects that the second time CS goes low, the data is to be sent to the master;
thus, it does not interpret the DI lead as containing a valid instruction during that CS excursion. Note that the CS
lead must allow the number of bytes sent in a read command to be transferred before a subsequent command can
be received by the codec. Figures 10—13 illustrate normal or byte-by-byte operation with continuous or gapped
DCLKs. Like a write command, transitions, not frequency, are critical with regard to gapped DCLK operation.
COMMAND FRAME
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
DI
0
1
0
START ADDRESS
7
1
0
7
1
0
7
1
0
7
DATA
LENGTH
1
0
DO
7
1
0
1
†
7
7
0
1
7
0079B
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 10. Read Operation, Normal Mode (Continuous DCLK)
14
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Read Command (continued)
COMMAND FRAME
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
0
DI
1
0
START ADDRESS
7
1
0
7
1
0
7
1
0
7
DATA
LENGTH
1
0
7
1
0
1
†
7
7
DO
0
1
7
0079C
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns before the next command frame.
Figure 11. Read Operation, Normal Mode (Gapped DCLK)
COMMAND FRAME
COMMAND
CS
START
ADDRESS
*
LENGTH
*
DATA
‡
WAIT ≥ 1.5 µs
†
0
DCLK
DI
0
1
1
7
7
0
0
1
1
7
7
0
0
D0
1
1
7
0
1
7
7
0
1
7
0073C
* Shows customary usage, CS not required to go high between bytes.
† Provides sufficient wait time to access read data.
‡ Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 12. Read Operation, Byte-by-Byte Mode (Gapped DCLK)
Agere Systems Inc.
15
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Read Command (continued)
COMMAND FRAME
CS
COMMAND
START
ADDRESS
*
LENGTH
*
DATA
‡
WAIT ≥ 1.5 µs
†
DCLK
DI
0
0
1
1
7
7
0
0
1
1
7
7
0
0
D0
1
1
7
0
1
7
7
0
1
7
0075B
* Shows customary usage, CS not required to go high between bytes.
† Provides sufficient wait time to access read data.
‡ Allow a minimum of 244 ns before the next command frame.
Note: Data field length of 1 shown.
Figure 13. Read Operation, Byte-by-Byte Mode (Continuous DCLK)
16
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Fast Scan Mode
The fast scan mode allows a single byte command to read two SLIC control leads for all four channels with a
1-byte reply. This mode significantly speeds up the normal scanning for off-hook, ring trip, and ring ground detection. This special command sequence allows the controlling microprocessor to fast scan 2 bits in the SLIC control
byte of each of the four channels. The command code is (00000010)2, there are no start address or length fields.
The command returns only a single byte of data, formatted as shown in Table 9.
Table 5. Bit Assignments for Fast Scan Mode
Bit
0 (LSB)
1
2
3
4
5
6
7 (MSB)
Reported Status
Channel 0, bit 0 (ckt a, address 160, bit 0)
Channel 0, bit 1 (ckt a, address 160, bit 1)
Channel 1, bit 0 (ckt b, address 160, bit 0)
Channel 1, bit 1 (ckt b, address 160, bit 1)
Channel 2, bit 0 (ckt c, address 160, bit 0)
Channel 2, bit 1 (ckt c, address 160, bit 1)
Channel 3, bit 0 (ckt d, address 160, bit 0)
Channel 3, bit 1 (ckt d, address 160, bit 1)
The circuit select in the command structure (Figure 4) is not used for this special single-byte command. The rules
for toggling chip select apply as for the read command. Figures 14—17 illustrate normal or byte-by-byte operation
with continuous or gapped DCLKs.
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
0
1
2
3
4
DATA
5
6
7
0
1
2
3
†
4
5
6
7
DI
0
DO
1
2
3
4
5
6
7
0125B
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns between bytes.
Figure 14. Fast Scan, Normal Mode (Continuous DCLK)
Agere Systems Inc.
17
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Fast Scan Mode (continued)
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
0
1
2
3
DATA
4
5
6
7
0
1
2
3
†
4
5
6
7
DI
0
DO
1
2
3
4
5
6
7
0125C
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns between bytes.
Figure 15. Fast Scan, Normal Mode (Gapped DCLK)
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
0
1
2
3
4
DATA
5
6
7
0
1
2
3
†
4
5
6
7
DI
DO
0
1
2
3
4
5
6
7
0126D
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns between bytes.
Figure 16. Fast Scan, Byte-by-Byte Mode (Gapped DCLK)
18
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
The Control Interface (continued)
Fast Scan Mode (continued)
WAIT ≥ 1.5 µs*
COMMAND
CS
DCLK
0
1
2
3
4
DATA*
5
6
7
0
1
2
3
†
4
5
6
7
DI
0
DO
1
2
3
4
5
6
7
0124C
* Provides sufficient wait time to access read data.
† Allow a minimum of 244 ns between bytes.
Figure 17. Fast Scan, Byte-by-Byte Mode (Continuous DCLK)
Write All Channels
The write all channels command causes all four channels to be loaded with the same coefficients with a single data
transfer from the master controller. This allows for a faster initialization of the device after a powerup. This command should be used with caution since it affects all four channels. The normal memory write and read commands
affect only one channel.
Reset Functionality
FS
RUNS CONTINUOUSLY
BCLK
RUNS CONTINUOUSLY
DEVICE CAN NOW BE PROGRAMMED
RST
≥ 1 ms
WAIT ≥ 5 ms
0071Amod
Figure 18. Hardware Reset Procedure
Agere Systems Inc.
19
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
Standby Mode
Reset Functionality (continued)
The device enters a low-power standby mode with
powerup or software reset, or by programming the
CHACTIVE register 129, bit 0. In standby mode, the
control interface is active, capable of writing or reading
registers. SLIC read and write data latches are also
active. Analog signals at VFXI and PCM signals at DR
are ignored in this mode. BCLK must be present for
proper standby mode operation.
The reset function allows the internal logic of the
device to be set to a known initial condition, either
externally by activating the reset lead, or on a perchannel basis through the microprocessor interface by
setting and then clearing bits, if required, in address
RESCTRL (address 128). These two reset functions
have different effects, and each of the software reset
functions is a subset of the hardware reset functionality. The primary difference is in the treatment of the
internal memory. The hardware reset is assumed to be
a result of a catastrophic hardware event, such as a
loss of power or an initial powerup. Accordingly, the
assumption is made that the internal memory does not
contain valid data and default values for all memory
locations are loaded. A software reset, however, can
only be initiated if the device is operational (at least the
microprocessor interface), so the contents of the memory may indeed be valid; thus, the resets may be more
specific. Additionally, software resets only affect the
selected channel.
A 0.1 µF capacitor between the RST lead and ground
will effectively hold the lead low long enough to reset
the device on powerup, allowing for a cost-effective
power-on reset function. Notice that the memory must
be reloaded through the serial interface after a hardware reset function. For proper operation, it is necessary for FS and BCLK to be present and stable during
a reset. A wait period for the internal PLL to stabilize is
required after reset goes high. See the timing diagram
shown in Figure 18 for the proper hardware or poweron reset procedure.
For a software reset, the control memory should not be
accessed for a minimum of 256 µs following the reset.
Memory Control Mapping
Several memory locations are used to control the
device. The software interface tables (Table 16 and
Table 17) show the memory assignments that are useful in call processing and system testing. It should be
noted that other memory locations are used by the
device to hold intermediate results and other device
state information. Writing to these other locations can
cause serious disruptions in the operation of the device
and should be avoided.
20
Test Capabilities
The device has several built-in test capabilities that can
be used to verify correct operation of the signal processing of the line card. These test functions are
accessed in several different control addresses. Five
loopback modes are employed: the first for the digital
signal from the PCM bus to be looped back to the PCM
bus. This loopback facility can be used to verify correct
operation of the PCM bus interface logic, as well as
operation of the PCM bus. The second digital loopback
function allows complete testing of the digital processing capability of the codec by looping the data back at
the analog/digital conversion interface. The third loopback function can be used to check the operation of all
the signal processing performed in the device, including the conversions to/from analog. These digital loopback functions can be used with tone generation and
reception via the PCM bus.
The first analog loopback facility is at the digital side of
the delta-sigma converters and loops analog transmit
data back to the analog receive path. The second analog loopback is at the PCM bus interface and loops the
transmit data from the line back to the receive path.
By assigning the transmit and receive time slots identically, a loopback arrangement at the PCM bus can be
effectively programmed for signals generated on the
line side of the codec. This mode is useful for testing
from the line side through the entire device.
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Functional Description (continued)
Suggested Initialization Procedures
SLIC Control Capabilities
It is suggested that upon powerup, a hardware reset be
used to set the device into a known state. The serial
interface should then be used to load the memory
addresses that differ from the default values (the write
all channels command is convenient for this function).
If other devices are controlled by the SLIC data memory location, then it also should be loaded with a known
configuration. After the completion of this sequence,
the device is ready to be activated. Depending on the
application, the next step may either be normal operation or a set of test sequences. After the initialization of
the memory, the device and associated line card
devices can be controlled by using memory locations
130, 131, 145, 155, 156, 157, 158, 159, and 129; that
is, by supplying the PCM bus time-slot addresses,
switching the SLIC into the proper mode, and activating
the codec. Within memory location 129, the codec
would normally be placed into active mode with both
directions of the PCM bus enabled at the start of a call.
At the completion of a call, the codec should be placed
into standby mode and the PCM bus disabled. Great
caution should be used when changing the memory
while the codec is in active mode since termination
impedances, balance impedances, and gains may
change. These changes are likely to yield undesirable
system effects. It is safe to refresh coefficients that are
known to be unchanging in the application. It is always
possible to read the memory to verify its contents without deleterious effects on codec operation. Normal
operation would load the memory and perform all gain
adjustments while the codec is in standby mode. Under
no circumstances should memory above address 162
be written, since this section of memory is used for
state data and intermediate results. Also, all reserved
addresses should not be written. Changing this information may have deleterious effects on system operation.
Memory locations 158, 159, and 160 are used to control five or six bidirectional latches that allow the serial
interface to control other devices, such as ringing/test
switches, telecom electromechanical relays, and SLIC
devices. When the TTL latches are configured as outputs, external devices should be set up to sink current
from the latch. Location 158 sets the operational mode
of these latches as either inputs or outputs. Location
159 specifies what is to be written on the latch leads
driven by the device. Updates occur within one frame
(125 µs). Location 160 reports the actual state of these
leads. Latches are strobed every 125 µs (coincident
with frame strobe). It should be noted that a channel
control reset forces all of these external leads, except
those corresponding to bits 2 and 3, to the high-impedance state, so any inputs connected to bits 0, 1, 4, and
5 should have appropriate pull-up or pull-down resistors (off-chip, if required) to force the external device
into a known state at power-up or in the event of a
reset. Bits 2 and 3 will reset to outputs with a value of
zero.
The fast scan mode allows for a minimal data transfer
on the serial bus to monitor bits 0 and 1 of the SLIC
data memory location (159). If these 2 bits are wired as
inputs to the off-hook and/or ring ground detection circuits, a convenient method of rapidly scanning for
these two functions is obtained. Bits 2 and 3 default to
outputs; thus, they are convenient to provide control of
the SLIC state. In any event, all six leads are programmable for maximum flexibility.
Agere Systems Inc.
21
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Signal Processing
Figure 19 details the signal processing functional blocks of one channel of the codec.
0 dB TO 24 dB
IN 5 STEPS
FROM
SLIC
GTX1
LPF
*
∑-∆
A/D
SINC3
XAG
TEQ
*
GTX2
YLPF
LIN.TO
COMP
*
GAIN
TWEAKING
TO
PCM
BUS
*
GAIN
TRANSFER
*
*
CTZ
8 STEPS
RTZ
ANALOG
BAL*
SMF
RCF
1-bit
D/A
∑-∆
D/A
GAIN
TRANSFER
GAIN
TWEAKING
DIGITAL
0 dB
TO
SLIC
LPF*
SINC3
XLPF
*
FROM
PCM
BUS
GRX1
GRX2
4096 kHz
COMP
TO LIN.
*
32 kHz
8 kHz
SPEED
0497F
* Programmable blocks.
Figure 19. Internal Signal Processing
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operational section of the data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
Parameter
Storage Temperature Range
Power Supply Voltage (all leads designated power)
Negative Voltage on Any Lead with Respect to Ground
Thermal Resistance, Junction to Ambient:
64-Pin TQFP1
100-Pin TQFP1
Package Power Dissipation
SLIC Control Interface Latches, Current per Device
Symbol
Tstg
VDDX
VSS
Min
−55
—
−0.25
Max
150
VDDX + 0.5
—
Unit
°C
V
V
RΘJA
RΘJA
PD
IL
—
—
—
—
40
30
1
160
°C/W
°C/W
W
mA
1. Four layer, JEDEC test board.
22
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Operating Ranges
Parameter
Ambient Operating Temperature
Operating Junction Temperature
Power Supply Voltage (all leads designated power)
Symbol
TA
TJ
VDDX
Min
−40
−40
3.0
Max
85
125
3.6
Unit
°C
°C
V
Handling Precautions
Although protection circuitry has been designed into this device, proper precautions should be taken to avoid exposure to electrostatic discharge (ESD) during handling and mounting. Agere Systems Inc. employs a human-body
model (HBM) and a charged-device model (CDM) for ESD-susceptibility testing and protection design evaluation.
ESD voltage thresholds are dependent on the circuit parameters used to define the model. No industry-wide standard has been adopted for the CDM. A standard HBM (resistance = 1500 Ω, capacitance = 100 pF) is widely
accepted and can be used for comparison.
HBM ESD Threshold Voltage
Device
Voltage
T8538B
>2000
Agere Systems Inc.
23
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics
For all specifications: TA = −40 °C to +85 °C, VDD = 3.3 V ± 5%, unless otherwise noted. Typical values are for
TA = 25 °C and VDD = 3.3 V. Input signal frequency is 1004 Hz, BCLK = 16.384 MHz, DCLK = 4.096 MHz, and coefficients are at default values, unless otherwise noted.
dc Characteristics
Table 6. dc Characteristics
Parameter
Input Voltage Low
Input Voltage High
Input Current
Output Voltage Low:
All Outputs
SLIC Controls, Configured as Outputs
Output Voltage High
Output Current in High-impedance State
Line Driver (DX and DO leads) Output
Voltage High
Line Driver (DX and DO leads) Output
Voltage Low
24
Symbol
VIL
VIH
IIL
Test Conditions
All inputs
All inputs
Digital, without pull-up, inputs,
GND < VIN < VDD
With internal pull-up, VIN = GND
(INTS and RST leads)
With internal pull-up, VIN = VDD
(INTS and RST leads)
Min
—
2.0
−10
Typ Max Unit
—
0.8
V
—
—
V
—
10
µA
−240
—
10
µA
−10
—
10
µA
VOL
VOL
VOH
IOZ
VOH
IL = 3.2 mA
IL = 24 mA
IL = −320 µA
—
IL = −10 mA
—
—
VDD − 0.5
−30
VDD − 0.5
—
—
—
—
—
0.4
1.0
—
30
—
V
V
V
µA
V
VOL
IL = 10 mA
—
—
1.0
V
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Analog Interface
The following specifications pertain to the analog SLIC interface for each channel.
Table 7. Analog Interface
Parameter
Input Resistance
dc Input Voltage
Load Resistance at VFROP and VFRON
(differential)
Symbol
RVFXI
VVFXI
Test Conditions
0.25 < VIN < (VDDX − 0.25) V
Relative to ground.
Signal should be capacitively
coupled to VFXI.
RL
Min
100
1.4
Typ
—
1.5
Max
300
1.6
Unit
kΩ
V
7.5
—
—
kΩ
—
2
10
Ω
−100
0
100
mV
−20
0
20
mV
1.4
1.5
1.6
V
1.4
1.5
1.6
V
RL
RL
RL
RL
5-8881F
Output Resistance
RO
Output Offset Voltage Between VFROP
and VFRON
Output Offset Voltage Between VFROP
and VFRON, Standby Mode
Common-mode Output Voltage, Active
Mode
VOS
Common-mode Output Voltage, Standby
Mode
VOSS
VOCM
VOCMS
Digital input code corresponding to idle PCM code (µ-law).
Digital input code corresponding to idle PCM code (µ-law).
RL = 100 kΩ
Digital input code corresponding to alternating ± zero µ-law
PCM code.
—
Table 8. Power Dissipation
Power measurements are made at BCLK = 2.048 MHz, DCLK = 2.048 MHz, no inputs from serial interface, interface latches set as outputs, outputs unloaded.
Parameter
All Channels in Standby, Dissipation for One Channel
One Channel Active, Dissipation for Active Channel
Four Channels Active, Dissipation for One Channel
Agere Systems Inc.
Symbol
IDDS
IDD1
IDD1
Test Conditions
—
—
—
Min
—
—
—
Typ
10
100
50
Max
—
—
—
Unit
mW
mW
mW
25
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Gain and Dynamic Range
Table 9. Gain and Dynamic Range
Parameter
Absolute Levels
Absolute Levels
Absolute Maximum Voltage Swings
Transmit Gain Absolute
Accuracy
Transmit Gain Variation
with Programmed Gain
Transmit Gain Variation
with Frequency, 600 Ω
Resistive Source
Impedance and Synthesized Termination
Impedance
26
Symbol
GAL
GAL
GAL
GXA
GXAG
GXAF
Test Conditions
Maximum 0 dBm0 levels (1004 Hz):
VFXI (encoder milliwatt), all programmable transmit gains set to 0 dB.
RCV (decoder milliwatt), termination
impedance off, GRX1 = 0 dB,
GRX2 = −2.34 dB.
Minimum 0 dBm0 levels (1004 Hz):
VFXI (encoder milliwatt),
XAG = 24 dB, GTX1 = 6 dB,
GTX2 = 0 dB.
RCV (decoder milliwatt), termination
impedance off, GRX1 = 0 dB,
GRX2 = −6 dB
VFXI
VFROP to VFRON (differential)
Transmit gain programmed for maximum 0 dBm0 test level, measured deviation of digital code from ideal
0 dBm0 level at DX digital outputs, with
transmit gain set to 0 dB:
20 °C to 70 °C
0 °C to 85 °C
−40 °C to +85 °C
Measured transmit gain over the range
from maximum to minimum, calculated
deviation from the programmed gain relative to GXA at 0 dB, VDD = 5 V.
Relative to 1004 Hz, minimum
gain < GX < maximum gain,
VFXI = 0 dBm0 signal, path gain
set to 0 dB:
f = 16.67 Hz
f = 40 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
f = 300 Hz to 3000 Hz
f = 3140 Hz
f = 3380 Hz
f = 3860 Hz
f = 4600 Hz and above
Min
Typ
Max
Unit
—
2.80
—
Vp-p
—
3.8
—
Vp-p
—
87.5
—
mVp-p
—
—
—
2.63
—
—
—
2.9
5.0
Vp-p
Vp-p
Vp-p
—
−0.25
−0.30
±0.15
—
—
—
0.25
0.30
dB
dB
dB
−0.1
—
0.1
dB
—
—
—
—
−3.0
−0.125
−0.57
−0.735
—
—
−50
−40
−40
−55
−2.0
±0.04
0.01
−0.03
−8.8
—
−30
−26
−30
−30
0
0.135
0.125
0.015
−8.98
−32
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Gain and Dynamic Range (continued)
Table 9. Gain and Dynamic Range (continued)
Parameter
Transmit Gain Variation
with Signal Level
Receive Gain Absolute
Accuracy
Symbol
GXAL
GRA
Relative Gain, VFROP to
—
VFRON
—
Relative Phase, VFROP
to VFRON
Receive Gain Variation
GRAG
with Programmed Gain
Receive Gain Variation
with Frequency, 600 Ω
Resistive Termination
Receive Gain Variation
with Signal Level
GRAF
GRAL
Test Conditions
Sinusoidal test method*,
reference level = 0 dBm0:
VFXI = −40 dBm0 to +3 dBm0
VFXI = −50 dBm0 to −40 dBm0
VFXI = −55 dBm0 to −50 dBm0
Receive gain programmed to −6 dB,
apply 0 dBm0 signal to IPCM, measure VRCV, RL = 100 kΩ differential:
20 °C to 70 °C
0 °C to 85 °C
−40 °C to +85 °C
Digital input 0 dBm0 signal,
f = 300 Hz to 3400 Hz.
Digital input 0 dBm0 signal,
f = 300 Hz to 3400 Hz.
Measure receive gain over the range
from maximum to minimum setting,
calculated deviation from the programmed gain relative to GRA at
0 dB, VDD = 5 V.
Relative to 1004 Hz, digital input =
0 dBm0 code, minimum gain < GR <
maximum gain, 0 dB path gain:
f = below 3000 Hz
f = 3140 Hz
f = 3380 Hz
f = 3860 Hz
f = 4600 Hz and above
Sinusoidal test method*,
reference level = 0 dBm0:
IPCM digital level =
−40 dBm0 to +3 dBm0
IPCM digital level =
−50 dBm0 to −40 dBm0
IPCM digital level =
−55 dBm0 to −50 dBm0
Min
Typ
Max
Unit
−0.25
−0.50
−1.40
—
—
—
0.25
0.50
1.40
dB
dB
dB
—
−0.25
−0.30
±0.15
—
—
—
0.25
0.30
dB
dB
dB
−0.01
—
0.01
dB
−0.25
—
0.25
Degrees
−0.1
—
−0.1
dB
−0.125
−0.57
−0.735
—
—
±0.04
±0.04
−0.550
−10.7
—
0.125
0.125
0.015
−8.98
−28
dB
dB
dB
dB
dB
−0.25
—
0.25
dB
−0.50
—
0.50
dB
−1.40
—
1.40
dB
* Applied to all four channels.
Agere Systems Inc.
27
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Noise Characteristics
Table 10. Per-Channel Noise Characteristics
Parameter
Symbol
Transmit Noise,
NXC
C-Message Weighted
Transmit Noise,
NXP
P-Message Weighted
Receive Noise,
NRC
C-Message Weighted
Receive Noise,
NRP
P-Message Weighted
Noise, Single Frequency
NRS
Power Supply Rejection,
Transmit
PSRX
Power Supply Rejection,
Receive
PSRR
Spurious Out-of-Band
Signals at the Channel Outputs
SOS
Test Conditions
0 dB transmit gain*
Min
—
Typ
—
Max
18
Unit
dBrnC0
0 dB transmit gain*
—
—
−68
dBm0p
0 dB receive gain, digital pattern
corresponding to idle PCM code, µ-law*.
0 dB receive gain, digital pattern
corresponding to idle PCM code, A-law*.
f = 0 kHz to 100 kHz, loop around
measurement, VVFxI = 0 Vrms.
VDD = 5.0 VDC + 100 mVrms:
f = 0 kHz to 4 kHz
f = 4 kHz to 50 kHz
C-message weighted
Measured on VFROP,
VDD = 5.0 VDC + 100 mVrms:
f = 0 kHz to 4 kHz
f = 4 kHz to 25 kHz
f = 25 kHz to 50 kHz
0 dBm0, 300 Hz to 3400 Hz signal applied
to VVFxI, transmit gain set to 0 dB:
4600 Hz to 7600 Hz
7600 Hz to 8400 Hz
8.4 kHz to 50 kHz
—
—
13
dBrnC0
—
—
−75
dBm0p
—
—
−53
dBm0
36
30
—
—
—
—
dBC
dBC
36
40
36
—
—
—
—
—
—
dBC
dBC
dBC
—
—
—
—
—
—
−30
−40
−30
dB
dB
dB
* RVFxI = 25 MΩ.
28
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Distortion and Group Delay
Table 11. Distortion and Group Delay
Parameter
Signal to Total Distortion,
Transmit or Receive
Symbol
STDX
STDR
Single Frequency Distortion,
Transmit
SFDX
Single Frequency Distortion,
Receive
SFDR
Intermodulation Distortion
IMD
TX Group Delay, Absolute*
DXA
RX Group Delay, Absolute*
DRA
Test Conditions
Sinusoidal test method level:
µ-law −30 dBm0 to +3 dBm0
A-law −30 dBm0 to +3 dBm0
µ-law −40 dBm0 to −30 dBm0
A-law −40 dBm0 to −30 dBm0
µ-law −45 dBm0 to −40 dBm0
A-law −45 dBm0 to −40 dBm0
0 dBm0 single frequency input,
200 Hz < fIN < 3400 Hz; measured
at any other single frequency.
0 dBm0 single frequency input,
200 Hz < fIN < 3400 Hz; measured
at any other single frequency.
Transmit or receive, two
frequencies in the range of
300 Hz to 3400 Hz.
f = 1600 Hz, 600 Ω
resistive termination.
f = 1600 Hz, 600 Ω
resistive termination
Min
Typ
Max
Unit
36
35
31
30
27
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
−46
dB
dB
dB
dB
dB
dB
dB
—
—
−46
dB
—
−55
−49
dB
—
—
475
µs
—
—
235
µs
* Absolute group delay is a function of time-slot assignment, and the maximum in this table refers to the optimal (minimum group delay) timeslot assignment.
Agere Systems Inc.
29
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Electrical Characteristics (continued)
Crosstalk
Table 12. Crosstalk
Parameter
Transmit to Transmit Crosstalk,
0 dBm0 Level
Transmit to Receive Crosstalk,
0 dBm0 Level
Symbol
CTX-X
Receive to Transmit Crosstalk,
0 dBm0 Level
CTR-X
Receive to Receive Crosstalk,
0 dBm0 Level
CTR-R
30
CTX-R
Test Conditions
f = 300 Hz to 3400 Hz,
any channel to any channel
f = 300 Hz to 3400 Hz,
any channel to any other channel
In-channel
f = 300 Hz to 3400 Hz,
any channel to any other channel
In-channel
f = 300 Hz to 3400 Hz,
any channel to any channel
Min
—
Typ
−100
Max
−80
Unit
dB
—
—
−100
−70
−80
−50
dB
dB
—
—
—
−100
−60
−100
−80
−50
−80
dB
dB
dB
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics
Control Interface Timing
Serial Control Port Timing
Table 13. Serial Control Port Timing (See Figures 20 and 21.)
Symbol
fDCLK
—
tCSSETUP
tCSHOLD
tSXDLY
tSDHOLD
tSDSETUP
tSDZ
tRISE
tFALL
tRISE,
tFALL
tCSBHOLD
tSXBDLY
tCSBSETUP
tSDBHOLD
tSDBSETUP
Parameter
Clock Frequency (all commands)
Clock Duty Cycle
Chip Select Setup Time, Normal Mode
Chip Select Hold Time, Normal Mode
Output Data Delay, Normal Mode
Input Data Hold Time, Normal Mode
Input Data Setup Time, Normal Mode
Output Data, High Impedance
Clock Edge Rise Time
Clock Edge Fall Time
Line Driver Rise/Fall Time (DO output)
Chip Select Hold Time, Byte-by-Byte Mode
Output Data Delay, Byte-by-Byte Mode
Chip Select Setup Time, Byte-by-Byte Mode
Data Hold Time, Byte-by-Byte Mode
Data Setup Time, Byte-by-Byte Mode
Test Conditions
—
—
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
IL = 15 mA,
CLOAD = 100 pF
DCLK = 4.096 MHz
DCLK = 4.096 MHz*
DCLK = 4.096 MHz
DCLK = 4.096 MHz
DCLK = 4.096 MHz
Min
—
40
7
4
—
4
7
100
—
—
—
Typ
—
50
—
—
—
—
—
—
—
—
—
Max
4096
60
—
—
9
—
—
—
12
12
30
Unit
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
—
7
4
7
—
—
—
—
—
—
9
—
—
—
ns
ns
ns
ns
ns
* The tSXBDLY delay is from either DCLK or CS, whichever transition is later, for the first bit of the byte.
Agere Systems Inc.
31
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics (continued)
Control Interface Timing (continued)
Normal Mode
tCSHOLD
CS
tCSSETUP
0
DCLK
1
2
3
4
5
6
7
tSDZ
LSB
0
DO
1
2
tSXDLY
3
4
5
6
7
3
4
5
6
7
tSDHOLD
0
DI
1
2
tSDSETUP
5-7185.f(F)
Figure 20. Serial Interface Timing, Normal Mode (One Byte Transfer and Continuous DCLK Shown)
Byte-by-Byte Mode
CS
tCSBHOLD
tCSBSETUP
DCLK
0
1
2
3
tSDBSETUP
0
DO
4
5
6
7
tSXBDLY
1
2
3
4
5
6
7
tSDBHOLD
LSB
DI
MSB
0
1
2
3
4
5
6
7
tSDBSETUP
5-7186e (F)
Figure 21. Byte-by-Byte Mode Timing (Gapped DCLK Shown)
32
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics (continued)
receive data (DR) beginning on the rising edge of
BCLK and being latched on the falling edge of BCLK.
Figure 20 shows DX and DR beginning and FS being
latched on the rising edge of BCLK and DX and DR
being latched on the falling edge of BCLK.
PCM Interface Timing
Single-Clocking Mode
Frame sync (FS) signifies the start of frame on the
PCM bus for all four channels. FS occurs every
125 µs at an 8 kHz rate. FS must be synchronous
with the PCM bus clock (BCLK) and must be high for a
minimum of one BCLK period. The PCM interface operates using fixed data rate timing, data timing for both
transmit and receive are controlled by BCLK. BCLK
can be any value from 512 kHz (eight time slots) to
16.384 MHz (256 time slots) as defined by Table 14.
The PCM bus transfers the most significant bit of the
time slot first, consistent with normal telephony practices. Figure 19 shows FS, transmit data (DX), and
Figure 19 portrays a bit offset of zero, and Figure 20
portrays a transmit bit offset of one and a receive bit
offset of two. Bit offset skews the PCM transmit and/or
receive data independently from the FS reference. Up
to seven BCLK cycles of bit offset can be employed on
a per-channel basis. This flexibility can accommodate
special timing requirements.
Linear coding is transmitted and received in two consecutive 8-bit time slots. TSX0 or TSX1 is active (low)
when DX data is transmitting (8 bits for companded
code, 16 bits for linear code).
Table 14. PCM Interface Timing: Single-Clocking Mode (See Figures 22 and 23.)
Symbol
Parameter
Allowable BCLK Frequencies
fBCLK
—
Jitter of BCLK
—
BCLK Duty Cycle
Frame Strobe Setup Time
Frame Strobe Hold Time
Frame Strobe Width
tFSSETUP
tFSHOLD
tFSWIDTH
tXDLY
tIDHOLD
tIDSETUP
tRISE
tFALL
tRISE,
tFALL
tDXHIGHZ
tTSXDELAY
tTSXHIGHZ
Test Conditions
—
—
—
—
—
—
—
—
—
—
BCLK = 16.384 MHz
BCLK = 16.384 MHz
FS synchronous with
BCLK
Output Data Delay
BCLK = 16.384 MHz
Input Data Hold Time
BCLK = 16.384 MHz
Input Data Setup Time
BCLK = 16.384 MHz
Clock Edge Rise Time
BCLK = 16.384 MHz
Clock Edge Fall Time
BCLK = 16.384 MHz
DX Output Rise/Fall Time
IL = 15 mA,
CLOAD = 100 pF
DX Output Data Float on TS Exit
CLOAD = 0
Line Driver Enable Delay
—
Line Driver Enable Float on TS Exit
—
Agere Systems Inc.
Min
—
—
—
—
—
—
—
—
—
Typ
512
1024
1536
2048
3072
4096
8192
16384
—
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
—
tBCLK
50
—
—
—
Max
—
—
—
—
—
—
—
—
100 ns in
100 ms =
1 ppm
60
—
—
125 µs − tBCLK
40
7
4
—
4
7
—
—
—
—
—
—
—
—
—
9
—
—
8
8
30
ns
ns
ns
ns
ns
ns
—
—
—
—
—
—
5
5
5
ns
ns
ns
%
ns
ns
—
33
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing (continued)
Single-Clocking Mode (continued)
TIME SLOT 0
tFSWIDTH
FS
tFSSETUP
tFSHOLD
1
BCLK
2
3
4
5
6
7
8
9
tDXHIGHZ
1
DX0/1
2
3
tXDLY
4
5
6
7
8
tIDHOLD
tTSXHIGHZ
tTSXDELAY
TSX0/1
SIGN BIT
LSB
1
DR0/1
2
3
4
5
6
7
8
tIDSETUP
5-7188d F
Figure 22. Single-Clocking Mode (TXBITOFF = 0, RXBITOFF = 0, PCMCTRL2 = 0x00)
FS
BCLK
DX0/1
1
2
3
1
4
5
6
7
8
9
2
3
4
5
6
7
8
1
2
3
4
5
6
7
TSX0/1
DR0/1
8
5-7185.g F
Figure 23. Single-Clocking Mode (TXBITOFF = 1, RXBITOFF = 2, PCMCTRL2 = 0x01)
34
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing (continued)
Double-Clocking Mode
As with the single-clocking mode, FS signifies the start
of frame on the PCM bus for all four channels and
occurs every 125 µs at an 8 kHz rate. FS must be
synchronous with BCLK and must be high for a minimum of one BCLK period. The PCM interface operates
using fixed data rate timing; data timing for both transmit and receive are controlled by BCLK. In doubleclocking mode, however, BCLK runs at twice the PCM
data rate. BCLK can be any value from 512 kHz (data
rate of 256 kbits/s, 4 time slots) to 16.384 MHz (data
rate of 8192 kbits/s, 128 time slots) as defined by Table
15.
In Figure 21, detail A, the falling edge of the first BCLK
latches FS. The falling edge of the second BCLK
latches DR (receive bit offset of 1). DX starts on the rising edge of the first BCLK. The PCM bus transfers the
most significant bit of the data first.
The codec defaults to FS and DR being latched on the
first BCLK cycle. To latch DR on the second BCLK
cycle, program receive bit offset for 1 (RXBITOFF =
0x20). For every bit programmed (0 to 7), bit offset
shifts transmit or receive data by one BCLK cycle.
Therefore, in double-clock mode, the time-slot assignment and bit offset registers need to be used in tandem
in order to achieve a full range of bit offset values. For
instance, in time-slot 0, bit offset will shift data up to
four bits. To shift data 5 to 8 bits, time-slot 1 needs to
be selected.
Linear coding is not allowed in double-clocking mode.
TSX0 or TSX1 (not shown in Figure 21) is active (low)
when DX data is transmitting.
Note that the device reverts back to single-clock mode
if reset (address 128, bit 0). Internal states of the codec
can be reset without going out of double-clock mode
(address 128, bit 1).
Table 15. PCM Interface Timing: Double-Clocking Mode (See Figure 24.)
Symbol
fBCLK
—
tBCL
tR, tF
tWL, tWH
tR, tF
tWFH
tWFL
tSF
tHF
tDDC
tDDF
tSD
tHD
Parameter
Allowable BCLK Frequencies
Jitter of BCLK
Signal
—
—
—
—
—
—
—
—
—
Min
—
—
—
—
—
—
—
—
—
Typ
512
1024
1536
2048
3072
4096
8192
16384
—
Clock Period
Clock Rise/Fall
Pulse Width
Frame Rise/Fall
Frame Width High
Frame Width Low
Frame Setup
Frame Hold
Data Delay Clock
Data Delay Frame
Data Setup
Data Hold
BCLK
BCLK
BCLK
FS
FS
FS
FS
FS
DX
DX
DR
DR
61
—
tBCL x 0.4
—
tBCL
tBCL
7
4
—
—
7
4
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
100 ns in
100 ms =
1 ppm
1953
8
tBCL x 0.6
15
—
—
tBCL − 50
—
9
9
—
—
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: DX load = 150 pF.
Agere Systems Inc.
35
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Timing Characteristics (continued)
PCM Interface Timing (continued)
Double-Clocking Mode (continued)
BCLK
FS
DX/DR
bit 0
bit 1
bit 2
DETAIL A
tR
tF
BCLK
tWH
tBCL
tWL
FS
tSF
tHF
tWFH
tDDF
DX
tDDC
DR
DETAIL A
tSD
tHD
5-7173F
Figure 24. Double-Clocking Mode (RXBITOFF = 0x20, PCMCTRL2 = 0x00)
36
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Software Interface
With the exceptions noted, all of these memory locations may be read to determine the state of the controls contained therein. In the following table, bit 0 is the LSB (transmitted first on the serial interface) and bit 7 is the most
significant bit of the byte. Unused bits in an address or multibyte address should be loaded as zero. All of the memory locations can be programmed on a per-channel basis.
Note that the entire coefficient set for a channel (or all four channels) may be loaded with one command.
Table 16. Memory Mapping
Control
Name
Address
(Decimal)
HBALTAPS
RESCTRL
0—27
64—91
28—63
92—127
128
CHACTIVE
RXBITOFF
RXOFF
GRX1
GRX2
129
130
131
132—133
134—135
1
4
8
11
11
Reserved
136—139
CTZCTRL 140—143
Reserved
144
PCMCTRL2
145
SDCTRL
146
—
31
—
6
7
Reserved
# of
Bits
Used
448
Default
Value
—
Balance impedance tap coefficients.
—
—
These addresses have no function.
2
0x00
SDTSI
147
7
GTX2
148—149
12
ZEQTX
150—152
GTX1
153—154
TXBITOFF
155
TXOFF
156
PCMCTRL1
157
SLICTS
158
SLICWR
159
21
12
4 or 5
8
7
6
6
SLICRD
160
6
Reserved
VERIFY
161
162
—
8
Agere Systems Inc.
Description
Reset address. Writing a one in the used positions causes a
reset as defined by the bit definition. This reset remains in
force until the bit is written as a zero.
0x00
Standby/active control.
0x00
Bit offset for receive direction.
16 * channel # Time-slot assignment for receive direction.
0x0400
Gain transfer for receive direction.
0x01ac
Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, receive direction.
—
This address has no function.
07ed0000
CTZ bleed coefficients.
—
This address has no function.
0x00
PCM transmission and sampling edge control.
0x19
RTZ, transmit analog gain (XAG), and digital loopback 3
controls.
17 * channel # Internal time-slot interchanger and loopback controls.
Default sets external pins to state referenced in this data
sheet.
0x0400
Gain tweaking. Control of gain sensitive to impedance and
SLIC parameter choices, transmit direction.
0x000000
Transmit line equalization.
0x051a
Gain transfer for transmit direction.
0x00
Bit offset for transmit direction.
16 * channel # Time-slot assignment for transmit direction.
0x00
PCM, companding, and loopback controls.
0x0c
SLIC 3-state control. Latch I/O.
0x00
Data to be written to the SLIC latches if the corresponding
bit is set in the SLICTS control word.
—
Current actual state of the SLIC leads. This will be the same
as SLICWR for those leads configured as outputs. All other
positions will reflect the actual state of the external lead. A
write operation to this word will be ignored, and within one
PCM frame (125 µs), the data will be overwritten.
—
This address has no function.
0x00
Test address for serial interface verification.
37
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Software Interface (continued)
Table 17. Control Bit Definition
The following table shows the control bit assignments in the memory control addresses. In all control bit cases, the
bit being set places the function into the active mode as defined in the function column.
Control Name
(Address, Decimal)
[Address, Hex]
HBALTAPS
(0—27, 64—91)
[0x00—0x1b,
0x40—0x5b]
RESCTRL
(128)
[0x80]
Bit
Assignment(s)
Function
448
Balance impedance coefficients. Default value is 0x00 for all bytes
except for addresses 3 and 5, which are 0x80, and address 69, which is
0x88.
2—7
1
0
CHACTIVE
(129)
[0x81]
1—7
0
RXBITOFF
(130)
[0x82]
5—7
Not used, load as zeros.
A one resets all other internal states. Control addresses are not reset.
A one resets all control addresses to default values. Note that setting
this bit will result in it and all others of this word becoming cleared on the
next PCM frame as a normal part of the reset functionality. Alternatively,
hardware reset can be used to reset all control and state functions. It is
necessary to wait at least 256 µs after asserting this bit before initiating
any other serial I/O transactions.
Load as zeros.
Active/standby mode. A zero causes the channel to enter standby (lowpower) mode and disables the PCM interface for this channel. A one
activates the channel and the corresponding PCM bus interface. Default
is zero.
Receive direction bit offset for the FS signal. Defaults to zero. These
3 bits can be thought of as the least significant bits (RXOFF contains the
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.
Load as zeros.
Receive time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 BCLK bits, allow for two time slots when using linear mode or double-clock mode.
Gain adjustment for gain transfer stage in receive direction. Defaults to
0x0400 (0 dB). This is an 11-bit multiply operation with a maximum gain
of two (6 dB). 0 dB is the maximum recommended setting.
Gain adjustment for tweak gain stage in receive direction. Defaults to
0x01ac (−7.58 dB). This is an 11-bit multiply operation with a maximum
gain of two (6 dB). 0 dB is the maximum recommended setting.
Coefficients for the CTZ termination bleed. Defaults to 0x07ed0000.
RXOFF
(131)
[0x83]
GRX1
(132—133)
[0x84—0x85]
GRX2
(134—135)
[0x86—0x87]
CTZCTRL
(140—143)
[0x8c—0x8f]
38
0—4
0—7
0—10
0—10
0—30
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Software Interface (continued)
Table 17. Control Bit Definition (continued)
Function
Control Name
Bit
(Address, Decimal) Assignment(s)
[Address, Hex]
PCMCTRL2
6—7
Load as zeros.
(145)
5
A one selects DX PCM port 1. A zero selects DX PCM port 0. Defaults to
[0x91]
zero. PCM port 1 is not available in all package types.
4
A one selects DR PCM port 1. A zero selects DR PCM port 0. Defaults to
zero. PCM port 1 is not available in all package types.
3
A one selects double-clocking mode. Defaults to zero (single-clocking
mode). A write to any channel affects all four channels.
2
A one starts transmit data on a falling BCLK edge. A zero starts transmit
data on a rising BCLK edge. Defaults to zero. A write to any channel
affects all four channels.
1
A one latches receive data on a rising BCLK edge. A zero latches
receive data on a falling BCLK edge. Defaults to zero. A write to any
channel affects all four channels.
0
A one latches FS on a rising BCLK edge. A zero latches FS on a falling
BCLK edge. Defaults to zero. A write to any channel affects all four channels.
7
Load as zero.
SDCTRL
(146)
6
Enable digital loopback 3. Defaults to zero (no loopback).
[0x92]
3—5
RTZ gain. Defaults to 3 (equal level point value of 3 * 0.075 = 0.225).
Turn off by writing to zero.
0—2
Transmit analog gain (XAG). Defaults to 1
Bit Number Function
(6 dB) gain.
(dB)
2
1
0
0
0
0
0.0
0
0
1
6.02
0
1
0
12.04
0
1
1
18.06
1
0
0
24.08
SDTSI
7
Load as zero.
(147)
6
Digital loopback, receive to transmit at the sigma-delta converters (digi[0x93]
tal loopback 2). Defaults to zero (no loopback).
4—5
Digital channel feeding this analog receive channel. Defaults to channel
number.
3
Send idle-channel code (alternating bits) to this analog receive path.
Defaults to zero (off).
2
Loopback from transmit to receive at the sigma-delta converters (analog
loopback 1). Defaults to zero (no loopback).
0—1
Analog channel feeding this digital channel in the transmit direction.
Defaults to channel number.
GTX2
0—11
Gain control for gain transfer stage in transmit direction. Defaults to
(148—149)
0x0400 (0 dB). This is a 12-bit multiply operation with a maximum gain of
[0x94—0x95]
four (12 dB).
ZEQTX
0—20
Coefficients for the transmit equalization stage. Varies frequency
(150—152)
response and accommodates current-sensing SLICs. Defaults to
[0x96—0x98]
0x000000.
Agere Systems Inc.
39
T8538B Quad Programmable Codec
Preliminary Data Sheet
August 2001
Software Interface (continued)
Table 17. Control Bit Definition (continued)
Function
Control Name
Bit
(Address, Decimal) Assignment(s)
[Address, Hex]
0—11
Gain control for tweak gain stage in transmit direction. Defaults to 0x051a
GTX1
(2.11 dB). This is a 12-bit multiply operation with a maximum gain of four
(153—154)
[0x99—0x9a]
(12 dB).
TXBITOFF
5—7
Transmit direction bit offset for the FS signal. Defaults to zero. These
(155)
3 bits can be thought of as the least significant bits (TXOFF contains the
[0x9b]
more significant bits) of a bit counter that determines the location of the
first bit of the PCM data from FS.
0—4
Load as zeros.
TXOFF
0—7
Transmit time-slot assignment. Defaults to (16 * channel number). Each
time slot represents 8 BCLK bits; allow for two time slots when using lin(156)
ear mode or double-clock mode.
[0x9c]
PCMCTRL1
7
3-state transmit PCM interface. Defaults to zero. A one forces the PCM
interface into a high-impedance state during its assigned time-slot on the
(157)
PCM bus. Placing the channel in standby mode also forces a high[0x9d]
impedance condition on the transmit interface.
6
Transmit zeros instead of data. Defaults to zero (off).
5
Linear mode significant bit. A one sets MSB first for both PCM transmit
data output and for PCM receive data input. A zero sets both PCM paths
to LSB first. Defaults to zero, LSB first.
4
Place idle-channel code on receive path. Defaults to zero (off).
3
Loopback receive to transmit at PCM conversion interface (digital loopback 1). Defaults to zero (no loopback).
2
Loopback transmit to receive at PCM conversion interface (analog loopback 2). Defaults to zero (no loopback).
1
Linear/companded mode. A one sets 16-bit linear mode with two adjacent time slots used. Linear data is in two’s complement form. Linear
mode is only available when using single-clocking mode. A zero sets
companded mode with only one time slot used. Defaults to zero. Linear
mode is programmed as LSB or MSB first using bit 5 of this word.
0
µ-law or A-law. A one sets A-law mode, and a zero sets µ-law mode.
Defaults to zero (µ-law).
SLICTS
6—7
Load as zeros.
(158)
0—5
Controls the drivers for the corresponding SLIC latches. A one enables
[0x9e]
the lead as an output. Defaults to 0x0C (bits 2 and 3 set, the rest
cleared).
SLICWR
6—7
Load as zeros.
(159)
0—5
SLIC data latches. If the corresponding bit in the SLICTS address is set
[0x9f]
for an output, the device will drive the corresponding bit according to the
contents of this address. Writes are performed within 125 µs. Wait
125 µs before a subsequent write to the same channel or between write
all channel commands. Default is zero.
SLICRD
6—7
Not used, ignore on read.
(160)
0—5
Reports the actual state of the SLIC leads. Anything written to this
[0xa0]
address is ignored. Updates within 125 µs.
VERIFY
0—7
Test location for serial interface. This location has no internal use, but
(162)
merely latches write data for the purpose of testing the serial interface.
[0xa2]
This register does not clear with reset.
40
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Applications
The following reference circuit shows a complete schematic for interfacing to the Agere L9215G SLIC. All ac
parameters are programmed by the T8538B. Note that this implementation differentiates itself in that no external
components are required in the ac interface to provide a dc termination impedance or for stability. For illustration
purposes, 0.5 Vrms PPM injection was assumed in this example and no meter pulse rejection is used. Also, this
example illustrates the device using programmable overhead and current limit.
VBAT1
DBAT1
CRT
0.1 µF
RRT
383 kΩ
FUSIBLE OR PTC
50 Ω
VBAT1
VBAT2 VCC
CBAT1
CBAT2
CCC
0.1 µF
0.1 µF
0.1 µF
VBAT1
BGND
VBAT2 VCC
AGND
ICM
TRGDET
RTFLT
RGX
4750 Ω
VTX
DCOUT
CTX
0.1 µF
PR
TXI
CC1
0.1 µF
AGERE
L7591
50 Ω
ITR
ground key
not used
RVFxI*
20 MΩ
L9215G
FUSIBLE OR PTC
FROM
PROGRAMMABLE
D/A VOLTAGE
SOURCE
VFXI
VITR
PT
RCVP
VFROP
RCVN
VFRON
OVH
DX1
PCM
HIGHWAY
DR1
VPROG
T8538B
rate of battery
reversal not
ramped
VREF
CF1
DX0
DR0
CF2
FS
B2 B1 B0 RINGIN
FB1 FB2 NSTAT BR
B2
SLIC4a
B1
SLIC3a
B0
SLIC2a
BR
SLIC1a
NSTAT
PPM
0.5 Vrms
SLIC0a
PPMIN
0.22 µF
CF2
0.1 µF
RPD1 10 kΩ
CF1
CRING
0.47 µF
FROM/TO
CONTROL
CPPM
10 nF
BCLK
SYNC
AND
CLOCK
DGND
VDD
VDD
* RVFxI is required for complex terminations. It is optional for resistive terminations.
Figure 25. POTS Interface
Agere Systems Inc.
41
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Outline Diagrams
100-Pin TQFP
Dimensions shown are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics
to assist your design efforts, please contact your Agere Sales Representative.
16.00 ± 0.20
14.00 ± 0.20
PIN #1 IDENTIFIER ZONE
100
76
1
75
14.00
± 0.20
16.00
± 0.20
25
51
26
50
DETAIL A
DETAIL B
1.40 ± 0.05
1.60 MAX
SEATING PLANE
0.08
0.05/0.15
0.50 TYP
1.00 REF
0.106/0.200
0.25
GAGE PLANE
0.19/0.27
SEATING PLANE
0.08
DETAIL B
M
0.45/0.75
DETAIL A
5-2146F
42
Agere Systems Inc.
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Outline Diagrams (continued)
64-Pin TQFP
Dimensions shown are in millimeters.
Note: The dimensions in this outline diagram are intended for informational purposes only. For detailed schematics to assist your design efforts, please contact your Agere Sales Representative.
12.00 ± 0.20
1.00 REF
10.00 ± 0.20
PIN #1
IDENTIFIER ZONE
64
49
0.25
GAGE PLANE
SEATING PLANE
48
1
0.45/0.75
DETAIL A
10.00
± 0.20
12.00
± 0.20
16
33
0.106/0.200
17
32
0.19/0.27
DETAIL A
DETAIL B
1.40 ± 0.05
0.08
1.60 MAX
M
DETAIL B
SEATING PLANE
0.08
0.50 TYP
0.05/0.15
5-3080
Agere Systems Inc.
43
Preliminary Data Sheet
August 2001
T8538B Quad Programmable Codec
Ordering Information
Device Code
Package
Temperature
Comcode
T8538B - - 1TL-DB
100-Pin TQFP
Dry Pack Tray
64-Pin TQFP
Dry Pack Tray
−40 °C to +85 °C
109060368
−40 °C to +85 °C
109060376
T8538B - - - TL-DB
Telcordia Technologies is a trademark of Telcordia Technologies, Inc.
For additional information, contact your Agere Systems Account Manager or the following:
INTERNET:
http://www.agere.com
E-MAIL:
docmaster@agere.com
N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286
1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)
ASIA:
Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon
Tel. (852) 3129-2000, FAX (852) 3129-2020
CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen)
JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)
EUROPE:
Tel. (44) 7000 624624, FAX (44) 1344 488 045
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liab ility is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
August 2001
DS01-280ALC (Replaces DS01-205ALC)