Four Character 5.0 mm (0.20 inch) 5 x 7 Alphanumeric Displays Technical Data HDSP-2301 HDSP-2302 HDSP-2303 Features Applications • Integrated Shift Registers with Constant Current Drivers • Compact Ceramic Package • Wide Viewing Angle • End Stackable Four Character Package • TTL Compatible • 5 x 7 LED Matrix Displays Full ASCII Set • Categorized for Luminous Intensity • HDSP-2301/2303 Categorized for Color • • • • Avionics Business Machines Medical Instruments Portable Data Entry Devices Description The HDSP-2301/-2302/-2303 series of displays are 5.0 mm (0.20 inch) 5 x 7 LED arrays for display of alphanumeric information. These devices are available in yellow, high efficiency red, and high performance green. Each four character cluster is contained in a 12 pin dual-in-line package. An Devices Yellow High Efficiency Red Green HDSP-2301 HDSP-2302 HDSP-2303 on-board SIPO (Serial-In-ParallelOut) 7-bit shift register associated with each digit controls constant current LED row drivers. Full character display is achieved by external column strobing. 2 Package Dimensions 20.01 MAX. (0.790) 2.84 REF. (0.112) SEE NOTE 3 12 11 10 9 8 7 SEE NOTE 3 4.87 (0.192) REF. 1 2 1 2 3 3 PIN 1 MARKED BY DOT ON BACK OF PACKAGE 4 4 5 8.43 MAX. (0.335) 6 CL 5.00 ± 0.13 (0.197 ± 0.005) PIN 1 2 3 4 5 6 FUNCTION COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4 COLUMN 5 INT. CONNECT* PIN 7 8 9 10 11 12 FUNCTION DATA OUT VB VCC CLOCK GROUND DATA IN *DO NOT CONNECT OR USE NOTES: 1. DIMENSIONS IN MILLIMETERS (INCHES). 2. UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON ALL DIMENSIONS IS ± 0.38 mm (± 0.015"). 3. CHARACTERS ARE CENTERED WITH RESPECT TO LEADS WITHIN ± 0.13 mm (± 0.005"). 1.27 ± 0.13 (0.050 ± 0.005) 5.08 (0.200) 6.85 (0.270) 2.54 (0.100) 1.27 TYP. (0.050) 2.54 ± 0.13 (0.100 ± 0.005) TYP. NON ACCUM. 0.25 ± 0.05 TYP. (0.010 ± 0.002) 0.54 ± 0.08 (0.020 ± 0.003) 6.35 ± 0.25 (0.250 ± 0.010) Absolute Maximum Ratings (HDSP-2301/-2302/-2303) Supply Voltage, VCC to Ground ...................................... –0.5 V to 6.0 V Inputs, Data Out and VB .................................................. –0.5 V to VCC Column Input Voltage, VCOL ....................................... –0.5 V to +6.0 V Free Air Operating Temperature Range, TA[1,2] .......... –20˚C to +85˚C Storage Temperature Range, T S ................................ –55˚C to +100˚C Maximum Allowable Package Dissipation at T A = 25˚C[1,2,3] HDSP-2301/-2302/-2303 .................................................. 1.46 Watts Maximum Solder Temperature 1.59 mm (0.63”) Below Seating Plane t < 5 sec ................................................. 260˚C Recommended Operating Conditions (HDSP-2301/-2302/-2303) Parameter Symbol Supply Voltage VCC Data Out Current, Low State Data Out Current, High State Min. Nom. Max. Units Fig. 4.75 5.0 5.25 V IOL 1.6 mA IOH –0.5 mA 3.5 V 4 Column Input Voltage, Column On HDSP-2301/-2302/-2303 VCOL 2.75 Setup Time tsetup 70 45 ns 1 Hold Time thold 30 0 ns 1 tw(Clock) 75 ns 1 fclock 0 3 MHz 1 200 ns 1 85 ˚C 2 Width of Clock Clock Frequency Clock Transition Time Free Air Operating Temperature tTHL Range [1,2] TA –20 3 Electrical Characteristics over Operating Temperature Range (Unless otherwise specified) Yellow HDSP-2301/High Efficiency Red HDSP-2302/ High Performance Green HDSP-2303 Description Supply Current Symbol ICC Column Current at any Column Input ICOL Column Current at any Column Input ICOL VB, Clock or Data Input Threshold High VIH VB, Clock or Data Input Threshold Low VIL Input Current Logical 1 IIH IIH Input Current Logical 0 VB, Clock Data In VB, Clock Data In IIL IIL Test Conditions Min. Typ.* Max. Units 45 60 mA 73 95 mA 500 µA 520 mA VCC = 5.25 V VB = 0.4 V VCLOCK = V DATA = 2.4 V All SR Stages = VB = 2.4 V Logical 1 VCC = 5.25 V VCOL = 3.5 V All SR Stages = Logical 1 VB = 0.4 V VB = 2.4 V 380 2.0 Fig. 4 V VCC = VCOL = 4.75 V VCC = 5.25 V, VIH = 2.4 V VCC = 5.25 V, VIL = 0.4V 0.8 V 20 80 µA 10 –500 40 –800 µA µA –250 –400 µA VOH VCC = 4.75 V, IOH = –0.5 mA, ICOL = 0 mA VOL VCC = 4.75 V, IOL = 1.6 mA, ICOL = 0 mA 0.2 Power Dissipation Per Package** PD VCC = 5.0 V, VCOL = 3.5 V, 17.5% DF 15 LEDs on per character, VB = 2.4 V 0.78 W 2 Thermal Resistance IC Junction-to-Case RθJ–C 25 ˚C/W/ Device 2 Data Out Voltage 2.4 3.4 V 0.4 V *All typical values specified at V CC = 5.0 V and TA = 25˚C unless otherwise noted. **Power dissipation per package with four characters illuminated. Notes: 1. Operation above 85˚C ambient is possible provided the following conditions are met. The junction temperature should not exceed 125˚C TJ and the case temperature (as measured at pin 1 or the back of the display) should not exceed 100˚C TC . 2. The HDSP-2301/-2302/-2303 should be derated linearly above 37˚C at 16.7 mW/˚C. This derating is based on a device mounted in a socket having a thermal resistance from case to ambient at 35˚** C/W per device. See Figure 2 for power deratings based on a lower thermal resistance. 3. Maximum allowable dissipation is derived from V CC = 5.25 V, VB = 2.4 V, VCOL = 3.5 V 20 LEDs on per character, 20% DF. 4 Optical Characteristics Yellow HDSP-2301 Description Symbol Test Conditions Min. Typ.* Max. Units Fig. Peak Luminous Intensity per LED[4,8] (Character Average) IvPeak VCC = 5.0 V, VCOL = 3.5 V 650 1140 Ti = 25˚C, VB = 2.4 V µcd Peak Wavelength λPEAK 583 nm λd 585 nm Dominant Wavelength[5,7] 3 High Efficiency Red HDSP-2302 Description Symbol Test Conditions Min. Typ.* Max. Units Fig. Peak Luminous Intensity per LED[4,8] (Character Average) IvPeak VCC = 5.0 V, VCOL = 3.5 V 650 1430 Ti = 25˚C, VB = 2.4 V µcd Peak Wavelength λPEAK 635 nm λd 626 nm Dominant Wavelength 3 High Performance Green HDSP-2303 Description Symbol Test Conditions Min. Typ.* Max. Units Fig. Peak Luminous Intensity per LED[4,8] (Character Average) I vPeak VCC = 5.0 V, VCOL = 3.5 V 1280 2410 Ti = 25˚C, VB = 2.4 V µcd Peak Wavelength λPEAK 568 nm λd 574 nm Dominant Wavelength[5,7] *All typical values specified at V CC = 5.0 V and TA = 25˚C unless otherwise noted. **Power dissipation per package with four characters illuminated. Notes: 4. The characters are categorized for luminous intensity with the intensity category designated by a letter code on the bottom of the package. 5. The HDSP-2301/-2303 are categorized for color with the color category designated by a number code on the bottom of the package. 6. Ti refers to the initial case temperature of the device immediately prior to the light measurement. 7. Dominant wavelength λd, is derived from the CIE chromaticity diagram, and represents the single wavelength which defines the color of the device. 8. The luminous sterance of the LED may be calculated using the following relationships: Lv (cd/m2) = lv (Candela)/A (Metre)2 Lv (Footlamberts) = π i v (Candela)/A (Foot) 2 A = 5.3 x 10 –8 M2 = 5.8 x 10–7 (Foot) 2 3 5 1/fMAX. tW tTHL 2.4 V CLOCK 90 % 1.5 V 1.5 V 1.5 V 1.5 V 10 % 0.4 V tHOLD PARAMETER tSETUP 2.4 V DATA IN 1.5 V 1.5 V 1.5 V tPLH, tPHL PROPAGATION DELAY CLOCK TO DATA OUT 1.5 V 0.4 V tSETUP CONDITION MIN. TYP. MAX. UNITS fCLOCK CLOCK RATE tHOLD CL = 15 pF RL = 2.4 KΩ 3 MHz 125 ns 2.4 V DATA OUT 1.5 V 1.5 V 0.4 V tPLH tPHL Figure 1. Switching Characteristics HDSP-2301/-2302/-2303 (T A = –20˚C to +85˚C). 4.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 RθJA = 60°C/W RθJA = 50°C/W RθJA = 40°C/W 0.4 0.2 0 0 10 20 30 40 50 60 70 80 90 100 TA – AMBIENT TEMPERATURE – °C Figure 2. Maximum Allowable Power Dissipation vs. Temperature. 3.0 HDSP-2302 2.0 HDSP-2301 HDSP-2303 1.0 0 -20 0 20 40 60 80 100 120 140 TJ – JUNCTION TEMPERATURE – °C Figure 3. Relative Luminous Intensity vs. Temperature. ICOL – PEAK COLUMN CURRENT – mA 2.0 RELATIVE LUMINOUS INTENSITY PD MAX. – MAXIMUM ALLOWABLE POWER DISSIPATION – WATTS HDSP-2301/-2302/-2303 500 400 300 200 100 0 0 1.0 2.0 3.0 4.0 5.0 VCOL – COLUMN VOLTAGE – VOLTS Figure 4. Peak Column Current vs. Column Voltage. 6 Electrical Description CLOCK The HDSP-230X series of four character alphanumeric displays have been designed to allow the user maximum flexibility in interface electronics design. Each four character display module features Data In and Data Out terminals arrayed for easy PC board interconnection. Data Out represents the output of the 7th bit of digit number 4 shift register. Shift register clocking occurs on the high to low transition of the Clock input. The like columns of each character in a display cluster are tied to a single pin. Figure 5 is the block diagram for the displays. High true data in the shift register enables the output current mirror driver stage associated with each row of LEDs in the 5 x 7 diode array. SERIAL DECODED DATA INPUT SERIAL DECODED DATA OUTPUT 28 BIT SIPO SHIFT REGISTER 1–7 7 DATA LOCATIONS 8 – 14 15 – 21 7 7 22 – 28 7 CONSTANT CURRENT SINKING LED DRIVERS BLANKING CONTROL ROWS 1–7 ROWS 1–7 ROWS 1–7 ROWS 1–7 7 7 7 7 LED MATRIX 1 LED MATRIX 2 LED MATRIX 3 LED MATRIX 4 5 5 5 5 5 The TTL compatible VB input may either be tied to V CC for maximum display intensity or pulse width modulated to achieve intensity control and reduction in power consumption. COLUMN DRIVE INPUTS Figure 5. Block Diagram of HDSP-2301/-2302/-2303. The normal mode of operation input data for digit 4, column 1, Ambient Lighting Display Color Dim Moderate HDSP-2301 (Yellow) Panelgraphic Yellow 27 Chequers Amber 107 Polaroid HNCP37 3M Light Control Film Panelgraphic Gray 10 HDSP-2302 (HER) Panelgraphic Ruby Red 60 Chequers Red 112 Chequers Grey 105 HDSP-2303 (HP Green) Panelgraphic Green 48 Chequers Green 107 Figure 6. Contrast Enhancement Filters. Bright Polaroid HNCP10 7 is loaded into the 7 on-board shift register locations 1 through 7. Column 1 data for digits 3, 2, and 1 is similarly shifted into the display shift register locations. The column 1 input is now enabled for an appropriate period of time, T. A similar process is repeated for columns 2, 3, 4, and 5. If the time necessary to decode and load data into the shift register is t, then with five columns, each column of the display is operating at a duty factor of: D.F. = T 5 (t + T) The time frame, t + T, allotted to each column of the display is generally chosen to provide the maximum duty factor consistent with the minimum refresh rate necessary to achieve a flicker free display. For most strobed display systems, each column of the display should be refreshed (turned on) at a minimum rate of 100 times per second. With columns to be addressed, this refresh rate then gives a value for the time t + T of: 1/[5 x (100)] = 2 msec If the device is operated at 3.0 MHz clock rate maximum, it is possible to maintain t << T. For short display strings, the duty factor will then approach 20%. For further applications information, refer to Agilent Application Note 1016. Mechanical and Thermal Considerations The HDSP-2301/-2302/-2303 are available in standard ceramic dual-in-line packages. They are designed for plugging into sockets or soldering into PC boards. The packages may be horizontally or vertically stacked for character arrays of any desired size. The HDSP-2301/2302/-2303 utilize a high output current IC to provide excellent readability in bright ambient lighting. Full power operation (VCC = 5.25 V, VB = 2.4 V, VCOL = 3.5 V) with worst case thermal resistance from IC junction to ambient of 60˚C/watt/device is possible up to ambient temperature of 37˚C. For operation above 37˚C, the maximum device dissipation should be derated linearly at 16.7 mW/˚C (see Figure 2). With an improved thermal design, operation at higher ambient temperatures without derating is possible. Power derating for this family of displays can be achieved in several ways. The power supply voltage can be lowered to a minimum of 4.75 V. Column Input Voltage, V COL, can be decreased to the recommended minimum value of 2.75 V for the HDSP-2301/-2302/-2303. Also, the average drive current can be decreased through pulse width modulation of V B. The HDSP-2301/-2302/-2303 displays have glass windows. A front panel contrast enhancement filter is desirable in most actual display applications. Some suggested filter materials are provided in Figure 6. Additional information on filtering and contrast enhancement can be found in Agilent Application Note 1015. For more information on soldering and post-solder cleaning, please see Application Note 1027, Soldering LED Components. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. Obsoletes 5953-7749E 5966-2487E (11/99) Using the HDSP-2000 Alphanumeric Display Family Application Note 1016 Introduction First introduced in 1975, the HDSP-2000 alphanumeric display has been designed into a variety of applications. The HDSP-2000 display was originally designed for commercial, industrial, instrumentation, and business equipment applications. However, the introduction of high efficiency red, yellow, and high performance green devices as well as several display sizes has opened up a multitude of new applications for the HDSP-2000 alphanumeric display family. The high efficiency red, yellow, and high performance green devices use gallium phosphide (GaP) LEDs. The GaP displays are readable in direct sunlight with proper contrast enhancement techniques. For this reason, the HDSP-2000 family displays have been designed into a variety of avionic and process control applications. The HDSP-2000 family displays are available in three character sizes of 3.8 mm (0.15"), 4.9 mm (0.19"), and 6.9 mm (0.27") to allow the designer to optimize display compactness versus long distance readability. Versions of the HDSP-2000 family alphanumeric displays are available with a true hermetic package and an operat- ing temperature range of –55°C to +85°C to allow designers to utilize the proven reliability of LED display technology in military and aerospace applications. Table 1. The overall package size is designed to allow end stacking of multiple clusters to form character strings of any desired length. This note is intended to serve as a design and application guide for users of the HDSP-2000 family of alphanumeric display devices. The information presented will cover: the theory of the device design and operation; considerations for specific circuit designs; thermal management, power derating and heat sinking; intensity modulation techniques. Electrical Description The HDSP-2000 family has been designed to provide a high resolution information display subsystem. Each character of the 4 character package consists of a 5 x 7 array of LEDs which can display a full range of alphabetic and numeric characters plus punctuation, mathematical and other special symbols. The HDSP-2000 family is available in four colors: red, high efficiency red, yellow, and high performance green. The on-board electronics of the HDSP-2000 display family eliminates some of the classical difficulties associated with the use of alphanumeric displays. Traditionally, single digit LED dot matrix displays have been organized in an x-y addressable array requiring 12 interconnect pins per digit plus extensive row and column drive support electronics. All members of the HDSP-2000 display family provide on-board storage of decoded row data plus constant current sinking row drivers for each of the 28 rows in the 4 character display. This approach allows the user to address each display package through just 11 active interconnections vs. the 176 interconnections and 36 components required to effect a similar function using conventional LED matrices. The character height, character spacing, color and part number of each member of the HDSP-2000 family of displays is shown in Figure 1 is a block diagram of the internal circuitry of the HDSP-2000 display. The device consists of four LED matrices and 2 Table 1. The HDSP-2000 Alphanumeric Display Family Device Color Character Height Character Spacing Operating Temperature HDSP-2000 HDSP-2001 HDSP-2002 HDSP-2003 Red Yellow High Efficiency Red High Performance Green 3.8 mm (0.15 in.) 3.8 mm (0.15 in.) 3.8 mm (0.15 in.) 3.8 mm (0.15 in.) 4.5 mm (0.175 in.) 4.5 mm (0.175 in.) 4.5 mm (0.175 in.) 4.5 mm (0.175 in.) –20°C to +85°C –20°C to +85°C –20°C to +85°C –20°C to +85°C HDSP-2300 HDSP-2301 HDSP-2302 HDSP-2303 Red Yellow High Efficiency Red High Performance Green 4.9 mm (0.192 in.) 4.9 mm (0.192 in.) 4.9 mm (0.192 in.) 4.9 mm (0.192 in.) 5.0 mm (0.197 in.) 5.0 mm (0.197 in.) 5.0 mm (0.197 in.) 5.0 mm (0.197 in.) –20°C to +85°C –20°C to +85°C –20°C to +85°C –20°C to +85°C HDSP-2490 HDSP-2491 HDSP-2492 HDSP-2493 Red Yellow High Efficiency Red High Performance Green 6.9 mm (0.27 in.) 6.9 mm (0.27 in.) 6.9 mm (0.27 in.) 6.9 mm (0.27 in.) 8.9 mm (0.35 in.) 8.9 mm (0.35 in.) 8.9 mm (0.35 in.) 8.9 mm (0.35 in.) –20°C to +85°C –20°C to +85°C –20°C to +85°C –20°C to +85°C HDSP-2010 Red 3.8 mm (0.15 in.) 4.5 mm (0.175 in.) –40°C to +85°C HDSP-2310 HDSP-2311 HDSP-2312 Red Yellow High Efficiency Red 4.9 mm (0.192 in.) 4.9 mm (0.192 in.) 4.9 mm (0.192 in.) 5.0 mm (0.197 in.) 5.0 mm (0.197 in.) 5.0 mm (0.197 in.) –55°C to +85°C –55°C to +85°C –55°C to +85°C HDSP-2450 HDSP-2451 HDSP-2452 Red Yellow High Efficiency Red 6.9 mm (0.27 in.) 6.9 mm (0.27 in.) 6.9 mm (0.27 in.) 8.9 mm (0.35 in.) 8.9 mm (0.35 in.) 8.9 mm (0.35 in.) –55°C to +85°C –55°C to +85°C –55°C to +85°C COLUMN DRIVE INPUTS COLUMN 1 2 3 4 5 LED MATRIX 2 BLANKING CONTROL, VB 1 2 3 4 5 6 7 ROWS 1 2 3 4 5 6 7 SERIAL DATA INPUT ROWS 1-7 LED MATRIX 3 ROWS 1-7 LED MATRIX 4 ROWS 1-7 CONSTANT CURRENT SINKING LED DRIVERS ROWS 8-14 ROWS 15-21 28-BIT SIPO SHIFT REGISTER ROWS 22-28 SERIAL DATA OUTPUT XXXXXX.XX CLOCK Figure 1. Block Diagram 3 two 14-bit serial-in-parallel-out shift registers. The LED matrix for each character is a 5 x 7 diode array organized with the anodes of each column tied in common and the cathodes of each row tied in common. The 7 row cathode commons of each character are tied to the constant current sinking outputs of 7 successive stages of the shift register. The like columns of the 4 characters are tied together and brought to a single address pin (i.e., column 1 of all 4 characters is tied to pin 1, etc.). In this way, any diode in the four 5 x 7 matrices may be addressed by shifting data to the appropriate shift register location and applying a voltage to the appropriate column. The serial-in-parallel-out (SIPO) shift register has a constant current sinking output associated with each shift register stage. This constant current output drives each LED at a nominal peak current of 12 to 14 mA peak. The output stage is a current mirror design with a nominal current gain of 10. A logical 1 loaded into each shift register bit will turn “ON” the corresponding current source provided that a logical 1 is applied to the Blanking Input, VB. If VCOL is applied to the appropriate Column Input, the corresponding LED diode will be turned “ON”. Since the row drivers have a constant current output, the LED current will remain constant as long as the Column Input voltage exceeds 2.4 V for red and 2.75 V for high efficiency red, yellow, and high performance green devices. Data is loaded serially into the shift register on the high to low transition of the Clock Input. During the time that data is being loaded into the display, the column current must be disabled to minimize the generation of “current spikes” between VCC, the columns, and ground. The resulting power supply noise could induce noise on the Clock and Data Inputs. The column current can be disabled either by switching off the column drivers or by applying a logical 0 to the Blanking Input. The Data Output terminal is a TTL buffer interface to the 28th bit of the shift register (i.e., the 7th row of character 4 in each package) The Data Output is arranged to directly interconnect to the Data Input on a succeeding 4 digit HDSP-2000 display package. The Data, Clock and VB inputs are all buffered to allow direct interface to any TTL logic family. Theory of Operation Dot matrix alphanumeric display systems generally have a logical organization which prescribes that any character be generated as a combination of several subsets of data. In a 5 x 7 matrix, this could be either 5 subsets of 7 bits each or 7 subsets of 5 bits each. This technique is utilized to reduce from 35 to 5 or 7 the number of outputs required from the character generator. In order to display a complete character, these subsets of data are then presented sequentially to the appropriate locations of the display matrix. If this process is repeated at a rate which insures that each of the appropriate matrix locations is reenergized a minimum of 100 times per second, the eye will perceive a continuous image of the entire character. The apparent intensity of each of the display elements will be equal to the intensity of that element during the “ON” period multiplied by the ratio of “ON” time to refresh period. This ratio is referred to as the display duty factor, and the technique is referred to as “strobing”. In the case of HDSP2000, each character is made up of 5 subsets of 7 bits. For a four character display, 28 bits representing the first subset of each of the four characters are loaded serially into the on-board SIPO shift register and the first column is then energized for a period of time, T. This process is then repeated for columns 2 through 5. If the time required to load the 28 bits into the SIPO shift register is t, then the duty factor is: D.F. = T ; 5 t+T ( ) (1) the term 5(t + T) is then the refresh period. For satisfactory display, the refresh period should be: [ ( )] 1 / 5 t + T ≥ 100 Hz (2) or conversely ( ) 5 t + T ≤ 10 m sec, (3 ) which gives (t + T) ≤ 2 m sec. (4 ) The time averaged luminous intensity of the display can be varied continuously over a range greater than 1000 to 1 by turning off or blanking the display before loading new data into the SIPO shift register. If the time that the display is blanked is TB, then the duty factor of the display becomes: 4 D.F. = T 5 t + T + TB ( ) (5) where (t + T + TB ) ≤ 2 m sec. (5a ) Drive Circuit Concepts A practical display system utilizing the HDSP-2000 family of displays requires interfacing with a character generator, refresh memory and some timing circuitry. A block diagram of such a display system is depicted in Figure 2. This circuit provides for ASCII data storage and decoding and properly refreshes the display at a 100 Hz refresh rate. In this figure, the display length is shown as N characters with the leftmost display character labeled as character 1 and the right most character of the display labeled as character N. The refreshing of the display is accomplished by a series of counters. The ÷N counter sequentially accesses N coded information symbols from the N x 7 RAM. Note that for the normal configuration of the HDSP-2000 displays, character 1 is the leftmost character, character 4 is the rightmost character and shift register cascades from left to right. Thus, the symbol corresponding to character N is decoded first, then the symbol corresponding to character (N-1), and the symbol corresponding to character 1 is decoded last. Each coded information symbol is read from the N x 7 RAM and decoded by a 5 x 7 decoder. The decoder can be selected to decode ASCII, EBDIC, or any customized character font In this example, the ASCII decoder is organized as 128 x 7 words of 5 bits each. The ASCII symbol and row select information is applied to the decoder and the decoder outputs information for all 5 columns for the selected row and symbol. The ÷7 counter sequentially accesses all seven rows of each ASCII symbol. Note that row 7 must be decoded first, then row 6, and row 1 is decoded last. The ÷M counter is used to periodically load new serial data into the HDSP-2000 display. During one count, the display clock is enabled and 7N bits of serial data are loaded into the display. During the remaining (M1) counts, this data is displayed. Thus the duty factor for the circuit in Figure 2 is D.F. = (M − 1) = .20 1 − M −1 5M The ÷5 counter sequentially refreshes all 5 columns of the display. The outputs of the ÷5 counter are connected to a data multiplexer which selects one of the 5 outputs from the ASCII decoder and loads it into the Data Input of the HDSP-2000 display string. The ÷5 counter also enables one of the 5 column driver CHARACTER N CHARACTER I COLUMN OUTPUT ASCII 5x7 DECODER Nx7 RAM HDSP-2000 DISPLAY MUX 5 VB LOG2 N 3 5 ROW SELECT 3 7xNxMx5x100 Hz VCC CLOCK IN ÷7 DOWN COUNTER ÷N DOWN COUNTER ÷M DOWN COUNTER ÷5 UP COUNTER 3 1/5 DECODER 5 ENABLE LOG2 M HIGH FIRST COUNT IN M AN1016.02 Figure 2. CKT Block Diagram (6 ) 5 transistors. Note that the display is blanked via the VB input and also that the column driver transistors are turned off during the time that new data is being loaded into the HDSP-2000 display string. This will eliminate any high current transients between the column inputs and ground during the data shifting operation. Since data is loaded for all of the like columns in the display string and these columns are then enabled simultaneously, only five column switch transistors are required regardless of the number of characters in the string. The column switch transistors should be selected to handle 105 to 130 mA per character in the display string. The collector emitter saturation voltage characteristics and column voltage supply should be chosen to provide 2.4 V ≤ VCOL ≤ VCC for the standard red displays and 2.75 V ≤ VCOL ≤ VCC for the high efficiency red, yellow, and high performance green displays. To save on power supply costs and improve efficiency, this supply may be a fullwave rectified unregulated DC voltage as long as the PEAK value does not exceed the value of VCC and the minimum value does not drop below 2.4 V or 2.75 V depending on display color. Figures 13 and 16 show practical implementations of the block diagram shown in Figure 2. In those circuits, the display is mounted upside down, so that pin 1 is in the upper right hand corner. With this technique, data is loaded into display character N and data shifts from right to left as new data is loaded. The first bit loaded into the display would be row 1, character 1, then row 2, etc., and the last bit loaded would be row 7 of character N. This allows the ÷7, ÷N and ÷M counters to be implemented as up counters instead of down counters. Since the display is upside down, column 5 of the display appears to be column 1 and column 4 of the display appears to be column 2. Thus, column 1 data for the display must be loaded into the display and column 5 must subsequently be enabled. This is accomplished by reversing the outputs of the 5 x 7 decoder. The D0, D1, D2, D3, and D4 outputs of the MCM6674 decoder output column 5, column 4, column 3, column 2, and column 1 information. Interfacing the HDSP-2000 Display to Microprocessors Because of the complexity of dealing with alphanumeric information, a microprocessor based system is typically used in conjunction with the HDSP-2000 family displays. Depending upon overall systems configuration, microprocessor time available to dedicate to display support, and the type of information to be displayed, one may choose several different partitioning schemes to drive such a display. Figure 3 shows four different techniques to interface the HDSP200 family displays to microprocessor systems: 1. The REFRESH CONTROLLER interrupts the microprocessor at a 500 Hz rate to request refresh data for the display. 2. The DECODED DATA CONTROLLER accepts 5 x 7 matrix data from the microprocessor and then automatically refreshes the display with the same information until new data is supplied by the microprocessor. 3. The CODED DATA CONTROLLER accepts ASCII data and interfaces like a RAM to the microprocessor. 4. The DISPLAY PROCESSOR CONTROLLER (HDSP-247X series) employs a dedicated single chip microprocessor as a data display/control/keyboard interface which has many of the features of a complete terminal. The interface techniques depicted are specifically for the 8080A or 6800 microprocessor families. Extension of these techniques to other processors should be a relatively simple software chore with little or no hardware changes required. The choice of a particular interface is an important consideration because it affects the design of the entire microprocessor system. The REFRESH CONTROLLER provides the lowest cost interface because it uses the microprocessor to provide ASCII decoding and display strobing. Because the ASCII decoder is located within the microprocessor system, the designer has total control over the display font within the program. This feature is particularly important when the system will be used to display different languages and special graphic symbols. However, the REFRESH CONTROLLER requires a significant amount of microprocessor time. Furthermore, while the interrupt allows the refresh program to operate asynchronously from the main program, this technique 6 limits some of the software techniques that can be used in the main program. The DECODED DATA CONTROLLER requires microprocessor interaction only when the display message is changed. Like the REFRESH CONTROLLER, the ASCII decoder is located within the microprocessor program. However, the time required to decode the ASCII string and store the resulting 5 x 7 display data into the interface requires several milliseconds of microprocessor time. The CODED DATA CONTROLLER also requires interaction from the microprocessor system only when the display message is changed. Because the ASCII decoder is located within the display interface, the microprocessor requires much less time to load a new message into the display. The DISPLAY PROCESSOR CONTROLLER, the HDSP-247X series, is the most powerful interface. The software within the DISPLAY PROCESSOR CONTROLLER further reduces the host ADDRESS BUS microprocessor interaction by providing more powerful left and right data entry modes compared to the RAM entry mode of the DECODED DATA and CODED DATA CONTROLLERS. The DISPLAY PROCESSOR CONTROLLER can also provide features such as a Blinking Cursor, Editing Commands, and a Data Out function. One version of the DISPLAY PROCESSOR CONTROLLER allows the user to provide a custom ASCII decoder for applications needing a special character font. ADDRESS BUS REFRESH CONTROLLER RAM CONTROLLER MUX ROM* PISO DATA, CLOCK DATA BUS DISPLAY LATCH INTERRUPT REQUEST 5 COLUMNS RAM** MICROPROCESSOR RAM DISPLAY COUNTER * PROGRAM ** SCRATCHPAD DECODER DATA CONTROLLER DISPLAY PROCESSOR CONTROLLER MUX ADDRESS BUS DATA BUS RAM DATA DISPLAY CLOCK, 5 COLUMNS * PROGRAM + ASCII LOOKUP TABLE ** SCRATCHPAD MICROPROCESSOR ROM* SYSTEM CLOCK ASCII DECODER CLOCK, 5 COLUMNS ADDRESS BUS MICROPROCESSOR DATA DATA BUS SYSTEM CLOCK 500 Hz CLOCK * PROGRAM + ASCII LOOKUP TABLE ** SCRATCHPAD WITH OR WITHOUT DECODED ASCII LOOKUP TABLE RAM** ROM* RAM** ROM* DATA BUS SLAVE MICROPROCESSOR MICROPROCESSOR RAM** *** DATA, CLOCK DISPLAY 1/5 DECODER COUNTER * PROGRAM ** SCRATCHPAD *** ASCII DECODER FOR CUSTOM FONT PISO 5 COLUMNS AN1016.03 Figure 3. Four Different Techniques to Interface the HDSP-2000 Alphanumeric Display to a Microprocessor System TO 6800 φ2 φ2 A14 VMA A12 A13 A15 TO 6800 φ1 φ1 A3 A4 22 Ω 22 Ω 4 5 74LS04 3 2 K 1K 8 VCC 6 VCC 74LS20 MC3459 1 2 4 5 1K 15 74LS20 MC3459 12 13 10 6 9 12 CL CK 4 5 J PR Q 13 74LS04 74LS112 1 3 VCC 6800 8080A DATA BUS A0 A1 A2 4 5 6 G3 G2 G 1 1 A 2 B 3 C 4 5 74LS138 11 10 5Q 4Q 3Q 2Q 1Q 15 12 10 74LS293 74165 A 1 2 4 5 12 13 74LS20 74LS00 5 120 Ω (TYP) 7 A B C D E F 9 QH G H SI CI S/L CK 74174 1D 2D 3D 4D 5D CK CL 9 QA 5 QB 11 B 4 QC 8 12 R01 QD R02 13 10 11 12 13 14 3 4 5 6 10 15 1 2 6 4 11 13 14 9 1 2.7 K (TYP) 6 11 Figure 4. 6800 or 8080A Microprocessor Interface to the HDSP-2000 REFRESH CONTROLLER 6800 8080 I/O WRITE 8080A φ2 VCC D0 D1 D2 D3 D4 D5 D6 1K 1 3 2 74LS00 12 MJE700 (TYP) 9 8 11 5 3 1 NE 555 TIMER 4 8 6 2 7 10 0.01 µF 220 K VCC 11 AN1016.04 500 Hz ASTABLE MULTIVIBRATOR 0.01 µF TO INTERRUPT REQUEST 74LS00 10 10 9 8 1 2 3 4 5 9 8 1 2 3 4 5 VCC VBR C1 C2 C3 C4 C5 V V C C C C C 7 12 CC BR 1 2 3 4 5 DIN DO DIN HDSP-2000 HDSP-2000 CK CK VCC 7 8 Refresh Controller The REFRESH CONTROLLER circuit depicted in Figure 4 operates by interrupting the microprocessor every two milliseconds to request a new block of display data and column select data. Display data is loaded from the data bus into the serial input of the HDSP-2000 via a 74165 parallel in, serial out shift register. The 74LS293 counter and associated gates insure that only seven clock pulses are delivered to the shift register and the HDSP-2000 for each word loaded. Column Select data is loaded into a 74174 latch which, in turn, drives the column switch transistors. The circuit timing relative to the microprocessor clock and I/O is depicted in Figure 5. The 6800 software necessary to support this interface is divided into two separate subroutines, “RFRSH” and “LOAD” (Figure 6). This approach is desirable to minimize microprocessor involvement during display refresh. The subroutine “RFRSH” loads a new set of decoded display data from the microprocessor scratchpad memory into the interface at each interrupt request. The subroutine “LOAD” is utilized to decode a string of 32 ASCII characters into 5 x 7 formatted display data and store this data in the scratchpad memory used by “RFRSH”. Figures 7 and 8 depict two different software routines for interfacing the REFRESH CONTROLLER to an 8080A microprocessor. The two subroutines shown in Figure 7 are functional replacements for the 6800 program shown in Figure 6. The programs shown in Figures 6 and 7 require a 5N byte scratchpad memory where N is the display length. The routine in Figure 8 eliminates this scratchpad memory by decoding and loading data each time a new interrupt request is received. Because the microprocessor system is interrupted every 2 ms, proper software design is especially important for the REFRESH CONTROLLER. The use of the scratchpad memory significantly reduces the time required to refresh the display. The fastest program, shown in Figure 6, uses in-line code to access data from the buffer and output it to the display. This program requires 3.7% + .50N% of the available microprocessor time for a 1 MHz clock. The program shown in Figure 7 is similar to the one shown in Figure 6, except that it uses a program 8080A MICROPROCESSOR TIMING φ1 φ2 ADDRESS BUS DATA BUS S/L 74165 6800 MICROPROCESSOR TIMING φ2 φ1 ADDRESS BUS DATA BUS S/L 74165 DATA ENTRY TIMING HDSP 2000 CLOCK HDSP 2000 DATA ROW 7 ROW 6 ROW 5 ROW 4 ROW 3 ROW 2 ROW 1 AN1016.05 Figure 5. REFRESH CONTROLLER Timing 9 loop instead of the in-line code. This program uses 5.4% + .93N% of the microprocessor time for a 2 MHz clock. These programs utilize a subroutine “LOAD” which is called whenever the display message is changed. This subroutine executes in 10.2 ms and 7.5 ms respectively for Figure 6 and Figure 7. The program in Figure 8 uses 7.6% + 1.35N% of the microprocessor time for a 2 MHz clock. A 50% reduction in the previously described microprocessor times can be achieved by using faster versions of the 6800 and 8080A microprocessors. The ASCII to 5 x 7 dot matrix decoder used by the programs in Figures 6, 7, and 8 is located within the microprocessor program. This decoder requires 640 bytes of storage to decode the 128 character ASCII set. The decoder used by these controllers is formatted so that the first 128 bytes contain column 1 information; the next 128 bytes contain column 2 information, etc. Each byte of this decoder is formatted such that D6 through D0 contain Row 7 through Row 1 display data respectively. The data is coded so that a HIGH bit will turn the corresponding 5 x 7 display dot ON. This decoder table is shown in Figure 9. The resulting 5 x 7 dot matrix display font is shown in the HDSP-2471 data sheet. Decoded Data Controller The DECODED DATA CONTROLLER circuit schematic for a 32 character display is depicted in Figure 10. The circuit is specifically designed for interface to an 8080A microprocessor. This circuit is designed to accept and store in local memory all of the display data for a 32 character HDSP-2000 display (1120 bits). The microprocessor loads 160 bytes of display data into the two 1 K x 1 RAM’s via the 74165 parallel in, serial out shift register. Each byte of data represents one column of display data. The counter string automatically generates the proper address location for each serial bit of data after initialization by MEM W, the character address, and the desired column. Once the loading is complete, the counter sequentially loads and displays each column (224 bits) of data at a 90 Hz rate (2 MHz input clock rate). The timing for this circuit is shown in Figure 11. The software required to decode a 32 character ASCII string is shown in Figure 12. This program decodes the 32 ASCII characters into 160 bytes of display data which are then stored in the controller. The program requires about 6.6 ms, for a 2 MHz clock, to decode and load the message into the DECODED DATA CONTROLLER. This program also uses the same decoder table as shown in Figure 9. Coded Data Controller The CODED DATA CONTROLLER (Figure 13) is designed to accept ASCII coded data for storage in a local 128 x 8 RAM. After the microprocessor has loaded the RAM, local scanning circuitry controls the decoding of the ASCII, the display data loading, and the column select function. With minor modification, the circuit can be utilized for up to 128 display characters. The RAM used in this circuit is an MCM6810P with the Address and Data inputs isolated via 74LS367 tri-state buffers. This allows the RAM to be accessed either by the microprocessor or by the local electronics. The protocol is arranged such that the microprocessor always takes precedence over the local scanning electronics. The “Write” cycle timing for the CODED DATA CONTROLLER is depicted in Figure 14. This circuit, as with the DECODED DATA CONTROLLER, requires no microprocessor time once the local RAM has been loaded with the desired data. The circuit shown in Figure 13 shows a CODED DATA CONTROLLER designed for a 32 character HDSP-2000 alphanumeric display. The key waveforms shown in Figure 15, labeled ①, ② , and ③, are shown to simplify the analysis of this circuit. Label ① is the 1 MHz clock. Label ② is the output of 7404 pin 2 which is the inverted QD output of the 74197. Label ③ is the output of the 7404 pin 6 which is the ANDed output of 2QB, 2QC, and 2QD of the 74393. The Motorola 6810 RAM stores 32 bytes of ASCII data which is continuously read, decoded, and displayed. The ASCII data from the RAM is decoded by the Motorola 6674 128 character ASCII decoder. The 6674 decoder has five column outputs which are gated to the Data Input of the display via a 74151 multiplexer. Strobing of the display is accomplished via the 74197, 74393, and 7490 counter string. The 74197 is connected as a divide by 8 counter that sequentially selects the seven rows within the 6674. As shown by waveform ② , the 74197 also enables seven clock cycles to be gated to the clock input of the display. The 74393 is a divide by 256 counter connected so that the five lowest order outputs select each of the 32 ASCII characters within the RAM. The three highest order outputs determine the relationship between load time and column on time. When 2QB = 2QC = 2QD = 1 of the 10 74393, waveform ③ goes to a logical 1. The circuit then scans 32 characters from the RAM and serializes the column data by counting through each of the seven rows of the 6674 and gating the appropriate column of the display. During the seven counts when 2QB, 2QC, and 2QD of the 74393 are not equal to a logical 1, the column data is displayed, as shown in waveform ④). The duty factor of the display shown in Figure 13 is 17.5%. Changing the display length to 64 characters is a simple modification. This configuration can be easily realized by disconnecting 2QB of the 74393 from the 7410 and connecting it through the remaining tri-state buffer on the 74LS367 and using the 6810 RAM to store 64 ASCII characters. By leaving only 2QC and 2QD attached to the 7410, the column on time of the display is reduced from 17.5% to 15%. This reduction is caused because the relationship between actual column on time and theoretical column on time is 3/4 as opposed to 7/8 for the 32 characters. Since the display length has been doubled, the drive transistors must be upgraded to handle the higher column currents. To implement a 128 character display, several modifications are needed. These changes are incorporated into the circuit in Figure 16. First, the input clock frequency has been increased to 2 MHz. This has been done to maintain a refresh rate of approximately 100 Hz for each digit, thus providing a flicker-free display. This higher speed of operation causes propagation delay problems within the MCM6674 (NMOS) whose maximum access time is 350 ns. For this reason, the OBJECT CODE LOC BF Bl 06 05 04 00 00 AD SOURCE STATEMENTS 0000 0002 0003 0005 0007 0009 000B 000C 000D 00AD 0400 0400 0402 0405 0407 0409 040C 040E 86 B7 DE A6 B7 A6 B7 FF BF 00 00 BF 01 BF 04A2 04A4 04A7 04A9 04AC 04AE 04B0 04B2 04B4 04B6 04B8 04BB 04BC 04BF 04C0 04C3 04C5 04C7 04C8 04CA 04CC 04CE A6 B7 96 B7 81 27 D6 CB D7 24 7C OD 79 3B CE DF DE 09 DF 86 97 3B 1F BF 02 BF EF 10 00 20 00 03 00 04CF 04D0 04D3 04D5 04D7 04D9 04DB 04DD 04DF 04E1 04E3 04E5 04E8 04EA 04EC 04ED 04EF 04F1 04F2 04F4 04F6 04F8 04FA 04FC 04FD 04FF 0502 0504 0506 0508 050B 050E 0510 5F CE DF 86 97 86 97 86 97 9B 24 7C 97 DE 09 A6 DF 1B 97 DE A6 DE A7 08 DF 7A 26 CB 24 7C 7A 26 39 * * CDVR RDVR DECDR POINT COLMN COUNT EQU EQU EQU RMB RMB RMB $BF05 $BF04 $0600 2 1 2 ASCII DISPNT DCRPNT COLCNT DIGCNT FDB RMB RMB RMB RMB DATA 2 2 1 1 BUFFR DATA RMB RMB 160 32 RFRSH 05 LOOPHH 04 04 04 05 00 LOOPA 00 02 00 00 03 OD LOOPB 03 FE 02 LOAD 00 07 06 09 05 OB 20 0C 06 03 00 06 05 OD LOOP I 05 LOOP2 LOOP3 00 05 0A 09 00 07 00 07 00 E6 80 03 00 00 CD 0C 09 0B LOOP4 ORG LDA STA LDX LDA STA LDA STA A A A A A A • • • LDA A STA A LDA A STA A CMP A BEQ LDA B ADD B STA B BCC INC SEC ROL RTI LDX STX LDX DEX STX LDA A STA A RTI CLR LDX STX LDA STA LDA STA LDA STA ADD BCC INC STA LDX DEX LDA STX ABA STA LDX LDA LDX STA INX STX DEC BNE ADD BCC INC DEC BNE RTS $0400 I, $FF E, CDVR D, POINT X, 0 E, RDVR X, I E, RDVR X, 31 E, RDVR D, COLMN E, CDVR I, $EF LOOPB D, POINT +1 I, 32 D, POINT +1 LOOPA E, POINT E, COLMN I, BUFFER D, POINT D, COUNT D, COUNT I, $FE D, COLMN B A A A A A A A A I, BUFFR D, DISPNT I, <DECDR D, DCRPNT I, 5 D, COLCNT I, 32 D, DIGCNT D, ASCII+1 LOOP2 E, ASCII D, ASCII+1 D, ASCII A X, 0 D, ASCII A D, DCRPNT+1 D, DCRPNT X, 0 D, DISPNT X, 0 A A B D, DISPNT E, DIGCNT LOOP3 I, $80 LOOP4 E, DCRPNT E, COLCNT LOOP1 Figure 6. 6800 Microprocessor Program Utilizing a 160 Byte RAM Buffer that Interfaces to the REFRESH CONTROLLER 11 RFRSH LOAD B←0 INITIALIZE COLUMN OFFSET = 0 CDVR ← FFH TURN OFF COLUMN DRIVERS DISPNT ← BUFFER LOAD DISPNT WITH ADDRESS OF DECODED DATA RAM RDVR ← (POINT) STORE FIRST BYTE DECODED DATA IN 74165 DCRPNT ← DECDR LOAD DCRPNT WITH ADDRESS OF DECODER ROM RDVR ← (POINT + 1) STORE SECOND BYTE DECODED DATA IN 74165 COLCNT ← 5 • • • DIGCNT ← 32 RDVR ← (POINT + 31) STORE 32nd BYTE DECODED DATA IN 74165 ASCII ← ASCII + 32 INITIALIZE ASCII WITH ADDRESS OF RIGHTMOST ASCII SYMBOL PLUS ONE CDVR ← COLMN TURN ON APPROPRIATE COLUMN DRIVER ASCII ← ASCII –1 UPDATE ASCII WITH ADDRESS OF NEXT SYMBOL TO LEFT JUST REFRESHED COLUMN 5? YES (LOOP B) DCRPNT ← (ASCII) + B + DECDR ACCESS BYTE OF DECODED DATA FROM DECODER NO POINT ← POINT + 32 UPDATE POINT WITH ADDRESS OF DECODED DATA FOR NEXT COLUMN TO BE REFRESHED DISPNT ← (DCRPNT) STORE BYTE OF DECODED DATA IN DECODED DATA RAM COLUMN ← 2 COLMN + 1 UPDATE COLMN FOR NEXT REFRESH CYCLE RETURN DISPNT ← DISPNT + 1 UPDATE DISPNT WITH ADDRESS OF NEXT BYTE IN DECODED DATA RAM POINT ← BUFFER UPDATE POINT WITH ADDRESS OF COLUMN 1 IN DECODED DATA RAM DIGCNT ← DIGCNT –1 DIGCNT = 0? COUNT ← COUNT –1 OPTIONAL 2 ms TIMER COLMN ← FEH UPDATE COLMN TO TURN ON COLUMN 1 RETURN NO (LOOP 3) YES B ← B + 80H ADD OFFSET FOR NEXT COLUMN IN DECODER ROM COLCNT ← COLCNT –1 COLCNT = 0? NO (LOOP 1) YES RETURN Figure 6. 6800 Microprocessor Program Utilizing a 160 Byte RAM Buffer that Interfaces to the REFRESH CONTROLLER (cont.) 12 MCM6674 must be replaced by a faster Bipolar PROM. If this PROM is programmed with the code listed in Figure 17, it will decode a character font identical to the MCM6674. This same propagation delay problem is present with the MCM6810 RAM. Following worst case design procedures, the MCM68A10 1.5 MHz RAM should be used. To accommodate the additional address line made necessary by the display length expansion, the two 74LS367 tri-state buffers have been replaced with the 74LS244 octal version. Strobing of the display is accomplished using the 74197, 74393, and 7490 counter string. The 74197 is connected as a divide by 8 counter that sequentially selects the seven rows within the 82S2708. The 74393 is a divide by 256 counter connected so that the seven lowest outputs select each of the 128 ASCII characters within the RAM. The previously unused input A/output QA of the 7490 has been used as an additional divide by 2 counter. Thus, when the highest output of the 74393, 2QD, and the QA output of the 7490 are NANDed through 7437, the basic relationship between load time and column on time is established. However, the external gating that has been added does affect the duty factor slightly. Although these additional gates increase the total package count by one, they perform the necessary function of ensuring that the column drivers are turned off before the clock is gated to the display. This prevents noise from being generated on the clock of the display and eliminates erroneous display data. The resultant duty factor is (23/32) (1/5) or 14.4%. Since the HDSP-2000 is rated at Icol(max) = 410 mA and OBJECT CODE LOC SOURCE STATEMENTS 0004 0005 E500 E000 E002 E003 E005 05 FE FF 00 E0 E0A5 E0A7 A7 00 E0 E400 E401 E402 E403 E406 E408 E40A F40C E40D E40F E410 E411 E414 E417 E419 E41B E41E E421 E422 E425 E428 E42B E42E E430 E433 E436 E437 E43A E43B E43C E43D F5 C5 E5 2A 06 3E D3 7E D3 23 05 C2 3A D3 FE CA 22 07 32 C3 21 22 3E 32 2A 2B 22 El Cl F1 C9 E43E E441 E443 E446 E447 E448 E44B E44D E44E E450 E451 E452 E453 E455 E456 E459 E45A E45B E45D E45E E45F E462 E463 E465 E466 E467 E46A 11 0E 2A 7E 23 22 26 6F 06 7E 12 7D C6 6F D2 24 7B C6 5F 05 C2 7B C6 5F 0D C2 C9 FF RDVR CDVR DECDR EQU EQU EQU 0004H 0005H 0E500H POINT COLMN COUNT BUFFR ORG DW DB DW DS 0E000H BUFFR 0FEH 0FFFFH 160 ASCII DATA ORG DW DS 0E0A5H DATA 32 ORG PUSH PUSH PUSH LHLD MVI MVI OUT MOV OUT INX DCR JNZ LDA OUT CPI JZ SHLD RLC STA JMP LXI SHLD MVI STA LHLD DCX SHLD POP POP POP RET 0E400H PSW B H POINT B, 32 A, 0FFH CDVR A, M RDVR H B LOOP COLMN CDVR 0EFH FIRST POINT LXI MVI LHLD MOV INX SHLD MVI MOV MVI MOV STAX MOV ADI MOV JNC INR MOV ADI MOV DCR JNZ MOV ADI MOV DCR JNZ RET D, BUFFR+31 C, 32 ASCII A, M H ASCII H, DECDR/256 L, A B, 5 A, M D A, L 80H L, A LOOP3 H A, E 32 E, A B LOOP2 A, E 5FH E, A C LOOP1 RFRSH 00 20 FF 05 E0 LOOP 04 0C 02 05 EF 28 00 E4 E0 02 3A 05 00 FE 02 03 E0 E4 E0 E0 03 E0 E4 E0 FIRST E0 E0 END 24 20 A5 A5 E5 E0 LOAD E0 LOOP1 E0 05 LOOP2 80 5A E4 LOOP3 20 50 E4 5F 43 E4 COLMN END H, BUFFR POINT A, 0FEH COLMN COUNT H COUNT H B PSW Figure 7. 8080A Microprocessor Program Utilizing a 160 Byte RAM Buffer that Interfaces to the REFRESH CONTROLLER 13 RFRSH LOAD DE ← BUFFER + 31 LOAD DE WITH ADDRESS FOR COLUMN 1 RIGHTMOST CHARACTER IN DECODED DATA RAM STORE MACHINE STATUS ON STACK B ← 32 C ← 32 CDVR ← FFH TURN OFF COLUMN DRIVERS A ← (ASCII) READ ASCII SYMBOL INTO A RDVR ← (POINT) STORE BYTE OF DECODED DATA IN 74165 ASCII ← ASCII + 1 UPDATE ASCII WITH ADDRESS OF NEXT SYMBOL TO RIGHT POINT ← POINT + 1 UPDATE POINT WITH ADDRESS OF NEXT BYTE HL ← DECDR LOAD HL WITH ADDRESS OF DECODER ROM B←5 B ← B –1 A ← (HL + A) READ BYTE OF DECODED DATA FROM DECODER NO B = 0? (LOOP) YES (DE) ← A STORE BYTE OF DECODED DATA IN DECODED DATA RAM CDVR ← COLMN TURN ON APPROPRIATE COLUMN DRIVER JUST REFRESHED COLUMN 5? HL ← HL + 80H UPDATE HL WITH ADDRESS OF NEXT COLUMN IN DECODER YES (FIRST) DE ← DE + 32 UPDATE DE WITH ADDRESS OF NEXT COLUMN IN DECODED DATA RAM NO COLUMN ← 2 COLMN + 1 UPDATE COLMN FOR NEXT REFRESH CYCLE B ← B –1 POINT ← BUFFER UPDATE POINT WITH ADDRESS OF COLUMN 1 IN DECODED DATA RAM NO B = 0? (LOOP 2) COLMN ← FEH UPDATE COLMN TO TURN ON COLUMN 1 YES DE ← DE – 161 UPDATE DE WITH ADDRESS FOR COLUMN 1 OF CHARACTER IN DECODED DATA ROM IMMEDIATELY TO LEFT OF PRECEEDING CHAR. COUNT ← COUNT –1 OPTIONAL 2 ms TIMER C ← C –1 (END) RESTORE MACHINE STATUS FROM STACK C = 0? NO (LOOP 1) RETURN YES RETURN Figure 7. 8080A Microprocessor Program Utilizing a 160 Byte RAM Buffer that Interfaces to the REFRESH CONTROLLER (cont.) 14 OBJECT CODE LOC 0004 0005 E500 E000 E002 E003 E005 E007 07 FE FF 00 00 E400 E401 E402 E403 E404 E407 E408 E40B E40E E40F E410 E412 E414 E416 E417 E418 E419 E41A E41C E41D E41E E421 E422 E425 E427 E429 E42C E42D E430 E431 E434 E435 E438 E43B E43D E440 E443 E446 E449 E44A E44D E44E E44F E450 E451 F5 C5 D5 E5 2A EB 2A 01 09 43 0E 3E D3 78 86 5F 1A D3 2B 0D C2 EB 3A D3 FE CA 07 32 68 01 09 22 C3 3E 32 21 22 2A 2B 22 E1 D1 C1 F1 C9 RFRSH SOURCE STATEMENTS E0 FF E5 RDVR CDVR DECDR EQU EQU EQU 0004H 0005H 0E500H ASCII COLMN COUNT BASE DATA ORG DW DB DW DW DS 0E000H DATA 0FEH 0FFFFH DECDR 32 ORG RFRSH 05 E0 00 1F E0 00 20 FF 05 LOOP 04 16 E4 02 05 EF 3B E0 02 E0 E4 80 00 05 4D FE 02 00 05 03 E0 E4 03 E0 FIRST E0 E5 E0 E0 END PUSH PUSH PUSH PUSH LHLD XCHG LHLD LXI DAD MOV MVI MVI OUT MOV ADD MOV LDAX OUT DCX DCR JNZ XCHG LDA OUT CPI JZ RLC STA MOV LXI DAD SHLD JMP MVI STA LXI SHLD LHLD DCX SHLD POP POP POP POP RET 0E400H PSW B D H BASE ASCII B, 31 B B, E C, 32 A, 0FFH CDVR A, B M E, A D RDVR H C LOOP COLMN CDVR 0EFH FIRST COLMN L, B B, 0080H B BASE END A, 0FEH COLMN H, DECDR BASE COUNT H COUNT H D B PSW STORE MACHINE STATUS ON STACK DE ← BASE LOAD DE WITH ADDRESS NEXT COLUMN TO BE DECODED IN DECODER ROM HL ← ASCII + 31 LOAD HL WITH ADDRESS OF RIGHTMOST ASCII SYMBOL C ← 32 CDVR ← FFH TURN OFF COLUMN DRIVERS A ← (HL) READ ASCII SYMBOL INTO A A ← (DE + A) READ BYTE OF DECODED DATA FROM DECODER RDVR ← A STORE BYTE OF DECODED DATA IN 74165 HL ← HL – 1 UPDATE HL WITH ADDRESS OF NEXT SYMBOL TO LEFT C←C–1 C = 0? NO (LOOP) YES CDVR ← COLMN TURN ON APPROPRIATE COLUMN DRIVER JUST REFRESHED COLUMN 5? YES (FIRST) NO COLUMN ← 2 COLMN + 1 UPDATE COLMN FOR NEXT REFRESH CYCLE COLMN ← FEH UPDATE COLMN TO TURN ON COLUMN 1 BASE ← BASE + 80H UPDATE BASE WITH ADDRESS OF NEXT COLUMN IN DECODER ROM BASE ← DECDR UPDATE BASE WITH ADDRESS OF COLUMN 1 DATA IN DECODER ROM COUNT ← COUNT –1 OPTIONAL 2 ms COUNTER (END) RESTORE MACHINE STATUS ON STACK Figure 8. 8080A Microprocessor Program that Decodes a 32 Character ASCII String Prior to Loading into the REFRESH CONTROLLER RETURN 15 there are 32 modules of four digits each, the transistors must source up to 32 times 410 mA or approximately 13 A. Darlington PNP power transistors (2N6285) with the proper resistors have been used to accomplish this task. the microprocessor software. The DISPLAY PROCESSOR CONTROLLER is a system which utilizes a dedicated 8048 single chip microprocessor to provide these important features. This controller, as depicted in Figure 18, is a series of printed circuit board subsystems available from Display Processor Controller The previously mentioned interface techniques provide only for the display of ASCII coded data. Such important features as a blinking cursor, editing routines, and character addressing must be provided by other subroutines in DECODER ADDRESS FOR FIG. 7,8,12 DECODER ADDRESS FOR FIG.6 E500 0600 080 090 0A0 0B0 0C0 0D0 0E0 0F0 08 10 00 3E 3E 7F 00 7C 30 18 00 00 7E 3E 38 18 45 7D 5E 78 00 14 62 22 7F 3E 7F 26 7F 38 00 48 7D 38 24 18 7F 01 38 04 38 78 23 27 7F 3F 38 3C 7E 38 36 3C 7F 07 08 1C 30 3C 00 01 3E 7F 08 3C 60 38 00 36 7F 63 7F 44 1E 3C 00 06 00 03 00 04 3E 38 08 00 20 61 20 44 62 08 08 00 7F 00 00 00 40 20 00 00 7F 02 00 00 08 12 08 14 7F 41 78 00 38 48 00 41 7F 04 7C 08 41 COLUMN1 01 20 06 3E 40 38 2A E580 0680 100 110 120 130 140 150 160 170 1C 08 00 51 41 09 07 14 48 24 5F 42 09 41 44 24 29 09 61 14 03 7F 51 41 49 41 09 49 48 44 7C 54 09 44 2A 14 41 01 44 3E 44 15 13 45 49 40 54 40 01 45 49 4A 09 18 7E 20 4A 43 0B 71 41 20 14 40 50 45 00 49 08 14 08 28 04 41 41 49 41 04 44 48 49 42 2A 36 40 51 40 64 14 08 08 5B 08 00 7F 08 3C 7E 58 08 40 04 41 00 7C 19 08 14 02 41 04 41 44 7E 30 22 04 02 08 04 63 COLUMN2 12 10 01 41 40 44 55 E600 0700 180 190 lA0 lB0 lC0 lD0 lE0 lF0 3E 78 00 49 5D 09 0B 24 45 7E 00 7F 09 51 44 14 11 01 00 49 49 19 44 08 11 15 14 49 41 49 44 54 05 45 7F 12 41 7F 44 44 44 14 08 45 49 40 54 40 29 44 56 49 09 60 09 40 4D 42 07 09 41 18 54 30 48 44 3E 49 08 08 04 10 04 40 3E 49 7F 78 7D 30 49 40 1C 36 40 49 44 54 08 2A 3E 3B 14 7F 10 36 20 02 38 14 40 08 7F 77 04 15 08 14 0C 7F 18 36 44 49 30 14 08 7F 04 08 55 COLUMN3 7C 08 51 41 40 44 2A E680 0780 200 210 220 230 240 250 260 270 7F 40 08 24 00 00 45 40 55 09 09 21 00 3C 24 7C 29 61 03 49 49 29 44 04 21 14 7F 49 41 49 44 54 05 3C 2A 7F 41 01 48 20 38 15 64 45 49 40 54 20 2E 3D 20 49 09 18 02 20 49 43 00 05 51 20 54 40 50 45 41 49 08 14 04 28 38 41 00 29 41 04 40 08 49 42 2A 00 40 45 3D 4C 10 1C 08 00 22 41 28 41 20 02 00 22 40 10 40 00 7C 12 08 14 02 00 04 08 3C 41 00 08 10 02 04 10 49 COLUMN4 12 04 09 41 40 44 55 E700 0800 280 290 2A0 2B0 2C0 2D0 2E0 2F0 00 04 00 3E 1E 06 00 18 45 7D 5E 78 00 14 46 36 36 22 46 32 38 20 04 20 79 40 12 10 3E 01 7F 00 44 78 62 39 41 3F 08 7C 10 40 50 30 01 07 00 1C 30 3C 00 03 72 7F 3C 3C 60 38 00 36 7F 63 78 44 40 3C 00 1E 00 03 00 04 3E 38 08 00 3F 43 00 44 60 08 08 00 41 41 44 00 1C 02 00 41 40 20 00 00 02 00 08 14 7F 00 78 00 04 42 00 00 7F 04 78 08 41 COLUMN5 01 02 06 3E 40 38 2A HDSP-2471 ROM ADDRESS HEXIDECIMAL DATA 30 18 00 00 7E 5E 40 40 Figure 9. 128 Character ASCII Decoder Table Used by the 6800 Refresh Program in Figure 6. 8080A Refresh Programs in Figures 7, 8, and 12, and the HDSP-2471 DISPLAY PROCESSOR CONTROLLER. Decoded 5x7 Display Font is shown in the HDSP-247X Data Sheet 74LS04 9 4 5 DATA BUS 74LS00 2 6 13 1 3 12 D6 D5 D4 D3 D2 D1 D0 74LS27 A0 A1 A2 7 EP QA QB QC QD J VCC 6 5 4 3 14 13 12 11 10 15 1 2 3 74LS27 6 4 5 C 5 14 13 12 11 74LS165 QH 9 11 J 13 12 K VCC 15 VCC 74LS112 H G F E D C B A SI CI S/L K S Q 74LS162 10 ET A B C D CL L 4 3 15 14 13 12 11 15 14 13 12 11 10 7 ET EP A B QA 14 C D QD 11 CL L 15 RCO 74LS162 10 7 ET EP A QA B QB C QC D QD CL L RCO 74LS163 VCC 1 2 1 9 2 3 4 5 6 3 4 5 6 1 9 2 1 9 2 3 4 5 6 74LS04 4 VCC VCC VCC 1 9 2 6 5 3 74LS27 8 10 7 ET EP A QA B QB C QC D QD CL L RCO 74LS163 Q 14 C Q 10 S 7 9 74LS00 10 74LS04 11 9 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 12 13 12 D 15 A 14 B 13 C 2.7 K (TYP) 11 1 130 5 130 4 130 3 130 2 130 12 INTEL 2102A-4 12 INTEL 2102A-4 74LS00 0 4 3 2 1 74LS145 DOUT 11 D 3 IN R/W 13 CE 8 4 5 6 7 2 1 16 15 14 13 74LS04 DOUT 11 D 3 IN R/W 13 CE 12 8 4 5 6 7 2 1 16 15 14 — — — — — — — — — — 1 0 0 1 A6 A7 — — — — — 1 0 A5 — — — — — 1 0 A4 — — — — — 1 0 A3 1 0 0 0 0 — A2 — NOTE: ADDRESS BUS DECODING 74LS04 81 2 Figure 10. 8080A Microprocessor Interface to the HDSP-2000 DECODED DATA CONTROLLER φ2 (TTL) MEMW A13 A12 A15 A14 1 8 2 ADDRESS BUS A7 A3 A4 A5 A6 9 10 11 VCC 3 4 5 6 VCC 0 1 1 0 0 — A1 — 0 1 0 1 0 — A0 — AN1016.10 1 2 3 4 5 MJE 700 (TYP) VCC 10 HDSP-2000 DISPLAY (32 CHAR) DIN * C1 C2 C3 C4 C5 CK COLUMN 5 COLUMN 4 COLUMN 3 COLUMN 2 COLUMN 1 LEFTMOST CHARACTER LOCATION RIGHTMOST CHARACTER LOCATION 12 16 17 φ1 φ2 ADDR = A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS BUS DATA BUS MEMWR 74165 CLOCK ROW 7 DATA OUT 74165, RAM DATA IN RAM ADDRESS ROW 6 ROW 5 ROW 4 ROW 3 ROW 2 ROW 1 (001)(ADDR) (010)(ADDR) (011)(ADDR) (100)(ADDR) (101)(ADDR) (110)(ADDR) (111)(ADDR) RAM WRITE ADDRESS BUS DECODING: A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 COL COL COL COL COL 1 2 3 4 5 A7 0 1 A6 0 1 A5 0 1 A4 0 1 A3 0 1 RIGHTMOST CHARACTER LEFTMOST CHARACTER AN1016.11 Figure 11. Data Entry Timing for DECODED DATA CONTROLLER Agilent Technologies under the following part numbers: • Flashing Cursor – Left Entry Only HDSP-2470 – Controller with 64 character ASCII to 5 x 7 decoder • Data Out (≤ 32 characters only) HDSP-2471 – Controller with 128 character universal ASCII to 5 x 7 decoder HDSP-2472 – Controller with socket for user supplied custom coded ROM/PROM/ EPROM. All of the controllers have the following features: • Choice of character string length: 4 to 48 characters in increments of four characters • Four modes of data entry Left Entry Right Entry RAM Entry (≤ 32 characters only) Block Entry • Edit Functions Clear RIGHT Display Backspace ENTRY Cursor Forward Cursor Insert Delete LEFT ENTRY These controllers have been designed to eliminate the burden of data handling between keyboard, display, and microprocessor. The product data sheet describes the technical function of the controllers in detail. Interfacing the controller to microprocessor systems depends on the needs of the particular application. Figure 19 depicts a latched interface from a master microprocessor to the HDSP-247X series of controllers. These interfaces are utilized to avoid having the master processor wait for the controller to accept data. In sophisticated systems, it may be desirable to have the HDSP-247X controller handle all of the keyboard/display interface while the microprocessor reads edited messages from the controller DATA OUT port. This function can be achieved through the use of peripheral interface adapters (PIA) available from the microprocessor manufacturers. Figure 20 depicts a 6800 based system in which data may enter the display from either a keyboard or a microprocessor. This interface uses a 6821 PIA configured so that PB7 controls whether the microprocessor or keyboard enters data into the controller. The 6800 program is shown in Figure 21. Subroutine “LOAD” uses CA1 and CA2 to provide a data entry handshake that allows the 6800 to load data into the controller as fast as the controller can accept it. After the prompting message has been loaded, the microprocessor turns the control of data entry over to the keyboard. A signal from the keyboard (“ER” in the example) sets a flag within the 6821. Depending on how the 6821 is configured, the microprocessor 18 OBJECT CODE LOC SOURCE STATEMENTS B000 E500 E000 E002 02 00 E0 E400 E403 E405 E408 E409 E40A E40D E40F E410 E412 E413 E414 E415 E416 E418 E419 E41C E41D E41E E421 E422 E424 E425 E426 E429 11 0E 2A 7E 23 22 26 6F 06 7E 12 13 7D C6 6F D2 24 05 C2 7B D6 5F 0D C2 C9 F8 20 00 00 E5 DISPL DECDR EQU EQU 0B000H 0E500H ASCII DATA ORG DW DS 0E000H DATA 32 ORG LXI MVI LHLD MOV INX SHLD MVI MOV MVI MOV STAX INX MOV ADI MOV JNC INR DCR JNZ MOV SUI MOV DCR JNZ RET 0E400H D, DISPL+00F8H C, 32 ASCII A, M H ASCII H, DECDR/256 L, A B, 5 A, M D D A, L 80H L, A L00P3 H B L00P2 A, E 13 E, A C LOOP1 B0 LOAD E0 LOOP1 E0 05 LOOP2 80 1D E4 L00P3 12 E4 0D 05 E4 LOAD DE ← DISL + F8H LOAD DE WITH ADDRESS OF DISPLAY CORRESPONDING TO COLUMN 1 LEFTMOST CHARACTER C ← 32 HL ← ASCII LOAD HL WITH ADDRESS OF LEFTMOST ASCII SYMBOL A ← (HL) READ ASCII SYMBOL INTO A ASCII ← ASCII + 1 UPDATE ASCII WITH ADDRESS OF NEXT ASCII SYMBOL HL ← DECDR + A LOAD HL WITH ADDRESS OF DECODER ROM CORRESPONDING TO COLUMN 1 OF DESIRED ASCII SYMBOL B←5 A ← (HL) READ BYTE OF DECODED DATA FROM DECODER ROM (DE) ← A STORE BYTE OF DECODED DATA IN DISPLAY DE ← DE + 1 UPDATE DE WITH ADDRESS OF NEXT COLUMN IN DISPLAY HL ← HL + 80H UPDATE HL WITH ADDRESS OF NEXT COLUMN IN DECODER ROM B←B–1 B = 0? NO (LOOP 2) YES DE ← DE – 13 UPDATE DE WITH ADDRESS OF DISPLAY CORRESPONDING TO COLUMN 1 NEXT CHARACTER TO RIGHT C←C–1 C = 0? NO (LOOP 1) YES RETURN Figure 12. 8080A Microprocessor Program that Decodes a 32 Character ASCII String Prior to Loading into the DECODED DATA CONTROLLER VCC 8 6 4 10 3 11 13 1 12 2 9 5 C B A 1 5 4 7410 3 ADDRESS BUS 74197 A QA B A QB B C QC D CLEAR C/L QD A0 A1 A2 A3 A4 DATA BUS 6 7404 2 15 15 1 15 74393 1A 1QA 1QB 2 CL 1QC 1QD 13 2A 2QA 2QB 12 CL 2QC 2QD 4 1 6A 5A 4A 3A 2A 1A 74LS367 11 9 7 5 3 5A 4A 3A 2A 1A 12 10 6 4 2 3 4 5 6 11 10 9 8 13 6Y 11 5Y 9 4Y 7 3Y 5 2Y 3 1Y 74LS367 7404 1 3 14 12 10 6 4 2 1 6A 5A 4A 3A 2A 1A 13 6Y 11 5Y 9 4Y 7 3Y 5 2Y 3 1Y 74LS367 A0 A1 A2 A3 A4 A5 A6 R/W CS CS CS CS 2 3 4 5 6 7 8 7404 12 6 5 VCC 13 CS 10 CS D0 D1 D2 D3 D4 D5 D6 MCM6610 1 2 7410 13 23 22 21 20 19 18 17 16 15 14 12 11 A0 A1 A2 A3 A4 A5 A6 7 6 3 2 1 R9 R9 R0 R0 B 7 16 15 15 1 14 2 13 3 12 4 9 QB 8 QC 11 QD 7490 D4 D3 D2 D1 D0 MCM6674 11 RS1 10 RS2 8 RS3 7 6 5 4 3 2 1 CS WR Y B A 5 10 11 7410 9 4 3 2 1 0 74145 CS (NOTE 2) 15 A 14 B 13 C 12 D ST A B C 11 10 9 D4 D3 D2 D1 D0 3 φ (NOTE 1) 74S32 74151 1 2 8080A, 6800 INTERFACE: Figure 13. 8080A Microprocessor Interface to the 32 Character HDSP-2000 CODED DATA CONTROLLER 1 MHz CLOCK INPUT D6 D5 D4 D3 D2 D1 D0 14 12 10 6 4 2 2 3 K J S 5 74LS113 Q 11 12 13 K J Q 8 VCC MJE 210 (TYP) MR750 B A C HDSP-2000 DISPLAY (32 CHAR) * CK C1 C2 C3 C4 C5 1 2 3 4 5 10 DI AN1016.13 * DISPLAY IS OPERATED WITH PIN 1 IN THE UPPER RIGHT HAND CORNER 5 39 Ω 4 39 Ω 3 39 Ω 2 39 Ω 1 39 Ω 10 K (TYP) 12 8 S Q 9 10 NOTE 1: φ IS MICROPROCESSOR CLOCK NOTE 2: CS IS IORQ ANDED WITH THE I/O ADDRESS OF THE DISPLAY 1 4 Z 80 INTERFACE: 19 20 tWC PARAMETER ADDRESS tAW tCW tCH CHIP SELECT tDW tDH DATA tWP tWR WR (6800 OR 8080A INTERFACE) SYMBOL MIN. WRITE CYCLE tWC 390 ns WRITE DELAY tAW tCW 65 ns CHIP ENABLE TO WRITE DATA SETUP tDW 220 ns DATA HOLD WRITE PULSE tDH tWP 310 ns WRITE RECOVERY tWR 10 ns CHIP ENABLE HOLD tCH 20 ns 65 ns 20 ns φ (Z-80 INTERFACE ONLY) AN1016.14 Figure 14. Memory Write Timing for the 32 Character HDSP-2000 CODED DATA CONTROLLER 1 2 3 DISPLAY CLOCK ROW 1 ROW 2 ROW 3 ROW 4 ROW 5 ROW6 ROW 7 ROW 1 ROW 2 ROW 3 ROW 4 CHARACTER 1 ROW 6 ROW 7 CHARACTERS 2—32 224 CLOCK CYCLES 224 CLOCK CYCLES 4 0 1 2 3 4 5 6 0 1 COLUMNS ON COLUMNS OFF (LOAD) 2 3 4 5 6 COLUMNS ON COLUMNS OFF (LOAD) COLUMNS OFF (LOAD) AN1016.15 Figure 15. Timing Information for the 32 Character HDSP-2000 CODED DATA CONTROLLER can either test the flag or allow the flag to automatically interrupt the microprocessor. Subroutine “READ” would then be used to read the DATA OUT outputs from the controller into the microprocessor system. The microprocessor uses the CB1 input of the 6821 PIA to determine when to read each of the 34 data output words into the system. A similar PIA interface for the 8080A microprocessor is depicted in Figures 22 and 23. The HDSP-247X series of controllers are programmed to default to “Left Entry” mode for a 32 character string of displays. If some other entry mode or string length is desired, it is necessary to either load the appropriate control word from the microprocessor or to provide a control word during POWER ON RESET. The controller will read the DATA IN lines during RESET and interpret the contents as the control word. The circuit depicted in Figure 24 can be utilized to load any desired preprogrammed word into the HDSP247X controller, during power on. 12 2 9 5 C B A 1 2 7437 1 ADDRESS BUS 74197 A QA B A QB B C QC D CLEAR C/L QD A0 A1 A2 A3 A4 A5 A6 DATA BUS 3 7404 2 7404 4 1 1A1 2A4 1A2 2A3 1A3 2A2 1A4 2A1 19 1 19 1Y1 2Y4 1Y2 2Y3 1Y3 2Y2 1Y4 2Y1 74LS244 15 74393 1 1A 1QA 1QB 2 CL 1QC 1QD 13 2A 2QA 2QB 12 CL 2QC 2QD 3 2 17 4 15 6 13 8 11 1 6A 5A 4A 3A 2A 1A 3 4 5 6 11 10 9 8 18 3 16 5 14 7 12 1Y1 1Y2 1Y3 1Y4 2Y4 2Y3 2Y2 74LS244 2A4 2A3 2A2 1A1 1A2 1A3 1A4 2 17 4 15 6 13 8 18 3 16 5 14 7 12 9 13 6Y 11 5Y 9 4Y 7 3Y 5 2Y 3 1Y 74LS367 1 2 4 5 R/W CS CS CS CS A0 A1 A2 A3 A4 A5 A6 7440 2 3 4 5 6 7 8 VCC 6 7404 6 6 5 13 12 10 9 MCM68A10 13 CS 10 CS D0 D1 D2 D3 D4 D5 D6 24 4 5 7437 16 15 14 12 11 23 22 21 20 19 18 17 VCC 7440 CE R9 R9 R0 R0 B A 12 10 8 7490 9 QB 8 QC 11 QD QA 9 10 7437 8 7 6 3 2 1 14 VCC 5 9 4 D0 10 3 D1 11 2 D2 13 1 D3 14 15 D4 7 82S2708 A0 A1 A2 A3 A4 A5 A6 1 A7 23 A8 22 A9 20 8 7 6 5 4 3 2 CS 74151 Y 5 9 10 7437 4 3 2 1 0 74145 15 A 14 B 13 C 12 D D4 ST A B C 11 10 9 D2 D3 D0 D1 CS (NOTE 2) φ (NOTE 1) B 8080A, 6800 INTERFACE: 74S32 1 WR 3 A 2 Figure 16. 6800, 8080A, and Z-80 Interface to the 128 Character HDSP-2000 CODED DATA CONTROLLER 8 6 VCC 4 10 3 11 13 1 2 MHz CLOCK INPUT D6 D5 D4 D3 D2 D1 D0 14 12 10 6 4 2 K J S 5 74LS113 Q 11 12 13 K J Q 11 5 36 Ω 4 36 Ω 3 36 Ω 2 36 Ω 1 36 Ω 100 Ω (TYP) B A C HDSP-2000 DISPLAY 8 (128 CHAR) VB * CK C1 C2 C3 C4 C5 1 2 3 4 5 10 VCC DI AN1016.16 * DISPLAY IS OPERATED WITH PIN 1 IN THE UPPER RIGHT HAND CORNER 2N6285 (TYP) 12 8 S Q 9 10 NOTE 1: φ IS MICROPROCESSOR CLOCK NOTE 2: CS IS IORQ ANDED WITH THE I/O ADDRESS OF THE DISPLAY 2 3 4 Z 80 INTERFACE: 21 22 PROM ADDRESS 080 090 0A0 0B0 0C0 0D0 0E0 0F0 100 110 120 130 140 150 160 170 180 190 1A0 1B0 1C0 1D0 1E0 1F0 FF FF E0 EE EE FE E6 F6 F1 F1 E0 F1 F1 F1 E6 F9 F1 F1 E0 F3 E1 F1 E4 F1 FF EE E4 E4 E4 EE E0 ED F0 F5 E4 EC EA F1 E0 F3 F0 F5 E4 E4 F1 F1 EE F1 E4 EE EA EE FE FE F0 E0 E4 F1 EA F1 E9 F1 F0 E0 E4 F1 EA E1 E9 F1 F6 F6 E1 EE EA EE EE EE E0 E0 E1 F1 EA F1 F1 F1 E0 E0 E1 F1 FF E1 F0 F0 EE EF E8 EE E4 E2 FE FF E1 E4 E4 F5 EF E6 E9 E4 E1 E4 E2 F5 F4 EA E9 E4 ED FF FF E0 F8 FF FF F1 E0 E0 F1 E5 F9 F0 F0 F1 E0 E0 FB E2 E2 FE F0 F1 EE F1 200 210 220 230 HEXIDECIMAL DATA 240 250 260 270 E0 EE E4 E0 FF E0 E4 E0 EE EE ROW 1 280 EE E1 FF E4 EE EE FF FF FF FF 290 E8 EC E2 E8 E4 E0 E0 E0 E0 E0 2A0 E6 FF EE EE E0 EC E2 E0 E8 EE 2B0 FF EF F1 EE E1 F1 F0 F1 F1 EE 2C0 F1 F1 F1 F1 FF EE E0 EE E4 E0 2D0 E2 ED F0 E4 E1 F0 EC E0 E0 E0 2E0 E0 E0 E0 F1 E0 E2 E4 E8 E8 EA 2F0 E1 F1 E8 E4 E0 E4 F5 E4 F1 F1 ROW 2 300 EA E1 F1 E4 F1 F1 F5 F1 F1 F5 310 F4 EC E4 E4 F5 E4 E0 E0 E0 E1 320 E8 E1 F1 F1 EC EC E4 E0 E4 F1 330 F0 F0 F1 E4 E1 F2 F0 FB F9 F1 340 F1 F1 F F1 E1 E8 F0 E2 EA E0 350 E5 F3 F0 E0 E0 F0 E4 E0 E0 E0 360 E0 E0 E0 F1 E0 E4 E4 E4 F5 F5 370 E2 F1 FE E2 E0 E4 EE E8 FB F1 ROW 3 380 EA E1 EA EE F0 F1 F5 F1 F1 F5 390 F4 E8 E8 E2 EE E4 E0 E0 E0 E2 3A0 F0 E2 F1 F1 EC E0 E8 FF E2 E1 3B0 F0 F0 F1 E4 E1 F4 F0 F5 F5 F1 3C0 F1 F1 EA EA E2 E8 E8 E2 F1 E0 3D0 E4 F3 F6 EC E1 F2 E4 FA F6 EE 3E0 F1 F1 F1 F1 FF E4 E4 E4 E2 EA 3F0 F1 FF E0 F5 ED FE E2 F9 F1 F1 E0 F9 F5 F0 E0 F6 F1 F1 E0 F1 F5 F0 E0 F0 FF FF E0 EE EE F0 E0 F0 F0 F7 E4 E4 F1 F1 E1 F3 F0 F1 E4 E4 FF F5 EF ED F0 F1 E0 E4 F1 F2 F1 E1 F0 EE E4 EE F1 ED EF E1 E4 F7 E0 EE EE FE F9 F9 E4 F5 E0 F0 E9 F4 F1 F0 E4 F5 E0 F0 E9 F2 F9 F0 FF EE E0 FF FE F1 F6 F0 E1 F0 EA E6 F0 EE F1 F0 E1 F5 FF E1 F0 E1 F0 EE E1 F5 EA F1 F1 F1 F1 E1 FF EE EA EE EE EE EE FE EF FD EE F2 E9 E4 F3 E4 E4 F1 E5 FF E9 E4 F1 E4 E2 F1 FE E2 E9 E4 F3 E5 E1 EE E4 E2 FE E4 ED E2 F5 F5 E4 E1 FC F1 F1 F1 FB F8 E8 E1 F0 F1 FF F1 F1 F0 F3 F1 F0 F1 F0 F3 FF E0 E3 EE FF EE EE ED F4 EA E8 FE FC EA EE F1 F8 EA F5 F1 F0 EA E4 F1 F0 EA F2 F1 F0 E4 E4 EA E0 FB ED EE F0 E4 E4 E4 FF FF F0 E4 F3 F1 ED F1 EA E1 E0 E8 F1 F5 E1 F5 EA E1 E0 F0 F1 FB F1 F5 FB E1 E0 F0 EF F1 EE EA E9 E4 E8 EE FF E4 F9 EA E5 EA E8 F1 F1 EA F1 E4 E1 F1 E4 F1 F1 F1 F1 EA E1 FF E2 EE F1 F1 F1 F1 FF EE E2 EF E4 E4 E4 EF E2 E4 E2 E1 E4 E4 E4 E1 E4 E4 E4 E2 E4 E4 E4 F1 E0 E4 E8 EC EE E4 EE EE FF E8 FF E0 E1 E4 E1 E2 E0 E4 EE EC E1 E8 E1 E4 E0 E0 F5 EC F1 F0 F1 E8 FF E4 E4 E0 EE FF EE FF F5 FF FF EC F8 E8 F4 E8 EE F1 E4 EC F4 E8 F8 E4 E4 F1 E4 E8 F2 E8 F4 E4 E0 EE E0 F0 F1 EE F2 E2 E4 FD EC F0 F0 E4 E4 E0 F5 F1 EC E8 F0 E2 E4 E4 EE F1 E8 E4 F0 E1 E4 E4 E4 FF F0 E2 FF E0 EE E4 FF FD FF E0 F5 E2 F5 E2 E8 F5 E0 FF F1 E2 F5 E4 E4 F5 E0 E0 F1 E2 F5 E4 E0 FF E0 E0 F1 EE F5 E8 F5 F7 E0 E1 F3 E0 F9 E0 FB F5 E0 E2 F1 E0 F1 E0 F1 F5 EC E4 F1 E0 F1 E0 EE FF EC E8 F1 E0 F1 E0 F5 F7 E4 E2 F1 E0 F1 F5 F1 F1 E8 E4 F1 E0 F1 EA F1 F1 F0 E0 F1 E0 F1 F5 EE FF E0 E4 EE FF EE EA ROW 4 ROW 5 ROW 6 ROW 7 Figure 17. 82S2708 PROM Listing Display Power Dissipation The HDSP-2000 combines a significant amount of logic and display capability in a very small package. As such, on-board power dissipation is relatively high and thermal design of the display mounting becomes an important consideration. The HDSP-2000 is designed to permit operation over a wide range of temperature and supply voltages. The design of a heat sink to maintain a junction temperature of less than 125°C for a multiple package system where every electrical input operates at maximum voltage and current would be difficult at best. However, in virtually all applications, the actual power dissipation is only a small fraction of the maximum power dissipation, since VCOL is less than 5.25 V, only a fraction of the 35 LEDs are on at any time, and the duty factor is never 20%. The calculation of power dissipation is important since the result is largely a function of external circuit parameters. The minimization of power dissipation will reduce the amount of heat sinking required for the displays. Furthermore, by the Arrhenius model, the display reliability is increased by 40% for a 10°C reduction in junction temperature. Thus, reduced power dissipation or better heat sinking can also increase the reliability of the display system. Calculation of power dissipation in the HDSP-2000 display family can be made using the following formulas: PD = P(ICC) + P(IREF) + P(ICOL) (7) where P(ICC) = ICC1 VCC when VCC is applied continuously to the display P(ICC) = ICC1 VCC (t + T)/ (t + T + TB) (9) when VCC is turned off during the time TB where P(IREF) = (ICC2 – ICC1) VCC (n/35) (10) when VB is connected to VCC and VCC is applied continuously to display P(IREF) = 5 (ICC2 – ICC1) VCC (n/35) D.F. (11) when VB is logical 0 during times t and TB where (8) P(ICOL) = 5 ICOL VCOL (n/35) D.F. (12) 23 where n = average number of diodes illuminated per character D.F. = column on time from equation (1) or (5) ICC1 = ICC (VB = 0.4 V) ICC2 = ICC (VB = 2.4 V) P(ICC) is the power which is dissipated in the logic within the shift register. P(ICC) is constant regardless of n, or D.F. as long as voltage is applied to the VCC pin. However, for low D.F., ICC can be switched off during the time the display is blanked. P(IREF) is the power dissipated in the logic to drive the current mirror output. Thus, if the output of the shift register and the VB input are both logical 1, P(IREF) will be dissipated. P(ICOL) is the power dissipated within the LEDs and the constant current outputs during the time that VCOL is applied and the LEDs are on. As can be seen from formulas (7) through (12) there are several techniques by which total power dissipation can be reduced: • Reduce n • Reduce VCOL • Reduce D. F. • Reduce VCC • Turn off VCC when display is blanked For most applications, n ≤ 20 dots. For example, the HDSP-2470 character generator has 3 characters with 20 dots on (#, @, B), 1 character with 19 dots on (zero), and 6 characters with 18 dots on (A,D,E,M,R,W). With custom PROM programming these 4 symbols (#, @, B, zero) can be modified to reduce the total number of dots on to 18 or less. The average of all 36 alphabetic and numeric symbols is 14.7 dots on. The calculations assume that every character has the same number of illuminated dots. This assumption can overstate the maximum power dissipation if the application includes a fixed number of spaces in the display. Above 2.4 V VCOL for standard red devices and 2.75 V VCOL for GaP devices, ICOL is nearly constant. While it is possible to operate the columns of the HDSP-2000 display using fullwave rectified unregulated DC, lower power dissipation can be achieved by using the regulated VCC supply. Then, VCOL is equal to VCC minus the collector to emitter saturation voltage across the column switching transistors. Since the minimum recommended VCOL is 2.4 V or 2.75 V, PNP Darlington transistors with a silicon diode in series with the emitter can be used to lower the power dissipation within the display. The time averaged luminous intensity for the display is equal to the peak luminous intensity on the data sheet times D.F. Thus, reduction in D.F. will also reduce the time averaged luminous intensity as well as power dissipation. For most indoor applications, a D.F. of 10% for standard red and 5% for GaP displays will provide satisfactory luminous intensity. For example, the 40 character HDSP-2470 system has a D.F. of 11.6%. However, a D.F. of 17% or higher is recommended for sunlight viewable applications for the GaP displays. The HDSP-2000 family of alphanumeric displays are specified for operation with a 5% tolerance 5 volt supply. A tighter tolerance supply will also reduce the power dissipation in the display. ICC can be switched off during the time the display is blanked. Thus, power would be applied to the display; the shift register would be loaded with information; the columns would be turned on; and then the column current, VB, and VCC would be switched off until the next column refresh cycle. For low D.F., this can significantly reduce the power dissipation within the display. As D.F. increases, the display is blanked for a smaller portion of the refresh cycle and the power reduction is reduced. When the blanking time goes to zero, the power reduction also goes to zero. For example, the maximum power dissipation for a four character HDSP-2000 display (n = 20, VCOL = 3.5 V, VB = 2.4 V, D.F. = 17.5%, VCC = 5.25 V) can be calculated as shown below: P(ICC) = (60 mA) (5.25 V) = 315 mW (13) P(IREF) = 5 (95 mA – 60 mA) (5.25 V) (20/35) (0.175) = 92 mW (14) P(ICOL) = 5 (410 mA) (3.5 V) (20/35) (0.175) = 718 mW (15) PD = P(ICC) + P(IREF) + P(ICOL) = 1125 mW (16) DO0 DO1 DO2 DO3 A2 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 A0 A1 8 74LS37 9 10 6 (1) HDSP-2470 HDSP-2471/2 39 34 27 (22) 28 (11) 31 (19) (13) 32 (21) 29 33 (23) (15) 1 (7) 30 21 (3) (17) 23 22 (7) (5) 24 7 (9) 1 µF 40 VCC 26 VDD T1 P17 IRQ P10 P11 P12 P13 P14 P15 P16 T0 HDSP2471/2 20 19 HDSP2470 10 WR 11 ALE HDSP2470 BUS7 VSS 18 17 16 15 14 13 12 38 P27 37 P26 36 P25 INTEL 8048 P20 P21 P22 P23 P24 EA XTAL1 BUS6 BUS5 6 MHz BUS4 3 XTAL2 BUS3 BUS2 BUS1 4 BUS RESET 0 + 2 35 VCC 1K 20 pF 20 pF VCC (25) (6) (26) (24) (2) (20) (18) (16) (14) (12) (10) (8) 2 1 12 13 74LS37 11 HDSP2471/2 74 LS37 3 4 5 74LS37 6 2 15 1 6 5 4 3 14 13 12 CLK QH CI S/L H G F E D C B 74LS165 9 GND VCC 0 1 2 3 74LS145 13 C 5 14 B 15 4 A HDSP-2470 8 7 6 5 4 3 2 1 23 22 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 12 MCM HDSP68308 OR 2471/2 EQUIV D0 D1 D2 D3 D4 D5 D6 CS 9 10 11 13 14 15 16 18 19 21 20 Figure 18. HDSP-2470/-2471/-2472 DISPLAY PROCESSOR CONTROLLER READY CHIP SELECT DATA IN RAM ADDRESS A3 A4 RESET DATA VALID COLUMN ON VB, DISPLAY BLANK DATA OUT DO4 DO5 DO6 1 2 3 4 1K 5 (TYP) 6 36 Ω VCC VCC TIP 105 (TYP) 100 Ω (TYP) (T) (R) (Q) (P) (S) (O) (N) (L) (M) (J) (K) (B) (C) (D) (E) (F) (G) (H) (I) VCC (A) AN1016.18 GND VCC CLOCK DISPLAY DATA COLUMN5 COLUMN1 COLUMN2 COLUMN3 COLUMN4 VB, DISPLAY BLANK 24 25 8080A INTERFACE CS* WR 74LS10 6800 INTERFACE 3 VMA 6 4 2 5 CS* 74LS10 ADDRESS BUS A4 A3 A2 A1 A0 VCC ONLY REQUIRED FOR RAM MODE 74LS10 14 6D 6Q 15 13 5D 5Q 12 11 4D 4Q 10 6 3D 3Q 7 4 2D 2Q 5 1 3 1D 1Q 2 12 2 9 13 1 CL 74LS10 HDSP 12470/1/2 (25) (9) (7) (5) (3) A4 A3 A2 A1 A0 CONFIGURATION a (22) LEFT, RIGHT OR BLOCK MODES 1 12 2 13 74LS10 *CS IS A LOGICAL COMBINATION OF HIGH ORDER ADDRESS BITS THAT DISTINGUISH THE ADDRESS OF THE HDSP-2470/1/2 FROM THE REST OF THE MICROPROCESSOR SYSTEM. READY b a (1) CS 9 8 10 11 74LS10 CONFIGURATION b 1 VCC DATA BUS D7 D6 D5 D4 D3 D2 D1 D0 18 17 14 13 8 7 4 3 11 CL BD 7D 6D 5D 4D 3D 2D 1D CL 8Q 7Q 6Q 5Q 4Q 3Q 2Q 1Q 74LS273 19 16 15 12 9 6 5 2 (4) (23) (21) (19) (17) (15) (13) (11) DI 7 DI 6 DI 5 DI 4 DI 3 DI 2 DI 1 DI 0 AN1016.19 Figure 19. Latched Interface to the HDSP-2470/-2471/-2472 DISPLAY PROCESSOR CONTROLLER 26 26 27 28 29 30 31 32 33 DATA BUS VMA-A15 A3 A13 A0 A1 R/W φ2 RESET IRQ 22 24 23 36 35 21 25 34 37 D7 D6 D5 D4 D3 D2 D1 D0 CS0 CS1 CS2 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 CB1 17 16 15 14 13 12 11 10 18 74LS132 9 19 8 CB2 10 VCC + 6 RESET 8 10 12 14 16 18 20 2 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DATA VALID 20 µF 1 K 74LS157 9 PA7 8 PA6 7 PA5 6 PA4 RS0 RS1 R/W 14 11 5 2 13 10 6 3 1 15 4A 3A 2A 1A 4B 3B 2B 1B SEL ST 14 11 5 2 13 10 6 3 1 15 4A 3A 2A 1A 4B 3B 2B 1B SEL ST E 4Y 3Y 2Y 1Y 12 9 7 4 4 23 21 19 HDSP2470/71/72 A DISPLAY PROCESSOR B CONTROLLER C C D D E E DI 7 DI 6 DI 5 DI 4 74LS157 RESET IRQ B 5 PA3 4 PA2 3 PA1 2 PA0 CA1 CA2 4Y 3Y 2Y 1Y 12 9 7 4 17 15 13 11 40 HDSP2416/24/32/40 DISPLAY* DI 3 DI 2 DI 1 DI 0 A B F F G G H H I I J J K K L L M M N N O O P P Q Q VB COLUMN1 COLUMN2 COLUMN3 COLUMN4 COLUMN5 CLOCK DISPLAY DATA VCC GND 22 READY 39 22 K 1 2 1000 pF VCC MOTOROLA 6821 13 3 4 1 2 5 3 4 5 74LS132 6 1 CS 11 B1 B2 A1 A2 CL Q 6 *16, 24, 32 OR 40 CHARACTER HDSP-2000 DISPLAY BOARD DESIGNED TO INTERFACE TO THE HDSP2470/71/72 DISPLAY PROCESSOR CONTROLLER 74LS122 7 1000 pF ER D6 D5 D4 D3 D2 D1 D0 ST MICROSWITCH 61SW12-1 KEYBOARD Figure 20. 6800 Microprocessor Interface Utilizing a 6820 PIA for an HDSP-2470/-2471/-2472 Alphanumeric Terminal AN1016.20 27 * PORT CONFIGURATION: * 1. PORT A: PA0-PA7 OUTPUTS TO DATA IN OF HDSP-247X * CA1 (INPUT) MODE 00 SET FLAG NEG EDGE OF READY * CA2 (OUTPUT) MODE 100 CLEARED MPU READ PRA, SET * NEG EDGE OF READY * 1. PORT B: * PB0-PB6 INPUTS DATA TO 6800 FROM DATA OUT OF HDSP-247X * CB1 (INPUT) MODE 00 SETS FLAG NEG EDGE OF DATA VALID * CB2 (INPUT) MODE 000 SETS FLAG NEG EDGE OF ER KEY * CB2 (INPUT) MODE 001 SETS FLAG NEG EDGE OF ER KEY CAUSING IRQ * PB7 (OUTPUT) LOW ENABLES PA0-PA7 TO MUX * HIGH ENABLES KEYBOARD TO MUX LOC OBJECT CODE SOURCE STATEMENT 8008 8008 8009 800A 800A 800B PRA DRA CRA PRB DRB CRB EQU EQU EQU EQU EQU EQU $8008 $8008 $8009 $800A $800A $800B 0000 MESSAGE ORG RMB $0000 2 0100 0101 0102 STATUS CURSOR DATA ORG RMB RMB RMB $0100 1 1 32 ORG LDX LDA CLR INC LDA BPL CMP HLS LDA LDA AND STA LDA BPL INX DEC BNE LDA AND STA RTS $0400 I, STATUS E, PRB READ X ← ADDRESS OF STATUS POINT TO ADDRESS OF DATA DESTINATION FORCE CA2 LOW; CLEAR CB1 FLAG CLEAR INTERRUPT REQUEST FROM IRQB B←0 WAIT FOR NEXT DISPLAY DATA OUTPUT CYCLE B←B+1 WAIT FOR DATA VALID A7 ← CB1 FLAG SET ON NEGATIVE EDGE OF DATA VALID CB1 FLAG CLEARED? YES (LOOP 2) NO 0400 0403 0406 0407 0408 040B 040D 040F 0411 0413 0416 0418 041A 041D 041F 0420 0421 0423 0426 0428 042A CE B6 5F 5C B6 2A C1 23 C6 B6 84 A7 B6 2A 08 5A 26 B6 84 A7 39 042B 042D 042F 0430 0432 0434 0437 043A 043D 043F 0441 0443 DE A6 08 81 27 B7 7D B6 2A 20 DF 39 0100 800A READ LOOP1 LOOP2 800B FA 0A F2 21 800A 7F 00 800B FB LOOP3 LOOP4 F0 800A 7F 00 00 00 FF 0D 8008 8008 8009 FB EC 00 LOAD LOOP10 LOOP11 ENDL LDX LDA INX CMP BEQ STA TST LDA BPL BRA STX RTS A B B A B B A A A A B ≤ 10 CLEAR CB1 AND CB2 NO E, CRB LOOP2 I, 10 LOOP1 I, 33 E, PRB I, $7F X, 0 E, CRB LOOP4 B = 33 WAIT FOR DATA VALID LOAD A7 ← PRB • 7FH READ DATA OUT WORD READ AND CLEAR CB1 STORE IN RAM 7F 7F 86 B7 86 B7 86 B7 86 B7 051A 051B 051E OE 7F BD 0521 0524 0526 0529 042B 052E 7D 86 B7 86 B7 0F 8009 800B FF 8008 24 8009 80 800A 04 800B START ORG CLR CLR LDA STA LDA STA LDA STA LDA STA NOT DONE A ← (X) READ ASCII CHARACTER B A A A LOOP3 E, PRB I, $7F X, 0 A D, MESSGE X, 0 READ DATA WAIT FOR DATA VALID A7 ← CB1 FLAG SET ON NEGATIVE EDGE OF DATA VALID A A I, $FF ENDL E, PRA E, PRA E, CRA LOOP11 LOOP10 D, MESSGE LAST WORD IN STRING JUMP WHEN DONE CLEAR CA1 AND CA2 WAIT A A A A A A A A $0500 E, CRA E, CRB I, $FF E, DRA I, $24 E, CRA I, $80 E, DRB I, $04 E, CRB LAST CHARACTER? DENOTED BY FFH YES (LOOP 4) A X←X+1 YES CB1 FLAG CLEARED? (ENDL) NO NO X←X+1 READ NEXT DATA OUT WORD MESSAGE ← X STORE ADDRESS OF NEXT CHARACTER STRING B←B–1 RETURN B = 0? (LOOP 3) * PROCEDURE TO LOAD HDSP-247X SYSTEM CLI 800A CLR E, PRB DISABLE KEYBD FROM MUX 042B JSR E, LOAD 800A 80 800A 0C 800B X ← MESSAGE POINT TO FIRST ASCII CHARACTER (X) ← A STORE DATA OUT WORD WAIT FOR DATA VALID NO 0500 0503 0506 0508 050B 050D 0510 0512 0515 0517 YES (LOOP 1) PRA ← A OUTPUT DATA WORD TO DISPLAY YES A ← PRB • 7FH READ DATA OUT WORD FORCE CA2 LOW CLEAR CA1 FLAG (X) ← A STORE DATA OUT WORD RETURN * PROCEDURE TO READ DATA OUT OF HDSP-247X SYSTEM TST E, PRB CLEAR CB1, CB2 LDA A I, $80 STA A E, PRB ENABLE KEYBD TO MUX LDA A I, $0C STA A E, CRB ENABLE IRQ, SEI IRQ CAUSE JSR TO READ Figure 21. 6800 Microprocessor Program that Interfaces to the Circuit shown in Figure 14. WAIT FOR READY YES A7 ← CA1 FLAG SET ON NEGATIVE EDGE OF READY CA1 FLAG CLEARED? (LOOP 11) NO (LOOP 10) 28 4 5 27 28 29 30 31 32 33 34 DATA BUS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 D7 D6 D5 D4 D3 D2 D1 D0 PC2 A4 A1 A0 I/O RD I/O WR SYSTEM RESET 6 8 9 5 36 35 25 24 23 22 21 20 19 18 6 16 (STB) 74LS132 9 8 10 8 10 12 14 16 18 20 DO6 DO5 DO4 DO3 DO2 DO1 DO0 2 DATA VALID 74LS157 14 11 5 2 13 10 6 3 1 15 A1 A0 RD WR 4A 3A 2A 1A 4B 3B 2B 1B SEL ST 4Y 3Y 2Y 1Y 12 9 7 4 4 23 21 19 RESET 14 11 5 2 13 10 6 3 1 15 PC4 PC6 PC7 13 17 15 13 11 1000 pF 13 3 4 1 2 5 12 13 3 74LS132 + 74LS132 1 2 VCC 20 µF 74LS00 A DI 3 DI 2 DI 1 DI 0 A B B C C D D E E F F G G H H I J K L L M M N N O O P P Q Q VB COLUMN1 COLUMN2 COLUMN3 COLUMN4 COLUMN5 CLOCK DISPLAY DATA VCC GND 22 READY 10 (OBF) VCC 3 4Y 3Y 2Y 1Y 12 9 7 4 10 (ACK) 22 K 1 11 2 4A 3A 2A 1A 4B 3B 2B 1B SEL ST DI 7 DI 6 DI 5 DI 4 HDSP2416/24/32/40 ALPHANUMERIC DISPLAY* HDSPI 2470/71/72 DISPLAY PROCESSOR J CONTROLLER K 74LS157 1 PA3 2 PA2 3 PA1 4 PA0 INTEL 8255A INTERRUPT REQUEST RESET 74LS132 37 PA7 38 PA6 39 PA5 40 PA4 CS 6 11 B1 B2 A1 A2 CL Q 4 5 6 1 CS 74LS00 6 *16, 24, 32 OR 40 CHARACTER HDSP-2000 DISPLAY BOARD DESIGNED TO INTERFACE TO THE HDSP2470/71/72 DISPLAY PROCESSOR CONTROLLER AN1016.22 74LS122 7 1K 1000 pF ER D6 D5 D4 D3 D2 D1 D0 ST MICROSWITCH 61SW12-1 KEYBOARD Figure 22. 8080A Microprocessor Interface Utilizing an 8255 PIA for an HDSP-2470/-2471/-2472 Alphanumeric Terminal Similarly, a typical power dissipation for a four character HDSP-2000 display (n = 15, VCOL = 3.0 V, D.F. = 17.5%, VCC = 5.00 V) can be calculated as: P(ICC) = (45 mA) (5.00 V) = 225 mW (17) P(IREF) = 5 (73 mA – 45 mA) (5.00 V) (15/35) (0.175) = 52 mW (18) P(ICOL) = 5 (335 mA) (3.0 V) (15/35) (0.175) = 377 mW (19) PD = P(ICC) + P(IREF) + P(ICOL) = 654 mW (20) Some typical power dissipations for other values of n, VCOL, D.F., VCC, are shown in Figure 25. Note that at a D.F. of 17.5%, which would be appropriate for a sunlight viewable application, the 29 * * * * * * * * * * * * * * * PORT CONFIGURATION: 1. PORT A (MODE 1 OUTPUT): PA0-PA7 OUTPUTS TO DATA IN OF HDSP-247X PC7 (OBF) OUTPUT; TO CHIP SELECT PC6 (ACK) INPUT; TO READY FLAG PC7 (OBF) CLEARED BY OUTPUT; SET BY READY READ STORE MACHINE STATUS ON STACK 2. PORT B (MODE 1 INPUT): PB0-PB6 INPUTS DATA FROM DATA OUT OF HDSP-247X PC2 (STB) INPUT; LOADS DATA ON NEG EDGE OF DATA VALID FLAG PCO (INTR) CLEARED BY INPUT; SET BY DATA VALID C ← 32 HL ← ADDRESS OF STAT POINT TO ADDRESS OF DATA DESTINATION 3. PORT C: PC4 OUTPUT; LOW ENABLES PA0-PA7 TO HDSP-247X HIGH ENABLES KEYBOARD TO HDSP-247X LOC OBJECT CODE SOURCE STATEMENTS 000C 000D 000E 000F PA PB PC CNTRL EQU EQU EQU EQU 0CH 0DH 0EH 0FH ASCII TEXT ORG DW DS 0E000H TEXT 32 STAT ADDR DATA ORG DB DB DS 0E100H 0 0 32 ORG DI PUSH PUSH PUSH MVI LXI IN MVI IN INR RAR JNC MVI CMP IN JNC MOV INX IN RAR JNC IN DCR JNZ MOV POP POP POP El RET 0E400H E000 02 E002 00 E0 E100 00 E101 00 E102 00 E400 E401 E402 E403 E404 E406 E409 E40B E40D E40F E410 E411 E414 E416 E417 E419 E41C E41D E41E E420 E421 E424 E426 E427 E42A E42B E42C E42D E42E E42F F3 F5 E5 C5 0E 21 DB 06 DB 04 1F D2 3E B8 DB D2 77 23 DB 1F D2 DB 0D C2 77 C1 E1 Fl FB C9 E430 E433 F434 E436 E439 E43B E43C E43E E43F E442 E445 E446 E449 2A 7E FE CA D3 23 DB 17 D2 C3 23 22 C9 E44A E44C E44E E450 E452 E454 3E D3 3E D3 3E D3 READ 20 00 0D 00 0E 0D 0A 0D 0B El LOOP1 LOOP2 E4 E4 LOOP3 0E LOOP4 1E 0D E4 1C E4 00 E0 FF 45 0C E4 0E LOAD LOOP5 LOOP6 3C 33 E4 E4 00 E0 ENDL A7 0F 0C 0F 05 0F START LHLD MOV CPI JZ OUT INX IN RAL JNC JMP INX SHLD RET MVI OUT MVI OUT MVI OUT PSW H B C, 32 H, STAT PB B, 0 PC B LOOP2 A, 10 B PB LOOP1 M, A H PC LOOP4 PB C LOOP3 M, A B H PSW READ PB CLEAR INTR FLAG (PC0) B←0 LOAD A0 ← INTR FLAG SET ON NEGATIVE EDGE OF DATA VALID WAIT FOR DATA VALID YES WAIT FOR NEXT DISPLAY DATA OUTPUT CYCLE B←B+1 INTR FLAG CLEARED? (LOOP 2) LAST CHARACTER? DENOTED BY FFH A ← PB CLEAR INTR FLAG (PC0) B ≤ 10 WAIT UNTIL INTR IS SET YES A, 0A7H CNTRL A, 0CH CNTRL A, 05H CNTRL (HL) ← A STORE DATA OUT WORD ASCII ← HL HL ← HL + 1 RETURN PA ← A OUTPUT DATA WORD TO DISPLAY WAIT UNTIL INTR IS SET WAIT FOR DATA VALID YES A0 ← INTR FLAG SET ON NEGATIVE EDGE OF DATA VALID READ NEXT DATA OUT WORD INTR FLAG CLEARED? (LOOP 4) FIRST WORD OF MESSAGE E45D 3E E45F D3 E461 FB 09 0F HL ← HL + 1 A7 ← OBF FLAG (PC7) SET ON NEGATIVE EDGE OF READY A ← PB CLEAR INTR FLAG (PC0) CHECK TO SEE IF DONE OUTPUT TO DISPLAY WAIT NEXT WORD WAIT FOR READY C←C–1 NO (LOOP 3) YES HL ← A STORE LAST DATA OUT WORD CLEAR INTE A OBF FLAG CLEARED? YES (LOOP 6) NO PA OUTPUT, PB INPUT RESTORE MACHINE STATUS FROM STACK SET INTE B RETURN E456 3E 08 E458 D3 0F E45A CD 30 HL ← HL + 1 (LOOP 1) NO WAIT UNTIL STATUS WORD STORE IN RAM STORE LAST WORD YES (ENDL) NO C = 0? LOOP6 LOOP5 H ASCII NOT DONE A ← (HL) READ ASCII CHARACTER NO FIRST WORD CLEAR INTR NO ASCII A, M 0FFH ENDL PA H PC HL ← ASCII POINT TO FIRST ASCII CHARACTER * PROCEDURE TO LOAD HDSP-247X SYSTEM MVI A, 08H OUT CNTRL ENABLE A SIDE OF MUX E4 CALL LOAD * PROCEDURE TO READ DATA OUT OF HDSP-247X SYSTEM MVI A, 09H OUT CNTRL ENABLE B SIDE OF MUX El INT MUST CALL READ Figure 23. 8080A Microprocessor Program that Interfaces to the Circuit shown in Figure 17. (LOOP 5) 30 VCC 11 DESIRED MODE, XX* 5 2 DI7 DI6 DI5 DI4 can be reduced .32 W and the typical power dissipation can be reduced to 0.20 W for the GaP displays. 74LS157 14 13 10 6 3 1 15 4A 3A 2A 1A 4B 4Y 3Y 3B 2Y 2B 1Y 12 (4) 9 (23) 7 (21) 4 (19) DI7 DI6 DI5 DI4 1B HDSP2470/1/2 SEL ST DESIRED LENGTH, YYYY* DI3 DI2 DI1 DI0 11 5 2 13 10 6 3 1 15 4A where TPIN = temperature of hottest pin 3A 2A 1A 4Y 4B 2Y 3B 3Y 2B 1Y 12 (17) 9 (15) 7 (13) 4 (11) DI3 DI2 DI1 DI0 1B SEL ST (1) CS READY For operation at the maximum temperature of 85°C, it is important that the following criteria be met: a. TPIN ≤ 100°C 74LS157 14 Heat Sinking Considerations CS (22) READY *SEE HDSP-2470/1/2 DATA SHEET AN1016.24 Figure 24. External Circuitry to Load a Control Word into the HDSP-2470/2471/-2472 Alphanumeric System upon Request b. TJ ≤ 125°C The thermal resistance IC junction to case, ΘJC, or IC junction to pin, ΘJ-PIN, is shown in Table 2. Using these factors, it is possible to determine the required heat sink power dissipation capability and associated power derating through the following equations: T* = Θ*A PD + TA (21) TJ = T* + ΘJ* PD (22) where * = Pin or Case maximum power dissipation can be reduced to under 1.0 W, while the typical power dissipation can be reduced to 0.60 W. In most indoor ambients, the D.F. can be reduced to 10% for standard red and 5% for GaP displays. Under these conditions the maximum power dissipation is 0.72 W or 0.52 W and the typical power dissipation is 0.43 W or 0.34 W. Thus, in power sensitive applications, GaP displays can be used to conserve power. Turning off VCC during the time the display is blanked can further reduce the power dissipation. In this manner the maximum power dissipation Table 2. Device Thermal Resistance Device HDSP-2000 Series HDSP-2300 Series HDSP-2490 Series ΘJC 20°C/W 7.5°C/W 7.5°C/W ΘJ-PIN 25°C/W 10°C/W 13°C/W For example, given ΘPIN-A of 35°C/W an ambient temperature of 60°C, and the operating conditions shown in equations (13), (14), and (16) the TPIN and TJ for the HDSP-2000 family can be calculated as shown below: TPIN = (35°C/W) (1.12 W) + 60°C = 99°C (23) TJ = 99°C + (25°C/W) (1.12 W) = 99°C + 28°C = 127°C (24) Heat sink design for the HDSP-2000 family of displays can be accomplished in a variety of ways. For single line applications, a maximum metalized printed circuit board such as shown in Figure 26 can be used. For example, the HDSP-2416/-2424/ -2432/-2440 display boards consist of 16, 24, 32 or 40 characters of HDSP-2000 displays mounted on a maximum metalized printed circuit board. The HDSP-2432 printed circuit board is 2.3" x 6.4" and has a ΘPIN-A of about 45°C/W per package for a 1/2 ounce copper clad printed circuit. These display boards are designed for free air operation of 55°C and operation to 70°C with forced air cooling of 150 fpm normal to the rear side of the board, for displays operating at a PD of 1.00 watt or less. Heat Sink Design for Operation Above 70°C A free air operating temperature of 85°C can be achieved by heat sinking the display. Figure 27 depicts a two part heat sink which can be assembled using two different extruded parts. In this design, the vertical fins promote heat transfer due to naturally induced convection. Care should be taken to insure a good thermal path between the two portions of the heat sink. To optimize power handling capability, the heat transfer contact area between the printed circuit board metallization and the heat sink should be maximized. A thermally conductive silicon rubber sheet can be used to insulate the printed circuit board. Heat sink assemblies similar to 31 Maximum Power Dissipation Operating Conditions (Unless otherwise specified) Power Dissipation VCC = 5.25 V VCOL = 3.5 V n = 20 D.F. = .175 VB = logical 0 during t (and TB) TB = 0 1.12 W 1. Reduce n n = 18 1.04 W 2. Reduce n 2. and VCOL n = 18 VCOL = 3.0 V .95 W 3. Reduce VCOL VCOL = 3.0 V 1.02 W Assumptions Used in 4. Reduce D.F. 5. Reduce VCOL 5. and D.F. 6. Reduce D.F. 5. Turn-off VCC 6. during TB 7. Reduce VCOL, 7. Reduce D.F., 7. Turn-off VCC 7. during TB Maximum Power Dissipation Operating Conditions (Unless otherwise specified) Power Dissipation VCC = 5.00 V VCOL = 3.0 V n = 15 D.F. = .175 VB = logical 0 during t (and TB) TB = 0 .65 W VCOL = 2.4 V .58 W VCOL = 2.75 V .62 W D.F. = .10 .78 W D.F. = .10 .47 W D.F. = .05 .55 W D.F. = .05 .35 W VCOL = 3.0 V D.F. = .10 .72 W VCOL = 2.4 V D.F. = .10 .43 W VCOL = 3.0 V D.F. = .05 .52 W VCOL = 2.75 V D.F. = .05 .34 W D.F. = .10 X = .625 .66 W D.F. = .10 X = .625 .39 W D.F. = .05 X = .375 .45 W D.F. = .05 X = .375 .21 W VCOL = 3.0 V D.F. = .10 X = .625 .60 W VCOL = 2.4 V D.F. = .10 X = .625 .34 W VCOL = 3.0 V D.F. = .05 X = .375 .32 W VCOL = 2.75 V D.F. = .05 X = .375 .20 W t+T where x = t + T + TB Figure 25. Maximum and Typical Power Dissipation for the HDSP-2000/1/2/3 and HDSP-2300 Alphanumeric Displays 32 the one shown in Figure 27 typically exhibit a thermal resistance, ΘPIN-A, of 14°C/W per package for a 32 character display. Copper or aluminum bars mounted underneath the displays can also be used to heat sink the display assembly. Heat generated within the displays is conducted through the ceramic substrate into the bar. The ends of the bar are mounted to a heat sink or to a metal front panel. The bar can be insulated from the pins of the display and the printed circuit board with a thermally conductive silicon rubber sheet. Figure 28 shows a metal plate with slots milled in the plate for each row of displays such that each horizontal row of displays straddles a bar. A thermal resistance model for this heat sinking technique is shown in Figure 29. This model assumes that all heat generated in the display is generated in the center of each display package and that the ends of the bar are connected to an ideal heat sink. Then the temperature rise of the centermost display in the bar can be calculated as shown below: TC = 4 (Θ/2) PD + 3ΘPD + 2ΘPD + ΘPD + TA = 8ΘPD + TA 25 MIL INSULATING “TRACES” TO SEPARATE METAL CONDUCTORS Figure 26. Maximum Metalized Printed Circuit for the Agilent HDSP-2000 THERMAL CONDUCTIVE SILICONE RUBBER SHEET (ELECTRICALLY INSULATING) THERMAL CONDUCTING COMPOUND TWO PIECE BLACK ANODIZED HEAT SINK METAL CHASSIS DISPLAY BEZEL AND CONTRAST ENHANCEMENT FILTER (25) For display strings of an even number of n displays, the case temperature of the centermost displays can be calculated as TC = (n2/8) ΘPD + TA HDSP-2000 DISPLAY HDSP-2000 DISPLAY (26) PRINTED CIRCUIT BOARD UTILIZING LARGE METALIZATION PATTERN Figure 27. Two-Part Heat Sink for the HDSP-2000 33 MOUNTING HOLES HDSP-2000 DISPLAYS STRADDLE COPPER BAR CROSS SECTION VIEW MILLED SLOTS SIP SOCKET HDSP-2000 DISPLAY HEAT CONDUCTED FROM ENDS OF PLATE TO HEAT SINK OR METAL PANEL W COPPER BAR L T a = WT θ=L Ka PRINTED CIRCUIT BOARD Figure 28. Multiline HDSP-2000 Heat Sink PD θJC PD θJC θ/2 θ PD θJC PD θJC θ θ PD θJC θ PD θJC θ PD θJC θ PD θJC θ θ/2 AN1016.29 Figure 29. Thermal Resistance Model for Multiline HDSP-2000 Heat Sink The effectiveness of this type of heatsink can be determined by calculating the thermal resistance of each section of bar under each display Θ= L Ka (27) where L = length of bar under each display, mm K = thermal conductivity of bar, W/mm°C (0.3937 W/mm°C for copper) a = cross sectional area of bar, mm2 If the displays are mounted in a strip socket such as the Robinson Nugent SB-25-100-G socket, then the bar cross sectional area could be 6.35 mm (0.25") thick times the row-to-row pin spacing of the display minus 2.54 mm (.10"). Thus, Θ can be calculated as shown below: The TC and TJ can be calculated for a 32 character HDSP-2000 display with a copper bar mounted under the row of displays for an ambient temperature of 85°C HDSP-2000 Family Θ = 17.8 mm ( 0.3937 W / mm °C ) ( 6.35 mm ) ( 5.08 mm ) = 1.40°C/W (28) HDSP-2300 Family Θ = 20.3 mm ( 0.3937 W / mm °C ) ( 6.35 mm ) ( 3.81 mm ) = 2.13°C/W (29) HDSP-2490 Family Θ = 35.6 mm ( 0.3937 W / mm °C ) ( 6.35 mm ) (12.7 mm ) = 1.12°C/W (30) 34 and the operating conditions shown in equations (13), (14), (15), and (16): TC = 8 (1.40°C/W) (1.12 W) + 85°C = 98°C (31) Adding in the junction-to-case temperature rise as shown in equation (22), the TJ can be calculated as: TJ = 98°C + (20°C/W) (1.12 W) = 98°C + 22°C = 120°C (32) possible to read and will also produce viewer fatigue and high error rates. For this reason, control of display intensity with respect to the environment ambient intensity is an important consideration. The HDSP-2000 family of displays is ideally suited for wide ranges of ambient lighting since the intensity of these displays can be varied over a very wide dynamic range. The propagation delay between the VB input and the time that the LEDs turn on or off is under a microsecond, allowing dynamic variations of over 2000 to 1 in display luminous intensity at a 100 Hz refresh rate. Intensity Control An important consideration regarding display intensity is the control of the intensity with respect to the ambient lighting level. In dim ambients, a very bright display will produce very rapid viewer fatigue. Conversely, in bright ambient situations, a dim display will be difficult if not imVCC CLAIREX CL5 P5L OR 500 K POT. 150 K 15 µF A1 A2 Q 74122 B1 B2 Q TO COL. ENABLE VCC TRIGGER CLR FOR DECREASING AMBIENT ILLUMINATION AN1016.30 Figure 30. Intensity Modulation Control Using a One Shot Multivibrator Figure 30 depicts a scheme which will automatically control display intensity over a range of 10 to 1 as a function of ambient intensity. This circuit utilizes a resettable monostable multivibrator which is triggered by the column enable pulse. The duration of the multivibrator output is controlled by a photoconductor. At the end of a column enable pulse, the multivibrator is reset to insure that column current is off prior to the initiation of a new display shift register loading sequence. The output of this circuit is used to modulate either the VB inputs of the HDSP-2000 displays or the column enable input circuitry. For maximum reduction in display power, both inputs should be modulated. In the circuit shown in Figure 30, the photocell may be replaced by a 50 KΩ potentiometer to allow manual control of display intensity. Figure 31 shows a manually adjustable dimming circuit that provides a very wide range of display intensity. With a 100 Hz display refresh rate, a 4000 to 1 dynamic range of display intensity can be achieved. The Intersil ICM7555 timer is used as a retriggerable monostable multivibrator. The output of the timer is used to simultaneously pulse width modulate VB, the display column current, and the display supply current. Initially the 100 pF capacitor is held discharged by the timer. At the negative transition of the trigger input the timer would normally allow the capacitor to charge, however the 2N3906 transistor keeps the capacitor discharged until the trigger input goes high. As soon as the trigger input goes high, the capacitor is charged by a constant current source formed by the RCA CA3084 transistor array. As soon as the voltage across the capacitor reaches 2/3 VCC the output of the timer goes low, and the timer discharges the capacitor. The 2N3906 transistor always discharges the capacitor when the trigger is low, therefore the output of the timer stays high if the voltage across the capacitor never reaches 2/3 VCC. For the values shown, t can be varied exponentially from .5 µs to about 1900 µs. Since Q1 and Q2 are monolithic transistors, t is relatively independent of temperature. Figure 31 also shows a circuit to switch VCC of the displays off during the time that the display is blanked. When the 2N2219A transistor is off, the LM350 provides a regulated 3 A 5 V output. However, when the 2N2219A transistor is turned on, the output of the LM350 regulator is reduced to 1.2 V. This reduces ICC to under 10 mA per display. Capacitive loading of the regulator should be minimized as much as possible to maximize the switching speed. 35 VCC LM350 1.5 K V+ 8V 10 7 CA3084 IN 5 V, 3 A OUT VCC 1 TO DISPLAY VCC ONLY ADJ 120 0.01 µF 9 1K 0.01 µF 1K 6 360 2N2219A 11 VCC 2 74LS04 8 4 R ICM7555 1 6 3 2 2N3906 1K 7 TH 8 V+ OUT TR DIS V C 100 pF 74145 3 0 74LS00 12 D 13 C 14 B 15 A GND 1 1 2 3 4 1 COLUMN1 2 3 4 COLUMN2 5 COLUMN3 TO CLOCK ENABLE CIRCUITRY COLUMN4 TO COLUMN COUNTER COLUMN5 74LS04 ICM 7555 TRIGGER INPUT VB AN1016.31 LOAD DISPLAY LOAD DISPLAY ICM 7555 OUTPUT t t Figure 31. Wide Range Intensity Modulation Control and Power Switching of Display ICC to Conserve Power The Intensity and Color Matching The luminous intensity and dominant wavelength of LED displays can vary over a wide range. If there is too great a difference between the luminous intensity or dominant wavelength of adjacent characters in the display string, the display will appear objectionable to the viewer. To solve the problem, all HDSP-2000 displays are categorized for luminous intensity. The category of each display package is indicated by a letter preceding the date code on the package. When assembling display strings, all packages in the string should have the same intensity category. This will insure satisfactory intensity matching of the characters. All HDSP-2000 family displays are categorized in overlapping intensity categories. All characters of all packages designated to be within a given letter category will fall within an intensity ratio of less than 2:1. For dot matrix displays, a character-tocharacter intensity ratio of 2:1 is not generally discernible to the human eye. Since the human eye is very sensitive to variations in dominant wavelength in the yellow and green region, all yellow and green HDSP-2000 family displays are also categorized for dominant wavelength. The dominant wavelength bin for each display package is indicated by a number code following the category letter code on the back of the package. The dominant wavelength bins are 3.5 nm wide for yellow and 4.0 nm wide for green. These dominant wavelength variations are generally not discernible by the human eye. Display Color HDSP-2XX0 Standard Red Contrast Enhancement Ambient Lighting Dim Moderate Homalite H100-1650 3M Panel Film R6510 Panelgraphic Dark Red 63 Ruby Red 60 Chequers Red 118 Rohm & Haas 2423 Homalite H100-1266 Gray H100-1250 Gray H100-1230 Bronze Rohm & Haas 2074 Gray 2370 Bronze HDSP-2XX1 (Yellow) Homalite H100-1726 H100-1720 3M Panel Film A5910 Panelgraphic Yellow 27 Amber 23 Chequers Amber 107 Polaroid HNCP37 3M Light Control Film N00220 Panelgraphic Gray 15 Gray 10 Chequers Gray 105 HDSP-2XX2 (HER) Homalite H100-1670 3M Panel Film R6310 Panelgraphic Scarlet Red 65 Chequers Red 112 HDSP-2XX3 ((Agilent HP Green) Green) Homalite H100-1440 H100-1425 Panelgraphic Green 48 Chequers Green 107 Figure 32. Contrast Enhancement Filters www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies, Inc. 5953-7787 (11/99) Bright Polaroid HNCP-10 Another important consideration for optimum display appearance and readability is the contrast between the display “ON” elements and the background. High contrast can be achieved by placing a filter over the display. The filter, if properly chosen, will transmit the luminance of the light emitting elements while attenuating the luminance of the background. Filter choice is dependent upon the LED display package, ambient lighting conditions and the desired front panel appearance. For alphanumeric displays in indoor lighting ambients a plastic or glass wavelength filter can be used. In sunlight ambients a neutral density circular polarizer sandwiched between two pieces of optically coated glass is recommended. Figure 32 lists the filter materials recommended for each particular display color. For further information please see Application Note 1015 on Contrast Enhancement for LED Displays.