PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 FEATURES 19 3 18 4 17 5 6 7 16 15 14 8 13 9 12 10 11 VCC SDA SCL INT SC3 SD3 INT3 SC2 SD2 INT2 20 19 18 17 16 RESET INT0 SD0 SC0 INT1 1 15 INT 2 14 SC3 3 13 SD3 4 12 INT3 11 5 6 7 8 9 10 SC2 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 2 3 4 5 6 7 8 9 VCC 20 2 1 20 10 11 INT2 1 RGY PACKAGE (TOP VIEW) A0 A0 A1 RESET INT0 SD0 SC0 INT1 SD1 SC1 GND RGW PACKAGE (TOP VIEW) A1 A0 DGV, DW, OR PW PACKAGE (TOP VIEW) GND • • • No Glitch on Power Up Supports Hot Insertion Low Standby Current Operating Power-Supply Voltage Range of 2.3 V to 5.5 V 5.5-V Tolerant Inputs 0 to 400-kHz Clock Frequency Latch-Up Performance Exceeds 100 mA Per JESD 78 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SDA SCL • • • • VCC • • • • • 1-of-4 Bidirectional Translating Switches I2C Bus and SMBus Compatible Four Active-Low Interrupt Inputs Active-Low Interrupt Output Active-Low Reset Input Two Address Pins, Allowing up to Four Devices on the I2C Bus Channel Selection Via I2C Bus, In Any Combination Power Up With All Switch Channels Deselected Low RON Switches Allows Voltage-Level Translation Between 1.8-V, 2.5-V, 3.3-V, and 5-V Buses SD1 SC1 GND INT2 SD2 • • • • • • 19 18 17 16 15 14 13 12 SDA SCL INT SC3 SD3 INT3 SC2 SD2 DESCRIPTION/ORDERING INFORMATION The PCA9545A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual SCn/SDn channel or combination of channels can be selected, determined by the contents of the programmable control register. Four interrupt inputs (INT3–INT0), one for each of the downstream pairs, are provided. One interrupt (INT) output acts as an AND of the four interrupt inputs. An active-low reset (RESET) input allows the PCA9545A to recover from a situation in which one of the downstream I2C buses is stuck in a low state. Pulling RESET low resets the I2C state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high voltage, which will be passed by the PCA9545A. This allows the use of different bus voltages on each pair, so that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5.5-V tolerant. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) ORDERING INFORMATION PACKAGE (1) TA Reel of 3000 PCA9545ARGWR PD545A QFN – RGY Reel of 1000 PCA9545ARGYR PD545A Tube of 25 PCA9545ADW Reel of 2000 PCA9545ADWR Reel of 250 PCA9545ADWT PCA9545A PCA9545APW PD545A Tube of 70 TSSOP – PW Reel of 2000 Reel of 250 PCA9545APWE4 PCA9545APWR PD545A PCA9545APWRE4 PCA9545APWT PD545A PCA9545APWTE4 PCA9545ADGVR Reel of 250 PCA9545ADGVT VFBGA – GQN Reel of 1000 PCA9545AGQNR PD545A VFBGA – ZQN (Pb-free) Reel of 1000 PCA9545AZQNR PD545A PD545A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. GQN OR ZQN PACKAGE (TOP VIEW) TERMINAL ASSIGNMENTS 1 2 3 4 A A1 A0 VCC SDA A B INT0 INT RESET SCL B C SC0 SD0 SD3 SC3 C D SD1 SC2 INT1 INT3 D E GND SC1 INT2 SD2 1 2 3 4 E 2 PCA9545A Reel of 2000 TVSOP – DGV (1) TOP-SIDE MARKING QFN – RGW SOIC – DW –40°C to 85°C ORDERABLE PART NUMBER Submit Documentation Feedback PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 TERMINAL FUNCTIONS NO. DGV, DW, PW, AND RGY RGW GQN AND ZQN NAME DESCRIPTION 1 19 A2 A0 Address input 0. Connect directly to VCC or ground. 2 20 A1 A1 Address input 1. Connect directly to VCC or ground. 3 1 B3 RESET 4 2 B1 INT0 Active-low interrupt input 0. Connect to VCC through a pullup resistor. 5 3 C2 SD0 Serial data 0. Connect to VCC through a pullup resistor. 6 4 C1 SC0 Serial clock 0. Connect to VCC through a pullup resistor. 7 5 D3 INT1 Active-low interrupt input 1. Connect to VCC through a pullup resistor. 8 6 D1 SD1 Serial data 1. Connect to VCC through a pullup resistor. 9 7 E2 SC1 Serial clock 1. Connect to VCC through a pullup resistor. 10 8 E1 GND Ground 11 9 E3 INT2 Active-low interrupt input 2. Connect to VCC through a pullup resistor. 12 10 E4 SD2 Serial data 2. Connect to VCC through a pullup resistor. 13 11 D2 SC2 Serial clock 2. Connect to VCC through a pullup resistor. 14 12 D4 INT3 Active-low interrupt input 3. Connect to VCC through a pullup resistor. 15 13 C3 SD3 Serial data 3. Connect to VCC through a pullup resistor. 16 14 C4 SC3 Serial clock 3. Connect to VCC through a pullup resistor. 17 15 B2 INT Active-low interrupt output. Connect to VCC through a pullup resistor. 18 16 B4 SCL Serial clock line. Connect to VCC through a pullup resistor. 19 17 A4 SDA Serial data line. Connect to VCC through a pullup resistor. 20 18 A3 VCC Supply power Active-low reset input. Connect to VCC through a pullup resistor, if not used. Submit Documentation Feedback 3 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 BLOCK DIAGRAM PCA9545A SC0 SC1 SC2 SC3 6 9 13 16 SD0 5 SD1 8 SD2 12 SD3 15 GND VCC RESET Switch Control Logic 10 20 3 Power-on Reset SCL 18 SDA INT0 INT1 19 1 Input Filter I2C Bus Control A0 A1 4 7 Interrupt Logic INT2 11 INT3 14 Pin numbers shown are for DGV, DW, PW, and RGY packages. 4 2 Submit Documentation Feedback Output Filter 17 INT PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Device Address Following a start condition, the bus master must output the address of the slave it is accessing. The address of the PCA9545A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. Slave Address 1 1 0 1 0 A1 A0 R/W Hardware Selectable Fixed Figure 1. PCA9545A Address The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected, while a logic 0 selects a write operation. Control Register Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9545A, which is stored in the control register (see Figure 2). If multiple bytes are received by the PCA9545A, it saves the last byte received. This register can be written and read via the I2C bus. Interrupt Bits (Read Only) 7 6 5 Channel-Selection Bits (Read/Write) 4 INT3 INT2 INT1 INT0 3 2 1 0 B3 B2 B1 B0 Channel 0 Channel 1 Channel 2 Channel 3 INT0 INT1 INT2 INT3 Figure 2. Control Register Control Register Definition One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see Table 1). After the PCA9545A has been addressed, the control register is written. The four LSBs of the control byte are used to determine which channel or channels are to be selected. When a channel is selected, the channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. A stop condition must occur always right after the acknowledge cycle. Submit Documentation Feedback 5 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status) (1) (1) INT3 INT2 INT1 INT0 D3 B2 B1 X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 0 X 1 0 0 Channel 0 disabled 1 Channel 0 enabled X X X X X 0 X 0 1 COMMAND Channel 1 disabled X 1 0 0 B0 Channel 1 enabled Channel 2 disabled Channel 2 enabled Channel 3 disabled Channel 3 enabled No channel selected, power-up/reset default state Several channels can be enabled at the same time. For example, B3 = 0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are disabled, and channels 1 are 2 and enabled. Care should be taken not to exceed the maximum bus capacity. Interrupt Handling The PCA9545A provides four interrupt inputs (one for each channel) and one open-drain interrupt output (see Table 2). When an interrupt is generated by any device, it is detected by the PCA9545A and the interrupt output is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control register. Bits 4–7 of the control register correspond to channels 0–3 of the PCA9545A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master then can address the PCA9545A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master then can reconfigure the PCA9545A to select this channel and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VCC. Table 2. Control Register Read (Interrupt) (1) INT3 INT2 INT1 X X X X X 0 1 (1) 6 X 0 1 X D3 B2 B1 B0 X X X X X X X X X X X X X X X X X X X X X 0 1 INT0 0 1 COMMAND No interrupt on channel 0 Interrupt on channel 0 No interrupt on channel 1 Interrupt on channel 1 No interrupt on channel 2 Interrupt on channel 2 No interrupt on channel 3 Interrupt on channel 3 Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt on channels 0 and 3, and there is interrupt on channels 1 and 2. Submit Documentation Feedback PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 RESET Input The RESET input can be used to recover the PCA9545A from a bus-fault condition. The registers and the I2C state machine within this device initialize to their default states if this signal is asserted low for a minimum of tWL. All channels also are deselected in this case. RESET must be connected to VCC through a pullup resistor. Power-On Reset When power is applied to VCC, an internal power-on reset holds the PCA9545A in a reset condition until VCC has reached VPOR. At this point, the reset condition is released and the PCA9545A registers and I2C state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device. Voltage Translation The pass-gate transistors of the PCA9545A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another. Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the electrical characteristics section of this data sheet). In order for the PCA9545A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 3, Vpass (max) is at 2.7 V when the PCA9545A supply voltage is 3.5 V or lower, so the PCA9545A supply voltage could be set to 3.3 V. Pullup resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 13). 5 4.5 Maximum Vpass (V) 4 Typical 3.5 3 2.5 2 Minimum 1.5 1 2 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 3. Vpass Voltage vs VCC I2C Interface The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 4). Submit Documentation Feedback 7 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 4. Bit Transfer Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is defined as the stop condition (P) (see Figure 5). SDA SCL S P Start Condition Stop Condition Figure 5. Definition of Start and Stop Conditions A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master, and the devices that are controlled by the master are the slaves (see Figure 6). SDA SCL Master Transmitter/ Receiver Slave Receiver Slave Transmitter/ Receiver Master Transmitter Master Transmitter/ Receiver I2C Multiplexer Slave Figure 6. System Configuration The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowlege (ACK) bit. The transmitter must release the SDA line before the receiver can send an ACK bit. When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold times must be taken into account. 8 Submit Documentation Feedback PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Start Condition Clock Pulse for ACK Figure 7. Acknowledgment on the I2C Bus A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Data is transmitted to the PCA9545A control register using the write mode shown in Figure 8. Slave Address SDA S 1 1 1 0 0 Control Register A1 A0 0 A X X X X B3 B2 B1 B0 P ACK From Slave R/W ACK From Slave Start Condition A Stop Condition Figure 8. Write Control Register Data is read from the PCA9545A control register using the read mode shown in Figure 9. Slave Address SDA S 1 Start Condition 1 1 0 0 Control Register A1 A0 1 R/W A INT3 INT2 INT1 INT0 B3 ACK From Slave B2 B1 B0 NA NACK From Master P Stop Condition Figure 9. Read Control Register Submit Documentation Feedback 9 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 7 V VI Input voltage range (2) –0.5 7 V II Input current ±20 mA IO Output current ±25 mA ±100 mA ±100 mA Continuous current through VCC Continuous current through GND θJA Package thermal impedance (3) DGV package 92 DW package 58 GQN/ZQN package 78 PW package 83 RGW package TBD RGY package 47 UNIT °C/W Ptot Total power dissipation 400 mW Tstg Storage temperature range –65 150 °C TA Operating free-air temperature range –40 85 °C (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage TA Operating free-air temperature (1) 10 MIN MAX 2.3 5.5 SCL, SDA 0.7 × VCC 6 A1, A0, INT3–INT0, RESET 0.7 × VCC VCC + 0.5 SCL, SDA –0.5 0.3 × VCC A1, A0, INT3–INT0, RESET –0.5 0.3 × VCC –40 85 UNIT All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback V V V °C PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VPOR Power-on reset TEST CONDITIONS voltage (2) No load, VI = VCC or GND VCC MIN TYP (1) MAX VPOR 1.6 2.1 5V 3.6 4.5 V to 5.5 V Vpass Switch output voltage VSWin = VCC, ISWout = –100 µA 2.6 3.3 V 3 V to 3.6 V IOH INT VO = VCC 1.6 VOL = 0.6 V INT 2.8 2.3 V to 5.5 V VOL = 0.4 V 2 10 3 7 6 10 A1, A0 ±1 VI = VCC or GND ±1 2.3 V to 5.5 V ±1 RESET Operating mode fSCL = 100 kHz Low inputs VI = VCC or GND, IO = 0 VI = GND, IO = 0 Standby mode High inputs INT3–INT0 Supply-current change SCL, SDA VI = VCC, IO = 0 5.5 V 3 12 3.6 V 3 11 2.7 V 3 10 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 5.5 V 0.3 1 3.6 V 0.1 1 2.7 V 0.1 1 8 15 8 15 8 15 8 15 4.5 6 One INT3–INT0 input at 0.6 V, Other inputs at VCC or GND One INT3–INT0 input at VCC – 0.6 V, Other inputs at VCC or GND SCL or SDA input at 0.6 V, Other inputs at VCC or GND INT3–INT0 SCL or SDA input at VCC – 0.6 V, Other inputs at VCC or GND VI = VCC or GND 2.3 V to 5.5 V RESET Cio(OFF) (3) RON (1) (2) (3) SCL, SDA SC3–SC0, SD3–SD0 Switch on-state resistance VI = VCC or GND, Switch OFF VO = 0.4 V, IO = 15 mA VO = 0.4 V, IO = 10 mA µA µA 2.3 V to 5.5 V A1, A0 Ci µA ±1 INT3–INT0 ∆ICC mA ±1 SC3–SC0, SD3–SD0 ICC µA 3 SCL, SDA II V 1.5 1.1 2.3 V to 5.5 V VOL = 0.4 V SCL, SDA IOL V 4.5 1.9 2.5 V 2.3 V to 2.7 V UNIT 2.3 V to 5.5 V 4.5 6 4.5 5.5 15 19 6 8 4.5 V to 5.5 V 4 9 16 3 V to 3.6 V 5 11 20 2.3 V to 2.7 V 7 16 45 pF pF Ω All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C. The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device. Cio(ON) depends on the device capacitance and load that is downstream from the device. Submit Documentation Feedback 11 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 I2C Interface Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 µs tscl I2C clock low time 4.7 1.3 µs tsp I2C tsds I2C serial-data setup time 250 100 ns tsdh I2C serial-data hold time 0 (1) 0 (1) µs ticr I2C input rise time ticf I2C tocf I2C output fall time tbuf I2C bus free time between stop and start 4.7 1.3 µs tsts I2C start or repeated start condition setup 4.7 0.6 µs tsth I2C start or repeated start condition hold 4 0.6 µs tsps I2C stop condition setup 4 0.6 µs tvdL(Data) Valid-data time (high to low) (3) SCL low to SDA output low valid tvdH(Data) Valid-data time (low to high) (3) SCL low to SDA output high valid tvd(ack) Valid-data time of ACK condition ACK signal from SCL low to SDA output low Cb I2C bus capacitive load (1) (2) (3) spike time 50 input fall time 10-pF to 400-pF bus 50 kHz ns 1000 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 300 20 + 0.1Cb (2) 300 ns 1 1 µs 0.6 0.6 µs 1 1 µs 400 400 pF A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order to bridge the undefined region of the falling edge of SCL. Cb = total bus capacitance of one bus line in pF Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10) Switching Characteristics over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 12) PARAMETER tpd (1) Propagation delay time tiv Interrupt valid time (2) tir (1) (2) 12 Interrupt reset delay time (2) RON = 20 Ω, CL = 15 pF RON = 20 Ω, CL = 50 pF FROM (INPUT) TO (OUTPUT) SDA or SCL SDn or SCn INTn INT 4 µs INTn INT 2 µs MIN MAX 0.3 1 The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 12) Submit Documentation Feedback UNIT ns PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 Interrupt and Reset Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12) PARAMETER MIN tPWRL Low-level pulse duration rejection of INTn inputs 1 µs tPWRH High-level pulse duration rejection of INTn inputs 0.5 µs tWL Pulse duration, RESET low trst (1) RESET time (SDA clear) tREC(STA) Recovery time from RESET to start (1) MAX UNIT 6 ns 500 0 ns ns trst is the propagation delay measured from the time the RESET pin is first asserted low to the time the SDA pin is asserted high, signaling a stop condition. It must be a minimum of tWL. Submit Documentation Feedback 13 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION VCC RL = 1 kΩ SDn, SCn DUT CL = 50 pF (See Note A) I2C PORT LOAD CONFIGURATION Two Bytes for Complete Device Programming Address Stop Start Address Bit 7 Condition Condition Bit 6 (MSB) (P) (S) BYTE Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) ACK (A) Stop Condition (P) DESCRIPTION I2C 1 2 address + R/W Control register data tscl tsch 0.7 × VCC SCL tvd(ACK) or tvdL tvdH ticr ticf tbuf tsp 0.3 × VCC tsts 0.7 × VCC SDA 0.3 × VCC ticr ticf tsth tsdh tsds tsps Repeat Start Condition Start or Repeat Start Condition Stop Condition VOLTAGE WAVEFORMS A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 30 ns. C. The outputs are measured one at a time, with one transition per measurement. Figure 10. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms 14 Submit Documentation Feedback PCA9545A 4-CHANNEL AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS I2C www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 PARAMETER MEASUREMENT INFORMATION (continued) Start ACK or Read Cycle SCL SDA 30% trst 50% RESET tREC tWL trst 50% LEDx LED OFF Figure 11. Reset Timing VCC RL = 4.7 kΩ DUT INT CL = 100 pF (See Note A) INTERRUPT LOAD CONFIGURATION INTn (input) 0.5 × VCC INTn (input) tiv INT (output) 0.5 × VCC tir 0.5 × VCC INT (output) VOLTAGE WAVEFORMS (tiv) 0.5 × VCC VOLTAGE WAVEFORMS (tir) A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 30 ns. Figure 12. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback 15 PCA9545A 4-CHANNEL I2C AND SMBus SWITCH WITH INTERRUPT LOGIC AND RESET FUNCTIONS www.ti.com SCPS147C – OCTOBER 2005 – REVISED OCTOBER 2006 APPLICATION INFORMATION Figure 13 shows an application in which the PCA9545A can be used. VCC = 2.7 V to 5.5 V VCC = 3.3 V VCC = 2.7 V to 5.5 V 20 SDA I2C/SMBus SCL Master 19 18 17 3 See Note A SDA SD0 SCL SC0 INT RESET INT0 5 6 4 Channel 0 VCC = 2.7 V to 5.5 V See Note A SD1 8 SC1 9 7 INT1 Channel 1 VCC = 2.7 V to 5.5 V PCA9545A See Note A SD2 SC2 INT2 2 1 10 A1 A0 GND 12 13 VCC = 2.7 V to 5.5 V See Note A SD3 SC3 INT3 15 16 Channel 3 14 A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required. If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required. The interrupt inputs should not be left floating. B. Pin numbers shown are for DGV, DW, PW, and RGY packages. Figure 13. Typical Application 16 Channel 2 11 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing PCA9545ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) PCA9545ADGVT PREVIEW TVSOP DGV 20 250 TBD Call TI PCA9545ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545ADWT PREVIEW SOIC DW 20 250 TBD Call TI Call TI PCA9545AGQNR NRND GQN 20 1000 TBD SNPB Level-1-240C-UNLIM PCA9545APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545APWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM PCA9545ARGWR PREVIEW QFN RGW 20 3000 TBD Call TI PCA9545ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR PCA9545ARGYRG4 ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR PCA9545AZQNR ACTIVE ZQN 20 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM BGA MI CROSTA R JUNI OR BGA MI CROSTA R JUNI OR Pins Package Eco Plan (2) Qty Lead/Ball Finish CU NIPDAU MSL Peak Temp (3) Level-1-260C-UNLIM Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 30-Mar-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony Mailing Address: Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright © 2007, Texas Instruments Incorporated