SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 D D D D D Look-Ahead Circuitry Enhances Cascaded Counters Fully Synchronous in Count Modes Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54ALS193A . . . J PACKAGE SN74ALS193A . . . D OR N PACKAGE (TOP VIEW) B QB QA DOWN UP QC QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLR BO CO LOAD C D description The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. QB B NC VCC A SN54ALS193A . . . FK PACKAGE (TOP VIEW) QA DOWN NC UP QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 CLR BO NC CO LOAD 9 10 11 12 13 QD GND NC D C The ’ALS193A are synchronous, reversible, 4-bit up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (rippleclock) counters. NC – No internal connection All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count and LOAD inputs. The UP, DOWN, and LOAD inputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. These counters are designed to be cascaded without the need for external circuitry. The borrow (BO) output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feeding BO and CO to the count-down and count-up inputs, respectively, of the succeeding counter. The SN54ALS193A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS193A is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 logic symbol† CLR UP DOWN LOAD A B C D 14 5 4 11 15 1 10 9 CTRDIV16 CT = 0 2+ G1 1CT = 15 1– G2 2CT = 0 13 CO BO C3 3D [1] [2] [4] [8] † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 2 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 2 6 7 QA QB QC QD SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 logic diagram (positive logic) CLR LOAD UP DOWN 14 12 13 11 CO BO 5 4 S A R 15 S C1 1D R B 3 QA 1 S C1 2 QB 1D R C 10 S C1 6 QC 1D R D 9 S C1 1D R 7 QD Pin numbers shown are for the D, J, and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 typical clear, load, and count sequence the following sequence is illustrated below: 1. Clear outputs to zero 2. Load (preset) to binary 13 3. Count up to 14, 15 (carry), 0, 1, and 2 4. Count down to 1, 0 (borrow), 15, 14, and 13 CLR LOAD A Data Inputs B C D UP DOWN QA Data Outputs QB QC QD CO BO 0 13 Sequence Illustrated Clear 14 15 0 Count Up 1 2 1 15 14 0 Count Down Preset NOTES: A. Clear overrides load, data, and count inputs. B. When counting up, count-down input must be high; when counting down, count-up input must be high. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS193A . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS193A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS193A SN74ALS193A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 High-level output current – 0.4 – 0.4 mA IOL fclock Low-level output current 4 8 mA 30 MHz tw tsu th TA High-level input voltage 2 Clock frequency 2 0 Pulse duration Setup time Hold time 20 10 LOAD low 25 20 UP or DOWN high or low 30 16.5 Data before LOAD↑ 25 20 CLR inactive before UP or DOWN 20 20 LOAD inactive before UP or DOWN 20 20 Data after LOAD↑ 5 5 UP high after DOWN↑ 5 0 DOWN high after UP↑ 5 0 Operating free-air temperature V 0 CLR high V V 10 – 55 125 ns ns ns 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL UP or DOWN All others VCC = 5 5.5 5V V, SN54ALS193A MIN TYP‡ MAX SN74ALS193A MIN TYP‡ MAX – 1.5 – 1.5 VCC – 2 VCC – 2 0.25 0.4 0.1 VI = 0 0.4 4V UNIT V V 0.25 0.4 0.35 0.5 0.35 V 0.1 mA 20 20 µA – 0.2 – 0.2 – 0.1 – 0.1 mA IO§ VCC = 5.5 V, VO = 2.25 V – 20 – 112 – 30 – 112 mA ICC VCC = 5.5 V, See Note 1 12 22 12 22 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with the clear and load inputs grounded and all other inputs at 4.5 V. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = R2 = 500 Ω, TA = MIN to MAX† SN54ALS193A SN74ALS193A MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL MAX 25 UP CO DOWN BO UP or DOWN Any Q LOAD Any Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX 30 MHz 3 20 3 16 3 21 5 18 4 20 4 16 5 22 5 18 3 27 3 19 4 23 4 17 7 38 7 30 8 37 8 28 5 17 CLR Any Q 5 20 † For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions. 6 MIN UNIT ns ns ns ns ns SN54ALS193A, SN74ALS193A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS WITH DUAL CLOCK AND CLEAR SDAS211C – DECEMBER 1982 – REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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