AKM AKD4309B

ASAHI KASEI
[AK4309B]
AK4309B
16Bit SCF DAC for Multimedia
General Description
The AK4309B is a 1bit stereo DAC for multimedia audio systems. A 1bit DAC can achieve monotonicity and
low distortion with no adjustment and is superior to traditional R-2R ladder based DACs. In the AK4309B, the
loss of accuracy from clock jitter is also improved by using SCF techniques for on-chip post filter. The
AK4309B includes continuous time filter with single end output and does not need any external parts. The
master clock can be either 256fs or 384fs, supporting various audio environment.
Features
† Sampling Rate Ranging from 8kHz to 50kHz
† On chip Perfect filtering
• 8 times FIR Interpolator
• 2nd order SCF and CTF
• Total Response: ±0.5dB at 20kHz
† On chip Buffer with Single End Output
† Master Clock: 256fs or 384fs
† High Tolerance to Clock Jitter
† TTL Level Digital Interface
† THD+N: -84dB
† Dynamic Range: 90dB
† Output Level: 3.4Vpp
† Power Supply: 5V±10%
† Low Power Dissipation: 80mW at 5V
† Small Package: 20pin SSOP
† Pin Compatible with AK4310/4309A
0177-E-00
1997/6
-1-
ASAHI KASEI
[AK4309B]
„ Ordering Guide
AK4309BVM
AKD4309B
20pin SSOP(0.65mm pitch)
-10∼ +70°C
Evaluation Board
(AK4309B's board is the same as AK4310's)
„ Pin Layout
„ Compatibility with AK4310/09A
Parameter
Power Supply
Digital I/F level
DR
Output Voltage
Click Noise
Function of Pin 4
Package
AK4310
3∼ 5.5V
AK4309A
4.5∼ 5.5V
AK4309B
4.5∼ 5.5V
CMOS
92dB
2.8Vpp
High
TTL
91dB
3.4Vpp
Middle
TTL
90dB
3.4Vpp
Low
NC
20SSOP
PD
PD
24SSOP
24SSOP
0177-E-00
1997/6
-2-
ASAHI KASEI
[AK4309B]
PIN/FUNCTION
No.
Pin Name
I/O
1
TST1
I
2
3
4
5
DVDD
DVSS
NC
RST
I
6
MCLK
I
7
CKS
I
8
BICK
I
9
SDATA
I
10
LRCK
I
11
12
13
AOUTR
AOUTL
VCOM
O
O
O
14
15
16
17
18
AVDD
AVSS
NC
NC
VREFH
-
19
20
VREFL
DZF
I
O
I
Function
Test Pin
(Pull-down pin)
Must be left floating or tied to DVSS.
Digital Power Supply Pin
Digital Ground Pin
No Connection
Reset Pin
When at "L", the AK4309B is in power-down mode and is held in reset.
The AK4309B should always be reset upon power-up.
Master Clock Input Pin
An external TTL clock should be input on this pin.
The fs is selected by CKS pin.
Master Clock Select Pin
"L": MCLK=256fs, "H": MCLK=384fs
Serial Bit Input Clock Pin
This clock is used to latch SDATA.
Serial Data Input Pin
2's complement MSB-first data is input on this pin.
L/R Clock Pin
This input determines which channel is currently being input on the Serial
Data Input pin, SDATA. "H": Lch, "L": Rch
Rch analog output pin
Lch analog output pin
Common Voltage pin, AVDD/2
Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel with
a 10uF electrolytic cap.
Analog Power Supply Pin
Analog Ground Pin
No Connection
"H" Voltage Reference Input Pin
The differential Voltage between VREFH and VREFL inputs set the analog
output range. The VREFH pin is normally connected to AVDD and the
VREFL pin is connected to AVSS. A 0.1uF ceramic capacitor should be as
near to both pins.
"L" Voltage Reference Input Pin
Zero Input Detect Pin
When SDATA of both channels follow a total 8192 LRCK cycles with "0"
input data, this pin goes "H".
* NC pins are not bonded internally.
0177-E-00
1997/6
-3-
ASAHI KASEI
[AK4309B]
ABSOLUTE MAXIMUM RATINGS
(AVSS,DVSS=0V; Note 1 )
Parameter
Power Supplies:
Analog
Digital
DVDD-AVDD
Input Current, Any Pin Except Supplies
Input Voltage
Ambient Operating Temperature
Storage Temperature
Symbol
AVDD
DVDD
VDA
IIN
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-10
-65
max
6.0
6.0
0.3
±10
AVDD+0.3
70
150
Units
V
V
V
mA
V
°C
°C
Note: 1 . All voltages with respect to ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS,DVSS=0V; Note 1 )
Parameter
Power Supplies:
Analog
Digital
Voltage Reference(VREFH)
(Note 2 )
(Note 3 )
Symbol
min
typ
max
Units
AVDD
DVDD
VREF
4.5
4.5
3.0
5.0
5.0
-
5.5
AVDD
AVDD
V
V
V
Notes: 2 . AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD.
3 . Analog output voltage scales with the voltage of VREFH at VREFL=AVSS.
AOUT([email protected])=3.4Vpp*VREFH/5.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
0177-E-00
1997/6
-4-
ASAHI KASEI
[AK4309B]
ANALOG CHARACTERISTICS
(Ta=25°C ; AVDD,DVDD=5.0V; VREFH=AVDD,VREFL=AVSS; fs=44.1kHz; Signal Frequency=1kHz;
Measurement Bandwidth=10Hz∼ 20kHz; RL≥ 10kΩ ; unless otherwise specified)
Parameter
min
Resolution
typ
max
Units
16
Bits
Dynamic Characteristics (Note 4 )
THD+N
(0dB Output)
Dynamic Range (-60dB Output, A weight)
S/N
(A weight)
Interchannel Isolation(1kHz)
85
85
80
-84
90
90
90
-79
dB
dB
dB
dB
0.15
60
0.3
-
dB
ppm/°C
3.4
3.57
Vpp
kΩ
13
3
18
5
mA
mA
10
50
uA
80
50
50
115
250
mW
uW
dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
(Note 5 )
DC Accuracy
Output Voltage
Load Resistance
(Note 6 )
3.23
10
Power Supplies
Power Supply Current
Normal Operation
( RST = "H")
AVDD
DVDD
Power-Down-Mode ( RST = "L")
AVDD+DVDD (Note 7 )
Power Dissipation (AVDD+DVDD)
Normal Operation
Power-Down-Mode
(Note 7 )
Power Supply Rejection
(Note 8 )
Notes: 4 . Measured by AD725C(SHIBASOKU). Averaging mode. Refer to the eva board manual.
5 . The voltage on VREFH pin is held +5V externally.
6 . Full-scale voltage(0dB). Output voltage scales with the voltage of VREH-VREFL.
AOUT([email protected])=3.4Vpp*(VREFH-VREFL)/5.
7 . Power Dissipation in the power-down mode is applied with no external clocks
(MCLK,BICK,LRCK held "H" or "L").
8 . PSR is applied to AVDD,DVDD with 1kHz, 100mVpp. VREF pin is held +5V.
0177-E-00
1997/6
-5-
ASAHI KASEI
[AK4309B]
FILTER CHARACTERISTICS
(Ta=25°C ; AVDD,DVDD=4.5V∼ 5.5V; fs=44.1kHz)
Parameter
Symbol
min
typ
max
Units
PB
0
24.3
22.05
20.0
-
Digital Filter
Passband
-0.2dB (Note 9 )
-6.0dB
(Note 9 )
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
(Note 10 )
SB
PR
SA
GD
41
-
14.5
-
kHz
kHz
kHz
dB
dB
1/fs
-
±0.5
-
dB
±0.05
Digital Filter + SCF + CTF
Frequency Response 0∼ 20.0kHz
Note: 9 . The passband and stopband frequencies scale with fs.
For example, PB=0.4535*fs(@-0.2dB), SB=0.55*fs.
10 . The calculating delay time which occurred by digital filtering. This time is from setting the 16bit
data of both channels to input register to the output of analog signal.
DIGITAL CHARACTERISTICS
(Ta=25°C ; AVDD,DVDD=4.5∼ 5.5V)
Parameter
Symbol
min
typ
max
Units
VIH
VIL
VOH
VOL
Iin
2.2
DVDD-0.5
-
-
0.8
0.5
±10
V
V
V
V
uA
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-100A)
Low-Level Output Voltage (Iout=100A)
Input Leakage Current
0177-E-00
-
1997/6
-6-
ASAHI KASEI
[AK4309B]
SWITCHING CHARACTERISTICS
(Ta=25°C ; AVDD,DVDD=4.5∼ 5.5V; CL=20pF)
Parameter
Master Clock Timing
Symbol
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
LRCK
Frequency
Duty Cycle
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK edge
LRCK Edge to BICK rising
SDATA Hold Time
SDATA Setup Time
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
Duty
(Note 11 )
(Note 11 )
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
min
typ
2.048
28
28
3.072
23
23
8
45
max
Unit
12.8
MHz
ns
ns
MHz
ns
ns
kHz
kHz
%
19.2
44.1
312.5
100
100
50
50
50
50
50
55
ns
ns
ns
ns
ns
ns
ns
Reset Timing
RST Pulse Width
(Note 12 )
tRST
150
Notes: 11 . BICK rising edge must not occur at the same time as LRCK edge.
12 . The AK4309B can be reset by bringing RST "L" to "H" only upon power up.
0177-E-00
ns
1997/6
-7-
ASAHI KASEI
[AK4309B]
„ Timing Diagram
0177-E-00
1997/6
-8-
ASAHI KASEI
[AK4309B]
OPERATION OVERVIEW
„ System Clock
The external clocks which are required to operate the AK4309B are MCLK, LRCK, BICK. The master
clock(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the
digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is determined by the
sampling rate (LRCK), CKS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs is
selected, the internal master clock becomes 256fs(=384fs*2/3). Refer to Figure 1 .
All external clocks(MCLK,BICK,LRCK) should always be present whenever the AK4309B is in normal
operation mode(RST="H"). If these clocks are not provided, the AK4309B may draw excess current because
the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4309B
should be in the power-down mode(RST ="L"). After exiting reset at power-up etc., the AK4309B is in powerdown mode until MCLK and LRCK are input.
Clock
frequency
8k∼ 50kHz
∼ 64fs
LRCK (fs)
BICK
MCLK
CKS="L"
CKS="H"
256fs
384fs
Table 1 . System Clocks
Figure 1 . MCLK divider
„ Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. A serial data is MSB-first, 2's compliment
format and is latched by the rising edge of BICK.
Figure 2 . Data Input Timing
0177-E-00
1997/6
-9-
ASAHI KASEI
[AK4309B]
„ Zero detection
When the input data at both channels are continuously zeros for 8192 LRCK cycles, DZF goes to "H". DZF
immediately goes "L" if input data are not zero after going DZF "H".
„ System Reset
The AK4309B should be reset once by bringing RST "L" upon power-up. The AK4309B is powered up and the
internal timing starts clocking by LRCK "↑ " after exiting reset and power down state by MCLK. The AK4309B is
in power-down mode until LRCK is input.
SYSTEM DESIGN
Figure 3 shows the system connection diagram. An evaluation board[AKD4310] is available which
demonstrates the optimum layout, power supply arrangements and measurement results.
Figure 3 . Typical Connection Diagram
Notes:
- LRCK=fs, BICK≥ 32fs, MCLK=256fs at CKS="L", MCLK=384fs at CKS="H".
- Power lines of AVDD and DVDD should be distributed separately from the point
with low impedance of regulator etc.
- When AOUT drives some capacitive load, some resistor should be added
in series between AOUT and capacitive load.
- The capacitor value on VCOM depends on low frequency noise level of power supply.
0177-E-00
1997/6
- 10 -
ASAHI KASEI
[AK4309B]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD,
respectively. AVDD is supplied from analog supply in system and DVDD is supplied from AVDD via 10Ω
resistor as shown in Figure 3 . Alternatively if AVDD and DVDD are supplied separately, AVDD and DVDD
should be powered at the same time or AVDD should be powered earlier than DVDD. Analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit
board. Decoupling capacitors for high frequency should be placed as near as possible.
2. Voltage reference
The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally
connected to AVDD and VREFL pin is connected to AVSS with a 0.1uF ceramic capacitor. VCOM is a signal
ground of this chip. An electrolytic capacitor of around 10uF in parallel with a 0.1uF ceramic capacitor attached
to these pins eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All
signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted
coupling into the AK4309B.
3. Analog Outputs
The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is
typically 3.4Vpp. AC coupling capacitors of larger than 1uF are recommended. The internal switched-capacitor
filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio
passband. Therefore, any external filters are not required for typical application. The output voltage is a
positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM
voltage for 0000H(@16bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM +
a few mV.
0177-E-00
1997/6
- 11 -
ASAHI KASEI
[AK4309B]
PACKAGE
z 20pin SSOP (Unit: mm)
NOTE: Dimension “*” does not include mold flash.
„ Package & Lead frame material
Package molding compound :
Lead frame material :
Lead frame surface treatment :
Epoxy
Cu
Solder plate
0177-E-00
1997/6
- 12 -
ASAHI KASEI
[AK4309B]
MARKING
Contents of AAXXXX
AA: Lot#
XXXX: Date Code
0177-E-00
1997/6
- 13 -
IMPORTANT NOTICE
zThese products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM)
sales office or authorized distributor concerning their current status.
zAKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
zAny export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
zAKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or
other fields, in which its failure to function or perform may reasonably be expected to
result in loss of life or in significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or
effectiveness of the device or system containing it, and which must therefore meet
very high standards of performance and reliability.
zIt is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.