TI SN74CBTD3306D

SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030F – JANUARY 1996 – REVISED MAY 1998
D
D
D
D
D OR PW PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Designed to Be Used in Level-Shifting
Applications
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages
1OE
1A
1B
GND
1
8
2
7
3
6
4
5
VCC
2OE
2B
2A
description
The SN74CBTD3306 features two independent line switches. Each switch is disabled when the associated
output-enable (OE) input is high. A diode to VCC is integrated on the chip to allow for level shifting between 5-V
inputs and 3.3-V outputs.
The SN74CBTD3306 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L
A port = B port
H
Disconnect
logic diagram (positive logic)
1A
1OE
2
3
1B
1
5
6
2A
2B
7
2OE
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030F – JANUARY 1996 – REVISED MAY 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VIL
TA
Low-level control input voltage
High-level control input voltage
MIN
MAX
4.5
5.5
2
Operating free-air temperature
–40
UNIT
V
V
0.8
V
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
VOH
VCC = 4.5 V,
See Figure 2
II = –18 mA
II
ICC
VCC = 5.5 V,
VCC = 5.5 V,
VI = 5.5 V or GND
IO = 0,
VCC = 5.5 V,
VI = 3 V or 0
One input at 3.4 V,
VO = 3 V or 0,
OE = VCC
∆ICC§
Ci
Cio(OFF)
ron¶
Control inputs
Control inputs
VCC = 4.5 V
MIN
TYP‡
VI = VCC or GND
Other inputs at VCC or GND
MAX
UNIT
–1.2
V
±1
µA
1.5
mA
2.5
mA
3
VI = 0
pF
4
II = 64 mA
II = 30 mA
pF
5
7
5
7
Ω
VI = 2.4 V,
II = 15 mA
35
50
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030F – JANUARY 1996 – REVISED MAY 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd†
A or B
B or A
ten
OE
A or B
tdis
OE
A or B
PARAMETER
MIN
MAX
UNIT
0.25
ns
2.1
5.4
ns
1
4.7
ns
† The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
GND
CL = 50 pF
(see Note A)
500 Ω
3V
Output
Control
(low-level
enabling)
LOAD CIRCUIT
1.5 V
Input
1.5 V
1.5 V
0V
tPLH
VOH
Output
1.5 V
Output
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
VOL
tPLZ
3.5 V
1.5 V
tPZH
tPHL
1.5 V
0V
tPZL
3V
S1
Open
7V
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH
VOH – 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74CBTD3306
DUAL FET BUS SWITCH
WITH LEVEL SHIFTING
SCDS030F – JANUARY 1996 – REVISED MAY 1998
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
4
TA = 25°C
3.75
100 µA
3.75
3.5
6 mA
12 mA
3.5
100 µA
3.25
6 mA
12 mA
3
24 mA
3.25
VOH – Output Voltage High – V
VOH – Output Voltage High – V
TA = 85°C
24 mA
3
2.75
2.5
2.25
2
1.75
1.5
4.5
2.75
2.5
2.25
2
1.75
4.75
5
5.25
5.5
5.75
1.5
4.5
4.75
VCC – Supply Voltage – V
5
VCC – Supply Voltage – V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
TA = 0°C
VOH – Output Voltage High – V
3.75
3.5
100 µA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
5.5
VCC – Supply Voltage – V
Figure 2. VOH Values
4
5.25
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• DALLAS, TEXAS 75265
5.75
5.5
5.75
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Copyright  1998, Texas Instruments Incorporated