Data Sheet 26301.102b 3935 3-PHASE POWER MOSFET CONTROLLER — For Automotive Applications Package ED, 44-Pin PLCC Package JP, 48-Pin LQFP The A3935 is designed specifically for automotive applications that require high-power motors. Each provides six high-current gate drive outputs capable of driving a wide range of n-channel power MOSFETs. A requirement of automotive systems is steady operation over a varying battery input range. The A3935 integrates a pulse-frequency modulated boost converter to create a constant supply voltage for driving the external MOSFETs. Bootstrap capacitors are utilized to provide the above battery supply voltage required for n-channel FETs. Direct control of each gate output is possible via six TTL-compatible inputs. A differential amplifier is integrated to allow accurate measurement of the current in the three-phase bridge. Package LQ, 36-Pin SOIC ABSOLUTE MAXIMUM RATINGS Load Supply Voltages, VBAT, VDRAIN, VBOOST, BOOSTD ... -0.6 V to 40 V Output Voltage Ranges, GHA/GHB/GHC, VGHX .. -4 V to 55 V SA/SB/SC, VSX ............... -4 V to 40 V GLA/GLB/GLC, VGLX .... -4 V to 16 V CA/CB/CC, VCX .......... -0.6 V to 55 V Sense Circuit Voltages, CSP,CSN, LSS ............... -4 V to 6.5 V Logic Supply Voltage, VDD ........................... -0.3 V to +6.5 V Logic Input/Outputs and OVSET, BOOSTS, CSOUT, VDSTH ......... -0.3 V to 6.5 V Operating Temperature Range, TA ........................... -40°C to +135°C Junction Temperature, TJ ........... +150°C Storage Temperature Range, TS ........................... -55°C to +150°C * Fault conditions that produce excessive junction temperature will activate device thermal shutdown circuitry. These conditions can be tolerated, but should be avoided. Diagnostic outputs can be continuously monitored to protect the driver from short-to-battery, short-to-supply, bridge-open, and battery under/overvoltage conditions. Additional protection features include dead-time, VDD undervoltage, and thermal shutdown. The A3935 is supplied in a choice of three packages, a 44-lead PLCC with copper batwing tabs (suffix ED), a 48-lead low profile QFP with exposed thermal pad (suffix JP), and a 36-lead 0.8 mm pitch SOIC (suffix LQ). FEATURES ! Drives wide range of n-channel MOSFETs in 3-phase bridges ! PFM boost converter for use with low-voltage battery supplies ! Internal LDO regulator for gate-driver supply ! Bootstrap circuits for high-side gate drivers ! Current monitor output ! Adjustable battery overvoltage detection. ! Diagnostic outputs ! Motor lead short-to-battery, short-to-ground, and bridge-open protection ! Undervoltage protection ! -40 °C to +150 °C, TJ operation ! Thermal shutdown Always order by complete part number, e.g., A3935KLQ . 3935 THREE-PHASE POWER MOSFET CONTROLLER Functional Block Diagram See pages 8 and 9 for terminal assignments and descriptions. 2 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright © 2003 Allegro MicroSystems, Inc. 3935 THREE-PHASE POWER MOSFET CONTROLLER A3935KED (PLCC) A3935KLQ (SOIC) * Measured on “High-K” multi-layer PWB per JEDEC Standard JESD51-7. † Measured on typical two-sided PWB with power tabs (terminals 1, 2, 11, 12, 22, 23, 34, and 35) connected to copper foil with an area of 3.8 square inches (2452 mm2) on each side. See Application Note 29501.5, Improving Batwing Power Dissipation, for additional information. www.allegromicro.com 3 3935 THREE-PHASE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Power Supply VDD Supply Current IDD All logic inputs = 0 V – – 7.0 mA VBAT Supply Current IBAT All logic inputs = 0 V – – 3.0 mA Battery Voltage Operating Range VBAT 7.0 – 40 V Bootstrap Diode Forward Voltage VDBOOT IDBOOT = -Icx = 10 mA, VDBOOT = VREG – VCX 0.8 – 2.0 V IDBOOT = -Icx = 100 mA 1.5 – 2.3 V rD(100 mA) = [VD(150 mA) – VD(50 mA)]/100 mA 2.5 – 7.5 Ω -150 – -1150 mA Bootstrap Diode Resistance rDBOOT Bootstrap Diode Current Limit IDM 3 V < [VREG – VCX] < 12 V Bootstrap Quiescent Current ICX VCX = 40 V, GHx = ON 10 – 30 µA – – 2.0 µs 12.7 – 14 V VREGDO = Vboost – Vreg, Ireg = 40 mA – 0.9 – V No external dc load at VREG, CREG = 10 µF – – 40 mA IREGBIAS Current into VBOOST, ENABLE = 0 – – 4.0 mA VBOOSTM VBAT = 7 V 14.9 – 16.3 V 35 – 180 mV – 1.4 3.3 Ω – – 300 mA 0.45 – 0.55 V toff 3.0 – 8.0 µs tblank 100 – 220 ns Bootstrap Refresh Time trefresh VSX = low to guarantee ∆V = +0.5 V refresh of 0.47 µF Boot Cap at Vcx – Vsx = +10 V VREG Output Voltage 1 VREG VBAT = 7 V to 40 V, VBOOST from Boost Reg VREG Dropout Voltage 2 VREGDO Gate Drive Avg. Supply Current VREG Input Bias Current IREG Boost Supply VBOOST Output Voltage Limit VBOOST Output Volt. Limit Hyst. ∆VBOOSTM Boost Switch ON Resistance rDS(on) Max. Boost Switch Current Boost Current Limit Threshold Volt. OFF Time Blanking Time IBOOSTD < 300 mA IBOOSTSW VBI(th) Increasing VBOOSTS NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. 1. For VBOOSTM < VBOOST < 40 V power dissipation in the VREG LDO increases. Observe TJ < 150 °C limit. 2. With VBOOST decreasing Dropout Voltage measured at VREG = VREGref – 200 mV where VREG(ref) = VREG at VBOOST = 16 V. 4 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 Continued next page … 3935 THREE-PHASE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units VI(1) Minimum high level input for logical “one” 2.0 – – V VI(0) Maximum low level input for logical “zero” – – 0.8 V Logic Input Currents II(1) VI = VDD – – 500 µA II(0) VI = 0.8 V Input Hysteresis Vhys Logic Output High Voltage VO(H) IO(H) = -800 µA Logic Output Low Voltage VI(L) IO(L) = 1.6 mA Control Logic Logic Input Voltages 50 – – µA 100 – 300 mV VDD – 0.8 – – V – – 0.4 V GHx: IxU = –10 mA, Vsx = 0 VREG – 2.26 – VREG V GLx: IxU = –10 mA, Vlss = 0 VREG – 0.26 – VREG V VSDU = 10 V, TJ = 25 °C – 800 – mA Gate Drives, GHx ( internal SOURCE or upper switch stages) Output High Voltage Source Current (pulsed) Source ON Resistance VDSL(H) IxU rSDU(on) VSDU = 10 V, TJ = 135 °C 400 – – mA IxU = –150 mA, TJ = 25 °C 4.0 – 10 Ω IxU = –150 mA, TJ = 35 °C 7.0 – 15 Ω VDSL = 10 V, TJ = 25 °C – 850 – mA VDSL = 10 V, TJ = 135 °C 550 – – mA Gate Drives, GLx ( internal SINK or lower switch stages) Sink Current (pulsed) Sink ON Resistance IxL rDSL(on) IxL = +150 mA, TJ = 25 °C 1.8 – 6.0 Ω IxL = +150 mA, TJ = 135 °C 3.0 – 7.5 Ω Gate Drives, GHx, GLx (General) Phase Leakage (Source) ISx ENABLE = 0, VSx = 1.7 V 0 – 100 µA Propagation Delay, Logic only tpd Logic input to unloaded GHx, GLx – – 150 ns Output Skew Time tsk(o) Grouped by edge, phase-to-phase – – 50 ns Dead Time (Shoot-Through Prevention) tdead Between GHx, GLx transitions of same phase 75 – 180 ns NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. For GHX: VSDU = VCX – VGHX, VDSL = VGHX – VSX, VDSL(H) = VCX – VSDU – VSX. For GLX: VSDU = VREG – VGLX, VDSL = VGLX – VLSS, VDSL(H) = VREG – VSDU – VLSS. www.allegromicro.com 5 3935 THREE-PHASE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Sense Amplifier Input Bias Current Ibias CSP = CSN = 0 V -180 – -360 µA Input Offset Current IIO CSP = CSN = 0 V – – ±35 µA Input Resistance ri CSP with respect to GND – 80 – kΩ CSN with respect to GND – 4.0 – kΩ Diff. Input Operating Voltage VID VID = CSP – CSN, -1.3V < CSP,N < 4V – – ±200 mV Output Offset Voltage VOO CSP = CSN = 0 V 77 250 450 mV ∆VOO CSP = CSN = 0 V – 100 – µV/°C Output Offset Voltage Drift Input Com-Mode Oper. Range VIC CSP = CSN -1.5 – 4.0 V Voltage Gain AV VID = 40 mV to 200 mV 18.6 19.2 19.8 V/V Low Output Voltage Error Ev Vid = 0 to 40 mV, Vo = (19.2 x VID) + Vo + Ev – – ±25 mV DC Common-Mode Attenuation AVC CSP = CSN = 200 mV 28 – – dB VCSOUT = 2.0 V – 8.0 – Ω 0.075 – VDD-0.25 V Output Resistance Output Dynamic Range Output Current, Sink Output Current, Source ro VCSOUT ICSOUT = -100 µA at top rail, 100 µA at bottom rail Isink VCSOUT = 2.5 V 20 – – mA Isource VCSOUT = 2.5 V -1.0 – – mA VDD Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 1 MHz 20 – – dB VREG Supply Ripple Rejection PSRR CSP = CSN = GND, freq. = 0 to 300 kHz 45 – – dB Small Signal 3-dB Bandwidth f3db 10 mV input – 1.6 – MHz AC Common-Mode Attenuation Avc Vcm = 250 mV/pp, freq. = 0 to 800 kHz 26 – – dB Output Slew Rate (positive or negative) SR 200 mV step input, meas. 10/90% points 10 – – V/µs NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. 6 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3935 THREE-PHASE POWER MOSFET CONTROLLER ELECTRICAL CHARACTERISTICS: unless otherwise noted at TJ = -40°C to +150°C, VBAT = 7 V to 16 V, VDD = 4.75 V to 5.25 V, ENABLE = 22.5 kHz, 50% Duty Cycle, Two Phases Active. Limits Characteristics Symbol Conditions Min Typ Max Units Decreasing VDD 3.8 – 4.3 V VDD(recovery) - VDD(uv) 100 – 300 mV Fault Logic VDD Undervoltage VDD(uv) VDD Undervoltage Hysteresis ∆VDD(uv) OVSET Operating Volt. Range VSET(ov) 0 – VDD V OVSET Calibrated Volt. Range VSET(ov) 0 – 2.5 V OVSET Input Current Range ISET(ov) -1.0 – +1.0 µA VBAT Overvoltage Range VBAT(ov) 0 V < VSET(ov) < 2.5 V 19.4 – 40 V VBAT Overvoltage VBAT(ov) Increasing VBAT, VSET(ov) = 0 V 19.4 22.4 25.4 V ∆VBAT(ov) Percent of VBAT(ov) value set by VSET(ov) 9.0 – 15 % VBAT Overvoltage Gain Constant KBAT(ov) VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov) [0] – 12 – V/V VBAT Undervoltage VBAT(uv) Decreasing VBAT 5.0 5.25 5.5 V VBAT Undervoltage Hysteresis ∆VBAT(uv) Percent of VBAT(uv) 8.0 – 12 % VREG Undervoltage VREG(uv) Decreasing VREG 9.9 – 11.1 V VDSTH Input Range VDSTH 0.5 – 3.0 V VDSTH Input Current IDSTH 40 – 100 µA VBAT Overvoltage Hysteresis VDSTH > 0.8 V Short-to-Ground Threshold VSTG(th) With a high-side driver “on”, as VSX decreases, VDRAIN - VSX > VSTG causes a fault VDSTH-0.3 – VDSTH+0.2 V Short-to-Battery Threshold VSTB(th) With a low-side driver “on”, as VSX increases, VSX - VLSS > VSTB causes a fault VDSTH-0.3 – VDSTH+0.2 V VDRAIN /Open Bridge Oper. Range VDRAIN 7 V < VBAT < 40 V -0.3 – VBAT+2.0 V VDRAIN /Open Bridge Current IVDRAIN 7 V < VBAT < 40 V 0 – 1.0 mA 1.0 – 3.0 V TJ 160 170 180 °C ∆TJ 7.0 10 13 °C VDRAIN /Open Bridge Threshold Volt. Thermal Shutdown Temp. Thermal Shutdown Hysteresis VBDGO(th) If VDRAIN < VBDGOTH then a bridge fault occurs NOTES: Typical Data and Typical Characteristics are for design information only. Negative current is defined as coming out of (sourcing) the specified device terminal. www.allegromicro.com 7 3935 THREE-PHASE POWER MOSFET CONTROLLER Terminal Functions Terminal Name CSP VDSTH LSS GLC SC GHC CC GLB SB GHB CB GLA SA GHA CA VREG A3935KED (PLCC) Function Current-sense input, positive-side 31 A3935KJP (QLFP) A3935KLQ (SOIC) 19 1 DC input, drain-to-source monitor threshold voltage 32 20 2 Gate-drive source return, low-side 33 21 3 Gate-drive C output, low-side 36 22 4 Load phase C input 37 26 5 Gate-drive C output, high-side 38 27 6 Bootstrap capacitor C 39 28 7 Gate-drive B output, low-side 40 29 8 Load phase B input 41 30 9 Gate-drive B output, high-side 42 31 10 Bootstrap capacitor B 43 32 11 Gate-drive A output, low-side 44 33 12 Load phase A input 3 34 13 Gate-drive A output, high-side 4 38 14 Bootstrap capacitor A 5 39 15 Gate drive supply, positive 6 40 16 VDRAIN Kelvin connection to MOSFET high-side drains 7 41 17 VBOOST Boost supply output 8 42 18 BOOSTS Boost switch, source 9 43 19 BOOSTD Boost switch, drain 10 44 20 VBAT Battery supply, positive 13 46 22 UVFLT VBAT undervoltage fault output 14 3 23 OVFLT VBAT overvoltage fault output 15 4 24 FAULT Active-low fault output, primary 16 5 25 ALO Gate control input A, low-side 17 6 26 AHI Gate control input A, high-side 18 7 27 BHI Gate control input B, high-side 19 8 28 BLO Gate control input B, low-side 20 9 29 CLO Gate control input C, low-side 21 10 30 Gate control input C, high-side 24 11 31 ENABLE CHI Gate output enable 25 12 32 OVSET DC input, overvoltage threshold setting for VBAT 26 15 33 Not connected, no external connection allowed 27 1,2,13,14,23,24, – NC 25,35,36,37,47,48 CSOUT 8 Current-sense amplifier output 28 16 34 VDD Logic supply, nominally +5 V 29 17 35 CSN Current-sense input, negative-side GND Ground, dc supply returns, negative, and (for ED package) heat sink tab 30 18 36 1, 2, 11, 12, 22, 23, 34, 35 45 21 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3935 THREE-PHASE POWER MOSFET CONTROLLER Terminal Descriptions AHI/BHI/CHI. Direct control of high-side gate outputs GHA/ GHB/GHC. Logic “1” drives the gate “on”. Logic ”0” pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. ALO/BLO/CLO. Direct control of low-side gate outputs GLA/ GLB/GLC. Logic “1” drives the gate “on”. Logic ”0” pulls the gate down, turning off the external power MOSFET. Internally pulled down when terminal is open. BOOSTD. Boost converter switch drain connection. BOOSTS. Boost converter switch source connection. CA/CB/CC. High-side connection for bootstrap capacitor, positive supply for high-side gate drive. The bootstrap capacitor is charged to VREG when the output Sx terminal is low. When the output swings high, the voltage on this terminal rises with the output to provide the boosted gate voltage needed for nchannel power MOSFETs. CSN. Input for current-sense, differential amplifier, inverting, negative side. Kelvin connection for ground side of currentsense resistor. CSOUT. Amplifier output voltage proportional to current sensed across an external low-value resistor placed in the ground-side of the power FET bridge. CSP. Input for current-sense differential amplifier, noninverting, positive side. Connected to positive side of sense resistor. ENABLE. Logic “0” disables the gate control signals and switches off all the gate drivers “low” causing a “coast”. Can be used in conjunction with the gate inputs to PWM the load current. Internally pulled down when terminal is open. FAULT. Diagnostic logic output signal, when “low” indicates that one or more fault condition have occurred. GHA/GHB/GHC. High-side gate-drive outputs for n-channel MOSFET drivers. External series gate resistors can control slew rate seen at the power driver gate; thereby, controlling the di/dt and dv/dt of Sx outputs. GLA/GLB/GLC. Low-side gate drive outputs for external, nchannel MOSFET drivers. External series gate resistors can control slew rate. www.allegromicro.com GND. Ground or negative side of VDD and VBAT supplies. LSS. Low-side gate driver returns. Connects to the common sources in the low-side of the power MOSFET bridge. OVFLT. Logic “1” means that the VBAT exceeded the VBAT overvoltage trip point set by OVSET level. It will recover after a hysteresis below that maximum value. Normally has a highimpedance state. OVSET. A positive, dc level that controls the VBAT overvoltage trip point. Usually, provided from precision resistor divider network between VDD and GND, but can be held grounded for a preset value. When terminal is open, sets unspecified but high overvoltage trip point. SA/SB/SC. Directly connected to the motor terminals, these terminals sense the voltages switched across the load and are connected to the negative side of the bootstrap capacitors. Also, are the negative supply connection for the floating, high-side drivers. UVFLT. Logic “1” means that VBAT is below its minimum value and will recover after a hysteresis above that minimum value. Has a high-impedance state. [If UVFLT and OVFLT are both in high-impedance state; then, at least, a thermal shutdown or VDD undervoltage has occurred.] VBAT. Battery voltage, positive input and is usually connected to the motor voltage supply. VBOOST. Boost converter output, nominally 16 V, is also input to regulator for VREG. Has internal boost current and boost voltage control loops. In high-voltage systems is approximately one diode drop below VBAT. VDD. Logic supply, nominally +5 V. VDRAIN. Kelvin connection for drain-to-source voltage monitor and is connected to high-side drains of MOSFET bridge. High impedance when terminal is open and registers as a short-to-ground fault on all motor phases. VDSTH. A positive, dc level that sets the drain-to-source monitor threshold voltage. Internally pulled down when terminal is open. VREG. High-side, gate-driver supply, nominally, 13.5 V. Has low-voltage dropout (LDO) feature. 9 3935 THREE-PHASE POWER MOSFET CONTROLLER Functional Description Motor Lead Protection. A fault detection circuit monitors the voltage across the drain to source of the external MOSFETs. A fault is asserted “low” on the output terminal, FAULT, if the drain-to-source voltage of any MOSFET that is instructed to turn on is greater than the voltage applied to the VDSTH input terminal. When a high-side switch is turned on, the voltage from VDRAIN to the appropriate motor phase output, VSX, is examined. If the motor lead is shorted to ground before the high side is turned on, the measured voltage will exceed the threshold and the FAULT terminal will go “low”. Similarly, when a low-side MOSFET is turned on, the differential voltage between the motor phase (drain) and the LSS terminal (source) is monitored. VDSTH is set by a resistor divider to VDD. The VDRAIN is intended to be a Kelvin connection for the highside, drain-source monitor circuit. Voltage drops across the power bus are eliminated by connecting an isolated PCB trace from the VDRAIN terminal to the drain of the MOSFET bridge. This allows improved accuracy in setting the VDSTH threshold voltage. The low-side, drain-source monitor uses the LSS terminal, rather than VDRAIN, in comparing against VDSTH. The A3935 merely reports these motor faults. Fault Outputs. Transient faults on any of the fault outputs are to be expected during switching and will not disable the gate drive outputs. External circuitry or controller logic must determine if the faults represent a hazardous condition. FAULT. This terminal will go active “low” when any of the following conditions occur: VBAT overvoltage, VBAT undervoltage, VREG undervoltage, Motor lead short-to-ground, Motor lead short-to-supply (or battery), Bridge (or VDRAIN) open, VDD undervoltage, or Thermal shutdown. 10 OVFLT. Asserts “high” when a VBAT overvoltage fault occurs and resets “low” after a recovery hysteresis. It has a highimpedance state when a thermal shutdown or VDD undervoltage occurs. The voltage at the OVSET terminal, VOVSET, controls the VBAT overvoltage set point VBAT(ov), i.e., VBAT(ov) = (KBAT(ov) x VSET(ov)) + VBAT(ov)(0), where KBAT(ov) is the gain (12) and VBAT(ov)(0) is the value of VBAT(ov) when VSET(ov) is zero (~22.4). For valid formula, all variables must be in range and below maximum operating specification. UVFLT. Asserts “high” when a VBAT undervoltage fault occurs and resets “low” after a recovery hysteresis. It has a highimpedance state when a thermal shutdown or VDD undervoltage occurs. OVFLT and UVFLT are mutually exclusive by definition. Current Sensing. A current-sense amplifier is provided to allow system monitoring of the load current. The differential amplifier inputs are intended to be Kelvin connected across a low-value sense resistor or current shunt. The output voltage is represented by: VCSOUT = ( ILOAD x AV x RS) + VOS where VOS is the output voltage calibrated at zero load current and AV is the differential amplifier gain of about 19.2. If either the CSP or CSN pin is open, the CSOUT pin will go to its maximum positive level. Shutdown. If a fault occurs because of excessive junction temperature or undervoltage on VDD or VBAT, all gate driver outputs are driven “low” until the fault condition is removed. In addition, the boost supply switch and the VREG are turned “off” until those undervoltages and junction temperatures recover. Boost Supply. VBOOST is controlled by an inner currentcontrol loop, and by an outer voltage-feedback loop. The current-control loop turns “off” the boost switch for 5 µs whenever the voltage across the boost current-sense resistor exceeds 500 mV. A diode reverse-recovery current flows through the sense resistor whenever the boost switch turns “on”, which could turn it “off” again if not for the “blanking time” circuit. Adjustment of this external sense resistor determines the maximum current in the inductor. Whenever VBOOST exceeds the predefined threshold, nominally 16 V, the boost switch is inhibited. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3935 THREE-PHASE POWER MOSFET CONTROLLER Functional Description (cont’d) Input Logic ENABLE xLO xHI GLx GHx Mode of Operation 0 X X 0 0 All gate drive outputs low 1 0 0 0 0 Both gate drive outputs low 1 0 1 0 1 High side on 1 1 0 1 0 Low side on 1 1 1 0 0 XOR circuitry prevents shoot-through Fault Responses ENABLE Input UVFLT Boost Reg. VREG Reg. FAULT OVFLT GHx GLx X 1 0 0 ON ON " " Short-to-Battery 1# 0 0 0 ON ON " " Short-to-Ground 1$ 0 0 0 ON ON " " Bridge (VDRAIN) Fault 1% 0 0 0 ON ON " " VREG Undervoltage X 0 0 0 ON ON " " VBAT Overvoltage X 0 1 0 OFF& ON " " VBAT Undervoltage' X 0 0 1 OFF OFF 0 0 VDD Undervoltage' X 0 Z Z OFF OFF 0 0 Thermal Shutdown' X 0 Z Z OFF OFF 0 0 Fault Mode No Fault NOTES: x = “Little x ”indicates A, B, or C phase. X = “Capital X “ indicates a “don’t care”. Z = High-impedance state. " = Depends on xLO input, xHI input, and ENABLE. See Input Logic table. # = Short-to-battery can only be detected when the corresponding GLx = 1. This fault is not detected when ENABLE = 0. $ = Short-to-ground can only be detected when the corresponding GHx = 1. This fault is not detected when ENABLE = 0. % = Bridge fault appears as a short-to-ground fault on all motor phases. This fault is not detected when ENABLE = 0. & = Off, only because VBOOST ≈ VBAT is above the voltage threshold of the regulator’s voltage control loop. ' = These faults are not only reported but action is taken by the internal logic to protect the A3935 and the system. www.allegromicro.com 11 3935 THREE-PHASE POWER MOSFET CONTROLLER 25 NC 26 SC 27 GHC 28 CC 30 SB 29 GLB 32 CB 31 GHB 33 GLA 35 NC 36 NC GND 40 GLB GND 1 41 SB SA 2 42 GHB GHA 3 43 CB CA 4 44 GLA VREG 6 5 34 SA Package JP, 48-Pin LQFP Package ED, 44-Pin PLCC NC 37 VDRAIN 7 39 CC VBOOST 8 38 GHC BOOSTS 9 37 SC 24 NC GHA 38 23 NC CA 39 22 GLC VREG 40 21 LSS 36 GLC VDRAIN 41 GND 11 35 GND VBOOST 42 19 CSP GND 12 34 GND BOOSTS 43 18 CSN VBAT 13 33 LSS BOOSTD 44 17 VDD BOOSTD 10 UVFLT 14 32 VDSTH 20 VDSTH GND 45 16 CSOUT 15 OVSET CSP 1 36 CSN VDSTH 2 35 VDD LSS 3 34 CSOUT1 GLC 4 33 OVSET SC 5 32 ENABLE GHC 6 31 CHI CC 7 30 CLO GLB 8 29 BLO SB 9 28 BHI GHB 10 27 AHI CB 11 25 FAULT SA 13 24 OVFLT GHA 14 23 UVFLT CA 15 VREG 16 12 5 6 7 8 9 FAULT ALO AHI BHI BLO 21 GND VDRAIN 17 20 BOOSTD VBOOST 18 19 BOOSTS 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 ENABLE 12 4 OVFLT 22 VBAT 11 3 UVFLT 26 ALO GLA 12 CHI 2 NC Package LQ, 36-Pin SOIC CLO 10 1 NC 48 CSOUT 28 NC 27 OVSET 26 13 NC ENABLE 25 NC CHI 24 29 VDD GND 23 ALO 17 GND 22 14 NC CLO 21 NC 47 BLO 20 30 CSN BHI 19 31 CSP FAULT 16 AHI 18 OVFLT 15 VBAT 46 3935 THREE-PHASE POWER MOSFET CONTROLLER A3935KED (PLCC) Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. 2. 3. 4. Exact body and lead configuration at vendor’s option within limits shown. Lead spacing tolerance is non-cumulative. Webbed lead frame. Terminals 1, 2, 11, 12, 22, 23, 34, and 35 are internally one piece. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel. www.allegromicro.com 13 3935 THREE-PHASE POWER MOSFET CONTROLLER A3935KJP (LQFP) 7º 0º .20 .09 9 0.354 BSC A 7 0.276 BSC 0.008 0.004 5 0.197 BSC 1 0.039 REF 48 1 2 .75 .45 0.030 0.018 .25 0.010 BSC Seating Plane Gauge Plane .27 .17 0.011 0.007 1.60 1.40 .50 .020 BSC .15 .05 0.063 0.055 0.006 0.002 Dimensions in millimeters U.S. Customary dimensions (in.) in brackets, for reference only A Exposed thermal pad (bottom surface) 14 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 3935 THREE-PHASE POWER MOSFET CONTROLLER A3935KLQ (SOIC) Dimensions in Inches (for reference only) Dimensions in Millimeters (controlling dimensions) NOTES: 1. Lead spacing tolerance is non-cumulative. 2. Exact body and lead configuration at vendor’s option within limits shown. 3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel. www.allegromicro.com 15 3935 THREE-PHASE POWER MOSFET CONTROLLER The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. 16 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000