3936 DMOS THREE-PHASE PWM MOTOR DRIVER ABSOLUTE MAXIMUM RATINGS at TA = +25°C Load Supply Voltage, VBB ........................... 50 V Output Current, IOUT................................... ±3 A* Logic Supply Voltage, VDD ......................... 7.0 V Logic Input Voltage Range, VIN (tW>30 ns) .......... -0.3 V to VDD + 0.3 V (tW<30 ns) ................ -1.0V to VDD +1V Sense Voltage, VSENSE ................................. 0.5 V Reference Voltage, VREF ................................ VDD Package Power Dissipation, PD ............................................... 3.9 W Operating Temperature Range, TA ................................ -20°C to +85°C Junction Temperature, TJ ......................... +150°C Storage Temperature Range, TS............................... -55°C to +150°C * Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C. Designed for pulse-width modulated (PWM) current control of threephase brushless dc motors, the A3936SED is capable of peak output currents to ± 3 A and operating voltages to 50 V. Internal fixed off-time PWM currentcontrol timing circuitry can be configured to operate in slow-, fast- and mixeddecay modes. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes thermal shutdown with hysteresis, and crossover current protection. Special power up sequencing is not required. The A3936 is supplied in a 44-pin plastic PLCC with a copper batwing tabs (suffix ‘ED’). The power tabs are at ground potential and need no electrical isolation. This device is also available in a lead-free version (100% matte tin leadframe). Features ±3 A, 50 V Continuous Output Rating Low rDS(on) Outputs (typically 500 mΩ source, 315 mΩ sink) Configurable Mixed, Fast and Slow Current-Decay Modes Synchronous Rectification for Low Power Dissipation Internal UVLO and Thermal Shutdown Circuitry Crossover-Current Protection Tachometer Output for External Speed Control Loop Always order by complete part number Part Number Package A3936SED 44-pin PLCC A3936SED-T 44-pin PLCC, Lead-free A3936-DS Rev. 1 3936 Three Phase PWM Motor Driver VDD CP2 REGULATOR CP1 .22uf/100V VREG .22uf/50V FUNCTIONAL BLOCK DIAGRAM CHARGE PUMP TACH BANDGAP HBIAS VREG HAHA+ HALL .22uf/50V VCP OVERVOLTAGE UNDERVOLTAGE AND FAULT DETECT VBB1 VCP VBB2 Comm Logic HBHB+ HALL OUTA HCControl Logic HC+ HALL GATE DRIVE OUTB SLEEP OUTC DIR EXTMODE LSS2 BRAKE LSS1 SR SENSE - ZERO CURRENT DETECT RS + GND VDD + CURRENT SENSE OSC BLANK - PFD1 PWM TIMER BUFFER/ DIVIDER REF PFD2 .1uF ENABLE 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at TJ = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Operating 9 – 50 V During Sleep Mode 0 50 V VOUT = VBB – <1.0 20 µA VOUT = 0 V – <–1.0 -20 µA Source Driver, IOUT = -3A – .55 Ω Sink Driver, IOUT = 3A – .35 Ω Source Diode, IF = -3A – – 1.4 V Sink Diode, IF = 3A – – 1.3 V fPWM < 50 kHz – 4 7 mA Charge Pump On, Outputs Disabled – 2 5 mA Sleep Mode – – 20 uA fPWM < 50 kHz – 10 mA Outputs Off – 8 mA 100 µA Output Drivers Load Supply Voltage Range Output Leakage Current Output On Resistance Body Diode Forward Voltage Motor Supply Current Logic Supply Current VBB IDSS RDSON VF IBB IDD Sleep Mode (Inputs below .5V) Control Logic Logic Supply Voltage Range VDD Logic Input Voltage Operating 3 5.0 5.5 V VIN(1) VDD*.5 – – V VIN(0) – – VDD*.2 V Logic Input Current IIN(1) VIN = VDD*.5 -20 <1.0 20 µA (except ENABLE) IIN(0) VIN = VDD*.2 -20 <-1.0 20 µA Logic Input Current IIN(1) VIN = VDD*.5 – 100 µA ENABLE Input IIN(0) VIN = VDD*.2 – 30 µA Internal Oscillator fOSC OSC shorted to GND 3 4 5 MHz 3.4 4 4.6 MHz ROSC= 51K 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at T J = +25°C, VBB = 50 V, VDD = 5.0 V, fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units Control Logic Buffer Input Offset Volt. VIO VREF Input Voltage Range ±10 mV Operating 0.0 – VDD V -.5 0 0.5 µA Reference Input Current IREF VREF = VDD ,VBB=0 to 50V Comparator Input Offset Volt. VIO VREF = 0 V VERR VREF = VDD -4 4 % (Note 3) VREF = .5V -14 14 % GM Error Propagation Delay Times Crossover Delay tpd Thermal Shutdown Hysteresis 50% TO 90%, SR Enabled 600 750 1000 ns PWM CHANGE TO SOURCE OFF 50 150 350 ns PWM CHANGE TO SINK ON 600 750 1000 ns PWM CHANGE TO SINK OFF 50 100 150 ns SR Enabled 300 600 1000 ns TJ – 165 – °C ∆TJ – 15 – °C 2.45 2.7 2.95 V 0.05 0.10 – V UVLO Enable Threshold Rising VDD UVLO Hysteresis NOTES: 1. 2. 3. mV PWM CHANGE TO SOURCE ON tCOD Thermal Shutdown Temp. ±5 Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin. VERR =((VREF/10) – VSENSE)/(VREF/10) 3936 Three Phase PWM Motor Driver ELECTRICAL CHARACTERISTICS at T A = +25°C, VBB = 50 V, VDD = 5.0 V fPWM < 50KHz (unless noted otherwise) Limits Characteristics Symbol Test Conditions Min. Typ. Max. Units -1 0 1 µA 2.5 V Hall Logic Hall Input Current IHALL Common Mode Input Range VIN = 1.2V VCMR .3 AC Input Voltage Range VHALL .120 Hysteresis VHYS TA= -20 to 85 deg C. Pulse Reject Filter VHB IOUT=40mA, TA= -20 to 85 deg C. IHB Tach Output NOTES: 1. 2. VOL IOUT= 500uA Typical Data is for design information only. Negative current is defined as coming out of (sourcing) the specified device pin. Commutation Truth Table 120 spacing HB HC + + + + + + + + + + + + + + + + + + + + + HA 1 2 3 4 5 6 1 2 3 4 5 6 10 3 Hall Bias Output Sat Voltage DIR FOR FOR FOR FOR FOR FOR REV REV REV REV REV REV X X OUTA HI HI Z LO LO Z LO LO Z HI HI Z Z Z Outputs OUTB OUTC LO Z Z LO HI LO HI Z Z HI LO HI HI Z Z HI LO HI LO Z Z LO HI LO Z Z Z Z Vp-p 30 mV 5.5 8 µs .4 .5 V 40 mA .5 V 3936 Three Phase PWM Motor Driver Functional Description VREG. The VREG pin should be decoupled with a 0.22 µF capacitor to ground. This supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Charge Pump. The Charge Pump is used to generate a supply above VBB to drive the source side DMOS gates. A 0.22 uF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.22 uF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high side DMOS devices. The VCP Voltage is internally monitored and in the case of a fault condition the outputs of the device are disabled. Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of the device are disabled until the fault condition is removed. At power up, and in the event of low VDD, the UVLO circuit disables the drivers. Current Regulation. Load current is regulated by an internal fixed off time PWM control circuit. When the outputs of the DMOS H-bridge are turned on, current increases in the motor winding until it reaches a value given by: ITRIP = VREF/(10*RSENSE) At the trip point, the sense comparator resets the source enable latch, turning off the source driver. At this point, load inductance causes the current to recirculate for the fixed off time period. The current path during recirculation is determined by the configuration of slow/mixed decay mode and the synchronous rectification control setting. Enable Logic. The Enable input terminal allows external PWM. ENABLE high turns ON the selected sinksource pair, enable low switches off the appropriate drivers and the load current decays. If the ENABLE pin is held high, the current will rise until it reaches the level set by the internal current control circuit. ENABLE 0 1 Outputs Source Chopped ON Extmode Logic. When using external PWM current control, the EXTMODE input determines the current path during the chopped cycle. With EXTMODE set low, fast decay mode, both the source and sink drivers are chopped OFF during the decay time (ENABLE=0). With EXTMODE high, slow decay mode, only the source driver turns off during the current decay time. EXTMODE 0 1 Decay Fast Slow Sleep Mode. The input pin SLEEP is dedicated to put the device into a minimum current draw mode. When asserted low, all circuits are disabled. Fixed Off-Time. The 3936 is set for a fixed off time of 96 counts of the internal oscillator, typically 24 µs with 4Mhz oscillator. Internal Current Control Mode. Input pins PFD1 and PFD2 determine the current decay method after an overcurrent event is detected at sense input. In slow decay mode both sink side drivers are turned on for the fixed off time period. Mixed decay mode starts out in fast decay mode for the selected percentage of the fixed off time, and then is followed by slow decay for the rest of the period. PFD2 0 0 1 1 PFD1 0 1 0 1 % tOFF 0 15 48 100 Decay Slow Mixed Mixed Fast 3936 Three Phase PWM Motor Driver PWM Blank Timer. When a source driver turns on, a current spike occurs due to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. To prevent this current spike from erroneously resetting the source enable latch, the sense comparator is blanked. The blank timer runs after the off time counter to provide the blanking function. The blank timer is reset when ENABLE is chopped or DIR is changed. For external PWM control, a DIR change or ENABLE ON will trigger the blanking function. The duration is adjusted by control input BLANK. BLANK 0 1 tBLANK 6/f OSC 12/f OSC Brake. Logic high to the brake terminal activates the brake function, logic low allows normal operation. Brake will turn all three sink drivers ON and effectively shorts out the motor generated BEMF. It is important to note that the internal PWM current control circuit will not limit the current when braking, since the current does not flow through the sense resistor. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations of high speed and high inertial loads. Oscillator. The PWM timer is based on an internal oscillator set by a resistor connected from the OSC terminal to VDD. Typical value of 4Mhz is set with 51k resistor. FOSC = 204E9/ROSC. Tach. A tachometer signal is available for speed measurement. This open collector output toggles at each Hall transition. Synchronous Rectification. Logic high applied to the SR terminal enables synchronous rectification. When a PWM off cycle is triggered, either by an ENABLE chop command or internal fixed off time cycle, load current will recirculate according to the decay mode selected by control logic. The A3936 synchronous rectification feature will turn on the appropriate MOSFET(s)during the current decay and effectively short out the body diodes with the low Rdson driver. This will lower power dissipation significantly and can eliminate the need for external schottky diodes. Reversal of load current is prevented by turning off synchronous rectification when a zero current level is detected. 3936 Terminal List Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Name GND GND HA+ HAHB+ HBHC+ HCVDD REF GND GND GND BRAKE SENSE SR OUTA HBIAS VBB1 LSS1 OUTB GND GND GND LSS2 VBB2 TACH OUTC VCP CP1 CP2 SLEEP GND GND GND OSC VREG DIR ENABLE EXTMODE BLANK PFD2 PFD1 GND Pin Description Hall input Hall input Hall input Hall input Hall input Hall input Logic Supply Voltage Gm Reference Input Voltage Logic Input Sense Resistor Connection Logic Input (Disabled = Low, Active SR = High) DMOS H – Bridge A Connection for hall element neg side Load Supply Voltage Low Side Source connection DMOS H – Bridge B Low Side Source connection Load Supply Voltage Speed output DMOS H – Bridge C Reservoir Capacitor Terminal Charge Pump Capacitor Terminal Charge Pump Capacitor Terminal Logic input for SLEEP mode Oscillator Terminal Regulator decoupling Terminal Logic Input Logic Input Logic Input Logic Input Logic Input Logic Input Power Ground Tab 3936